1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/mm_types.h> 27 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "cik_regs.h" 31 #include "cik_structs.h" 32 #include "oss/oss_2_4_sh_mask.h" 33 34 static inline struct cik_mqd *get_mqd(void *mqd) 35 { 36 return (struct cik_mqd *)mqd; 37 } 38 39 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) 40 { 41 return (struct cik_sdma_rlc_registers *)mqd; 42 } 43 44 static int init_mqd(struct mqd_manager *mm, void **mqd, 45 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 46 struct queue_properties *q) 47 { 48 uint64_t addr; 49 struct cik_mqd *m; 50 int retval; 51 52 retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), 53 mqd_mem_obj); 54 55 if (retval != 0) 56 return -ENOMEM; 57 58 m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr; 59 addr = (*mqd_mem_obj)->gpu_addr; 60 61 memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); 62 63 m->header = 0xC0310800; 64 m->compute_pipelinestat_enable = 1; 65 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 66 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 67 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 68 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 69 70 /* 71 * Make sure to use the last queue state saved on mqd when the cp 72 * reassigns the queue, so when queue is switched on/off (e.g over 73 * subscription or quantum timeout) the context will be consistent 74 */ 75 m->cp_hqd_persistent_state = 76 DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ; 77 78 m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; 79 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 80 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 81 82 m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | 83 QUANTUM_DURATION(10); 84 85 /* 86 * Pipe Priority 87 * Identifies the pipe relative priority when this queue is connected 88 * to the pipeline. The pipe priority is against the GFX pipe and HP3D. 89 * In KFD we are using a fixed pipe priority set to CS_MEDIUM. 90 * 0 = CS_LOW (typically below GFX) 91 * 1 = CS_MEDIUM (typically between HP3D and GFX 92 * 2 = CS_HIGH (typically above HP3D) 93 */ 94 m->cp_hqd_pipe_priority = 1; 95 m->cp_hqd_queue_priority = 15; 96 97 if (q->format == KFD_QUEUE_FORMAT_AQL) 98 m->cp_hqd_iq_rptr = AQL_ENABLE; 99 100 *mqd = m; 101 if (gart_addr) 102 *gart_addr = addr; 103 retval = mm->update_mqd(mm, m, q); 104 105 return retval; 106 } 107 108 static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, 109 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 110 struct queue_properties *q) 111 { 112 int retval; 113 struct cik_sdma_rlc_registers *m; 114 115 retval = kfd_gtt_sa_allocate(mm->dev, 116 sizeof(struct cik_sdma_rlc_registers), 117 mqd_mem_obj); 118 119 if (retval != 0) 120 return -ENOMEM; 121 122 m = (struct cik_sdma_rlc_registers *) (*mqd_mem_obj)->cpu_ptr; 123 124 memset(m, 0, sizeof(struct cik_sdma_rlc_registers)); 125 126 *mqd = m; 127 if (gart_addr) 128 *gart_addr = (*mqd_mem_obj)->gpu_addr; 129 130 retval = mm->update_mqd(mm, m, q); 131 132 return retval; 133 } 134 135 static void uninit_mqd(struct mqd_manager *mm, void *mqd, 136 struct kfd_mem_obj *mqd_mem_obj) 137 { 138 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 139 } 140 141 static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd, 142 struct kfd_mem_obj *mqd_mem_obj) 143 { 144 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 145 } 146 147 static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, 148 uint32_t queue_id, struct queue_properties *p, 149 struct mm_struct *mms) 150 { 151 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 152 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 153 uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1); 154 155 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, 156 (uint32_t __user *)p->write_ptr, 157 wptr_shift, wptr_mask, mms); 158 } 159 160 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 161 uint32_t pipe_id, uint32_t queue_id, 162 struct queue_properties *p, struct mm_struct *mms) 163 { 164 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd, 165 (uint32_t __user *)p->write_ptr, 166 mms); 167 } 168 169 static int __update_mqd(struct mqd_manager *mm, void *mqd, 170 struct queue_properties *q, unsigned int atc_bit) 171 { 172 struct cik_mqd *m; 173 174 m = get_mqd(mqd); 175 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | 176 DEFAULT_MIN_AVAIL_SIZE; 177 m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE; 178 if (atc_bit) { 179 m->cp_hqd_pq_control |= PQ_ATC_EN; 180 m->cp_hqd_ib_control |= IB_ATC_EN; 181 } 182 183 /* 184 * Calculating queue size which is log base 2 of actual queue size -1 185 * dwords and another -1 for ffs 186 */ 187 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 188 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 189 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 190 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 191 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 192 m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); 193 194 m->cp_hqd_vmid = q->vmid; 195 196 if (q->format == KFD_QUEUE_FORMAT_AQL) 197 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; 198 199 q->is_active = (q->queue_size > 0 && 200 q->queue_address != 0 && 201 q->queue_percent > 0 && 202 !q->is_evicted); 203 204 return 0; 205 } 206 207 static int update_mqd(struct mqd_manager *mm, void *mqd, 208 struct queue_properties *q) 209 { 210 return __update_mqd(mm, mqd, q, 1); 211 } 212 213 static int update_mqd_hawaii(struct mqd_manager *mm, void *mqd, 214 struct queue_properties *q) 215 { 216 return __update_mqd(mm, mqd, q, 0); 217 } 218 219 static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, 220 struct queue_properties *q) 221 { 222 struct cik_sdma_rlc_registers *m; 223 224 m = get_sdma_mqd(mqd); 225 m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4) 226 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 227 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 228 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 229 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 230 231 m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); 232 m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8); 233 m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 234 m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 235 m->sdma_rlc_doorbell = 236 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; 237 238 m->sdma_rlc_virtual_addr = q->sdma_vm_addr; 239 240 m->sdma_engine_id = q->sdma_engine_id; 241 m->sdma_queue_id = q->sdma_queue_id; 242 243 q->is_active = (q->queue_size > 0 && 244 q->queue_address != 0 && 245 q->queue_percent > 0 && 246 !q->is_evicted); 247 248 return 0; 249 } 250 251 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 252 enum kfd_preempt_type type, 253 unsigned int timeout, uint32_t pipe_id, 254 uint32_t queue_id) 255 { 256 return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, mqd, type, timeout, 257 pipe_id, queue_id); 258 } 259 260 /* 261 * preempt type here is ignored because there is only one way 262 * to preempt sdma queue 263 */ 264 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 265 enum kfd_preempt_type type, 266 unsigned int timeout, uint32_t pipe_id, 267 uint32_t queue_id) 268 { 269 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); 270 } 271 272 static bool is_occupied(struct mqd_manager *mm, void *mqd, 273 uint64_t queue_address, uint32_t pipe_id, 274 uint32_t queue_id) 275 { 276 277 return mm->dev->kfd2kgd->hqd_is_occupied(mm->dev->kgd, queue_address, 278 pipe_id, queue_id); 279 280 } 281 282 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 283 uint64_t queue_address, uint32_t pipe_id, 284 uint32_t queue_id) 285 { 286 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); 287 } 288 289 /* 290 * HIQ MQD Implementation, concrete implementation for HIQ MQD implementation. 291 * The HIQ queue in Kaveri is using the same MQD structure as all the user mode 292 * queues but with different initial values. 293 */ 294 295 static int init_mqd_hiq(struct mqd_manager *mm, void **mqd, 296 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 297 struct queue_properties *q) 298 { 299 uint64_t addr; 300 struct cik_mqd *m; 301 int retval; 302 303 retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), 304 mqd_mem_obj); 305 306 if (retval != 0) 307 return -ENOMEM; 308 309 m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr; 310 addr = (*mqd_mem_obj)->gpu_addr; 311 312 memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); 313 314 m->header = 0xC0310800; 315 m->compute_pipelinestat_enable = 1; 316 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 317 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 318 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 319 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 320 321 m->cp_hqd_persistent_state = DEFAULT_CP_HQD_PERSISTENT_STATE | 322 PRELOAD_REQ; 323 m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | 324 QUANTUM_DURATION(10); 325 326 m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; 327 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 328 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 329 330 m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE; 331 332 /* 333 * Pipe Priority 334 * Identifies the pipe relative priority when this queue is connected 335 * to the pipeline. The pipe priority is against the GFX pipe and HP3D. 336 * In KFD we are using a fixed pipe priority set to CS_MEDIUM. 337 * 0 = CS_LOW (typically below GFX) 338 * 1 = CS_MEDIUM (typically between HP3D and GFX 339 * 2 = CS_HIGH (typically above HP3D) 340 */ 341 m->cp_hqd_pipe_priority = 1; 342 m->cp_hqd_queue_priority = 15; 343 344 *mqd = m; 345 if (gart_addr) 346 *gart_addr = addr; 347 retval = mm->update_mqd(mm, m, q); 348 349 return retval; 350 } 351 352 static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, 353 struct queue_properties *q) 354 { 355 struct cik_mqd *m; 356 357 m = get_mqd(mqd); 358 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | 359 DEFAULT_MIN_AVAIL_SIZE | 360 PRIV_STATE | 361 KMD_QUEUE; 362 363 /* 364 * Calculating queue size which is log base 2 of actual queue 365 * size -1 dwords 366 */ 367 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 368 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 369 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 370 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 371 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 372 m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); 373 374 m->cp_hqd_vmid = q->vmid; 375 376 q->is_active = (q->queue_size > 0 && 377 q->queue_address != 0 && 378 q->queue_percent > 0 && 379 !q->is_evicted); 380 381 return 0; 382 } 383 384 #if defined(CONFIG_DEBUG_FS) 385 386 static int debugfs_show_mqd(struct seq_file *m, void *data) 387 { 388 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 389 data, sizeof(struct cik_mqd), false); 390 return 0; 391 } 392 393 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 394 { 395 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 396 data, sizeof(struct cik_sdma_rlc_registers), false); 397 return 0; 398 } 399 400 #endif 401 402 403 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 404 struct kfd_dev *dev) 405 { 406 struct mqd_manager *mqd; 407 408 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 409 return NULL; 410 411 mqd = kzalloc(sizeof(*mqd), GFP_NOIO); 412 if (!mqd) 413 return NULL; 414 415 mqd->dev = dev; 416 417 switch (type) { 418 case KFD_MQD_TYPE_CP: 419 case KFD_MQD_TYPE_COMPUTE: 420 mqd->init_mqd = init_mqd; 421 mqd->uninit_mqd = uninit_mqd; 422 mqd->load_mqd = load_mqd; 423 mqd->update_mqd = update_mqd; 424 mqd->destroy_mqd = destroy_mqd; 425 mqd->is_occupied = is_occupied; 426 #if defined(CONFIG_DEBUG_FS) 427 mqd->debugfs_show_mqd = debugfs_show_mqd; 428 #endif 429 break; 430 case KFD_MQD_TYPE_HIQ: 431 mqd->init_mqd = init_mqd_hiq; 432 mqd->uninit_mqd = uninit_mqd; 433 mqd->load_mqd = load_mqd; 434 mqd->update_mqd = update_mqd_hiq; 435 mqd->destroy_mqd = destroy_mqd; 436 mqd->is_occupied = is_occupied; 437 #if defined(CONFIG_DEBUG_FS) 438 mqd->debugfs_show_mqd = debugfs_show_mqd; 439 #endif 440 break; 441 case KFD_MQD_TYPE_SDMA: 442 mqd->init_mqd = init_mqd_sdma; 443 mqd->uninit_mqd = uninit_mqd_sdma; 444 mqd->load_mqd = load_mqd_sdma; 445 mqd->update_mqd = update_mqd_sdma; 446 mqd->destroy_mqd = destroy_mqd_sdma; 447 mqd->is_occupied = is_occupied_sdma; 448 #if defined(CONFIG_DEBUG_FS) 449 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 450 #endif 451 break; 452 default: 453 kfree(mqd); 454 return NULL; 455 } 456 457 return mqd; 458 } 459 460 struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type, 461 struct kfd_dev *dev) 462 { 463 struct mqd_manager *mqd; 464 465 mqd = mqd_manager_init_cik(type, dev); 466 if (!mqd) 467 return NULL; 468 if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE)) 469 mqd->update_mqd = update_mqd_hawaii; 470 return mqd; 471 } 472