1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/mm_types.h> 28 29 #include "kfd_priv.h" 30 #include "kfd_mqd_manager.h" 31 #include "cik_regs.h" 32 #include "cik_structs.h" 33 #include "oss/oss_2_4_sh_mask.h" 34 35 static inline struct cik_mqd *get_mqd(void *mqd) 36 { 37 return (struct cik_mqd *)mqd; 38 } 39 40 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) 41 { 42 return (struct cik_sdma_rlc_registers *)mqd; 43 } 44 45 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 46 struct mqd_update_info *minfo) 47 { 48 struct cik_mqd *m; 49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 50 51 if (!minfo || !minfo->cu_mask.ptr) 52 return; 53 54 mqd_symmetrically_map_cu_mask(mm, 55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); 56 57 m = get_mqd(mqd); 58 m->compute_static_thread_mgmt_se0 = se_mask[0]; 59 m->compute_static_thread_mgmt_se1 = se_mask[1]; 60 m->compute_static_thread_mgmt_se2 = se_mask[2]; 61 m->compute_static_thread_mgmt_se3 = se_mask[3]; 62 63 pr_debug("Update cu mask to %#x %#x %#x %#x\n", 64 m->compute_static_thread_mgmt_se0, 65 m->compute_static_thread_mgmt_se1, 66 m->compute_static_thread_mgmt_se2, 67 m->compute_static_thread_mgmt_se3); 68 } 69 70 static void set_priority(struct cik_mqd *m, struct queue_properties *q) 71 { 72 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 73 /* m->cp_hqd_queue_priority = q->priority; */ 74 } 75 76 static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 77 struct queue_properties *q) 78 { 79 struct kfd_node *kfd = mm->dev; 80 struct kfd_mem_obj *mqd_mem_obj; 81 82 if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd), 83 &mqd_mem_obj)) 84 return NULL; 85 86 return mqd_mem_obj; 87 } 88 89 static void init_mqd(struct mqd_manager *mm, void **mqd, 90 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 91 struct queue_properties *q) 92 { 93 uint64_t addr; 94 struct cik_mqd *m; 95 96 m = (struct cik_mqd *) mqd_mem_obj->cpu_ptr; 97 addr = mqd_mem_obj->gpu_addr; 98 99 memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); 100 101 m->header = 0xC0310800; 102 m->compute_pipelinestat_enable = 1; 103 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 104 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 105 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 106 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 107 108 /* 109 * Make sure to use the last queue state saved on mqd when the cp 110 * reassigns the queue, so when queue is switched on/off (e.g over 111 * subscription or quantum timeout) the context will be consistent 112 */ 113 m->cp_hqd_persistent_state = 114 DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ; 115 116 m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; 117 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 118 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 119 120 m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | 121 QUANTUM_DURATION(10); 122 123 /* 124 * Pipe Priority 125 * Identifies the pipe relative priority when this queue is connected 126 * to the pipeline. The pipe priority is against the GFX pipe and HP3D. 127 * In KFD we are using a fixed pipe priority set to CS_MEDIUM. 128 * 0 = CS_LOW (typically below GFX) 129 * 1 = CS_MEDIUM (typically between HP3D and GFX 130 * 2 = CS_HIGH (typically above HP3D) 131 */ 132 set_priority(m, q); 133 134 if (q->format == KFD_QUEUE_FORMAT_AQL) 135 m->cp_hqd_iq_rptr = AQL_ENABLE; 136 137 *mqd = m; 138 if (gart_addr) 139 *gart_addr = addr; 140 mm->update_mqd(mm, m, q, NULL); 141 } 142 143 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 144 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 145 struct queue_properties *q) 146 { 147 struct cik_sdma_rlc_registers *m; 148 149 m = (struct cik_sdma_rlc_registers *) mqd_mem_obj->cpu_ptr; 150 151 memset(m, 0, sizeof(struct cik_sdma_rlc_registers)); 152 153 *mqd = m; 154 if (gart_addr) 155 *gart_addr = mqd_mem_obj->gpu_addr; 156 157 mm->update_mqd(mm, m, q, NULL); 158 } 159 160 static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, 161 uint32_t queue_id, struct queue_properties *p, 162 struct mm_struct *mms) 163 { 164 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 165 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 166 uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1); 167 168 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 169 (uint32_t __user *)p->write_ptr, 170 wptr_shift, wptr_mask, mms, 0); 171 } 172 173 static void __update_mqd(struct mqd_manager *mm, void *mqd, 174 struct queue_properties *q, struct mqd_update_info *minfo, 175 unsigned int atc_bit) 176 { 177 struct cik_mqd *m; 178 179 m = get_mqd(mqd); 180 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | 181 DEFAULT_MIN_AVAIL_SIZE; 182 m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE; 183 if (atc_bit) { 184 m->cp_hqd_pq_control |= PQ_ATC_EN; 185 m->cp_hqd_ib_control |= IB_ATC_EN; 186 } 187 188 /* 189 * Calculating queue size which is log base 2 of actual queue size -1 190 * dwords and another -1 for ffs 191 */ 192 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 193 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 194 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 195 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 196 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 197 m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); 198 199 m->cp_hqd_vmid = q->vmid; 200 201 if (q->format == KFD_QUEUE_FORMAT_AQL) 202 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; 203 204 update_cu_mask(mm, mqd, minfo); 205 set_priority(m, q); 206 207 q->is_active = QUEUE_IS_ACTIVE(*q); 208 } 209 210 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 211 { 212 struct cik_mqd *m = (struct cik_mqd *)mqd; 213 214 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); 215 } 216 217 static void update_mqd(struct mqd_manager *mm, void *mqd, 218 struct queue_properties *q, 219 struct mqd_update_info *minfo) 220 { 221 __update_mqd(mm, mqd, q, minfo, 0); 222 } 223 224 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 225 struct queue_properties *q, 226 struct mqd_update_info *minfo) 227 { 228 struct cik_sdma_rlc_registers *m; 229 230 m = get_sdma_mqd(mqd); 231 m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4) 232 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 233 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 234 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 235 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 236 237 m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); 238 m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8); 239 m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 240 m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 241 m->sdma_rlc_doorbell = 242 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; 243 244 m->sdma_rlc_virtual_addr = q->sdma_vm_addr; 245 246 m->sdma_engine_id = q->sdma_engine_id; 247 m->sdma_queue_id = q->sdma_queue_id; 248 249 q->is_active = QUEUE_IS_ACTIVE(*q); 250 } 251 252 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 253 { 254 struct cik_mqd *m; 255 256 m = get_mqd(mqd); 257 258 memcpy(mqd_dst, m, sizeof(struct cik_mqd)); 259 } 260 261 static void restore_mqd(struct mqd_manager *mm, void **mqd, 262 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 263 struct queue_properties *qp, 264 const void *mqd_src, 265 const void *ctl_stack_src, const u32 ctl_stack_size) 266 { 267 uint64_t addr; 268 struct cik_mqd *m; 269 270 m = (struct cik_mqd *) mqd_mem_obj->cpu_ptr; 271 addr = mqd_mem_obj->gpu_addr; 272 273 memcpy(m, mqd_src, sizeof(*m)); 274 275 *mqd = m; 276 if (gart_addr) 277 *gart_addr = addr; 278 279 m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(qp->doorbell_off); 280 281 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 282 m->cp_hqd_pq_doorbell_control); 283 284 qp->is_active = 0; 285 } 286 287 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 288 void *mqd, 289 void *mqd_dst, 290 void *ctl_stack_dst) 291 { 292 struct cik_sdma_rlc_registers *m; 293 294 m = get_sdma_mqd(mqd); 295 296 memcpy(mqd_dst, m, sizeof(struct cik_sdma_rlc_registers)); 297 } 298 299 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 300 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 301 struct queue_properties *qp, 302 const void *mqd_src, 303 const void *ctl_stack_src, const u32 ctl_stack_size) 304 { 305 uint64_t addr; 306 struct cik_sdma_rlc_registers *m; 307 308 m = (struct cik_sdma_rlc_registers *) mqd_mem_obj->cpu_ptr; 309 addr = mqd_mem_obj->gpu_addr; 310 311 memcpy(m, mqd_src, sizeof(*m)); 312 313 m->sdma_rlc_doorbell = 314 qp->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; 315 316 *mqd = m; 317 if (gart_addr) 318 *gart_addr = addr; 319 320 qp->is_active = 0; 321 } 322 323 /* 324 * HIQ MQD Implementation, concrete implementation for HIQ MQD implementation. 325 * The HIQ queue in Kaveri is using the same MQD structure as all the user mode 326 * queues but with different initial values. 327 */ 328 329 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 330 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 331 struct queue_properties *q) 332 { 333 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 334 } 335 336 static void update_mqd_hiq(struct mqd_manager *mm, void *mqd, 337 struct queue_properties *q, 338 struct mqd_update_info *minfo) 339 { 340 struct cik_mqd *m; 341 342 m = get_mqd(mqd); 343 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | 344 DEFAULT_MIN_AVAIL_SIZE | 345 PRIV_STATE | 346 KMD_QUEUE; 347 348 /* 349 * Calculating queue size which is log base 2 of actual queue 350 * size -1 dwords 351 */ 352 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 353 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 354 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 355 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 356 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 357 m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); 358 359 m->cp_hqd_vmid = q->vmid; 360 361 q->is_active = QUEUE_IS_ACTIVE(*q); 362 363 set_priority(m, q); 364 } 365 366 #if defined(CONFIG_DEBUG_FS) 367 368 static int debugfs_show_mqd(struct seq_file *m, void *data) 369 { 370 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 371 data, sizeof(struct cik_mqd), false); 372 return 0; 373 } 374 375 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 376 { 377 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 378 data, sizeof(struct cik_sdma_rlc_registers), false); 379 return 0; 380 } 381 382 #endif 383 384 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 385 struct kfd_node *dev) 386 { 387 struct mqd_manager *mqd; 388 389 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 390 return NULL; 391 392 mqd = kzalloc_obj(*mqd); 393 if (!mqd) 394 return NULL; 395 396 mqd->dev = dev; 397 398 switch (type) { 399 case KFD_MQD_TYPE_CP: 400 mqd->allocate_mqd = allocate_mqd; 401 mqd->init_mqd = init_mqd; 402 mqd->free_mqd = kfd_free_mqd_cp; 403 mqd->load_mqd = load_mqd; 404 mqd->update_mqd = update_mqd; 405 mqd->destroy_mqd = kfd_destroy_mqd_cp; 406 mqd->is_occupied = kfd_is_occupied_cp; 407 mqd->checkpoint_mqd = checkpoint_mqd; 408 mqd->restore_mqd = restore_mqd; 409 mqd->mqd_size = sizeof(struct cik_mqd); 410 #if defined(CONFIG_DEBUG_FS) 411 mqd->debugfs_show_mqd = debugfs_show_mqd; 412 #endif 413 break; 414 case KFD_MQD_TYPE_HIQ: 415 mqd->allocate_mqd = allocate_hiq_mqd; 416 mqd->init_mqd = init_mqd_hiq; 417 mqd->free_mqd = free_mqd_hiq_sdma; 418 mqd->load_mqd = load_mqd; 419 mqd->update_mqd = update_mqd_hiq; 420 mqd->destroy_mqd = kfd_destroy_mqd_cp; 421 mqd->is_occupied = kfd_is_occupied_cp; 422 mqd->mqd_size = sizeof(struct cik_mqd); 423 mqd->mqd_stride = kfd_mqd_stride; 424 #if defined(CONFIG_DEBUG_FS) 425 mqd->debugfs_show_mqd = debugfs_show_mqd; 426 #endif 427 mqd->check_preemption_failed = check_preemption_failed; 428 break; 429 case KFD_MQD_TYPE_DIQ: 430 mqd->allocate_mqd = allocate_mqd; 431 mqd->init_mqd = init_mqd_hiq; 432 mqd->free_mqd = kfd_free_mqd_cp; 433 mqd->load_mqd = load_mqd; 434 mqd->update_mqd = update_mqd_hiq; 435 mqd->destroy_mqd = kfd_destroy_mqd_cp; 436 mqd->is_occupied = kfd_is_occupied_cp; 437 mqd->mqd_size = sizeof(struct cik_mqd); 438 mqd->mqd_stride = kfd_mqd_stride; 439 #if defined(CONFIG_DEBUG_FS) 440 mqd->debugfs_show_mqd = debugfs_show_mqd; 441 #endif 442 break; 443 case KFD_MQD_TYPE_SDMA: 444 mqd->allocate_mqd = allocate_sdma_mqd; 445 mqd->init_mqd = init_mqd_sdma; 446 mqd->free_mqd = free_mqd_hiq_sdma; 447 mqd->load_mqd = kfd_load_mqd_sdma; 448 mqd->update_mqd = update_mqd_sdma; 449 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 450 mqd->is_occupied = kfd_is_occupied_sdma; 451 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 452 mqd->restore_mqd = restore_mqd_sdma; 453 mqd->mqd_size = sizeof(struct cik_sdma_rlc_registers); 454 mqd->mqd_stride = kfd_mqd_stride; 455 #if defined(CONFIG_DEBUG_FS) 456 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 457 #endif 458 break; 459 default: 460 kfree(mqd); 461 return NULL; 462 } 463 464 return mqd; 465 } 466