1 /* 2 * Copyright 2016-2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "kfd_priv.h" 24 #include "kfd_events.h" 25 #include "soc15_int.h" 26 #include "kfd_device_queue_manager.h" 27 #include "kfd_smi_events.h" 28 29 enum SQ_INTERRUPT_WORD_ENCODING { 30 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, 31 SQ_INTERRUPT_WORD_ENCODING_INST, 32 SQ_INTERRUPT_WORD_ENCODING_ERROR, 33 }; 34 35 enum SQ_INTERRUPT_ERROR_TYPE { 36 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0, 37 SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST, 38 SQ_INTERRUPT_ERROR_TYPE_MEMVIOL, 39 SQ_INTERRUPT_ERROR_TYPE_EDC_FED, 40 }; 41 42 /* SQ_INTERRUPT_WORD_AUTO_CTXID */ 43 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0 44 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 1 45 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 2 46 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 3 47 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 4 48 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 5 49 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 6 50 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 7 51 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 8 52 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 24 53 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 26 54 55 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x00000001 56 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x00000002 57 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x00000004 58 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x00000008 59 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x00000010 60 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x00000020 61 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x00000040 62 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x00000080 63 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x00000100 64 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x03000000 65 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0x0c000000 66 67 /* SQ_INTERRUPT_WORD_WAVE_CTXID */ 68 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0 69 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 12 70 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 13 71 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 14 72 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 18 73 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 20 74 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 24 75 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 26 76 77 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x00000fff 78 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x00001000 79 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x00002000 80 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x0003c000 81 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x000c0000 82 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x00f00000 83 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x03000000 84 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0x0c000000 85 86 #define KFD_CONTEXT_ID_GET_SQ_INT_DATA(ctx0, ctx1) \ 87 ((ctx0 & 0xfff) | ((ctx0 >> 16) & 0xf000) | ((ctx1 << 16) & 0xff0000)) 88 89 #define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000 90 #define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20 91 92 static void event_interrupt_poison_consumption(struct kfd_dev *dev, 93 uint16_t pasid, uint16_t source_id) 94 { 95 int ret = -EINVAL; 96 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); 97 98 if (!p) 99 return; 100 101 /* all queues of a process will be unmapped in one time */ 102 if (atomic_read(&p->poison)) { 103 kfd_unref_process(p); 104 return; 105 } 106 107 atomic_set(&p->poison, 1); 108 kfd_unref_process(p); 109 110 switch (source_id) { 111 case SOC15_INTSRC_SQ_INTERRUPT_MSG: 112 if (dev->dqm->ops.reset_queues) 113 ret = dev->dqm->ops.reset_queues(dev->dqm, pasid); 114 break; 115 case SOC15_INTSRC_SDMA_ECC: 116 default: 117 break; 118 } 119 120 kfd_signal_poison_consumed_event(dev, pasid); 121 122 /* resetting queue passes, do page retirement without gpu reset 123 resetting queue fails, fallback to gpu reset solution */ 124 if (!ret) 125 amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false); 126 else 127 amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true); 128 } 129 130 static bool event_interrupt_isr_v9(struct kfd_dev *dev, 131 const uint32_t *ih_ring_entry, 132 uint32_t *patched_ihre, 133 bool *patched_flag) 134 { 135 uint16_t source_id, client_id, pasid, vmid; 136 const uint32_t *data = ih_ring_entry; 137 138 /* Only handle interrupts from KFD VMIDs */ 139 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 140 if (vmid < dev->vm_info.first_vmid_kfd || 141 vmid > dev->vm_info.last_vmid_kfd) 142 return false; 143 144 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 145 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 146 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 147 148 /* Only handle clients we care about */ 149 if (client_id != SOC15_IH_CLIENTID_GRBM_CP && 150 client_id != SOC15_IH_CLIENTID_SDMA0 && 151 client_id != SOC15_IH_CLIENTID_SDMA1 && 152 client_id != SOC15_IH_CLIENTID_SDMA2 && 153 client_id != SOC15_IH_CLIENTID_SDMA3 && 154 client_id != SOC15_IH_CLIENTID_SDMA4 && 155 client_id != SOC15_IH_CLIENTID_SDMA5 && 156 client_id != SOC15_IH_CLIENTID_SDMA6 && 157 client_id != SOC15_IH_CLIENTID_SDMA7 && 158 client_id != SOC15_IH_CLIENTID_VMC && 159 client_id != SOC15_IH_CLIENTID_VMC1 && 160 client_id != SOC15_IH_CLIENTID_UTCL2 && 161 client_id != SOC15_IH_CLIENTID_SE0SH && 162 client_id != SOC15_IH_CLIENTID_SE1SH && 163 client_id != SOC15_IH_CLIENTID_SE2SH && 164 client_id != SOC15_IH_CLIENTID_SE3SH) 165 return false; 166 167 /* This is a known issue for gfx9. Under non HWS, pasid is not set 168 * in the interrupt payload, so we need to find out the pasid on our 169 * own. 170 */ 171 if (!pasid && dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 172 const uint32_t pasid_mask = 0xffff; 173 174 *patched_flag = true; 175 memcpy(patched_ihre, ih_ring_entry, 176 dev->device_info.ih_ring_entry_size); 177 178 pasid = dev->dqm->vmid_pasid[vmid]; 179 180 /* Patch the pasid field */ 181 patched_ihre[3] = cpu_to_le32((le32_to_cpu(patched_ihre[3]) 182 & ~pasid_mask) | pasid); 183 } 184 185 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n", 186 client_id, source_id, vmid, pasid); 187 pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n", 188 data[0], data[1], data[2], data[3], 189 data[4], data[5], data[6], data[7]); 190 191 /* If there is no valid PASID, it's likely a bug */ 192 if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt")) 193 return false; 194 195 /* Interrupt types we care about: various signals and faults. 196 * They will be forwarded to a work queue (see below). 197 */ 198 return source_id == SOC15_INTSRC_CP_END_OF_PIPE || 199 source_id == SOC15_INTSRC_SDMA_TRAP || 200 source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG || 201 source_id == SOC15_INTSRC_CP_BAD_OPCODE || 202 ((client_id == SOC15_IH_CLIENTID_VMC || 203 client_id == SOC15_IH_CLIENTID_VMC1 || 204 client_id == SOC15_IH_CLIENTID_UTCL2) && 205 !amdgpu_no_queue_eviction_on_vm_fault); 206 } 207 208 static void event_interrupt_wq_v9(struct kfd_dev *dev, 209 const uint32_t *ih_ring_entry) 210 { 211 uint16_t source_id, client_id, pasid, vmid; 212 uint32_t context_id0, context_id1; 213 uint32_t sq_intr_err, sq_int_data, encoding; 214 215 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 216 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 217 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 218 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 219 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); 220 context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry); 221 222 if (client_id == SOC15_IH_CLIENTID_GRBM_CP || 223 client_id == SOC15_IH_CLIENTID_SE0SH || 224 client_id == SOC15_IH_CLIENTID_SE1SH || 225 client_id == SOC15_IH_CLIENTID_SE2SH || 226 client_id == SOC15_IH_CLIENTID_SE3SH) { 227 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) 228 kfd_signal_event_interrupt(pasid, context_id0, 32); 229 else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { 230 sq_int_data = KFD_CONTEXT_ID_GET_SQ_INT_DATA(context_id0, context_id1); 231 encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); 232 switch (encoding) { 233 case SQ_INTERRUPT_WORD_ENCODING_AUTO: 234 pr_debug( 235 "sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n", 236 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID), 237 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE), 238 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT), 239 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_BUF_FULL), 240 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, REG_TIMESTAMP), 241 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, CMD_TIMESTAMP), 242 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_CMD_OVERFLOW), 243 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_REG_OVERFLOW), 244 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, IMMED_OVERFLOW), 245 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_UTC_ERROR)); 246 break; 247 case SQ_INTERRUPT_WORD_ENCODING_INST: 248 pr_debug("sq_intr: inst, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, intr_data 0x%x\n", 249 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 250 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 251 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 252 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 253 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 254 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 255 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 256 sq_int_data); 257 break; 258 case SQ_INTERRUPT_WORD_ENCODING_ERROR: 259 sq_intr_err = REG_GET_FIELD(sq_int_data, KFD_SQ_INT_DATA, ERR_TYPE); 260 pr_warn("sq_intr: error, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, err_type %d\n", 261 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 262 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 263 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 264 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 265 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 266 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 267 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 268 sq_intr_err); 269 if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST && 270 sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) { 271 event_interrupt_poison_consumption(dev, pasid, source_id); 272 return; 273 } 274 break; 275 default: 276 break; 277 } 278 kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24); 279 } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) 280 kfd_signal_hw_exception_event(pasid); 281 } else if (client_id == SOC15_IH_CLIENTID_SDMA0 || 282 client_id == SOC15_IH_CLIENTID_SDMA1 || 283 client_id == SOC15_IH_CLIENTID_SDMA2 || 284 client_id == SOC15_IH_CLIENTID_SDMA3 || 285 client_id == SOC15_IH_CLIENTID_SDMA4 || 286 client_id == SOC15_IH_CLIENTID_SDMA5 || 287 client_id == SOC15_IH_CLIENTID_SDMA6 || 288 client_id == SOC15_IH_CLIENTID_SDMA7) { 289 if (source_id == SOC15_INTSRC_SDMA_TRAP) { 290 kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); 291 } else if (source_id == SOC15_INTSRC_SDMA_ECC) { 292 event_interrupt_poison_consumption(dev, pasid, source_id); 293 return; 294 } 295 } else if (client_id == SOC15_IH_CLIENTID_VMC || 296 client_id == SOC15_IH_CLIENTID_VMC1 || 297 client_id == SOC15_IH_CLIENTID_UTCL2) { 298 struct kfd_vm_fault_info info = {0}; 299 uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); 300 301 info.vmid = vmid; 302 info.mc_id = client_id; 303 info.page_addr = ih_ring_entry[4] | 304 (uint64_t)(ih_ring_entry[5] & 0xf) << 32; 305 info.prot_valid = ring_id & 0x08; 306 info.prot_read = ring_id & 0x10; 307 info.prot_write = ring_id & 0x20; 308 309 kfd_smi_event_update_vmfault(dev, pasid); 310 kfd_process_vm_fault(dev->dqm, pasid); 311 kfd_signal_vm_fault_event(dev, pasid, &info); 312 } 313 } 314 315 const struct kfd_event_interrupt_class event_interrupt_class_v9 = { 316 .interrupt_isr = event_interrupt_isr_v9, 317 .interrupt_wq = event_interrupt_wq_v9, 318 }; 319