1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "kfd_priv.h" 25 #include "kfd_events.h" 26 #include "kfd_debug.h" 27 #include "soc15_int.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_smi_events.h" 30 #include "amdgpu_ras.h" 31 32 /* 33 * GFX9 SQ Interrupts 34 * 35 * There are 3 encoding types of interrupts sourced from SQ sent as a 44-bit 36 * packet to the Interrupt Handler: 37 * Auto - Generated by the SQG (various cmd overflows, timestamps etc) 38 * Wave - Generated by S_SENDMSG through a shader program 39 * Error - HW generated errors (Illegal instructions, Memviols, EDC etc) 40 * 41 * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus 42 * 4-bits for VMID (SOC15_VMID_FROM_IH_ENTRY) as such: 43 * 44 * - context_id0[27:26] 45 * Encoding type (0 = Auto, 1 = Wave, 2 = Error) 46 * 47 * - context_id0[13] 48 * PRIV bit indicates that Wave S_SEND or error occurred within trap 49 * 50 * - {context_id1[7:0],context_id0[31:28],context_id0[11:0]} 51 * 24-bit data with the following layout per encoding type: 52 * Auto - only context_id0[8:0] is used, which reports various interrupts 53 * generated by SQG. The rest is 0. 54 * Wave - user data sent from m0 via S_SENDMSG 55 * Error - Error type (context_id1[7:4]), Error Details (rest of bits) 56 * 57 * The other context_id bits show coordinates (SE/SH/CU/SIMD/WAVE) for wave 58 * S_SENDMSG and Errors. These are 0 for Auto. 59 */ 60 61 enum SQ_INTERRUPT_WORD_ENCODING { 62 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, 63 SQ_INTERRUPT_WORD_ENCODING_INST, 64 SQ_INTERRUPT_WORD_ENCODING_ERROR, 65 }; 66 67 enum SQ_INTERRUPT_ERROR_TYPE { 68 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0, 69 SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST, 70 SQ_INTERRUPT_ERROR_TYPE_MEMVIOL, 71 SQ_INTERRUPT_ERROR_TYPE_EDC_FED, 72 }; 73 74 /* SQ_INTERRUPT_WORD_AUTO_CTXID */ 75 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0 76 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 1 77 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 2 78 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 3 79 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 4 80 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 5 81 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 6 82 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 7 83 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 8 84 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 24 85 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 26 86 87 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x00000001 88 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x00000002 89 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x00000004 90 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x00000008 91 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x00000010 92 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x00000020 93 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x00000040 94 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x00000080 95 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x00000100 96 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x03000000 97 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0x0c000000 98 99 /* SQ_INTERRUPT_WORD_WAVE_CTXID */ 100 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0 101 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 12 102 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 13 103 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 14 104 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 18 105 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 20 106 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 24 107 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 26 108 109 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x00000fff 110 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x00001000 111 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x00002000 112 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x0003c000 113 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x000c0000 114 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x00f00000 115 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x03000000 116 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0x0c000000 117 118 /* GFX9 SQ interrupt 24-bit data from context_id<0,1> */ 119 #define KFD_CONTEXT_ID_GET_SQ_INT_DATA(ctx0, ctx1) \ 120 ((ctx0 & 0xfff) | ((ctx0 >> 16) & 0xf000) | ((ctx1 << 16) & 0xff0000)) 121 122 #define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000 123 #define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20 124 125 /* 126 * The debugger will send user data(m0) with PRIV=1 to indicate it requires 127 * notification from the KFD with the following queue id (DOORBELL_ID) and 128 * trap code (TRAP_CODE). 129 */ 130 #define KFD_INT_DATA_DEBUG_DOORBELL_MASK 0x0003ff 131 #define KFD_INT_DATA_DEBUG_TRAP_CODE_SHIFT 10 132 #define KFD_INT_DATA_DEBUG_TRAP_CODE_MASK 0x07fc00 133 #define KFD_DEBUG_DOORBELL_ID(sq_int_data) ((sq_int_data) & \ 134 KFD_INT_DATA_DEBUG_DOORBELL_MASK) 135 #define KFD_DEBUG_TRAP_CODE(sq_int_data) (((sq_int_data) & \ 136 KFD_INT_DATA_DEBUG_TRAP_CODE_MASK) \ 137 >> KFD_INT_DATA_DEBUG_TRAP_CODE_SHIFT) 138 #define KFD_DEBUG_CP_BAD_OP_ECODE_MASK 0x3fffc00 139 #define KFD_DEBUG_CP_BAD_OP_ECODE_SHIFT 10 140 #define KFD_DEBUG_CP_BAD_OP_ECODE(ctxid0) (((ctxid0) & \ 141 KFD_DEBUG_CP_BAD_OP_ECODE_MASK) \ 142 >> KFD_DEBUG_CP_BAD_OP_ECODE_SHIFT) 143 144 static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, 145 uint16_t pasid, uint16_t client_id) 146 { 147 enum amdgpu_ras_block block = 0; 148 uint32_t reset = 0; 149 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, NULL); 150 enum ras_event_type type = RAS_EVENT_TYPE_POISON_CONSUMPTION; 151 u64 event_id; 152 int old_poison, ret; 153 154 if (!p) 155 return; 156 157 /* all queues of a process will be unmapped in one time */ 158 old_poison = atomic_cmpxchg(&p->poison, 0, 1); 159 kfd_unref_process(p); 160 if (old_poison) 161 return; 162 163 switch (client_id) { 164 case SOC15_IH_CLIENTID_SE0SH: 165 case SOC15_IH_CLIENTID_SE1SH: 166 case SOC15_IH_CLIENTID_SE2SH: 167 case SOC15_IH_CLIENTID_SE3SH: 168 case SOC15_IH_CLIENTID_UTCL2: 169 block = AMDGPU_RAS_BLOCK__GFX; 170 if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 171 /* driver mode-2 for gfx poison is only supported by 172 * pmfw 0x00557300 and onwards */ 173 if (dev->adev->pm.fw_version < 0x00557300) 174 reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; 175 else 176 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 177 } else if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 178 /* driver mode-2 for gfx poison is only supported by 179 * pmfw 0x05550C00 and onwards */ 180 if (dev->adev->pm.fw_version < 0x05550C00) 181 reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; 182 else 183 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 184 } else { 185 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 186 } 187 amdgpu_ras_set_err_poison(dev->adev, AMDGPU_RAS_BLOCK__GFX); 188 break; 189 case SOC15_IH_CLIENTID_VMC: 190 case SOC15_IH_CLIENTID_VMC1: 191 block = AMDGPU_RAS_BLOCK__MMHUB; 192 reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; 193 break; 194 case SOC15_IH_CLIENTID_SDMA0: 195 case SOC15_IH_CLIENTID_SDMA1: 196 case SOC15_IH_CLIENTID_SDMA2: 197 case SOC15_IH_CLIENTID_SDMA3: 198 case SOC15_IH_CLIENTID_SDMA4: 199 block = AMDGPU_RAS_BLOCK__SDMA; 200 if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2)) { 201 /* driver mode-2 for gfx poison is only supported by 202 * pmfw 0x00557300 and onwards */ 203 if (dev->adev->pm.fw_version < 0x00557300) 204 reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; 205 else 206 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 207 } else if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 208 /* driver mode-2 for gfx poison is only supported by 209 * pmfw 0x05550C00 and onwards */ 210 if (dev->adev->pm.fw_version < 0x05550C00) 211 reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; 212 else 213 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 214 } else { 215 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 216 } 217 amdgpu_ras_set_err_poison(dev->adev, AMDGPU_RAS_BLOCK__SDMA); 218 break; 219 default: 220 dev_warn(dev->adev->dev, 221 "client %d does not support poison consumption\n", client_id); 222 return; 223 } 224 225 ret = amdgpu_ras_mark_ras_event(dev->adev, type); 226 if (ret) 227 return; 228 229 kfd_signal_poison_consumed_event(dev, pasid); 230 231 event_id = amdgpu_ras_acquire_event_id(dev->adev, type); 232 233 RAS_EVENT_LOG(dev->adev, event_id, 234 "poison is consumed by client %d, kick off gpu reset flow\n", client_id); 235 236 amdgpu_amdkfd_ras_pasid_poison_consumption_handler(dev->adev, 237 block, pasid, NULL, NULL, reset); 238 } 239 240 static bool context_id_expected(struct kfd_dev *dev) 241 { 242 switch (KFD_GC_VERSION(dev)) { 243 case IP_VERSION(9, 0, 1): 244 return dev->mec_fw_version >= 0x817a; 245 case IP_VERSION(9, 1, 0): 246 case IP_VERSION(9, 2, 1): 247 case IP_VERSION(9, 2, 2): 248 case IP_VERSION(9, 3, 0): 249 case IP_VERSION(9, 4, 0): 250 return dev->mec_fw_version >= 0x17a; 251 default: 252 /* Other GFXv9 and later GPUs always sent valid context IDs 253 * on legitimate events 254 */ 255 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 1); 256 } 257 } 258 259 static bool event_interrupt_isr_v9(struct kfd_node *dev, 260 const uint32_t *ih_ring_entry, 261 uint32_t *patched_ihre, 262 bool *patched_flag) 263 { 264 uint16_t source_id, client_id, pasid, vmid; 265 const uint32_t *data = ih_ring_entry; 266 267 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 268 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 269 270 /* Only handle interrupts from KFD VMIDs */ 271 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 272 if (!KFD_IRQ_IS_FENCE(client_id, source_id) && 273 (vmid < dev->vm_info.first_vmid_kfd || 274 vmid > dev->vm_info.last_vmid_kfd)) 275 return false; 276 277 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 278 279 /* Only handle clients we care about */ 280 if (client_id != SOC15_IH_CLIENTID_GRBM_CP && 281 client_id != SOC15_IH_CLIENTID_SDMA0 && 282 client_id != SOC15_IH_CLIENTID_SDMA1 && 283 client_id != SOC15_IH_CLIENTID_SDMA2 && 284 client_id != SOC15_IH_CLIENTID_SDMA3 && 285 client_id != SOC15_IH_CLIENTID_SDMA4 && 286 client_id != SOC15_IH_CLIENTID_SDMA5 && 287 client_id != SOC15_IH_CLIENTID_SDMA6 && 288 client_id != SOC15_IH_CLIENTID_SDMA7 && 289 client_id != SOC15_IH_CLIENTID_VMC && 290 client_id != SOC15_IH_CLIENTID_VMC1 && 291 client_id != SOC15_IH_CLIENTID_UTCL2 && 292 client_id != SOC15_IH_CLIENTID_SE0SH && 293 client_id != SOC15_IH_CLIENTID_SE1SH && 294 client_id != SOC15_IH_CLIENTID_SE2SH && 295 client_id != SOC15_IH_CLIENTID_SE3SH && 296 !KFD_IRQ_IS_FENCE(client_id, source_id)) 297 return false; 298 299 /* This is a known issue for gfx9. Under non HWS, pasid is not set 300 * in the interrupt payload, so we need to find out the pasid on our 301 * own. 302 */ 303 if (!pasid && dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 304 const uint32_t pasid_mask = 0xffff; 305 306 *patched_flag = true; 307 memcpy(patched_ihre, ih_ring_entry, 308 dev->kfd->device_info.ih_ring_entry_size); 309 310 pasid = dev->dqm->vmid_pasid[vmid]; 311 312 /* Patch the pasid field */ 313 patched_ihre[3] = cpu_to_le32((le32_to_cpu(patched_ihre[3]) 314 & ~pasid_mask) | pasid); 315 } 316 317 dev_dbg(dev->adev->dev, 318 "client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n", 319 client_id, source_id, vmid, pasid); 320 dev_dbg(dev->adev->dev, "%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n", 321 data[0], data[1], data[2], data[3], data[4], data[5], data[6], 322 data[7]); 323 324 /* If there is no valid PASID, it's likely a bug */ 325 if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt")) 326 return false; 327 328 /* Workaround CP firmware sending bogus signals with 0 context_id. 329 * Those can be safely ignored on hardware and firmware versions that 330 * include a valid context_id on legitimate signals. This avoids the 331 * slow path in kfd_signal_event_interrupt that scans all event slots 332 * for signaled events. 333 */ 334 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) { 335 uint32_t context_id = 336 SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); 337 338 if (context_id == 0 && context_id_expected(dev->kfd)) 339 return false; 340 } 341 342 /* Interrupt types we care about: various signals and faults. 343 * They will be forwarded to a work queue (see below). 344 */ 345 return source_id == SOC15_INTSRC_CP_END_OF_PIPE || 346 source_id == SOC15_INTSRC_SDMA_TRAP || 347 source_id == SOC15_INTSRC_SDMA_ECC || 348 source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG || 349 source_id == SOC15_INTSRC_CP_BAD_OPCODE || 350 KFD_IRQ_IS_FENCE(client_id, source_id) || 351 ((client_id == SOC15_IH_CLIENTID_VMC || 352 client_id == SOC15_IH_CLIENTID_VMC1 || 353 client_id == SOC15_IH_CLIENTID_UTCL2) && 354 !amdgpu_no_queue_eviction_on_vm_fault); 355 } 356 357 static void event_interrupt_wq_v9(struct kfd_node *dev, 358 const uint32_t *ih_ring_entry) 359 { 360 uint16_t source_id, client_id, pasid, vmid; 361 uint32_t context_id0, context_id1; 362 uint32_t sq_intr_err, sq_int_data, encoding; 363 364 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 365 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 366 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 367 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 368 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); 369 context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry); 370 371 if (client_id == SOC15_IH_CLIENTID_GRBM_CP || 372 client_id == SOC15_IH_CLIENTID_SE0SH || 373 client_id == SOC15_IH_CLIENTID_SE1SH || 374 client_id == SOC15_IH_CLIENTID_SE2SH || 375 client_id == SOC15_IH_CLIENTID_SE3SH) { 376 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) 377 kfd_signal_event_interrupt(pasid, context_id0, 32); 378 else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { 379 sq_int_data = KFD_CONTEXT_ID_GET_SQ_INT_DATA(context_id0, context_id1); 380 encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); 381 switch (encoding) { 382 case SQ_INTERRUPT_WORD_ENCODING_AUTO: 383 dev_dbg_ratelimited( 384 dev->adev->dev, 385 "sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n", 386 REG_GET_FIELD( 387 context_id0, 388 SQ_INTERRUPT_WORD_AUTO_CTXID, 389 SE_ID), 390 REG_GET_FIELD( 391 context_id0, 392 SQ_INTERRUPT_WORD_AUTO_CTXID, 393 THREAD_TRACE), 394 REG_GET_FIELD( 395 context_id0, 396 SQ_INTERRUPT_WORD_AUTO_CTXID, 397 WLT), 398 REG_GET_FIELD( 399 context_id0, 400 SQ_INTERRUPT_WORD_AUTO_CTXID, 401 THREAD_TRACE_BUF_FULL), 402 REG_GET_FIELD( 403 context_id0, 404 SQ_INTERRUPT_WORD_AUTO_CTXID, 405 REG_TIMESTAMP), 406 REG_GET_FIELD( 407 context_id0, 408 SQ_INTERRUPT_WORD_AUTO_CTXID, 409 CMD_TIMESTAMP), 410 REG_GET_FIELD( 411 context_id0, 412 SQ_INTERRUPT_WORD_AUTO_CTXID, 413 HOST_CMD_OVERFLOW), 414 REG_GET_FIELD( 415 context_id0, 416 SQ_INTERRUPT_WORD_AUTO_CTXID, 417 HOST_REG_OVERFLOW), 418 REG_GET_FIELD( 419 context_id0, 420 SQ_INTERRUPT_WORD_AUTO_CTXID, 421 IMMED_OVERFLOW), 422 REG_GET_FIELD( 423 context_id0, 424 SQ_INTERRUPT_WORD_AUTO_CTXID, 425 THREAD_TRACE_UTC_ERROR)); 426 break; 427 case SQ_INTERRUPT_WORD_ENCODING_INST: 428 dev_dbg_ratelimited( 429 dev->adev->dev, 430 "sq_intr: inst, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, intr_data 0x%x\n", 431 REG_GET_FIELD( 432 context_id0, 433 SQ_INTERRUPT_WORD_WAVE_CTXID, 434 SE_ID), 435 REG_GET_FIELD( 436 context_id0, 437 SQ_INTERRUPT_WORD_WAVE_CTXID, 438 DATA), 439 REG_GET_FIELD( 440 context_id0, 441 SQ_INTERRUPT_WORD_WAVE_CTXID, 442 SH_ID), 443 REG_GET_FIELD( 444 context_id0, 445 SQ_INTERRUPT_WORD_WAVE_CTXID, 446 PRIV), 447 REG_GET_FIELD( 448 context_id0, 449 SQ_INTERRUPT_WORD_WAVE_CTXID, 450 WAVE_ID), 451 REG_GET_FIELD( 452 context_id0, 453 SQ_INTERRUPT_WORD_WAVE_CTXID, 454 SIMD_ID), 455 REG_GET_FIELD( 456 context_id0, 457 SQ_INTERRUPT_WORD_WAVE_CTXID, 458 CU_ID), 459 sq_int_data); 460 if (context_id0 & SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK) { 461 if (kfd_set_dbg_ev_from_interrupt(dev, pasid, 462 KFD_DEBUG_DOORBELL_ID(sq_int_data), 463 KFD_DEBUG_TRAP_CODE(sq_int_data), 464 NULL, 0)) 465 return; 466 } 467 break; 468 case SQ_INTERRUPT_WORD_ENCODING_ERROR: 469 sq_intr_err = REG_GET_FIELD(sq_int_data, KFD_SQ_INT_DATA, ERR_TYPE); 470 dev_warn_ratelimited( 471 dev->adev->dev, 472 "sq_intr: error, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, err_type %d\n", 473 REG_GET_FIELD( 474 context_id0, 475 SQ_INTERRUPT_WORD_WAVE_CTXID, 476 SE_ID), 477 REG_GET_FIELD( 478 context_id0, 479 SQ_INTERRUPT_WORD_WAVE_CTXID, 480 DATA), 481 REG_GET_FIELD( 482 context_id0, 483 SQ_INTERRUPT_WORD_WAVE_CTXID, 484 SH_ID), 485 REG_GET_FIELD( 486 context_id0, 487 SQ_INTERRUPT_WORD_WAVE_CTXID, 488 PRIV), 489 REG_GET_FIELD( 490 context_id0, 491 SQ_INTERRUPT_WORD_WAVE_CTXID, 492 WAVE_ID), 493 REG_GET_FIELD( 494 context_id0, 495 SQ_INTERRUPT_WORD_WAVE_CTXID, 496 SIMD_ID), 497 REG_GET_FIELD( 498 context_id0, 499 SQ_INTERRUPT_WORD_WAVE_CTXID, 500 CU_ID), 501 sq_intr_err); 502 if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST && 503 sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) { 504 event_interrupt_poison_consumption_v9(dev, pasid, client_id); 505 return; 506 } 507 break; 508 default: 509 break; 510 } 511 kfd_signal_event_interrupt(pasid, sq_int_data, 24); 512 } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && 513 KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) { 514 kfd_set_dbg_ev_from_interrupt(dev, pasid, 515 KFD_DEBUG_DOORBELL_ID(context_id0), 516 KFD_EC_MASK(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0)), 517 NULL, 0); 518 } 519 } else if (client_id == SOC15_IH_CLIENTID_SDMA0 || 520 client_id == SOC15_IH_CLIENTID_SDMA1 || 521 client_id == SOC15_IH_CLIENTID_SDMA2 || 522 client_id == SOC15_IH_CLIENTID_SDMA3 || 523 client_id == SOC15_IH_CLIENTID_SDMA4 || 524 client_id == SOC15_IH_CLIENTID_SDMA5 || 525 client_id == SOC15_IH_CLIENTID_SDMA6 || 526 client_id == SOC15_IH_CLIENTID_SDMA7) { 527 if (source_id == SOC15_INTSRC_SDMA_TRAP) { 528 kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); 529 } else if (source_id == SOC15_INTSRC_SDMA_ECC) { 530 event_interrupt_poison_consumption_v9(dev, pasid, client_id); 531 return; 532 } 533 } else if (client_id == SOC15_IH_CLIENTID_VMC || 534 client_id == SOC15_IH_CLIENTID_VMC1 || 535 client_id == SOC15_IH_CLIENTID_UTCL2) { 536 struct kfd_vm_fault_info info = {0}; 537 uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); 538 struct kfd_hsa_memory_exception_data exception_data; 539 540 if (source_id == SOC15_INTSRC_VMC_UTCL2_POISON) { 541 event_interrupt_poison_consumption_v9(dev, pasid, client_id); 542 return; 543 } 544 545 info.vmid = vmid; 546 info.mc_id = client_id; 547 info.page_addr = ih_ring_entry[4] | 548 (uint64_t)(ih_ring_entry[5] & 0xf) << 32; 549 info.prot_valid = ring_id & 0x08; 550 info.prot_read = ring_id & 0x10; 551 info.prot_write = ring_id & 0x20; 552 553 memset(&exception_data, 0, sizeof(exception_data)); 554 exception_data.gpu_id = dev->id; 555 exception_data.va = (info.page_addr) << PAGE_SHIFT; 556 exception_data.failure.NotPresent = info.prot_valid ? 1 : 0; 557 exception_data.failure.NoExecute = info.prot_exec ? 1 : 0; 558 exception_data.failure.ReadOnly = info.prot_write ? 1 : 0; 559 exception_data.failure.imprecise = 0; 560 561 kfd_set_dbg_ev_from_interrupt(dev, 562 pasid, 563 -1, 564 KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION), 565 &exception_data, 566 sizeof(exception_data)); 567 kfd_smi_event_update_vmfault(dev, pasid); 568 } else if (KFD_IRQ_IS_FENCE(client_id, source_id)) { 569 kfd_process_close_interrupt_drain(pasid); 570 } 571 } 572 573 static bool event_interrupt_isr_v9_4_3(struct kfd_node *node, 574 const uint32_t *ih_ring_entry, 575 uint32_t *patched_ihre, 576 bool *patched_flag) 577 { 578 uint16_t node_id, vmid; 579 580 /* 581 * For GFX 9.4.3, process the interrupt if: 582 * - NodeID field in IH entry matches the corresponding bit 583 * set in interrupt_bitmap Bits 0-15. 584 * OR 585 * - If partition mode is CPX and interrupt came from 586 * Node_id 0,4,8,12, then check if the Bit (16 + client id) 587 * is set in interrupt bitmap Bits 16-31. 588 */ 589 node_id = SOC15_NODEID_FROM_IH_ENTRY(ih_ring_entry); 590 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 591 if (kfd_irq_is_from_node(node, node_id, vmid)) 592 return event_interrupt_isr_v9(node, ih_ring_entry, 593 patched_ihre, patched_flag); 594 return false; 595 } 596 597 const struct kfd_event_interrupt_class event_interrupt_class_v9 = { 598 .interrupt_isr = event_interrupt_isr_v9, 599 .interrupt_wq = event_interrupt_wq_v9, 600 }; 601 602 const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3 = { 603 .interrupt_isr = event_interrupt_isr_v9_4_3, 604 .interrupt_wq = event_interrupt_wq_v9, 605 }; 606