1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "kfd_priv.h" 25 #include "kfd_events.h" 26 #include "kfd_debug.h" 27 #include "soc15_int.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_smi_events.h" 30 31 /* 32 * GFX9 SQ Interrupts 33 * 34 * There are 3 encoding types of interrupts sourced from SQ sent as a 44-bit 35 * packet to the Interrupt Handler: 36 * Auto - Generated by the SQG (various cmd overflows, timestamps etc) 37 * Wave - Generated by S_SENDMSG through a shader program 38 * Error - HW generated errors (Illegal instructions, Memviols, EDC etc) 39 * 40 * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus 41 * 4-bits for VMID (SOC15_VMID_FROM_IH_ENTRY) as such: 42 * 43 * - context_id0[27:26] 44 * Encoding type (0 = Auto, 1 = Wave, 2 = Error) 45 * 46 * - context_id0[13] 47 * PRIV bit indicates that Wave S_SEND or error occurred within trap 48 * 49 * - {context_id1[7:0],context_id0[31:28],context_id0[11:0]} 50 * 24-bit data with the following layout per encoding type: 51 * Auto - only context_id0[8:0] is used, which reports various interrupts 52 * generated by SQG. The rest is 0. 53 * Wave - user data sent from m0 via S_SENDMSG 54 * Error - Error type (context_id1[7:4]), Error Details (rest of bits) 55 * 56 * The other context_id bits show coordinates (SE/SH/CU/SIMD/WAVE) for wave 57 * S_SENDMSG and Errors. These are 0 for Auto. 58 */ 59 60 enum SQ_INTERRUPT_WORD_ENCODING { 61 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, 62 SQ_INTERRUPT_WORD_ENCODING_INST, 63 SQ_INTERRUPT_WORD_ENCODING_ERROR, 64 }; 65 66 enum SQ_INTERRUPT_ERROR_TYPE { 67 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0, 68 SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST, 69 SQ_INTERRUPT_ERROR_TYPE_MEMVIOL, 70 SQ_INTERRUPT_ERROR_TYPE_EDC_FED, 71 }; 72 73 /* SQ_INTERRUPT_WORD_AUTO_CTXID */ 74 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0 75 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 1 76 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 2 77 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 3 78 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 4 79 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 5 80 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 6 81 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 7 82 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 8 83 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 24 84 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 26 85 86 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x00000001 87 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x00000002 88 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x00000004 89 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x00000008 90 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x00000010 91 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x00000020 92 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x00000040 93 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x00000080 94 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x00000100 95 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x03000000 96 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0x0c000000 97 98 /* SQ_INTERRUPT_WORD_WAVE_CTXID */ 99 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0 100 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 12 101 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 13 102 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 14 103 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 18 104 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 20 105 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 24 106 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 26 107 108 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x00000fff 109 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x00001000 110 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x00002000 111 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x0003c000 112 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x000c0000 113 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x00f00000 114 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x03000000 115 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0x0c000000 116 117 /* GFX9 SQ interrupt 24-bit data from context_id<0,1> */ 118 #define KFD_CONTEXT_ID_GET_SQ_INT_DATA(ctx0, ctx1) \ 119 ((ctx0 & 0xfff) | ((ctx0 >> 16) & 0xf000) | ((ctx1 << 16) & 0xff0000)) 120 121 #define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000 122 #define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20 123 124 /* 125 * The debugger will send user data(m0) with PRIV=1 to indicate it requires 126 * notification from the KFD with the following queue id (DOORBELL_ID) and 127 * trap code (TRAP_CODE). 128 */ 129 #define KFD_INT_DATA_DEBUG_DOORBELL_MASK 0x0003ff 130 #define KFD_INT_DATA_DEBUG_TRAP_CODE_SHIFT 10 131 #define KFD_INT_DATA_DEBUG_TRAP_CODE_MASK 0x07fc00 132 #define KFD_DEBUG_DOORBELL_ID(sq_int_data) ((sq_int_data) & \ 133 KFD_INT_DATA_DEBUG_DOORBELL_MASK) 134 #define KFD_DEBUG_TRAP_CODE(sq_int_data) (((sq_int_data) & \ 135 KFD_INT_DATA_DEBUG_TRAP_CODE_MASK) \ 136 >> KFD_INT_DATA_DEBUG_TRAP_CODE_SHIFT) 137 #define KFD_DEBUG_CP_BAD_OP_ECODE_MASK 0x3fffc00 138 #define KFD_DEBUG_CP_BAD_OP_ECODE_SHIFT 10 139 #define KFD_DEBUG_CP_BAD_OP_ECODE(ctxid0) (((ctxid0) & \ 140 KFD_DEBUG_CP_BAD_OP_ECODE_MASK) \ 141 >> KFD_DEBUG_CP_BAD_OP_ECODE_SHIFT) 142 143 static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, 144 uint16_t pasid, uint16_t client_id) 145 { 146 enum amdgpu_ras_block block = 0; 147 int old_poison; 148 uint32_t reset = 0; 149 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); 150 151 if (!p) 152 return; 153 154 /* all queues of a process will be unmapped in one time */ 155 old_poison = atomic_cmpxchg(&p->poison, 0, 1); 156 kfd_unref_process(p); 157 if (old_poison) 158 return; 159 160 switch (client_id) { 161 case SOC15_IH_CLIENTID_SE0SH: 162 case SOC15_IH_CLIENTID_SE1SH: 163 case SOC15_IH_CLIENTID_SE2SH: 164 case SOC15_IH_CLIENTID_SE3SH: 165 case SOC15_IH_CLIENTID_UTCL2: 166 block = AMDGPU_RAS_BLOCK__GFX; 167 if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 168 reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; 169 else 170 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 171 break; 172 case SOC15_IH_CLIENTID_VMC: 173 case SOC15_IH_CLIENTID_VMC1: 174 block = AMDGPU_RAS_BLOCK__MMHUB; 175 reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; 176 break; 177 case SOC15_IH_CLIENTID_SDMA0: 178 case SOC15_IH_CLIENTID_SDMA1: 179 case SOC15_IH_CLIENTID_SDMA2: 180 case SOC15_IH_CLIENTID_SDMA3: 181 case SOC15_IH_CLIENTID_SDMA4: 182 block = AMDGPU_RAS_BLOCK__SDMA; 183 if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 184 reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; 185 else 186 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 187 break; 188 default: 189 dev_warn(dev->adev->dev, 190 "client %d does not support poison consumption\n", client_id); 191 return; 192 } 193 194 kfd_signal_poison_consumed_event(dev, pasid); 195 196 dev_warn(dev->adev->dev, 197 "poison is consumed by client %d, kick off gpu reset flow\n", client_id); 198 199 amdgpu_amdkfd_ras_pasid_poison_consumption_handler(dev->adev, 200 block, pasid, NULL, NULL, reset); 201 } 202 203 static bool context_id_expected(struct kfd_dev *dev) 204 { 205 switch (KFD_GC_VERSION(dev)) { 206 case IP_VERSION(9, 0, 1): 207 return dev->mec_fw_version >= 0x817a; 208 case IP_VERSION(9, 1, 0): 209 case IP_VERSION(9, 2, 1): 210 case IP_VERSION(9, 2, 2): 211 case IP_VERSION(9, 3, 0): 212 case IP_VERSION(9, 4, 0): 213 return dev->mec_fw_version >= 0x17a; 214 default: 215 /* Other GFXv9 and later GPUs always sent valid context IDs 216 * on legitimate events 217 */ 218 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 1); 219 } 220 } 221 222 static bool event_interrupt_isr_v9(struct kfd_node *dev, 223 const uint32_t *ih_ring_entry, 224 uint32_t *patched_ihre, 225 bool *patched_flag) 226 { 227 uint16_t source_id, client_id, pasid, vmid; 228 const uint32_t *data = ih_ring_entry; 229 230 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 231 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 232 233 /* Only handle interrupts from KFD VMIDs */ 234 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 235 if (!KFD_IRQ_IS_FENCE(client_id, source_id) && 236 (vmid < dev->vm_info.first_vmid_kfd || 237 vmid > dev->vm_info.last_vmid_kfd)) 238 return false; 239 240 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 241 242 /* Only handle clients we care about */ 243 if (client_id != SOC15_IH_CLIENTID_GRBM_CP && 244 client_id != SOC15_IH_CLIENTID_SDMA0 && 245 client_id != SOC15_IH_CLIENTID_SDMA1 && 246 client_id != SOC15_IH_CLIENTID_SDMA2 && 247 client_id != SOC15_IH_CLIENTID_SDMA3 && 248 client_id != SOC15_IH_CLIENTID_SDMA4 && 249 client_id != SOC15_IH_CLIENTID_SDMA5 && 250 client_id != SOC15_IH_CLIENTID_SDMA6 && 251 client_id != SOC15_IH_CLIENTID_SDMA7 && 252 client_id != SOC15_IH_CLIENTID_VMC && 253 client_id != SOC15_IH_CLIENTID_VMC1 && 254 client_id != SOC15_IH_CLIENTID_UTCL2 && 255 client_id != SOC15_IH_CLIENTID_SE0SH && 256 client_id != SOC15_IH_CLIENTID_SE1SH && 257 client_id != SOC15_IH_CLIENTID_SE2SH && 258 client_id != SOC15_IH_CLIENTID_SE3SH && 259 !KFD_IRQ_IS_FENCE(client_id, source_id)) 260 return false; 261 262 /* This is a known issue for gfx9. Under non HWS, pasid is not set 263 * in the interrupt payload, so we need to find out the pasid on our 264 * own. 265 */ 266 if (!pasid && dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 267 const uint32_t pasid_mask = 0xffff; 268 269 *patched_flag = true; 270 memcpy(patched_ihre, ih_ring_entry, 271 dev->kfd->device_info.ih_ring_entry_size); 272 273 pasid = dev->dqm->vmid_pasid[vmid]; 274 275 /* Patch the pasid field */ 276 patched_ihre[3] = cpu_to_le32((le32_to_cpu(patched_ihre[3]) 277 & ~pasid_mask) | pasid); 278 } 279 280 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n", 281 client_id, source_id, vmid, pasid); 282 pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n", 283 data[0], data[1], data[2], data[3], 284 data[4], data[5], data[6], data[7]); 285 286 /* If there is no valid PASID, it's likely a bug */ 287 if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt")) 288 return false; 289 290 /* Workaround CP firmware sending bogus signals with 0 context_id. 291 * Those can be safely ignored on hardware and firmware versions that 292 * include a valid context_id on legitimate signals. This avoids the 293 * slow path in kfd_signal_event_interrupt that scans all event slots 294 * for signaled events. 295 */ 296 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) { 297 uint32_t context_id = 298 SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); 299 300 if (context_id == 0 && context_id_expected(dev->kfd)) 301 return false; 302 } 303 304 /* Interrupt types we care about: various signals and faults. 305 * They will be forwarded to a work queue (see below). 306 */ 307 return source_id == SOC15_INTSRC_CP_END_OF_PIPE || 308 source_id == SOC15_INTSRC_SDMA_TRAP || 309 source_id == SOC15_INTSRC_SDMA_ECC || 310 source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG || 311 source_id == SOC15_INTSRC_CP_BAD_OPCODE || 312 KFD_IRQ_IS_FENCE(client_id, source_id) || 313 ((client_id == SOC15_IH_CLIENTID_VMC || 314 client_id == SOC15_IH_CLIENTID_VMC1 || 315 client_id == SOC15_IH_CLIENTID_UTCL2) && 316 !amdgpu_no_queue_eviction_on_vm_fault); 317 } 318 319 static void event_interrupt_wq_v9(struct kfd_node *dev, 320 const uint32_t *ih_ring_entry) 321 { 322 uint16_t source_id, client_id, pasid, vmid; 323 uint32_t context_id0, context_id1; 324 uint32_t sq_intr_err, sq_int_data, encoding; 325 326 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 327 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 328 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 329 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 330 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); 331 context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry); 332 333 if (client_id == SOC15_IH_CLIENTID_GRBM_CP || 334 client_id == SOC15_IH_CLIENTID_SE0SH || 335 client_id == SOC15_IH_CLIENTID_SE1SH || 336 client_id == SOC15_IH_CLIENTID_SE2SH || 337 client_id == SOC15_IH_CLIENTID_SE3SH) { 338 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) 339 kfd_signal_event_interrupt(pasid, context_id0, 32); 340 else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { 341 sq_int_data = KFD_CONTEXT_ID_GET_SQ_INT_DATA(context_id0, context_id1); 342 encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); 343 switch (encoding) { 344 case SQ_INTERRUPT_WORD_ENCODING_AUTO: 345 pr_debug_ratelimited( 346 "sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n", 347 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID), 348 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE), 349 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT), 350 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_BUF_FULL), 351 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, REG_TIMESTAMP), 352 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, CMD_TIMESTAMP), 353 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_CMD_OVERFLOW), 354 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_REG_OVERFLOW), 355 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, IMMED_OVERFLOW), 356 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_UTC_ERROR)); 357 break; 358 case SQ_INTERRUPT_WORD_ENCODING_INST: 359 pr_debug_ratelimited("sq_intr: inst, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, intr_data 0x%x\n", 360 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 361 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 362 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 363 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 364 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 365 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 366 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 367 sq_int_data); 368 if (context_id0 & SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK) { 369 if (kfd_set_dbg_ev_from_interrupt(dev, pasid, 370 KFD_DEBUG_DOORBELL_ID(sq_int_data), 371 KFD_DEBUG_TRAP_CODE(sq_int_data), 372 NULL, 0)) 373 return; 374 } 375 break; 376 case SQ_INTERRUPT_WORD_ENCODING_ERROR: 377 sq_intr_err = REG_GET_FIELD(sq_int_data, KFD_SQ_INT_DATA, ERR_TYPE); 378 pr_warn_ratelimited("sq_intr: error, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, err_type %d\n", 379 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 380 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 381 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 382 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 383 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 384 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 385 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 386 sq_intr_err); 387 if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST && 388 sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) { 389 event_interrupt_poison_consumption_v9(dev, pasid, client_id); 390 return; 391 } 392 break; 393 default: 394 break; 395 } 396 kfd_signal_event_interrupt(pasid, sq_int_data, 24); 397 } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && 398 KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) { 399 kfd_set_dbg_ev_from_interrupt(dev, pasid, 400 KFD_DEBUG_DOORBELL_ID(context_id0), 401 KFD_EC_MASK(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0)), 402 NULL, 0); 403 } 404 } else if (client_id == SOC15_IH_CLIENTID_SDMA0 || 405 client_id == SOC15_IH_CLIENTID_SDMA1 || 406 client_id == SOC15_IH_CLIENTID_SDMA2 || 407 client_id == SOC15_IH_CLIENTID_SDMA3 || 408 client_id == SOC15_IH_CLIENTID_SDMA4 || 409 client_id == SOC15_IH_CLIENTID_SDMA5 || 410 client_id == SOC15_IH_CLIENTID_SDMA6 || 411 client_id == SOC15_IH_CLIENTID_SDMA7) { 412 if (source_id == SOC15_INTSRC_SDMA_TRAP) { 413 kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); 414 } else if (source_id == SOC15_INTSRC_SDMA_ECC) { 415 event_interrupt_poison_consumption_v9(dev, pasid, client_id); 416 return; 417 } 418 } else if (client_id == SOC15_IH_CLIENTID_VMC || 419 client_id == SOC15_IH_CLIENTID_VMC1 || 420 client_id == SOC15_IH_CLIENTID_UTCL2) { 421 struct kfd_vm_fault_info info = {0}; 422 uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); 423 uint32_t node_id = SOC15_NODEID_FROM_IH_ENTRY(ih_ring_entry); 424 uint32_t vmid_type = SOC15_VMID_TYPE_FROM_IH_ENTRY(ih_ring_entry); 425 int hub_inst = 0; 426 struct kfd_hsa_memory_exception_data exception_data; 427 428 /* gfxhub */ 429 if (!vmid_type && dev->adev->gfx.funcs->ih_node_to_logical_xcc) { 430 hub_inst = dev->adev->gfx.funcs->ih_node_to_logical_xcc(dev->adev, 431 node_id); 432 if (hub_inst < 0) 433 hub_inst = 0; 434 } 435 436 /* mmhub */ 437 if (vmid_type && client_id == SOC15_IH_CLIENTID_VMC) 438 hub_inst = node_id / 4; 439 440 if (amdgpu_amdkfd_ras_query_utcl2_poison_status(dev->adev, 441 hub_inst, vmid_type)) { 442 event_interrupt_poison_consumption_v9(dev, pasid, client_id); 443 return; 444 } 445 446 info.vmid = vmid; 447 info.mc_id = client_id; 448 info.page_addr = ih_ring_entry[4] | 449 (uint64_t)(ih_ring_entry[5] & 0xf) << 32; 450 info.prot_valid = ring_id & 0x08; 451 info.prot_read = ring_id & 0x10; 452 info.prot_write = ring_id & 0x20; 453 454 memset(&exception_data, 0, sizeof(exception_data)); 455 exception_data.gpu_id = dev->id; 456 exception_data.va = (info.page_addr) << PAGE_SHIFT; 457 exception_data.failure.NotPresent = info.prot_valid ? 1 : 0; 458 exception_data.failure.NoExecute = info.prot_exec ? 1 : 0; 459 exception_data.failure.ReadOnly = info.prot_write ? 1 : 0; 460 exception_data.failure.imprecise = 0; 461 462 kfd_set_dbg_ev_from_interrupt(dev, 463 pasid, 464 -1, 465 KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION), 466 &exception_data, 467 sizeof(exception_data)); 468 kfd_smi_event_update_vmfault(dev, pasid); 469 } else if (KFD_IRQ_IS_FENCE(client_id, source_id)) { 470 kfd_process_close_interrupt_drain(pasid); 471 } 472 } 473 474 static bool event_interrupt_isr_v9_4_3(struct kfd_node *node, 475 const uint32_t *ih_ring_entry, 476 uint32_t *patched_ihre, 477 bool *patched_flag) 478 { 479 uint16_t node_id, vmid; 480 481 /* 482 * For GFX 9.4.3, process the interrupt if: 483 * - NodeID field in IH entry matches the corresponding bit 484 * set in interrupt_bitmap Bits 0-15. 485 * OR 486 * - If partition mode is CPX and interrupt came from 487 * Node_id 0,4,8,12, then check if the Bit (16 + client id) 488 * is set in interrupt bitmap Bits 16-31. 489 */ 490 node_id = SOC15_NODEID_FROM_IH_ENTRY(ih_ring_entry); 491 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 492 if (kfd_irq_is_from_node(node, node_id, vmid)) 493 return event_interrupt_isr_v9(node, ih_ring_entry, 494 patched_ihre, patched_flag); 495 return false; 496 } 497 498 const struct kfd_event_interrupt_class event_interrupt_class_v9 = { 499 .interrupt_isr = event_interrupt_isr_v9, 500 .interrupt_wq = event_interrupt_wq_v9, 501 }; 502 503 const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3 = { 504 .interrupt_isr = event_interrupt_isr_v9_4_3, 505 .interrupt_wq = event_interrupt_wq_v9, 506 }; 507