1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/ratelimit.h> 26 #include <linux/printk.h> 27 #include <linux/slab.h> 28 #include <linux/list.h> 29 #include <linux/types.h> 30 #include <linux/bitops.h> 31 #include <linux/sched.h> 32 #include "kfd_priv.h" 33 #include "kfd_device_queue_manager.h" 34 #include "kfd_mqd_manager.h" 35 #include "cik_regs.h" 36 #include "kfd_kernel_queue.h" 37 #include "amdgpu_amdkfd.h" 38 #include "amdgpu_reset.h" 39 #include "amdgpu_sdma.h" 40 #include "mes_v11_api_def.h" 41 #include "kfd_debug.h" 42 43 /* Size of the per-pipe EOP queue */ 44 #define CIK_HPD_EOP_BYTES_LOG2 11 45 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) 46 /* See unmap_queues_cpsch() */ 47 #define USE_DEFAULT_GRACE_PERIOD 0xffffffff 48 49 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, 50 u32 pasid, unsigned int vmid); 51 52 static int execute_queues_cpsch(struct device_queue_manager *dqm, 53 enum kfd_unmap_queues_filter filter, 54 uint32_t filter_param, 55 uint32_t grace_period); 56 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 57 enum kfd_unmap_queues_filter filter, 58 uint32_t filter_param, 59 uint32_t grace_period, 60 bool reset); 61 62 static int map_queues_cpsch(struct device_queue_manager *dqm); 63 64 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 65 struct queue *q); 66 67 static inline void deallocate_hqd(struct device_queue_manager *dqm, 68 struct queue *q); 69 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q); 70 static int allocate_sdma_queue(struct device_queue_manager *dqm, 71 struct queue *q, const uint32_t *restore_sdma_id); 72 73 static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma); 74 75 static inline 76 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) 77 { 78 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI) 79 return KFD_MQD_TYPE_SDMA; 80 return KFD_MQD_TYPE_CP; 81 } 82 83 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) 84 { 85 int i; 86 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec 87 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe; 88 89 /* queue is available for KFD usage if bit is 1 */ 90 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i) 91 if (test_bit(pipe_offset + i, 92 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 93 return true; 94 return false; 95 } 96 97 unsigned int get_cp_queues_num(struct device_queue_manager *dqm) 98 { 99 return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap, 100 AMDGPU_MAX_QUEUES); 101 } 102 103 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) 104 { 105 return dqm->dev->kfd->shared_resources.num_queue_per_pipe; 106 } 107 108 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) 109 { 110 return dqm->dev->kfd->shared_resources.num_pipe_per_mec; 111 } 112 113 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm) 114 { 115 return kfd_get_num_sdma_engines(dqm->dev) + 116 kfd_get_num_xgmi_sdma_engines(dqm->dev); 117 } 118 119 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm) 120 { 121 return kfd_get_num_sdma_engines(dqm->dev) * 122 dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 123 } 124 125 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm) 126 { 127 return kfd_get_num_xgmi_sdma_engines(dqm->dev) * 128 dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 129 } 130 131 static void init_sdma_bitmaps(struct device_queue_manager *dqm) 132 { 133 bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES); 134 bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm)); 135 136 bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES); 137 bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm)); 138 139 /* Mask out the reserved queues */ 140 bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap, 141 dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap, 142 KFD_MAX_SDMA_QUEUES); 143 } 144 145 void program_sh_mem_settings(struct device_queue_manager *dqm, 146 struct qcm_process_device *qpd) 147 { 148 uint32_t xcc_mask = dqm->dev->xcc_mask; 149 int xcc_id; 150 151 for_each_inst(xcc_id, xcc_mask) 152 dqm->dev->kfd2kgd->program_sh_mem_settings( 153 dqm->dev->adev, qpd->vmid, qpd->sh_mem_config, 154 qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit, 155 qpd->sh_mem_bases, xcc_id); 156 } 157 158 static void kfd_hws_hang(struct device_queue_manager *dqm) 159 { 160 struct device_process_node *cur; 161 struct qcm_process_device *qpd; 162 struct queue *q; 163 164 /* Mark all device queues as reset. */ 165 list_for_each_entry(cur, &dqm->queues, list) { 166 qpd = cur->qpd; 167 list_for_each_entry(q, &qpd->queues_list, list) { 168 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 169 170 pdd->has_reset_queue = true; 171 } 172 } 173 174 /* 175 * Issue a GPU reset if HWS is unresponsive 176 */ 177 amdgpu_amdkfd_gpu_reset(dqm->dev->adev); 178 } 179 180 static int convert_to_mes_queue_type(int queue_type) 181 { 182 int mes_queue_type; 183 184 switch (queue_type) { 185 case KFD_QUEUE_TYPE_COMPUTE: 186 mes_queue_type = MES_QUEUE_TYPE_COMPUTE; 187 break; 188 case KFD_QUEUE_TYPE_SDMA: 189 mes_queue_type = MES_QUEUE_TYPE_SDMA; 190 break; 191 default: 192 WARN(1, "Invalid queue type %d", queue_type); 193 mes_queue_type = -EINVAL; 194 break; 195 } 196 197 return mes_queue_type; 198 } 199 200 static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, 201 struct qcm_process_device *qpd) 202 { 203 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 204 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 205 struct mes_add_queue_input queue_input; 206 int r, queue_type; 207 uint64_t wptr_addr_off; 208 209 if (!dqm->sched_running || dqm->sched_halt) 210 return 0; 211 if (!down_read_trylock(&adev->reset_domain->sem)) 212 return -EIO; 213 214 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 215 queue_input.process_id = pdd->pasid; 216 queue_input.page_table_base_addr = qpd->page_table_base; 217 queue_input.process_va_start = 0; 218 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 219 /* MES unit for quantum is 100ns */ 220 queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */ 221 queue_input.process_context_addr = pdd->proc_ctx_gpu_addr; 222 queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */ 223 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 224 queue_input.inprocess_gang_priority = q->properties.priority; 225 queue_input.gang_global_priority_level = 226 AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 227 queue_input.doorbell_offset = q->properties.doorbell_off; 228 queue_input.mqd_addr = q->gart_mqd_addr; 229 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; 230 231 wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1); 232 queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q->properties.wptr_bo) + wptr_addr_off; 233 234 queue_input.is_kfd_process = 1; 235 queue_input.is_aql_queue = (q->properties.format == KFD_QUEUE_FORMAT_AQL); 236 queue_input.queue_size = q->properties.queue_size >> 2; 237 238 queue_input.paging = false; 239 queue_input.tba_addr = qpd->tba_addr; 240 queue_input.tma_addr = qpd->tma_addr; 241 queue_input.trap_en = !kfd_dbg_has_cwsr_workaround(q->device); 242 queue_input.skip_process_ctx_clear = 243 qpd->pqm->process->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED && 244 (qpd->pqm->process->debug_trap_enabled || 245 kfd_dbg_has_ttmps_always_setup(q->device)); 246 247 queue_type = convert_to_mes_queue_type(q->properties.type); 248 if (queue_type < 0) { 249 dev_err(adev->dev, "Queue type not supported with MES, queue:%d\n", 250 q->properties.type); 251 up_read(&adev->reset_domain->sem); 252 return -EINVAL; 253 } 254 queue_input.queue_type = (uint32_t)queue_type; 255 256 queue_input.exclusively_scheduled = q->properties.is_gws; 257 258 amdgpu_mes_lock(&adev->mes); 259 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 260 amdgpu_mes_unlock(&adev->mes); 261 up_read(&adev->reset_domain->sem); 262 if (r) { 263 dev_err(adev->dev, "failed to add hardware queue to MES, doorbell=0x%x\n", 264 q->properties.doorbell_off); 265 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); 266 kfd_hws_hang(dqm); 267 } 268 269 return r; 270 } 271 272 static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, 273 struct qcm_process_device *qpd) 274 { 275 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 276 int r; 277 struct mes_remove_queue_input queue_input; 278 279 if (!dqm->sched_running || dqm->sched_halt) 280 return 0; 281 if (!down_read_trylock(&adev->reset_domain->sem)) 282 return -EIO; 283 284 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 285 queue_input.doorbell_offset = q->properties.doorbell_off; 286 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 287 288 amdgpu_mes_lock(&adev->mes); 289 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 290 amdgpu_mes_unlock(&adev->mes); 291 up_read(&adev->reset_domain->sem); 292 293 if (r) { 294 dev_err(adev->dev, "failed to remove hardware queue from MES, doorbell=0x%x\n", 295 q->properties.doorbell_off); 296 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); 297 kfd_hws_hang(dqm); 298 } 299 300 return r; 301 } 302 303 static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) 304 { 305 struct device_process_node *cur; 306 struct device *dev = dqm->dev->adev->dev; 307 struct qcm_process_device *qpd; 308 struct queue *q; 309 int retval = 0; 310 311 list_for_each_entry(cur, &dqm->queues, list) { 312 qpd = cur->qpd; 313 list_for_each_entry(q, &qpd->queues_list, list) { 314 if (q->properties.is_active) { 315 retval = remove_queue_mes(dqm, q, qpd); 316 if (retval) { 317 dev_err(dev, "%s: Failed to remove queue %d for dev %d", 318 __func__, 319 q->properties.queue_id, 320 dqm->dev->id); 321 return retval; 322 } 323 } 324 } 325 } 326 327 return retval; 328 } 329 330 static int add_all_kfd_queues_mes(struct device_queue_manager *dqm) 331 { 332 struct device_process_node *cur; 333 struct device *dev = dqm->dev->adev->dev; 334 struct qcm_process_device *qpd; 335 struct queue *q; 336 int retval = 0; 337 338 list_for_each_entry(cur, &dqm->queues, list) { 339 qpd = cur->qpd; 340 list_for_each_entry(q, &qpd->queues_list, list) { 341 if (!q->properties.is_active) 342 continue; 343 retval = add_queue_mes(dqm, q, qpd); 344 if (retval) { 345 dev_err(dev, "%s: Failed to add queue %d for dev %d", 346 __func__, 347 q->properties.queue_id, 348 dqm->dev->id); 349 return retval; 350 } 351 } 352 } 353 354 return retval; 355 } 356 357 static int suspend_all_queues_mes(struct device_queue_manager *dqm) 358 { 359 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 360 int r = 0; 361 362 if (!down_read_trylock(&adev->reset_domain->sem)) 363 return -EIO; 364 365 r = amdgpu_mes_suspend(adev); 366 up_read(&adev->reset_domain->sem); 367 368 if (r) { 369 dev_err(adev->dev, "failed to suspend gangs from MES\n"); 370 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); 371 kfd_hws_hang(dqm); 372 } 373 374 return r; 375 } 376 377 static int resume_all_queues_mes(struct device_queue_manager *dqm) 378 { 379 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 380 int r = 0; 381 382 if (!down_read_trylock(&adev->reset_domain->sem)) 383 return -EIO; 384 385 r = amdgpu_mes_resume(adev); 386 up_read(&adev->reset_domain->sem); 387 388 if (r) { 389 dev_err(adev->dev, "failed to resume gangs from MES\n"); 390 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); 391 kfd_hws_hang(dqm); 392 } 393 394 return r; 395 } 396 397 static void increment_queue_count(struct device_queue_manager *dqm, 398 struct qcm_process_device *qpd, 399 struct queue *q) 400 { 401 dqm->active_queue_count++; 402 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 403 q->properties.type == KFD_QUEUE_TYPE_DIQ) 404 dqm->active_cp_queue_count++; 405 406 if (q->properties.is_gws) { 407 dqm->gws_queue_count++; 408 qpd->mapped_gws_queue = true; 409 } 410 } 411 412 static void decrement_queue_count(struct device_queue_manager *dqm, 413 struct qcm_process_device *qpd, 414 struct queue *q) 415 { 416 dqm->active_queue_count--; 417 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 418 q->properties.type == KFD_QUEUE_TYPE_DIQ) 419 dqm->active_cp_queue_count--; 420 421 if (q->properties.is_gws) { 422 dqm->gws_queue_count--; 423 qpd->mapped_gws_queue = false; 424 } 425 } 426 427 /* 428 * Allocate a doorbell ID to this queue. 429 * If doorbell_id is passed in, make sure requested ID is valid then allocate it. 430 */ 431 static int allocate_doorbell(struct qcm_process_device *qpd, 432 struct queue *q, 433 uint32_t const *restore_id) 434 { 435 struct kfd_node *dev = qpd->dqm->dev; 436 437 if (!KFD_IS_SOC15(dev)) { 438 /* On pre-SOC15 chips we need to use the queue ID to 439 * preserve the user mode ABI. 440 */ 441 442 if (restore_id && *restore_id != q->properties.queue_id) 443 return -EINVAL; 444 445 q->doorbell_id = q->properties.queue_id; 446 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 447 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 448 /* For SDMA queues on SOC15 with 8-byte doorbell, use static 449 * doorbell assignments based on the engine and queue id. 450 * The doobell index distance between RLC (2*i) and (2*i+1) 451 * for a SDMA engine is 512. 452 */ 453 454 uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx; 455 456 /* 457 * q->properties.sdma_engine_id corresponds to the virtual 458 * sdma engine number. However, for doorbell allocation, 459 * we need the physical sdma engine id in order to get the 460 * correct doorbell offset. 461 */ 462 uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id * 463 get_num_all_sdma_engines(qpd->dqm) + 464 q->properties.sdma_engine_id] 465 + (q->properties.sdma_queue_id & 1) 466 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET 467 + (q->properties.sdma_queue_id >> 1); 468 469 if (restore_id && *restore_id != valid_id) 470 return -EINVAL; 471 q->doorbell_id = valid_id; 472 } else { 473 /* For CP queues on SOC15 */ 474 if (restore_id) { 475 /* make sure that ID is free */ 476 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap)) 477 return -EINVAL; 478 479 q->doorbell_id = *restore_id; 480 } else { 481 /* or reserve a free doorbell ID */ 482 unsigned int found; 483 484 found = find_first_zero_bit(qpd->doorbell_bitmap, 485 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 486 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 487 pr_debug("No doorbells available"); 488 return -EBUSY; 489 } 490 set_bit(found, qpd->doorbell_bitmap); 491 q->doorbell_id = found; 492 } 493 } 494 495 q->properties.doorbell_off = amdgpu_doorbell_index_on_bar(dev->adev, 496 qpd->proc_doorbells, 497 q->doorbell_id, 498 dev->kfd->device_info.doorbell_size); 499 return 0; 500 } 501 502 static void deallocate_doorbell(struct qcm_process_device *qpd, 503 struct queue *q) 504 { 505 unsigned int old; 506 struct kfd_node *dev = qpd->dqm->dev; 507 508 if (!KFD_IS_SOC15(dev) || 509 q->properties.type == KFD_QUEUE_TYPE_SDMA || 510 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 511 return; 512 513 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap); 514 WARN_ON(!old); 515 } 516 517 static void program_trap_handler_settings(struct device_queue_manager *dqm, 518 struct qcm_process_device *qpd) 519 { 520 uint32_t xcc_mask = dqm->dev->xcc_mask; 521 int xcc_id; 522 523 if (dqm->dev->kfd2kgd->program_trap_handler_settings) 524 for_each_inst(xcc_id, xcc_mask) 525 dqm->dev->kfd2kgd->program_trap_handler_settings( 526 dqm->dev->adev, qpd->vmid, qpd->tba_addr, 527 qpd->tma_addr, xcc_id); 528 } 529 530 static int allocate_vmid(struct device_queue_manager *dqm, 531 struct qcm_process_device *qpd, 532 struct queue *q) 533 { 534 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 535 struct device *dev = dqm->dev->adev->dev; 536 int allocated_vmid = -1, i; 537 538 for (i = dqm->dev->vm_info.first_vmid_kfd; 539 i <= dqm->dev->vm_info.last_vmid_kfd; i++) { 540 if (!dqm->vmid_pasid[i]) { 541 allocated_vmid = i; 542 break; 543 } 544 } 545 546 if (allocated_vmid < 0) { 547 dev_err(dev, "no more vmid to allocate\n"); 548 return -ENOSPC; 549 } 550 551 pr_debug("vmid allocated: %d\n", allocated_vmid); 552 553 dqm->vmid_pasid[allocated_vmid] = pdd->pasid; 554 555 set_pasid_vmid_mapping(dqm, pdd->pasid, allocated_vmid); 556 557 qpd->vmid = allocated_vmid; 558 q->properties.vmid = allocated_vmid; 559 560 program_sh_mem_settings(dqm, qpd); 561 562 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->kfd->cwsr_enabled) 563 program_trap_handler_settings(dqm, qpd); 564 565 /* qpd->page_table_base is set earlier when register_process() 566 * is called, i.e. when the first queue is created. 567 */ 568 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev, 569 qpd->vmid, 570 qpd->page_table_base); 571 /* invalidate the VM context after pasid and vmid mapping is set up */ 572 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 573 574 if (dqm->dev->kfd2kgd->set_scratch_backing_va) 575 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev, 576 qpd->sh_hidden_private_base, qpd->vmid); 577 578 return 0; 579 } 580 581 static int flush_texture_cache_nocpsch(struct kfd_node *kdev, 582 struct qcm_process_device *qpd) 583 { 584 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf; 585 int ret; 586 587 if (!qpd->ib_kaddr) 588 return -ENOMEM; 589 590 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr); 591 if (ret) 592 return ret; 593 594 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid, 595 qpd->ib_base, (uint32_t *)qpd->ib_kaddr, 596 pmf->release_mem_size / sizeof(uint32_t)); 597 } 598 599 static void deallocate_vmid(struct device_queue_manager *dqm, 600 struct qcm_process_device *qpd, 601 struct queue *q) 602 { 603 struct device *dev = dqm->dev->adev->dev; 604 605 /* On GFX v7, CP doesn't flush TC at dequeue */ 606 if (q->device->adev->asic_type == CHIP_HAWAII) 607 if (flush_texture_cache_nocpsch(q->device, qpd)) 608 dev_err(dev, "Failed to flush TC\n"); 609 610 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 611 612 /* Release the vmid mapping */ 613 set_pasid_vmid_mapping(dqm, 0, qpd->vmid); 614 dqm->vmid_pasid[qpd->vmid] = 0; 615 616 qpd->vmid = 0; 617 q->properties.vmid = 0; 618 } 619 620 static int create_queue_nocpsch(struct device_queue_manager *dqm, 621 struct queue *q, 622 struct qcm_process_device *qpd, 623 const struct kfd_criu_queue_priv_data *qd, 624 const void *restore_mqd, const void *restore_ctl_stack) 625 { 626 struct mqd_manager *mqd_mgr; 627 int retval; 628 629 dqm_lock(dqm); 630 631 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 632 pr_warn("Can't create new usermode queue because %d queues were already created\n", 633 dqm->total_queue_count); 634 retval = -EPERM; 635 goto out_unlock; 636 } 637 638 if (list_empty(&qpd->queues_list)) { 639 retval = allocate_vmid(dqm, qpd, q); 640 if (retval) 641 goto out_unlock; 642 } 643 q->properties.vmid = qpd->vmid; 644 /* 645 * Eviction state logic: mark all queues as evicted, even ones 646 * not currently active. Restoring inactive queues later only 647 * updates the is_evicted flag but is a no-op otherwise. 648 */ 649 q->properties.is_evicted = !!qpd->evicted; 650 651 q->properties.tba_addr = qpd->tba_addr; 652 q->properties.tma_addr = qpd->tma_addr; 653 654 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 655 q->properties.type)]; 656 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { 657 retval = allocate_hqd(dqm, q); 658 if (retval) 659 goto deallocate_vmid; 660 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", 661 q->pipe, q->queue); 662 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 663 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 664 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 665 if (retval) 666 goto deallocate_vmid; 667 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 668 } 669 670 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 671 if (retval) 672 goto out_deallocate_hqd; 673 674 /* Temporarily release dqm lock to avoid a circular lock dependency */ 675 dqm_unlock(dqm); 676 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 677 dqm_lock(dqm); 678 679 if (!q->mqd_mem_obj) { 680 retval = -ENOMEM; 681 goto out_deallocate_doorbell; 682 } 683 684 if (qd) 685 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 686 &q->properties, restore_mqd, restore_ctl_stack, 687 qd->ctl_stack_size); 688 else 689 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 690 &q->gart_mqd_addr, &q->properties); 691 692 if (q->properties.is_active) { 693 if (!dqm->sched_running) { 694 WARN_ONCE(1, "Load non-HWS mqd while stopped\n"); 695 goto add_queue_to_list; 696 } 697 698 if (WARN(q->process->mm != current->mm, 699 "should only run in user thread")) 700 retval = -EFAULT; 701 else 702 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 703 q->queue, &q->properties, current->mm); 704 if (retval) 705 goto out_free_mqd; 706 } 707 708 add_queue_to_list: 709 list_add(&q->list, &qpd->queues_list); 710 qpd->queue_count++; 711 if (q->properties.is_active) 712 increment_queue_count(dqm, qpd, q); 713 714 /* 715 * Unconditionally increment this counter, regardless of the queue's 716 * type or whether the queue is active. 717 */ 718 dqm->total_queue_count++; 719 pr_debug("Total of %d queues are accountable so far\n", 720 dqm->total_queue_count); 721 goto out_unlock; 722 723 out_free_mqd: 724 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 725 out_deallocate_doorbell: 726 deallocate_doorbell(qpd, q); 727 out_deallocate_hqd: 728 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 729 deallocate_hqd(dqm, q); 730 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 731 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 732 deallocate_sdma_queue(dqm, q); 733 deallocate_vmid: 734 if (list_empty(&qpd->queues_list)) 735 deallocate_vmid(dqm, qpd, q); 736 out_unlock: 737 dqm_unlock(dqm); 738 return retval; 739 } 740 741 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) 742 { 743 bool set; 744 int pipe, bit, i; 745 746 set = false; 747 748 for (pipe = dqm->next_pipe_to_allocate, i = 0; 749 i < get_pipes_per_mec(dqm); 750 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { 751 752 if (!is_pipe_enabled(dqm, 0, pipe)) 753 continue; 754 755 if (dqm->allocated_queues[pipe] != 0) { 756 bit = ffs(dqm->allocated_queues[pipe]) - 1; 757 dqm->allocated_queues[pipe] &= ~(1 << bit); 758 q->pipe = pipe; 759 q->queue = bit; 760 set = true; 761 break; 762 } 763 } 764 765 if (!set) 766 return -EBUSY; 767 768 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); 769 /* horizontal hqd allocation */ 770 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); 771 772 return 0; 773 } 774 775 static inline void deallocate_hqd(struct device_queue_manager *dqm, 776 struct queue *q) 777 { 778 dqm->allocated_queues[q->pipe] |= (1 << q->queue); 779 } 780 781 #define SQ_IND_CMD_CMD_KILL 0x00000003 782 #define SQ_IND_CMD_MODE_BROADCAST 0x00000001 783 784 static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process *p) 785 { 786 int status = 0; 787 unsigned int vmid; 788 uint16_t queried_pasid; 789 union SQ_CMD_BITS reg_sq_cmd; 790 union GRBM_GFX_INDEX_BITS reg_gfx_index; 791 struct kfd_process_device *pdd; 792 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd; 793 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd; 794 uint32_t xcc_mask = dev->xcc_mask; 795 int xcc_id; 796 797 reg_sq_cmd.u32All = 0; 798 reg_gfx_index.u32All = 0; 799 800 pr_debug("Killing all process wavefronts\n"); 801 802 if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) { 803 dev_err(dev->adev->dev, "no vmid pasid mapping supported\n"); 804 return -EOPNOTSUPP; 805 } 806 807 /* taking the VMID for that process on the safe way using PDD */ 808 pdd = kfd_get_process_device_data(dev, p); 809 if (!pdd) 810 return -EFAULT; 811 812 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING .. 813 * ATC_VMID15_PASID_MAPPING 814 * to check which VMID the current process is mapped to. 815 */ 816 817 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) { 818 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info 819 (dev->adev, vmid, &queried_pasid); 820 821 if (status && queried_pasid == pdd->pasid) { 822 pr_debug("Killing wave fronts of vmid %d and process pid %d\n", 823 vmid, p->lead_thread->pid); 824 break; 825 } 826 } 827 828 if (vmid > last_vmid_to_scan) { 829 dev_err(dev->adev->dev, "Didn't find vmid for process pid %d\n", 830 p->lead_thread->pid); 831 return -EFAULT; 832 } 833 834 reg_gfx_index.bits.sh_broadcast_writes = 1; 835 reg_gfx_index.bits.se_broadcast_writes = 1; 836 reg_gfx_index.bits.instance_broadcast_writes = 1; 837 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; 838 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL; 839 reg_sq_cmd.bits.vm_id = vmid; 840 841 for_each_inst(xcc_id, xcc_mask) 842 dev->kfd2kgd->wave_control_execute( 843 dev->adev, reg_gfx_index.u32All, 844 reg_sq_cmd.u32All, xcc_id); 845 846 return 0; 847 } 848 849 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked 850 * to avoid asynchronized access 851 */ 852 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, 853 struct qcm_process_device *qpd, 854 struct queue *q) 855 { 856 int retval; 857 struct mqd_manager *mqd_mgr; 858 859 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 860 q->properties.type)]; 861 862 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 863 deallocate_hqd(dqm, q); 864 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 865 deallocate_sdma_queue(dqm, q); 866 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 867 deallocate_sdma_queue(dqm, q); 868 else { 869 pr_debug("q->properties.type %d is invalid\n", 870 q->properties.type); 871 return -EINVAL; 872 } 873 dqm->total_queue_count--; 874 875 deallocate_doorbell(qpd, q); 876 877 if (!dqm->sched_running) { 878 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n"); 879 return 0; 880 } 881 882 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 883 KFD_PREEMPT_TYPE_WAVEFRONT_RESET, 884 KFD_UNMAP_LATENCY_MS, 885 q->pipe, q->queue); 886 if (retval == -ETIME) 887 qpd->reset_wavefronts = true; 888 889 list_del(&q->list); 890 if (list_empty(&qpd->queues_list)) { 891 if (qpd->reset_wavefronts) { 892 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n", 893 dqm->dev); 894 /* dbgdev_wave_reset_wavefronts has to be called before 895 * deallocate_vmid(), i.e. when vmid is still in use. 896 */ 897 dbgdev_wave_reset_wavefronts(dqm->dev, 898 qpd->pqm->process); 899 qpd->reset_wavefronts = false; 900 } 901 902 deallocate_vmid(dqm, qpd, q); 903 } 904 qpd->queue_count--; 905 if (q->properties.is_active) 906 decrement_queue_count(dqm, qpd, q); 907 908 return retval; 909 } 910 911 static int destroy_queue_nocpsch(struct device_queue_manager *dqm, 912 struct qcm_process_device *qpd, 913 struct queue *q) 914 { 915 int retval; 916 uint64_t sdma_val = 0; 917 struct device *dev = dqm->dev->adev->dev; 918 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 919 struct mqd_manager *mqd_mgr = 920 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 921 922 /* Get the SDMA queue stats */ 923 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 924 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 925 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 926 &sdma_val); 927 if (retval) 928 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n", 929 q->properties.queue_id); 930 } 931 932 dqm_lock(dqm); 933 retval = destroy_queue_nocpsch_locked(dqm, qpd, q); 934 if (!retval) 935 pdd->sdma_past_activity_counter += sdma_val; 936 dqm_unlock(dqm); 937 938 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 939 940 return retval; 941 } 942 943 static int update_queue(struct device_queue_manager *dqm, struct queue *q, 944 struct mqd_update_info *minfo) 945 { 946 int retval = 0; 947 struct device *dev = dqm->dev->adev->dev; 948 struct mqd_manager *mqd_mgr; 949 struct kfd_process_device *pdd; 950 bool prev_active = false; 951 952 dqm_lock(dqm); 953 pdd = kfd_get_process_device_data(q->device, q->process); 954 if (!pdd) { 955 retval = -ENODEV; 956 goto out_unlock; 957 } 958 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 959 q->properties.type)]; 960 961 /* Save previous activity state for counters */ 962 prev_active = q->properties.is_active; 963 964 /* Make sure the queue is unmapped before updating the MQD */ 965 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 966 if (!dqm->dev->kfd->shared_resources.enable_mes) 967 retval = unmap_queues_cpsch(dqm, 968 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false); 969 else if (prev_active) 970 retval = remove_queue_mes(dqm, q, &pdd->qpd); 971 972 /* queue is reset so inaccessable */ 973 if (pdd->has_reset_queue) { 974 retval = -EACCES; 975 goto out_unlock; 976 } 977 978 if (retval) { 979 dev_err(dev, "unmap queue failed\n"); 980 goto out_unlock; 981 } 982 } else if (prev_active && 983 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 984 q->properties.type == KFD_QUEUE_TYPE_SDMA || 985 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 986 987 if (!dqm->sched_running) { 988 WARN_ONCE(1, "Update non-HWS queue while stopped\n"); 989 goto out_unlock; 990 } 991 992 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 993 (dqm->dev->kfd->cwsr_enabled ? 994 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 995 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 996 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 997 if (retval) { 998 dev_err(dev, "destroy mqd failed\n"); 999 goto out_unlock; 1000 } 1001 } 1002 1003 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo); 1004 1005 /* 1006 * check active state vs. the previous state and modify 1007 * counter accordingly. map_queues_cpsch uses the 1008 * dqm->active_queue_count to determine whether a new runlist must be 1009 * uploaded. 1010 */ 1011 if (q->properties.is_active && !prev_active) { 1012 increment_queue_count(dqm, &pdd->qpd, q); 1013 } else if (!q->properties.is_active && prev_active) { 1014 decrement_queue_count(dqm, &pdd->qpd, q); 1015 } else if (q->gws && !q->properties.is_gws) { 1016 if (q->properties.is_active) { 1017 dqm->gws_queue_count++; 1018 pdd->qpd.mapped_gws_queue = true; 1019 } 1020 q->properties.is_gws = true; 1021 } else if (!q->gws && q->properties.is_gws) { 1022 if (q->properties.is_active) { 1023 dqm->gws_queue_count--; 1024 pdd->qpd.mapped_gws_queue = false; 1025 } 1026 q->properties.is_gws = false; 1027 } 1028 1029 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 1030 if (!dqm->dev->kfd->shared_resources.enable_mes) 1031 retval = map_queues_cpsch(dqm); 1032 else if (q->properties.is_active) 1033 retval = add_queue_mes(dqm, q, &pdd->qpd); 1034 } else if (q->properties.is_active && 1035 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 1036 q->properties.type == KFD_QUEUE_TYPE_SDMA || 1037 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1038 if (WARN(q->process->mm != current->mm, 1039 "should only run in user thread")) 1040 retval = -EFAULT; 1041 else 1042 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, 1043 q->pipe, q->queue, 1044 &q->properties, current->mm); 1045 } 1046 1047 out_unlock: 1048 dqm_unlock(dqm); 1049 return retval; 1050 } 1051 1052 /* suspend_single_queue does not lock the dqm like the 1053 * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should 1054 * lock the dqm before calling, and unlock after calling. 1055 * 1056 * The reason we don't lock the dqm is because this function may be 1057 * called on multiple queues in a loop, so rather than locking/unlocking 1058 * multiple times, we will just keep the dqm locked for all of the calls. 1059 */ 1060 static int suspend_single_queue(struct device_queue_manager *dqm, 1061 struct kfd_process_device *pdd, 1062 struct queue *q) 1063 { 1064 bool is_new; 1065 1066 if (q->properties.is_suspended) 1067 return 0; 1068 1069 pr_debug("Suspending process pid %d queue [%i]\n", 1070 pdd->process->lead_thread->pid, 1071 q->properties.queue_id); 1072 1073 is_new = q->properties.exception_status & KFD_EC_MASK(EC_QUEUE_NEW); 1074 1075 if (is_new || q->properties.is_being_destroyed) { 1076 pr_debug("Suspend: skip %s queue id %i\n", 1077 is_new ? "new" : "destroyed", 1078 q->properties.queue_id); 1079 return -EBUSY; 1080 } 1081 1082 q->properties.is_suspended = true; 1083 if (q->properties.is_active) { 1084 if (dqm->dev->kfd->shared_resources.enable_mes) { 1085 int r = remove_queue_mes(dqm, q, &pdd->qpd); 1086 1087 if (r) 1088 return r; 1089 } 1090 1091 decrement_queue_count(dqm, &pdd->qpd, q); 1092 q->properties.is_active = false; 1093 } 1094 1095 return 0; 1096 } 1097 1098 /* resume_single_queue does not lock the dqm like the functions 1099 * restore_process_queues_cpsch or restore_process_queues_nocpsch. You should 1100 * lock the dqm before calling, and unlock after calling. 1101 * 1102 * The reason we don't lock the dqm is because this function may be 1103 * called on multiple queues in a loop, so rather than locking/unlocking 1104 * multiple times, we will just keep the dqm locked for all of the calls. 1105 */ 1106 static int resume_single_queue(struct device_queue_manager *dqm, 1107 struct qcm_process_device *qpd, 1108 struct queue *q) 1109 { 1110 struct kfd_process_device *pdd; 1111 1112 if (!q->properties.is_suspended) 1113 return 0; 1114 1115 pdd = qpd_to_pdd(qpd); 1116 1117 pr_debug("Restoring from suspend process pid %d queue [%i]\n", 1118 pdd->process->lead_thread->pid, 1119 q->properties.queue_id); 1120 1121 q->properties.is_suspended = false; 1122 1123 if (QUEUE_IS_ACTIVE(q->properties)) { 1124 if (dqm->dev->kfd->shared_resources.enable_mes) { 1125 int r = add_queue_mes(dqm, q, &pdd->qpd); 1126 1127 if (r) 1128 return r; 1129 } 1130 1131 q->properties.is_active = true; 1132 increment_queue_count(dqm, qpd, q); 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm, 1139 struct qcm_process_device *qpd) 1140 { 1141 struct queue *q; 1142 struct mqd_manager *mqd_mgr; 1143 struct kfd_process_device *pdd; 1144 int retval, ret = 0; 1145 1146 dqm_lock(dqm); 1147 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 1148 goto out; 1149 1150 pdd = qpd_to_pdd(qpd); 1151 pr_debug_ratelimited("Evicting process pid %d queues\n", 1152 pdd->process->lead_thread->pid); 1153 1154 pdd->last_evict_timestamp = get_jiffies_64(); 1155 /* Mark all queues as evicted. Deactivate all active queues on 1156 * the qpd. 1157 */ 1158 list_for_each_entry(q, &qpd->queues_list, list) { 1159 q->properties.is_evicted = true; 1160 if (!q->properties.is_active) 1161 continue; 1162 1163 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1164 q->properties.type)]; 1165 q->properties.is_active = false; 1166 decrement_queue_count(dqm, qpd, q); 1167 1168 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n")) 1169 continue; 1170 1171 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 1172 (dqm->dev->kfd->cwsr_enabled ? 1173 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 1174 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 1175 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 1176 if (retval && !ret) 1177 /* Return the first error, but keep going to 1178 * maintain a consistent eviction state 1179 */ 1180 ret = retval; 1181 } 1182 1183 out: 1184 dqm_unlock(dqm); 1185 return ret; 1186 } 1187 1188 static int evict_process_queues_cpsch(struct device_queue_manager *dqm, 1189 struct qcm_process_device *qpd) 1190 { 1191 struct queue *q; 1192 struct device *dev = dqm->dev->adev->dev; 1193 struct kfd_process_device *pdd; 1194 int retval = 0; 1195 1196 dqm_lock(dqm); 1197 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 1198 goto out; 1199 1200 pdd = qpd_to_pdd(qpd); 1201 1202 /* The debugger creates processes that temporarily have not acquired 1203 * all VMs for all devices and has no VMs itself. 1204 * Skip queue eviction on process eviction. 1205 */ 1206 if (!pdd->drm_priv) 1207 goto out; 1208 1209 pr_debug_ratelimited("Evicting process pid %d queues\n", 1210 pdd->process->lead_thread->pid); 1211 1212 if (dqm->dev->kfd->shared_resources.enable_mes) { 1213 pdd->last_evict_timestamp = get_jiffies_64(); 1214 retval = suspend_all_queues_mes(dqm); 1215 if (retval) { 1216 dev_err(dev, "Suspending all queues failed"); 1217 goto out; 1218 } 1219 } 1220 1221 /* Mark all queues as evicted. Deactivate all active queues on 1222 * the qpd. 1223 */ 1224 list_for_each_entry(q, &qpd->queues_list, list) { 1225 q->properties.is_evicted = true; 1226 if (!q->properties.is_active) 1227 continue; 1228 1229 q->properties.is_active = false; 1230 decrement_queue_count(dqm, qpd, q); 1231 1232 if (dqm->dev->kfd->shared_resources.enable_mes) { 1233 retval = remove_queue_mes(dqm, q, qpd); 1234 if (retval) { 1235 dev_err(dev, "Failed to evict queue %d\n", 1236 q->properties.queue_id); 1237 goto out; 1238 } 1239 } 1240 } 1241 1242 if (!dqm->dev->kfd->shared_resources.enable_mes) { 1243 pdd->last_evict_timestamp = get_jiffies_64(); 1244 retval = execute_queues_cpsch(dqm, 1245 qpd->is_debug ? 1246 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : 1247 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 1248 USE_DEFAULT_GRACE_PERIOD); 1249 } else { 1250 retval = resume_all_queues_mes(dqm); 1251 if (retval) 1252 dev_err(dev, "Resuming all queues failed"); 1253 } 1254 1255 out: 1256 dqm_unlock(dqm); 1257 return retval; 1258 } 1259 1260 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, 1261 struct qcm_process_device *qpd) 1262 { 1263 struct mm_struct *mm = NULL; 1264 struct queue *q; 1265 struct mqd_manager *mqd_mgr; 1266 struct kfd_process_device *pdd; 1267 uint64_t pd_base; 1268 uint64_t eviction_duration; 1269 int retval, ret = 0; 1270 1271 pdd = qpd_to_pdd(qpd); 1272 /* Retrieve PD base */ 1273 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1274 1275 dqm_lock(dqm); 1276 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 1277 goto out; 1278 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 1279 qpd->evicted--; 1280 goto out; 1281 } 1282 1283 pr_debug_ratelimited("Restoring process pid %d queues\n", 1284 pdd->process->lead_thread->pid); 1285 1286 /* Update PD Base in QPD */ 1287 qpd->page_table_base = pd_base; 1288 pr_debug("Updated PD address to 0x%llx\n", pd_base); 1289 1290 if (!list_empty(&qpd->queues_list)) { 1291 dqm->dev->kfd2kgd->set_vm_context_page_table_base( 1292 dqm->dev->adev, 1293 qpd->vmid, 1294 qpd->page_table_base); 1295 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); 1296 } 1297 1298 /* Take a safe reference to the mm_struct, which may otherwise 1299 * disappear even while the kfd_process is still referenced. 1300 */ 1301 mm = get_task_mm(pdd->process->lead_thread); 1302 if (!mm) { 1303 ret = -EFAULT; 1304 goto out; 1305 } 1306 1307 /* Remove the eviction flags. Activate queues that are not 1308 * inactive for other reasons. 1309 */ 1310 list_for_each_entry(q, &qpd->queues_list, list) { 1311 q->properties.is_evicted = false; 1312 if (!QUEUE_IS_ACTIVE(q->properties)) 1313 continue; 1314 1315 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1316 q->properties.type)]; 1317 q->properties.is_active = true; 1318 increment_queue_count(dqm, qpd, q); 1319 1320 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n")) 1321 continue; 1322 1323 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 1324 q->queue, &q->properties, mm); 1325 if (retval && !ret) 1326 /* Return the first error, but keep going to 1327 * maintain a consistent eviction state 1328 */ 1329 ret = retval; 1330 } 1331 qpd->evicted = 0; 1332 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 1333 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 1334 out: 1335 if (mm) 1336 mmput(mm); 1337 dqm_unlock(dqm); 1338 return ret; 1339 } 1340 1341 static int restore_process_queues_cpsch(struct device_queue_manager *dqm, 1342 struct qcm_process_device *qpd) 1343 { 1344 struct queue *q; 1345 struct device *dev = dqm->dev->adev->dev; 1346 struct kfd_process_device *pdd; 1347 uint64_t eviction_duration; 1348 int retval = 0; 1349 1350 pdd = qpd_to_pdd(qpd); 1351 1352 dqm_lock(dqm); 1353 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 1354 goto out; 1355 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 1356 qpd->evicted--; 1357 goto out; 1358 } 1359 1360 /* The debugger creates processes that temporarily have not acquired 1361 * all VMs for all devices and has no VMs itself. 1362 * Skip queue restore on process restore. 1363 */ 1364 if (!pdd->drm_priv) 1365 goto vm_not_acquired; 1366 1367 pr_debug_ratelimited("Restoring process pid %d queues\n", 1368 pdd->process->lead_thread->pid); 1369 1370 /* Update PD Base in QPD */ 1371 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1372 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base); 1373 1374 /* activate all active queues on the qpd */ 1375 list_for_each_entry(q, &qpd->queues_list, list) { 1376 q->properties.is_evicted = false; 1377 if (!QUEUE_IS_ACTIVE(q->properties)) 1378 continue; 1379 1380 q->properties.is_active = true; 1381 increment_queue_count(dqm, &pdd->qpd, q); 1382 1383 if (dqm->dev->kfd->shared_resources.enable_mes) { 1384 retval = add_queue_mes(dqm, q, qpd); 1385 if (retval) { 1386 dev_err(dev, "Failed to restore queue %d\n", 1387 q->properties.queue_id); 1388 goto out; 1389 } 1390 } 1391 } 1392 if (!dqm->dev->kfd->shared_resources.enable_mes) 1393 retval = execute_queues_cpsch(dqm, 1394 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1395 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 1396 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 1397 vm_not_acquired: 1398 qpd->evicted = 0; 1399 out: 1400 dqm_unlock(dqm); 1401 return retval; 1402 } 1403 1404 static int register_process(struct device_queue_manager *dqm, 1405 struct qcm_process_device *qpd) 1406 { 1407 struct device_process_node *n; 1408 struct kfd_process_device *pdd; 1409 uint64_t pd_base; 1410 int retval; 1411 1412 n = kzalloc(sizeof(*n), GFP_KERNEL); 1413 if (!n) 1414 return -ENOMEM; 1415 1416 n->qpd = qpd; 1417 1418 pdd = qpd_to_pdd(qpd); 1419 /* Retrieve PD base */ 1420 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1421 1422 dqm_lock(dqm); 1423 list_add(&n->list, &dqm->queues); 1424 1425 /* Update PD Base in QPD */ 1426 qpd->page_table_base = pd_base; 1427 pr_debug("Updated PD address to 0x%llx\n", pd_base); 1428 1429 retval = dqm->asic_ops.update_qpd(dqm, qpd); 1430 1431 dqm->processes_count++; 1432 1433 dqm_unlock(dqm); 1434 1435 /* Outside the DQM lock because under the DQM lock we can't do 1436 * reclaim or take other locks that others hold while reclaiming. 1437 */ 1438 kfd_inc_compute_active(dqm->dev); 1439 1440 return retval; 1441 } 1442 1443 static int unregister_process(struct device_queue_manager *dqm, 1444 struct qcm_process_device *qpd) 1445 { 1446 int retval; 1447 struct device_process_node *cur, *next; 1448 1449 pr_debug("qpd->queues_list is %s\n", 1450 list_empty(&qpd->queues_list) ? "empty" : "not empty"); 1451 1452 retval = 0; 1453 dqm_lock(dqm); 1454 1455 list_for_each_entry_safe(cur, next, &dqm->queues, list) { 1456 if (qpd == cur->qpd) { 1457 list_del(&cur->list); 1458 kfree(cur); 1459 dqm->processes_count--; 1460 goto out; 1461 } 1462 } 1463 /* qpd not found in dqm list */ 1464 retval = 1; 1465 out: 1466 dqm_unlock(dqm); 1467 1468 /* Outside the DQM lock because under the DQM lock we can't do 1469 * reclaim or take other locks that others hold while reclaiming. 1470 */ 1471 if (!retval) 1472 kfd_dec_compute_active(dqm->dev); 1473 1474 return retval; 1475 } 1476 1477 static int 1478 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid, 1479 unsigned int vmid) 1480 { 1481 uint32_t xcc_mask = dqm->dev->xcc_mask; 1482 int xcc_id, ret; 1483 1484 for_each_inst(xcc_id, xcc_mask) { 1485 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping( 1486 dqm->dev->adev, pasid, vmid, xcc_id); 1487 if (ret) 1488 break; 1489 } 1490 1491 return ret; 1492 } 1493 1494 static void init_interrupts(struct device_queue_manager *dqm) 1495 { 1496 uint32_t xcc_mask = dqm->dev->xcc_mask; 1497 unsigned int i, xcc_id; 1498 1499 for_each_inst(xcc_id, xcc_mask) { 1500 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) { 1501 if (is_pipe_enabled(dqm, 0, i)) { 1502 dqm->dev->kfd2kgd->init_interrupts( 1503 dqm->dev->adev, i, xcc_id); 1504 } 1505 } 1506 } 1507 } 1508 1509 static int initialize_nocpsch(struct device_queue_manager *dqm) 1510 { 1511 int pipe, queue; 1512 1513 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1514 1515 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), 1516 sizeof(unsigned int), GFP_KERNEL); 1517 if (!dqm->allocated_queues) 1518 return -ENOMEM; 1519 1520 mutex_init(&dqm->lock_hidden); 1521 INIT_LIST_HEAD(&dqm->queues); 1522 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0; 1523 dqm->active_cp_queue_count = 0; 1524 dqm->gws_queue_count = 0; 1525 1526 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 1527 int pipe_offset = pipe * get_queues_per_pipe(dqm); 1528 1529 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) 1530 if (test_bit(pipe_offset + queue, 1531 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 1532 dqm->allocated_queues[pipe] |= 1 << queue; 1533 } 1534 1535 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid)); 1536 1537 init_sdma_bitmaps(dqm); 1538 1539 return 0; 1540 } 1541 1542 static void uninitialize(struct device_queue_manager *dqm) 1543 { 1544 int i; 1545 1546 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0); 1547 1548 kfree(dqm->allocated_queues); 1549 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) 1550 kfree(dqm->mqd_mgrs[i]); 1551 mutex_destroy(&dqm->lock_hidden); 1552 } 1553 1554 static int start_nocpsch(struct device_queue_manager *dqm) 1555 { 1556 int r = 0; 1557 1558 pr_info("SW scheduler is used"); 1559 init_interrupts(dqm); 1560 1561 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1562 r = pm_init(&dqm->packet_mgr, dqm); 1563 if (!r) 1564 dqm->sched_running = true; 1565 1566 return r; 1567 } 1568 1569 static int stop_nocpsch(struct device_queue_manager *dqm) 1570 { 1571 dqm_lock(dqm); 1572 if (!dqm->sched_running) { 1573 dqm_unlock(dqm); 1574 return 0; 1575 } 1576 1577 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1578 pm_uninit(&dqm->packet_mgr); 1579 dqm->sched_running = false; 1580 dqm_unlock(dqm); 1581 1582 return 0; 1583 } 1584 1585 static int allocate_sdma_queue(struct device_queue_manager *dqm, 1586 struct queue *q, const uint32_t *restore_sdma_id) 1587 { 1588 struct device *dev = dqm->dev->adev->dev; 1589 int bit; 1590 1591 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1592 if (bitmap_empty(dqm->sdma_bitmap, get_num_sdma_queues(dqm))) { 1593 dev_warn(dev, "No more SDMA queue to allocate (%d total queues)\n", 1594 get_num_sdma_queues(dqm)); 1595 return -ENOMEM; 1596 } 1597 1598 if (restore_sdma_id) { 1599 /* Re-use existing sdma_id */ 1600 if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) { 1601 dev_err(dev, "SDMA queue already in use\n"); 1602 return -EBUSY; 1603 } 1604 clear_bit(*restore_sdma_id, dqm->sdma_bitmap); 1605 q->sdma_id = *restore_sdma_id; 1606 } else { 1607 /* Find first available sdma_id */ 1608 bit = find_first_bit(dqm->sdma_bitmap, 1609 get_num_sdma_queues(dqm)); 1610 clear_bit(bit, dqm->sdma_bitmap); 1611 q->sdma_id = bit; 1612 } 1613 1614 q->properties.sdma_engine_id = 1615 q->sdma_id % kfd_get_num_sdma_engines(dqm->dev); 1616 q->properties.sdma_queue_id = q->sdma_id / 1617 kfd_get_num_sdma_engines(dqm->dev); 1618 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1619 if (bitmap_empty(dqm->xgmi_sdma_bitmap, get_num_xgmi_sdma_queues(dqm))) { 1620 dev_warn(dev, "No more XGMI SDMA queue to allocate (%d total queues)\n", 1621 get_num_xgmi_sdma_queues(dqm)); 1622 return -ENOMEM; 1623 } 1624 if (restore_sdma_id) { 1625 /* Re-use existing sdma_id */ 1626 if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) { 1627 dev_err(dev, "SDMA queue already in use\n"); 1628 return -EBUSY; 1629 } 1630 clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap); 1631 q->sdma_id = *restore_sdma_id; 1632 } else { 1633 bit = find_first_bit(dqm->xgmi_sdma_bitmap, 1634 get_num_xgmi_sdma_queues(dqm)); 1635 clear_bit(bit, dqm->xgmi_sdma_bitmap); 1636 q->sdma_id = bit; 1637 } 1638 /* sdma_engine_id is sdma id including 1639 * both PCIe-optimized SDMAs and XGMI- 1640 * optimized SDMAs. The calculation below 1641 * assumes the first N engines are always 1642 * PCIe-optimized ones 1643 */ 1644 q->properties.sdma_engine_id = 1645 kfd_get_num_sdma_engines(dqm->dev) + 1646 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev); 1647 q->properties.sdma_queue_id = q->sdma_id / 1648 kfd_get_num_xgmi_sdma_engines(dqm->dev); 1649 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 1650 int i, num_queues, num_engines, eng_offset = 0, start_engine; 1651 bool free_bit_found = false, is_xgmi = false; 1652 1653 if (q->properties.sdma_engine_id < kfd_get_num_sdma_engines(dqm->dev)) { 1654 num_queues = get_num_sdma_queues(dqm); 1655 num_engines = kfd_get_num_sdma_engines(dqm->dev); 1656 q->properties.type = KFD_QUEUE_TYPE_SDMA; 1657 } else { 1658 num_queues = get_num_xgmi_sdma_queues(dqm); 1659 num_engines = kfd_get_num_xgmi_sdma_engines(dqm->dev); 1660 eng_offset = kfd_get_num_sdma_engines(dqm->dev); 1661 q->properties.type = KFD_QUEUE_TYPE_SDMA_XGMI; 1662 is_xgmi = true; 1663 } 1664 1665 /* Scan available bit based on target engine ID. */ 1666 start_engine = q->properties.sdma_engine_id - eng_offset; 1667 for (i = start_engine; i < num_queues; i += num_engines) { 1668 1669 if (!test_bit(i, is_xgmi ? dqm->xgmi_sdma_bitmap : dqm->sdma_bitmap)) 1670 continue; 1671 1672 clear_bit(i, is_xgmi ? dqm->xgmi_sdma_bitmap : dqm->sdma_bitmap); 1673 q->sdma_id = i; 1674 q->properties.sdma_queue_id = q->sdma_id / num_engines; 1675 free_bit_found = true; 1676 break; 1677 } 1678 1679 if (!free_bit_found) { 1680 dev_warn(dev, "No more SDMA queue to allocate for target ID %i (%d total queues)\n", 1681 q->properties.sdma_engine_id, num_queues); 1682 return -ENOMEM; 1683 } 1684 } 1685 1686 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); 1687 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); 1688 1689 return 0; 1690 } 1691 1692 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 1693 struct queue *q) 1694 { 1695 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1696 if (q->sdma_id >= get_num_sdma_queues(dqm)) 1697 return; 1698 set_bit(q->sdma_id, dqm->sdma_bitmap); 1699 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1700 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm)) 1701 return; 1702 set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap); 1703 } 1704 } 1705 1706 /* 1707 * Device Queue Manager implementation for cp scheduler 1708 */ 1709 1710 static int set_sched_resources(struct device_queue_manager *dqm) 1711 { 1712 int i, mec; 1713 struct scheduling_resources res; 1714 struct device *dev = dqm->dev->adev->dev; 1715 1716 res.vmid_mask = dqm->dev->compute_vmid_bitmap; 1717 1718 res.queue_mask = 0; 1719 for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) { 1720 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) 1721 / dqm->dev->kfd->shared_resources.num_pipe_per_mec; 1722 1723 if (!test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 1724 continue; 1725 1726 /* only acquire queues from the first MEC */ 1727 if (mec > 0) 1728 continue; 1729 1730 /* This situation may be hit in the future if a new HW 1731 * generation exposes more than 64 queues. If so, the 1732 * definition of res.queue_mask needs updating 1733 */ 1734 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { 1735 dev_err(dev, "Invalid queue enabled by amdgpu: %d\n", i); 1736 break; 1737 } 1738 1739 res.queue_mask |= 1ull 1740 << amdgpu_queue_mask_bit_to_set_resource_bit( 1741 dqm->dev->adev, i); 1742 } 1743 res.gws_mask = ~0ull; 1744 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; 1745 1746 pr_debug("Scheduling resources:\n" 1747 "vmid mask: 0x%8X\n" 1748 "queue mask: 0x%8llX\n", 1749 res.vmid_mask, res.queue_mask); 1750 1751 return pm_send_set_resources(&dqm->packet_mgr, &res); 1752 } 1753 1754 static int initialize_cpsch(struct device_queue_manager *dqm) 1755 { 1756 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1757 1758 mutex_init(&dqm->lock_hidden); 1759 INIT_LIST_HEAD(&dqm->queues); 1760 dqm->active_queue_count = dqm->processes_count = 0; 1761 dqm->active_cp_queue_count = 0; 1762 dqm->gws_queue_count = 0; 1763 dqm->active_runlist = false; 1764 dqm->trap_debug_vmid = 0; 1765 1766 init_sdma_bitmaps(dqm); 1767 1768 update_dqm_wait_times(dqm); 1769 return 0; 1770 } 1771 1772 /* halt_cpsch: 1773 * Unmap queues so the schedule doesn't continue remaining jobs in the queue. 1774 * Then set dqm->sched_halt so queues don't map to runlist until unhalt_cpsch 1775 * is called. 1776 */ 1777 static int halt_cpsch(struct device_queue_manager *dqm) 1778 { 1779 int ret = 0; 1780 1781 dqm_lock(dqm); 1782 if (!dqm->sched_running) { 1783 dqm_unlock(dqm); 1784 return 0; 1785 } 1786 1787 WARN_ONCE(dqm->sched_halt, "Scheduling is already on halt\n"); 1788 1789 if (!dqm->is_hws_hang) { 1790 if (!dqm->dev->kfd->shared_resources.enable_mes) 1791 ret = unmap_queues_cpsch(dqm, 1792 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 1793 USE_DEFAULT_GRACE_PERIOD, false); 1794 else 1795 ret = remove_all_kfd_queues_mes(dqm); 1796 } 1797 dqm->sched_halt = true; 1798 dqm_unlock(dqm); 1799 1800 return ret; 1801 } 1802 1803 /* unhalt_cpsch 1804 * Unset dqm->sched_halt and map queues back to runlist 1805 */ 1806 static int unhalt_cpsch(struct device_queue_manager *dqm) 1807 { 1808 int ret = 0; 1809 1810 dqm_lock(dqm); 1811 if (!dqm->sched_running || !dqm->sched_halt) { 1812 WARN_ONCE(!dqm->sched_halt, "Scheduling is not on halt.\n"); 1813 dqm_unlock(dqm); 1814 return 0; 1815 } 1816 dqm->sched_halt = false; 1817 if (!dqm->dev->kfd->shared_resources.enable_mes) 1818 ret = execute_queues_cpsch(dqm, 1819 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 1820 0, USE_DEFAULT_GRACE_PERIOD); 1821 else 1822 ret = add_all_kfd_queues_mes(dqm); 1823 1824 dqm_unlock(dqm); 1825 1826 return ret; 1827 } 1828 1829 static int start_cpsch(struct device_queue_manager *dqm) 1830 { 1831 struct device *dev = dqm->dev->adev->dev; 1832 int retval, num_hw_queue_slots; 1833 1834 retval = 0; 1835 1836 dqm_lock(dqm); 1837 1838 if (!dqm->dev->kfd->shared_resources.enable_mes) { 1839 retval = pm_init(&dqm->packet_mgr, dqm); 1840 if (retval) 1841 goto fail_packet_manager_init; 1842 1843 retval = set_sched_resources(dqm); 1844 if (retval) 1845 goto fail_set_sched_resources; 1846 } 1847 pr_debug("Allocating fence memory\n"); 1848 1849 /* allocate fence memory on the gart */ 1850 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), 1851 &dqm->fence_mem); 1852 1853 if (retval) 1854 goto fail_allocate_vidmem; 1855 1856 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr; 1857 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; 1858 1859 init_interrupts(dqm); 1860 1861 /* clear hang status when driver try to start the hw scheduler */ 1862 dqm->sched_running = true; 1863 1864 if (!dqm->dev->kfd->shared_resources.enable_mes) { 1865 if (pm_config_dequeue_wait_counts(&dqm->packet_mgr, 1866 KFD_DEQUEUE_WAIT_INIT, 0 /* unused */)) 1867 dev_err(dev, "Setting optimized dequeue wait failed. Using default values\n"); 1868 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1869 } 1870 1871 /* setup per-queue reset detection buffer */ 1872 num_hw_queue_slots = dqm->dev->kfd->shared_resources.num_queue_per_pipe * 1873 dqm->dev->kfd->shared_resources.num_pipe_per_mec * 1874 NUM_XCC(dqm->dev->xcc_mask); 1875 1876 dqm->detect_hang_info_size = num_hw_queue_slots * sizeof(struct dqm_detect_hang_info); 1877 dqm->detect_hang_info = kzalloc(dqm->detect_hang_info_size, GFP_KERNEL); 1878 1879 if (!dqm->detect_hang_info) { 1880 retval = -ENOMEM; 1881 goto fail_detect_hang_buffer; 1882 } 1883 1884 dqm_unlock(dqm); 1885 1886 return 0; 1887 fail_detect_hang_buffer: 1888 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 1889 fail_allocate_vidmem: 1890 fail_set_sched_resources: 1891 if (!dqm->dev->kfd->shared_resources.enable_mes) 1892 pm_uninit(&dqm->packet_mgr); 1893 fail_packet_manager_init: 1894 dqm_unlock(dqm); 1895 return retval; 1896 } 1897 1898 static int stop_cpsch(struct device_queue_manager *dqm) 1899 { 1900 dqm_lock(dqm); 1901 if (!dqm->sched_running) { 1902 dqm_unlock(dqm); 1903 return 0; 1904 } 1905 1906 if (!dqm->dev->kfd->shared_resources.enable_mes) 1907 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false); 1908 else 1909 remove_all_kfd_queues_mes(dqm); 1910 1911 dqm->sched_running = false; 1912 1913 if (!dqm->dev->kfd->shared_resources.enable_mes) 1914 pm_release_ib(&dqm->packet_mgr); 1915 1916 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 1917 if (!dqm->dev->kfd->shared_resources.enable_mes) 1918 pm_uninit(&dqm->packet_mgr); 1919 kfree(dqm->detect_hang_info); 1920 dqm->detect_hang_info = NULL; 1921 dqm_unlock(dqm); 1922 1923 return 0; 1924 } 1925 1926 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, 1927 struct kernel_queue *kq, 1928 struct qcm_process_device *qpd) 1929 { 1930 dqm_lock(dqm); 1931 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1932 pr_warn("Can't create new kernel queue because %d queues were already created\n", 1933 dqm->total_queue_count); 1934 dqm_unlock(dqm); 1935 return -EPERM; 1936 } 1937 1938 /* 1939 * Unconditionally increment this counter, regardless of the queue's 1940 * type or whether the queue is active. 1941 */ 1942 dqm->total_queue_count++; 1943 pr_debug("Total of %d queues are accountable so far\n", 1944 dqm->total_queue_count); 1945 1946 list_add(&kq->list, &qpd->priv_queue_list); 1947 increment_queue_count(dqm, qpd, kq->queue); 1948 qpd->is_debug = true; 1949 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 1950 USE_DEFAULT_GRACE_PERIOD); 1951 dqm_unlock(dqm); 1952 1953 return 0; 1954 } 1955 1956 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, 1957 struct kernel_queue *kq, 1958 struct qcm_process_device *qpd) 1959 { 1960 dqm_lock(dqm); 1961 list_del(&kq->list); 1962 decrement_queue_count(dqm, qpd, kq->queue); 1963 qpd->is_debug = false; 1964 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 1965 USE_DEFAULT_GRACE_PERIOD); 1966 /* 1967 * Unconditionally decrement this counter, regardless of the queue's 1968 * type. 1969 */ 1970 dqm->total_queue_count--; 1971 pr_debug("Total of %d queues are accountable so far\n", 1972 dqm->total_queue_count); 1973 dqm_unlock(dqm); 1974 } 1975 1976 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, 1977 struct qcm_process_device *qpd, 1978 const struct kfd_criu_queue_priv_data *qd, 1979 const void *restore_mqd, const void *restore_ctl_stack) 1980 { 1981 int retval; 1982 struct mqd_manager *mqd_mgr; 1983 1984 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1985 pr_warn("Can't create new usermode queue because %d queues were already created\n", 1986 dqm->total_queue_count); 1987 retval = -EPERM; 1988 goto out; 1989 } 1990 1991 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1992 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI || 1993 q->properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 1994 dqm_lock(dqm); 1995 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 1996 dqm_unlock(dqm); 1997 if (retval) 1998 goto out; 1999 } 2000 2001 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 2002 if (retval) 2003 goto out_deallocate_sdma_queue; 2004 2005 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2006 q->properties.type)]; 2007 2008 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 2009 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 2010 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 2011 q->properties.tba_addr = qpd->tba_addr; 2012 q->properties.tma_addr = qpd->tma_addr; 2013 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 2014 if (!q->mqd_mem_obj) { 2015 retval = -ENOMEM; 2016 goto out_deallocate_doorbell; 2017 } 2018 2019 dqm_lock(dqm); 2020 /* 2021 * Eviction state logic: mark all queues as evicted, even ones 2022 * not currently active. Restoring inactive queues later only 2023 * updates the is_evicted flag but is a no-op otherwise. 2024 */ 2025 q->properties.is_evicted = !!qpd->evicted; 2026 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled && 2027 kfd_dbg_has_cwsr_workaround(q->device); 2028 2029 if (qd) 2030 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 2031 &q->properties, restore_mqd, restore_ctl_stack, 2032 qd->ctl_stack_size); 2033 else 2034 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 2035 &q->gart_mqd_addr, &q->properties); 2036 2037 list_add(&q->list, &qpd->queues_list); 2038 qpd->queue_count++; 2039 2040 if (q->properties.is_active) { 2041 increment_queue_count(dqm, qpd, q); 2042 2043 if (!dqm->dev->kfd->shared_resources.enable_mes) 2044 retval = execute_queues_cpsch(dqm, 2045 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 2046 else 2047 retval = add_queue_mes(dqm, q, qpd); 2048 if (retval) 2049 goto cleanup_queue; 2050 } 2051 2052 /* 2053 * Unconditionally increment this counter, regardless of the queue's 2054 * type or whether the queue is active. 2055 */ 2056 dqm->total_queue_count++; 2057 2058 pr_debug("Total of %d queues are accountable so far\n", 2059 dqm->total_queue_count); 2060 2061 dqm_unlock(dqm); 2062 return retval; 2063 2064 cleanup_queue: 2065 qpd->queue_count--; 2066 list_del(&q->list); 2067 if (q->properties.is_active) 2068 decrement_queue_count(dqm, qpd, q); 2069 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2070 dqm_unlock(dqm); 2071 out_deallocate_doorbell: 2072 deallocate_doorbell(qpd, q); 2073 out_deallocate_sdma_queue: 2074 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 2075 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 2076 dqm_lock(dqm); 2077 deallocate_sdma_queue(dqm, q); 2078 dqm_unlock(dqm); 2079 } 2080 out: 2081 return retval; 2082 } 2083 2084 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, 2085 uint64_t fence_value, 2086 unsigned int timeout_ms) 2087 { 2088 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; 2089 struct device *dev = dqm->dev->adev->dev; 2090 uint64_t *fence_addr = dqm->fence_addr; 2091 2092 while (*fence_addr != fence_value) { 2093 /* Fatal err detected, this response won't come */ 2094 if (amdgpu_amdkfd_is_fed(dqm->dev->adev)) 2095 return -EIO; 2096 2097 if (time_after(jiffies, end_jiffies)) { 2098 dev_err(dev, "qcm fence wait loop timeout expired\n"); 2099 /* In HWS case, this is used to halt the driver thread 2100 * in order not to mess up CP states before doing 2101 * scandumps for FW debugging. 2102 */ 2103 while (halt_if_hws_hang) 2104 schedule(); 2105 2106 return -ETIME; 2107 } 2108 schedule(); 2109 } 2110 2111 return 0; 2112 } 2113 2114 /* dqm->lock mutex has to be locked before calling this function */ 2115 static int map_queues_cpsch(struct device_queue_manager *dqm) 2116 { 2117 struct device *dev = dqm->dev->adev->dev; 2118 int retval; 2119 2120 if (!dqm->sched_running || dqm->sched_halt) 2121 return 0; 2122 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0) 2123 return 0; 2124 if (dqm->active_runlist) 2125 return 0; 2126 2127 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues); 2128 pr_debug("%s sent runlist\n", __func__); 2129 if (retval) { 2130 dev_err(dev, "failed to execute runlist\n"); 2131 return retval; 2132 } 2133 dqm->active_runlist = true; 2134 2135 return retval; 2136 } 2137 2138 static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q, 2139 struct qcm_process_device *qpd) 2140 { 2141 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 2142 2143 dev_err(dqm->dev->adev->dev, "queue id 0x%0x at pasid %d is reset\n", 2144 q->properties.queue_id, pdd->process->lead_thread->pid); 2145 2146 pdd->has_reset_queue = true; 2147 if (q->properties.is_active) { 2148 q->properties.is_active = false; 2149 decrement_queue_count(dqm, qpd, q); 2150 } 2151 } 2152 2153 static int detect_queue_hang(struct device_queue_manager *dqm) 2154 { 2155 int i; 2156 2157 /* detect should be used only in dqm locked queue reset */ 2158 if (WARN_ON(dqm->detect_hang_count > 0)) 2159 return 0; 2160 2161 memset(dqm->detect_hang_info, 0, dqm->detect_hang_info_size); 2162 2163 for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) { 2164 uint32_t mec, pipe, queue; 2165 int xcc_id; 2166 2167 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) 2168 / dqm->dev->kfd->shared_resources.num_pipe_per_mec; 2169 2170 if (mec || !test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 2171 continue; 2172 2173 amdgpu_queue_mask_bit_to_mec_queue(dqm->dev->adev, i, &mec, &pipe, &queue); 2174 2175 for_each_inst(xcc_id, dqm->dev->xcc_mask) { 2176 uint64_t queue_addr = dqm->dev->kfd2kgd->hqd_get_pq_addr( 2177 dqm->dev->adev, pipe, queue, xcc_id); 2178 struct dqm_detect_hang_info hang_info; 2179 2180 if (!queue_addr) 2181 continue; 2182 2183 hang_info.pipe_id = pipe; 2184 hang_info.queue_id = queue; 2185 hang_info.xcc_id = xcc_id; 2186 hang_info.queue_address = queue_addr; 2187 2188 dqm->detect_hang_info[dqm->detect_hang_count] = hang_info; 2189 dqm->detect_hang_count++; 2190 } 2191 } 2192 2193 return dqm->detect_hang_count; 2194 } 2195 2196 static struct queue *find_queue_by_address(struct device_queue_manager *dqm, uint64_t queue_address) 2197 { 2198 struct device_process_node *cur; 2199 struct qcm_process_device *qpd; 2200 struct queue *q; 2201 2202 list_for_each_entry(cur, &dqm->queues, list) { 2203 qpd = cur->qpd; 2204 list_for_each_entry(q, &qpd->queues_list, list) { 2205 if (queue_address == q->properties.queue_address) 2206 return q; 2207 } 2208 } 2209 2210 return NULL; 2211 } 2212 2213 static int reset_hung_queues(struct device_queue_manager *dqm) 2214 { 2215 int r = 0, reset_count = 0, i; 2216 2217 if (!dqm->detect_hang_info || dqm->is_hws_hang) 2218 return -EIO; 2219 2220 /* assume dqm locked. */ 2221 if (!detect_queue_hang(dqm)) 2222 return -ENOTRECOVERABLE; 2223 2224 for (i = 0; i < dqm->detect_hang_count; i++) { 2225 struct dqm_detect_hang_info hang_info = dqm->detect_hang_info[i]; 2226 struct queue *q = find_queue_by_address(dqm, hang_info.queue_address); 2227 struct kfd_process_device *pdd; 2228 uint64_t queue_addr = 0; 2229 2230 if (!q) { 2231 r = -ENOTRECOVERABLE; 2232 goto reset_fail; 2233 } 2234 2235 pdd = kfd_get_process_device_data(dqm->dev, q->process); 2236 if (!pdd) { 2237 r = -ENOTRECOVERABLE; 2238 goto reset_fail; 2239 } 2240 2241 queue_addr = dqm->dev->kfd2kgd->hqd_reset(dqm->dev->adev, 2242 hang_info.pipe_id, hang_info.queue_id, hang_info.xcc_id, 2243 KFD_UNMAP_LATENCY_MS); 2244 2245 /* either reset failed or we reset an unexpected queue. */ 2246 if (queue_addr != q->properties.queue_address) { 2247 r = -ENOTRECOVERABLE; 2248 goto reset_fail; 2249 } 2250 2251 set_queue_as_reset(dqm, q, &pdd->qpd); 2252 reset_count++; 2253 } 2254 2255 if (reset_count == dqm->detect_hang_count) 2256 kfd_signal_reset_event(dqm->dev); 2257 else 2258 r = -ENOTRECOVERABLE; 2259 2260 reset_fail: 2261 dqm->detect_hang_count = 0; 2262 2263 return r; 2264 } 2265 2266 static bool sdma_has_hang(struct device_queue_manager *dqm) 2267 { 2268 int engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 2269 int engine_end = engine_start + get_num_all_sdma_engines(dqm); 2270 int num_queues_per_eng = dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 2271 int i, j; 2272 2273 for (i = engine_start; i < engine_end; i++) { 2274 for (j = 0; j < num_queues_per_eng; j++) { 2275 if (!dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j)) 2276 continue; 2277 2278 return true; 2279 } 2280 } 2281 2282 return false; 2283 } 2284 2285 static bool set_sdma_queue_as_reset(struct device_queue_manager *dqm, 2286 uint32_t doorbell_off) 2287 { 2288 struct device_process_node *cur; 2289 struct qcm_process_device *qpd; 2290 struct queue *q; 2291 2292 list_for_each_entry(cur, &dqm->queues, list) { 2293 qpd = cur->qpd; 2294 list_for_each_entry(q, &qpd->queues_list, list) { 2295 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA || 2296 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) && 2297 q->properties.doorbell_off == doorbell_off) { 2298 set_queue_as_reset(dqm, q, qpd); 2299 return true; 2300 } 2301 } 2302 } 2303 2304 return false; 2305 } 2306 2307 static int reset_hung_queues_sdma(struct device_queue_manager *dqm) 2308 { 2309 int engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 2310 int engine_end = engine_start + get_num_all_sdma_engines(dqm); 2311 int num_queues_per_eng = dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 2312 int r = 0, i, j; 2313 2314 if (dqm->is_hws_hang) 2315 return -EIO; 2316 2317 /* Scan for hung HW queues and reset engine. */ 2318 dqm->detect_hang_count = 0; 2319 for (i = engine_start; i < engine_end; i++) { 2320 for (j = 0; j < num_queues_per_eng; j++) { 2321 uint32_t doorbell_off = 2322 dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j); 2323 2324 if (!doorbell_off) 2325 continue; 2326 2327 /* Reset engine and check. */ 2328 if (amdgpu_sdma_reset_engine(dqm->dev->adev, i, false) || 2329 dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j) || 2330 !set_sdma_queue_as_reset(dqm, doorbell_off)) { 2331 r = -ENOTRECOVERABLE; 2332 goto reset_fail; 2333 } 2334 2335 /* Should only expect one queue active per engine */ 2336 dqm->detect_hang_count++; 2337 break; 2338 } 2339 } 2340 2341 /* Signal process reset */ 2342 if (dqm->detect_hang_count) 2343 kfd_signal_reset_event(dqm->dev); 2344 else 2345 r = -ENOTRECOVERABLE; 2346 2347 reset_fail: 2348 dqm->detect_hang_count = 0; 2349 2350 return r; 2351 } 2352 2353 static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma) 2354 { 2355 struct amdgpu_device *adev = dqm->dev->adev; 2356 2357 while (halt_if_hws_hang) 2358 schedule(); 2359 2360 if (adev->debug_disable_gpu_ring_reset) { 2361 dev_info_once(adev->dev, 2362 "%s queue hung, but ring reset disabled", 2363 is_sdma ? "sdma" : "compute"); 2364 2365 return -EPERM; 2366 } 2367 if (!amdgpu_gpu_recovery) 2368 return -ENOTRECOVERABLE; 2369 2370 return is_sdma ? reset_hung_queues_sdma(dqm) : reset_hung_queues(dqm); 2371 } 2372 2373 /* dqm->lock mutex has to be locked before calling this function 2374 * 2375 * @grace_period: If USE_DEFAULT_GRACE_PERIOD then default wait time 2376 * for context switch latency. Lower values are used by debugger 2377 * since context switching are triggered at high frequency. 2378 * This is configured by setting CP_IQ_WAIT_TIME2.SCH_WAVE 2379 * 2380 */ 2381 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 2382 enum kfd_unmap_queues_filter filter, 2383 uint32_t filter_param, 2384 uint32_t grace_period, 2385 bool reset) 2386 { 2387 struct device *dev = dqm->dev->adev->dev; 2388 struct mqd_manager *mqd_mgr; 2389 int retval; 2390 2391 if (!dqm->sched_running) 2392 return 0; 2393 if (!dqm->active_runlist) 2394 return 0; 2395 if (!down_read_trylock(&dqm->dev->adev->reset_domain->sem)) 2396 return -EIO; 2397 2398 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 2399 retval = pm_config_dequeue_wait_counts(&dqm->packet_mgr, 2400 KFD_DEQUEUE_WAIT_SET_SCH_WAVE, grace_period); 2401 if (retval) 2402 goto out; 2403 } 2404 2405 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset); 2406 if (retval) 2407 goto out; 2408 2409 *dqm->fence_addr = KFD_FENCE_INIT; 2410 mb(); 2411 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, 2412 KFD_FENCE_COMPLETED); 2413 /* should be timed out */ 2414 retval = amdkfd_fence_wait_timeout(dqm, KFD_FENCE_COMPLETED, 2415 queue_preemption_timeout_ms); 2416 if (retval) { 2417 dev_err(dev, "The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n"); 2418 kfd_hws_hang(dqm); 2419 goto out; 2420 } 2421 2422 /* In the current MEC firmware implementation, if compute queue 2423 * doesn't response to the preemption request in time, HIQ will 2424 * abandon the unmap request without returning any timeout error 2425 * to driver. Instead, MEC firmware will log the doorbell of the 2426 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields. 2427 * To make sure the queue unmap was successful, driver need to 2428 * check those fields 2429 */ 2430 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; 2431 if (mqd_mgr->check_preemption_failed(mqd_mgr, dqm->packet_mgr.priv_queue->queue->mqd) && 2432 reset_queues_on_hws_hang(dqm, false)) 2433 goto reset_fail; 2434 2435 /* Check for SDMA hang and attempt SDMA reset */ 2436 if (sdma_has_hang(dqm) && reset_queues_on_hws_hang(dqm, true)) 2437 goto reset_fail; 2438 2439 /* We need to reset the grace period value for this device */ 2440 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 2441 if (pm_config_dequeue_wait_counts(&dqm->packet_mgr, 2442 KFD_DEQUEUE_WAIT_RESET, 0 /* unused */)) 2443 dev_err(dev, "Failed to reset grace period\n"); 2444 } 2445 2446 pm_release_ib(&dqm->packet_mgr); 2447 dqm->active_runlist = false; 2448 out: 2449 up_read(&dqm->dev->adev->reset_domain->sem); 2450 return retval; 2451 2452 reset_fail: 2453 dqm->is_hws_hang = true; 2454 kfd_hws_hang(dqm); 2455 up_read(&dqm->dev->adev->reset_domain->sem); 2456 return -ETIME; 2457 } 2458 2459 /* only for compute queue */ 2460 static int reset_queues_cpsch(struct device_queue_manager *dqm, uint16_t pasid) 2461 { 2462 int retval; 2463 2464 dqm_lock(dqm); 2465 2466 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID, 2467 pasid, USE_DEFAULT_GRACE_PERIOD, true); 2468 2469 dqm_unlock(dqm); 2470 return retval; 2471 } 2472 2473 /* dqm->lock mutex has to be locked before calling this function */ 2474 static int execute_queues_cpsch(struct device_queue_manager *dqm, 2475 enum kfd_unmap_queues_filter filter, 2476 uint32_t filter_param, 2477 uint32_t grace_period) 2478 { 2479 int retval; 2480 2481 if (!down_read_trylock(&dqm->dev->adev->reset_domain->sem)) 2482 return -EIO; 2483 retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false); 2484 if (!retval) 2485 retval = map_queues_cpsch(dqm); 2486 up_read(&dqm->dev->adev->reset_domain->sem); 2487 return retval; 2488 } 2489 2490 static int wait_on_destroy_queue(struct device_queue_manager *dqm, 2491 struct queue *q) 2492 { 2493 struct kfd_process_device *pdd = kfd_get_process_device_data(q->device, 2494 q->process); 2495 int ret = 0; 2496 2497 if (WARN_ON(!pdd)) 2498 return ret; 2499 2500 if (pdd->qpd.is_debug) 2501 return ret; 2502 2503 q->properties.is_being_destroyed = true; 2504 2505 if (pdd->process->debug_trap_enabled && q->properties.is_suspended) { 2506 dqm_unlock(dqm); 2507 mutex_unlock(&q->process->mutex); 2508 ret = wait_event_interruptible(dqm->destroy_wait, 2509 !q->properties.is_suspended); 2510 2511 mutex_lock(&q->process->mutex); 2512 dqm_lock(dqm); 2513 } 2514 2515 return ret; 2516 } 2517 2518 static int destroy_queue_cpsch(struct device_queue_manager *dqm, 2519 struct qcm_process_device *qpd, 2520 struct queue *q) 2521 { 2522 int retval; 2523 struct mqd_manager *mqd_mgr; 2524 uint64_t sdma_val = 0; 2525 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 2526 struct device *dev = dqm->dev->adev->dev; 2527 2528 /* Get the SDMA queue stats */ 2529 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 2530 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 2531 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 2532 &sdma_val); 2533 if (retval) 2534 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n", 2535 q->properties.queue_id); 2536 } 2537 2538 /* remove queue from list to prevent rescheduling after preemption */ 2539 dqm_lock(dqm); 2540 2541 retval = wait_on_destroy_queue(dqm, q); 2542 2543 if (retval) { 2544 dqm_unlock(dqm); 2545 return retval; 2546 } 2547 2548 if (qpd->is_debug) { 2549 /* 2550 * error, currently we do not allow to destroy a queue 2551 * of a currently debugged process 2552 */ 2553 retval = -EBUSY; 2554 goto failed_try_destroy_debugged_queue; 2555 2556 } 2557 2558 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2559 q->properties.type)]; 2560 2561 deallocate_doorbell(qpd, q); 2562 2563 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 2564 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 2565 deallocate_sdma_queue(dqm, q); 2566 pdd->sdma_past_activity_counter += sdma_val; 2567 } 2568 2569 if (q->properties.is_active) { 2570 decrement_queue_count(dqm, qpd, q); 2571 q->properties.is_active = false; 2572 if (!dqm->dev->kfd->shared_resources.enable_mes) { 2573 retval = execute_queues_cpsch(dqm, 2574 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 2575 USE_DEFAULT_GRACE_PERIOD); 2576 if (retval == -ETIME) 2577 qpd->reset_wavefronts = true; 2578 } else { 2579 retval = remove_queue_mes(dqm, q, qpd); 2580 } 2581 } 2582 list_del(&q->list); 2583 qpd->queue_count--; 2584 2585 /* 2586 * Unconditionally decrement this counter, regardless of the queue's 2587 * type 2588 */ 2589 dqm->total_queue_count--; 2590 pr_debug("Total of %d queues are accountable so far\n", 2591 dqm->total_queue_count); 2592 2593 dqm_unlock(dqm); 2594 2595 /* 2596 * Do free_mqd and raise delete event after dqm_unlock(dqm) to avoid 2597 * circular locking 2598 */ 2599 kfd_dbg_ev_raise(KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE), 2600 qpd->pqm->process, q->device, 2601 -1, false, NULL, 0); 2602 2603 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2604 2605 return retval; 2606 2607 failed_try_destroy_debugged_queue: 2608 2609 dqm_unlock(dqm); 2610 return retval; 2611 } 2612 2613 static bool set_cache_memory_policy(struct device_queue_manager *dqm, 2614 struct qcm_process_device *qpd, 2615 enum cache_policy default_policy, 2616 enum cache_policy alternate_policy, 2617 void __user *alternate_aperture_base, 2618 uint64_t alternate_aperture_size, 2619 u32 misc_process_properties) 2620 { 2621 bool retval = true; 2622 2623 if (!dqm->asic_ops.set_cache_memory_policy) 2624 return retval; 2625 2626 dqm_lock(dqm); 2627 2628 retval = dqm->asic_ops.set_cache_memory_policy( 2629 dqm, 2630 qpd, 2631 default_policy, 2632 alternate_policy, 2633 alternate_aperture_base, 2634 alternate_aperture_size, 2635 misc_process_properties); 2636 2637 if (retval) 2638 goto out; 2639 2640 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) 2641 program_sh_mem_settings(dqm, qpd); 2642 2643 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", 2644 qpd->sh_mem_config, qpd->sh_mem_ape1_base, 2645 qpd->sh_mem_ape1_limit); 2646 2647 out: 2648 dqm_unlock(dqm); 2649 return retval; 2650 } 2651 2652 static int process_termination_nocpsch(struct device_queue_manager *dqm, 2653 struct qcm_process_device *qpd) 2654 { 2655 struct queue *q; 2656 struct device_process_node *cur, *next_dpn; 2657 int retval = 0; 2658 bool found = false; 2659 2660 dqm_lock(dqm); 2661 2662 /* Clear all user mode queues */ 2663 while (!list_empty(&qpd->queues_list)) { 2664 struct mqd_manager *mqd_mgr; 2665 int ret; 2666 2667 q = list_first_entry(&qpd->queues_list, struct queue, list); 2668 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2669 q->properties.type)]; 2670 ret = destroy_queue_nocpsch_locked(dqm, qpd, q); 2671 if (ret) 2672 retval = ret; 2673 dqm_unlock(dqm); 2674 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2675 dqm_lock(dqm); 2676 } 2677 2678 /* Unregister process */ 2679 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 2680 if (qpd == cur->qpd) { 2681 list_del(&cur->list); 2682 kfree(cur); 2683 dqm->processes_count--; 2684 found = true; 2685 break; 2686 } 2687 } 2688 2689 dqm_unlock(dqm); 2690 2691 /* Outside the DQM lock because under the DQM lock we can't do 2692 * reclaim or take other locks that others hold while reclaiming. 2693 */ 2694 if (found) 2695 kfd_dec_compute_active(dqm->dev); 2696 2697 return retval; 2698 } 2699 2700 static int get_wave_state(struct device_queue_manager *dqm, 2701 struct queue *q, 2702 void __user *ctl_stack, 2703 u32 *ctl_stack_used_size, 2704 u32 *save_area_used_size) 2705 { 2706 struct mqd_manager *mqd_mgr; 2707 2708 dqm_lock(dqm); 2709 2710 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 2711 2712 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || 2713 q->properties.is_active || !q->device->kfd->cwsr_enabled || 2714 !mqd_mgr->get_wave_state) { 2715 dqm_unlock(dqm); 2716 return -EINVAL; 2717 } 2718 2719 dqm_unlock(dqm); 2720 2721 /* 2722 * get_wave_state is outside the dqm lock to prevent circular locking 2723 * and the queue should be protected against destruction by the process 2724 * lock. 2725 */ 2726 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, &q->properties, 2727 ctl_stack, ctl_stack_used_size, save_area_used_size); 2728 } 2729 2730 static void get_queue_checkpoint_info(struct device_queue_manager *dqm, 2731 const struct queue *q, 2732 u32 *mqd_size, 2733 u32 *ctl_stack_size) 2734 { 2735 struct mqd_manager *mqd_mgr; 2736 enum KFD_MQD_TYPE mqd_type = 2737 get_mqd_type_from_queue_type(q->properties.type); 2738 2739 dqm_lock(dqm); 2740 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 2741 *mqd_size = mqd_mgr->mqd_size * NUM_XCC(mqd_mgr->dev->xcc_mask); 2742 *ctl_stack_size = 0; 2743 2744 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info) 2745 mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size); 2746 2747 dqm_unlock(dqm); 2748 } 2749 2750 static int checkpoint_mqd(struct device_queue_manager *dqm, 2751 const struct queue *q, 2752 void *mqd, 2753 void *ctl_stack) 2754 { 2755 struct mqd_manager *mqd_mgr; 2756 int r = 0; 2757 enum KFD_MQD_TYPE mqd_type = 2758 get_mqd_type_from_queue_type(q->properties.type); 2759 2760 dqm_lock(dqm); 2761 2762 if (q->properties.is_active || !q->device->kfd->cwsr_enabled) { 2763 r = -EINVAL; 2764 goto dqm_unlock; 2765 } 2766 2767 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 2768 if (!mqd_mgr->checkpoint_mqd) { 2769 r = -EOPNOTSUPP; 2770 goto dqm_unlock; 2771 } 2772 2773 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack); 2774 2775 dqm_unlock: 2776 dqm_unlock(dqm); 2777 return r; 2778 } 2779 2780 static int process_termination_cpsch(struct device_queue_manager *dqm, 2781 struct qcm_process_device *qpd) 2782 { 2783 int retval; 2784 struct queue *q; 2785 struct device *dev = dqm->dev->adev->dev; 2786 struct kernel_queue *kq, *kq_next; 2787 struct mqd_manager *mqd_mgr; 2788 struct device_process_node *cur, *next_dpn; 2789 enum kfd_unmap_queues_filter filter = 2790 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; 2791 bool found = false; 2792 2793 retval = 0; 2794 2795 dqm_lock(dqm); 2796 2797 /* Clean all kernel queues */ 2798 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) { 2799 list_del(&kq->list); 2800 decrement_queue_count(dqm, qpd, kq->queue); 2801 qpd->is_debug = false; 2802 dqm->total_queue_count--; 2803 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES; 2804 } 2805 2806 /* Clear all user mode queues */ 2807 list_for_each_entry(q, &qpd->queues_list, list) { 2808 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 2809 deallocate_sdma_queue(dqm, q); 2810 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 2811 deallocate_sdma_queue(dqm, q); 2812 2813 if (q->properties.is_active) { 2814 decrement_queue_count(dqm, qpd, q); 2815 2816 if (dqm->dev->kfd->shared_resources.enable_mes) { 2817 retval = remove_queue_mes(dqm, q, qpd); 2818 if (retval) 2819 dev_err(dev, "Failed to remove queue %d\n", 2820 q->properties.queue_id); 2821 } 2822 } 2823 2824 dqm->total_queue_count--; 2825 } 2826 2827 /* Unregister process */ 2828 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 2829 if (qpd == cur->qpd) { 2830 list_del(&cur->list); 2831 kfree(cur); 2832 dqm->processes_count--; 2833 found = true; 2834 break; 2835 } 2836 } 2837 2838 if (!dqm->dev->kfd->shared_resources.enable_mes) 2839 retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD); 2840 2841 if ((retval || qpd->reset_wavefronts) && 2842 down_read_trylock(&dqm->dev->adev->reset_domain->sem)) { 2843 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev); 2844 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process); 2845 qpd->reset_wavefronts = false; 2846 up_read(&dqm->dev->adev->reset_domain->sem); 2847 } 2848 2849 /* Lastly, free mqd resources. 2850 * Do free_mqd() after dqm_unlock to avoid circular locking. 2851 */ 2852 while (!list_empty(&qpd->queues_list)) { 2853 q = list_first_entry(&qpd->queues_list, struct queue, list); 2854 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2855 q->properties.type)]; 2856 list_del(&q->list); 2857 qpd->queue_count--; 2858 dqm_unlock(dqm); 2859 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2860 dqm_lock(dqm); 2861 } 2862 dqm_unlock(dqm); 2863 2864 /* Outside the DQM lock because under the DQM lock we can't do 2865 * reclaim or take other locks that others hold while reclaiming. 2866 */ 2867 if (found) 2868 kfd_dec_compute_active(dqm->dev); 2869 2870 return retval; 2871 } 2872 2873 static int init_mqd_managers(struct device_queue_manager *dqm) 2874 { 2875 int i, j; 2876 struct device *dev = dqm->dev->adev->dev; 2877 struct mqd_manager *mqd_mgr; 2878 2879 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) { 2880 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev); 2881 if (!mqd_mgr) { 2882 dev_err(dev, "mqd manager [%d] initialization failed\n", i); 2883 goto out_free; 2884 } 2885 dqm->mqd_mgrs[i] = mqd_mgr; 2886 } 2887 2888 return 0; 2889 2890 out_free: 2891 for (j = 0; j < i; j++) { 2892 kfree(dqm->mqd_mgrs[j]); 2893 dqm->mqd_mgrs[j] = NULL; 2894 } 2895 2896 return -ENOMEM; 2897 } 2898 2899 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/ 2900 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) 2901 { 2902 int retval; 2903 struct kfd_node *dev = dqm->dev; 2904 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd; 2905 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * 2906 get_num_all_sdma_engines(dqm) * 2907 dev->kfd->device_info.num_sdma_queues_per_engine + 2908 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size * 2909 NUM_XCC(dqm->dev->xcc_mask)); 2910 2911 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size, 2912 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), 2913 (void *)&(mem_obj->cpu_ptr), false); 2914 2915 return retval; 2916 } 2917 2918 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) 2919 { 2920 struct device_queue_manager *dqm; 2921 2922 pr_debug("Loading device queue manager\n"); 2923 2924 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL); 2925 if (!dqm) 2926 return NULL; 2927 2928 switch (dev->adev->asic_type) { 2929 /* HWS is not available on Hawaii. */ 2930 case CHIP_HAWAII: 2931 /* HWS depends on CWSR for timely dequeue. CWSR is not 2932 * available on Tonga. 2933 * 2934 * FIXME: This argument also applies to Kaveri. 2935 */ 2936 case CHIP_TONGA: 2937 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS; 2938 break; 2939 default: 2940 dqm->sched_policy = sched_policy; 2941 break; 2942 } 2943 2944 dqm->dev = dev; 2945 switch (dqm->sched_policy) { 2946 case KFD_SCHED_POLICY_HWS: 2947 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: 2948 /* initialize dqm for cp scheduling */ 2949 dqm->ops.create_queue = create_queue_cpsch; 2950 dqm->ops.initialize = initialize_cpsch; 2951 dqm->ops.start = start_cpsch; 2952 dqm->ops.stop = stop_cpsch; 2953 dqm->ops.halt = halt_cpsch; 2954 dqm->ops.unhalt = unhalt_cpsch; 2955 dqm->ops.destroy_queue = destroy_queue_cpsch; 2956 dqm->ops.update_queue = update_queue; 2957 dqm->ops.register_process = register_process; 2958 dqm->ops.unregister_process = unregister_process; 2959 dqm->ops.uninitialize = uninitialize; 2960 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; 2961 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; 2962 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 2963 dqm->ops.process_termination = process_termination_cpsch; 2964 dqm->ops.evict_process_queues = evict_process_queues_cpsch; 2965 dqm->ops.restore_process_queues = restore_process_queues_cpsch; 2966 dqm->ops.get_wave_state = get_wave_state; 2967 dqm->ops.reset_queues = reset_queues_cpsch; 2968 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 2969 dqm->ops.checkpoint_mqd = checkpoint_mqd; 2970 break; 2971 case KFD_SCHED_POLICY_NO_HWS: 2972 /* initialize dqm for no cp scheduling */ 2973 dqm->ops.start = start_nocpsch; 2974 dqm->ops.stop = stop_nocpsch; 2975 dqm->ops.create_queue = create_queue_nocpsch; 2976 dqm->ops.destroy_queue = destroy_queue_nocpsch; 2977 dqm->ops.update_queue = update_queue; 2978 dqm->ops.register_process = register_process; 2979 dqm->ops.unregister_process = unregister_process; 2980 dqm->ops.initialize = initialize_nocpsch; 2981 dqm->ops.uninitialize = uninitialize; 2982 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 2983 dqm->ops.process_termination = process_termination_nocpsch; 2984 dqm->ops.evict_process_queues = evict_process_queues_nocpsch; 2985 dqm->ops.restore_process_queues = 2986 restore_process_queues_nocpsch; 2987 dqm->ops.get_wave_state = get_wave_state; 2988 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 2989 dqm->ops.checkpoint_mqd = checkpoint_mqd; 2990 break; 2991 default: 2992 dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); 2993 goto out_free; 2994 } 2995 2996 switch (dev->adev->asic_type) { 2997 case CHIP_KAVERI: 2998 case CHIP_HAWAII: 2999 device_queue_manager_init_cik(&dqm->asic_ops); 3000 break; 3001 3002 case CHIP_CARRIZO: 3003 case CHIP_TONGA: 3004 case CHIP_FIJI: 3005 case CHIP_POLARIS10: 3006 case CHIP_POLARIS11: 3007 case CHIP_POLARIS12: 3008 case CHIP_VEGAM: 3009 device_queue_manager_init_vi(&dqm->asic_ops); 3010 break; 3011 3012 default: 3013 if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 0, 0)) 3014 device_queue_manager_init_v12(&dqm->asic_ops); 3015 else if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0)) 3016 device_queue_manager_init_v11(&dqm->asic_ops); 3017 else if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1)) 3018 device_queue_manager_init_v10(&dqm->asic_ops); 3019 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) 3020 device_queue_manager_init_v9(&dqm->asic_ops); 3021 else { 3022 WARN(1, "Unexpected ASIC family %u", 3023 dev->adev->asic_type); 3024 goto out_free; 3025 } 3026 } 3027 3028 if (init_mqd_managers(dqm)) 3029 goto out_free; 3030 3031 if (!dev->kfd->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) { 3032 dev_err(dev->adev->dev, "Failed to allocate hiq sdma mqd trunk buffer\n"); 3033 goto out_free; 3034 } 3035 3036 if (!dqm->ops.initialize(dqm)) { 3037 init_waitqueue_head(&dqm->destroy_wait); 3038 return dqm; 3039 } 3040 3041 out_free: 3042 kfree(dqm); 3043 return NULL; 3044 } 3045 3046 static void deallocate_hiq_sdma_mqd(struct kfd_node *dev, 3047 struct kfd_mem_obj *mqd) 3048 { 3049 WARN(!mqd, "No hiq sdma mqd trunk to free"); 3050 3051 amdgpu_amdkfd_free_gtt_mem(dev->adev, &mqd->gtt_mem); 3052 } 3053 3054 void device_queue_manager_uninit(struct device_queue_manager *dqm) 3055 { 3056 dqm->ops.stop(dqm); 3057 dqm->ops.uninitialize(dqm); 3058 if (!dqm->dev->kfd->shared_resources.enable_mes) 3059 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd); 3060 kfree(dqm); 3061 } 3062 3063 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id) 3064 { 3065 struct kfd_process_device *pdd = NULL; 3066 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, &pdd); 3067 struct device_queue_manager *dqm = knode->dqm; 3068 struct device *dev = dqm->dev->adev->dev; 3069 struct qcm_process_device *qpd; 3070 struct queue *q = NULL; 3071 int ret = 0; 3072 3073 if (!pdd) 3074 return -EINVAL; 3075 3076 dqm_lock(dqm); 3077 3078 if (pdd) { 3079 qpd = &pdd->qpd; 3080 3081 list_for_each_entry(q, &qpd->queues_list, list) { 3082 if (q->doorbell_id == doorbell_id && q->properties.is_active) { 3083 ret = suspend_all_queues_mes(dqm); 3084 if (ret) { 3085 dev_err(dev, "Suspending all queues failed"); 3086 goto out; 3087 } 3088 3089 q->properties.is_evicted = true; 3090 q->properties.is_active = false; 3091 decrement_queue_count(dqm, qpd, q); 3092 3093 ret = remove_queue_mes(dqm, q, qpd); 3094 if (ret) { 3095 dev_err(dev, "Removing bad queue failed"); 3096 goto out; 3097 } 3098 3099 ret = resume_all_queues_mes(dqm); 3100 if (ret) 3101 dev_err(dev, "Resuming all queues failed"); 3102 3103 break; 3104 } 3105 } 3106 } 3107 3108 out: 3109 dqm_unlock(dqm); 3110 kfd_unref_process(p); 3111 return ret; 3112 } 3113 3114 int kfd_evict_process_device(struct kfd_process_device *pdd) 3115 { 3116 struct device_queue_manager *dqm; 3117 struct kfd_process *p; 3118 3119 p = pdd->process; 3120 dqm = pdd->dev->dqm; 3121 3122 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 3123 3124 return dqm->ops.evict_process_queues(dqm, &pdd->qpd); 3125 } 3126 3127 int reserve_debug_trap_vmid(struct device_queue_manager *dqm, 3128 struct qcm_process_device *qpd) 3129 { 3130 int r; 3131 struct device *dev = dqm->dev->adev->dev; 3132 int updated_vmid_mask; 3133 3134 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3135 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3136 return -EINVAL; 3137 } 3138 3139 dqm_lock(dqm); 3140 3141 if (dqm->trap_debug_vmid != 0) { 3142 dev_err(dev, "Trap debug id already reserved\n"); 3143 r = -EBUSY; 3144 goto out_unlock; 3145 } 3146 3147 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 3148 USE_DEFAULT_GRACE_PERIOD, false); 3149 if (r) 3150 goto out_unlock; 3151 3152 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap; 3153 updated_vmid_mask &= ~(1 << dqm->dev->vm_info.last_vmid_kfd); 3154 3155 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask; 3156 dqm->trap_debug_vmid = dqm->dev->vm_info.last_vmid_kfd; 3157 r = set_sched_resources(dqm); 3158 if (r) 3159 goto out_unlock; 3160 3161 r = map_queues_cpsch(dqm); 3162 if (r) 3163 goto out_unlock; 3164 3165 pr_debug("Reserved VMID for trap debug: %i\n", dqm->trap_debug_vmid); 3166 3167 out_unlock: 3168 dqm_unlock(dqm); 3169 return r; 3170 } 3171 3172 /* 3173 * Releases vmid for the trap debugger 3174 */ 3175 int release_debug_trap_vmid(struct device_queue_manager *dqm, 3176 struct qcm_process_device *qpd) 3177 { 3178 struct device *dev = dqm->dev->adev->dev; 3179 int r; 3180 int updated_vmid_mask; 3181 uint32_t trap_debug_vmid; 3182 3183 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3184 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3185 return -EINVAL; 3186 } 3187 3188 dqm_lock(dqm); 3189 trap_debug_vmid = dqm->trap_debug_vmid; 3190 if (dqm->trap_debug_vmid == 0) { 3191 dev_err(dev, "Trap debug id is not reserved\n"); 3192 r = -EINVAL; 3193 goto out_unlock; 3194 } 3195 3196 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 3197 USE_DEFAULT_GRACE_PERIOD, false); 3198 if (r) 3199 goto out_unlock; 3200 3201 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap; 3202 updated_vmid_mask |= (1 << dqm->dev->vm_info.last_vmid_kfd); 3203 3204 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask; 3205 dqm->trap_debug_vmid = 0; 3206 r = set_sched_resources(dqm); 3207 if (r) 3208 goto out_unlock; 3209 3210 r = map_queues_cpsch(dqm); 3211 if (r) 3212 goto out_unlock; 3213 3214 pr_debug("Released VMID for trap debug: %i\n", trap_debug_vmid); 3215 3216 out_unlock: 3217 dqm_unlock(dqm); 3218 return r; 3219 } 3220 3221 #define QUEUE_NOT_FOUND -1 3222 /* invalidate queue operation in array */ 3223 static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids) 3224 { 3225 int i; 3226 3227 for (i = 0; i < num_queues; i++) 3228 queue_ids[i] |= KFD_DBG_QUEUE_INVALID_MASK; 3229 } 3230 3231 /* find queue index in array */ 3232 static int q_array_get_index(unsigned int queue_id, 3233 uint32_t num_queues, 3234 uint32_t *queue_ids) 3235 { 3236 int i; 3237 3238 for (i = 0; i < num_queues; i++) 3239 if (queue_id == (queue_ids[i] & ~KFD_DBG_QUEUE_INVALID_MASK)) 3240 return i; 3241 3242 return QUEUE_NOT_FOUND; 3243 } 3244 3245 struct copy_context_work_handler_workarea { 3246 struct work_struct copy_context_work; 3247 struct kfd_process *p; 3248 }; 3249 3250 static void copy_context_work_handler(struct work_struct *work) 3251 { 3252 struct copy_context_work_handler_workarea *workarea; 3253 struct mqd_manager *mqd_mgr; 3254 struct queue *q; 3255 struct mm_struct *mm; 3256 struct kfd_process *p; 3257 uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size; 3258 int i; 3259 3260 workarea = container_of(work, 3261 struct copy_context_work_handler_workarea, 3262 copy_context_work); 3263 3264 p = workarea->p; 3265 mm = get_task_mm(p->lead_thread); 3266 3267 if (!mm) 3268 return; 3269 3270 kthread_use_mm(mm); 3271 for (i = 0; i < p->n_pdds; i++) { 3272 struct kfd_process_device *pdd = p->pdds[i]; 3273 struct device_queue_manager *dqm = pdd->dev->dqm; 3274 struct qcm_process_device *qpd = &pdd->qpd; 3275 3276 list_for_each_entry(q, &qpd->queues_list, list) { 3277 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE) 3278 continue; 3279 3280 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 3281 3282 /* We ignore the return value from get_wave_state 3283 * because 3284 * i) right now, it always returns 0, and 3285 * ii) if we hit an error, we would continue to the 3286 * next queue anyway. 3287 */ 3288 mqd_mgr->get_wave_state(mqd_mgr, 3289 q->mqd, 3290 &q->properties, 3291 (void __user *) q->properties.ctx_save_restore_area_address, 3292 &tmp_ctl_stack_used_size, 3293 &tmp_save_area_used_size); 3294 } 3295 } 3296 kthread_unuse_mm(mm); 3297 mmput(mm); 3298 } 3299 3300 static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array) 3301 { 3302 size_t array_size = num_queues * sizeof(uint32_t); 3303 3304 if (!usr_queue_id_array) 3305 return NULL; 3306 3307 return memdup_user(usr_queue_id_array, array_size); 3308 } 3309 3310 int resume_queues(struct kfd_process *p, 3311 uint32_t num_queues, 3312 uint32_t *usr_queue_id_array) 3313 { 3314 uint32_t *queue_ids = NULL; 3315 int total_resumed = 0; 3316 int i; 3317 3318 if (usr_queue_id_array) { 3319 queue_ids = get_queue_ids(num_queues, usr_queue_id_array); 3320 3321 if (IS_ERR(queue_ids)) 3322 return PTR_ERR(queue_ids); 3323 3324 /* mask all queues as invalid. unmask per successful request */ 3325 q_array_invalidate(num_queues, queue_ids); 3326 } 3327 3328 for (i = 0; i < p->n_pdds; i++) { 3329 struct kfd_process_device *pdd = p->pdds[i]; 3330 struct device_queue_manager *dqm = pdd->dev->dqm; 3331 struct device *dev = dqm->dev->adev->dev; 3332 struct qcm_process_device *qpd = &pdd->qpd; 3333 struct queue *q; 3334 int r, per_device_resumed = 0; 3335 3336 dqm_lock(dqm); 3337 3338 /* unmask queues that resume or already resumed as valid */ 3339 list_for_each_entry(q, &qpd->queues_list, list) { 3340 int q_idx = QUEUE_NOT_FOUND; 3341 3342 if (queue_ids) 3343 q_idx = q_array_get_index( 3344 q->properties.queue_id, 3345 num_queues, 3346 queue_ids); 3347 3348 if (!queue_ids || q_idx != QUEUE_NOT_FOUND) { 3349 int err = resume_single_queue(dqm, &pdd->qpd, q); 3350 3351 if (queue_ids) { 3352 if (!err) { 3353 queue_ids[q_idx] &= 3354 ~KFD_DBG_QUEUE_INVALID_MASK; 3355 } else { 3356 queue_ids[q_idx] |= 3357 KFD_DBG_QUEUE_ERROR_MASK; 3358 break; 3359 } 3360 } 3361 3362 if (dqm->dev->kfd->shared_resources.enable_mes) { 3363 wake_up_all(&dqm->destroy_wait); 3364 if (!err) 3365 total_resumed++; 3366 } else { 3367 per_device_resumed++; 3368 } 3369 } 3370 } 3371 3372 if (!per_device_resumed) { 3373 dqm_unlock(dqm); 3374 continue; 3375 } 3376 3377 r = execute_queues_cpsch(dqm, 3378 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 3379 0, 3380 USE_DEFAULT_GRACE_PERIOD); 3381 if (r) { 3382 dev_err(dev, "Failed to resume process queues\n"); 3383 if (queue_ids) { 3384 list_for_each_entry(q, &qpd->queues_list, list) { 3385 int q_idx = q_array_get_index( 3386 q->properties.queue_id, 3387 num_queues, 3388 queue_ids); 3389 3390 /* mask queue as error on resume fail */ 3391 if (q_idx != QUEUE_NOT_FOUND) 3392 queue_ids[q_idx] |= 3393 KFD_DBG_QUEUE_ERROR_MASK; 3394 } 3395 } 3396 } else { 3397 wake_up_all(&dqm->destroy_wait); 3398 total_resumed += per_device_resumed; 3399 } 3400 3401 dqm_unlock(dqm); 3402 } 3403 3404 if (queue_ids) { 3405 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids, 3406 num_queues * sizeof(uint32_t))) 3407 pr_err("copy_to_user failed on queue resume\n"); 3408 3409 kfree(queue_ids); 3410 } 3411 3412 return total_resumed; 3413 } 3414 3415 int suspend_queues(struct kfd_process *p, 3416 uint32_t num_queues, 3417 uint32_t grace_period, 3418 uint64_t exception_clear_mask, 3419 uint32_t *usr_queue_id_array) 3420 { 3421 uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array); 3422 int total_suspended = 0; 3423 int i; 3424 3425 if (IS_ERR(queue_ids)) 3426 return PTR_ERR(queue_ids); 3427 3428 /* mask all queues as invalid. umask on successful request */ 3429 q_array_invalidate(num_queues, queue_ids); 3430 3431 for (i = 0; i < p->n_pdds; i++) { 3432 struct kfd_process_device *pdd = p->pdds[i]; 3433 struct device_queue_manager *dqm = pdd->dev->dqm; 3434 struct device *dev = dqm->dev->adev->dev; 3435 struct qcm_process_device *qpd = &pdd->qpd; 3436 struct queue *q; 3437 int r, per_device_suspended = 0; 3438 3439 mutex_lock(&p->event_mutex); 3440 dqm_lock(dqm); 3441 3442 /* unmask queues that suspend or already suspended */ 3443 list_for_each_entry(q, &qpd->queues_list, list) { 3444 int q_idx = q_array_get_index(q->properties.queue_id, 3445 num_queues, 3446 queue_ids); 3447 3448 if (q_idx != QUEUE_NOT_FOUND) { 3449 int err = suspend_single_queue(dqm, pdd, q); 3450 bool is_mes = dqm->dev->kfd->shared_resources.enable_mes; 3451 3452 if (!err) { 3453 queue_ids[q_idx] &= ~KFD_DBG_QUEUE_INVALID_MASK; 3454 if (exception_clear_mask && is_mes) 3455 q->properties.exception_status &= 3456 ~exception_clear_mask; 3457 3458 if (is_mes) 3459 total_suspended++; 3460 else 3461 per_device_suspended++; 3462 } else if (err != -EBUSY) { 3463 r = err; 3464 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 3465 break; 3466 } 3467 } 3468 } 3469 3470 if (!per_device_suspended) { 3471 dqm_unlock(dqm); 3472 mutex_unlock(&p->event_mutex); 3473 if (total_suspended) 3474 amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev); 3475 continue; 3476 } 3477 3478 r = execute_queues_cpsch(dqm, 3479 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 3480 grace_period); 3481 3482 if (r) 3483 dev_err(dev, "Failed to suspend process queues.\n"); 3484 else 3485 total_suspended += per_device_suspended; 3486 3487 list_for_each_entry(q, &qpd->queues_list, list) { 3488 int q_idx = q_array_get_index(q->properties.queue_id, 3489 num_queues, queue_ids); 3490 3491 if (q_idx == QUEUE_NOT_FOUND) 3492 continue; 3493 3494 /* mask queue as error on suspend fail */ 3495 if (r) 3496 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 3497 else if (exception_clear_mask) 3498 q->properties.exception_status &= 3499 ~exception_clear_mask; 3500 } 3501 3502 dqm_unlock(dqm); 3503 mutex_unlock(&p->event_mutex); 3504 amdgpu_device_flush_hdp(dqm->dev->adev, NULL); 3505 } 3506 3507 if (total_suspended) { 3508 struct copy_context_work_handler_workarea copy_context_worker; 3509 3510 INIT_WORK_ONSTACK( 3511 ©_context_worker.copy_context_work, 3512 copy_context_work_handler); 3513 3514 copy_context_worker.p = p; 3515 3516 schedule_work(©_context_worker.copy_context_work); 3517 3518 3519 flush_work(©_context_worker.copy_context_work); 3520 destroy_work_on_stack(©_context_worker.copy_context_work); 3521 } 3522 3523 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids, 3524 num_queues * sizeof(uint32_t))) 3525 pr_err("copy_to_user failed on queue suspend\n"); 3526 3527 kfree(queue_ids); 3528 3529 return total_suspended; 3530 } 3531 3532 static uint32_t set_queue_type_for_user(struct queue_properties *q_props) 3533 { 3534 switch (q_props->type) { 3535 case KFD_QUEUE_TYPE_COMPUTE: 3536 return q_props->format == KFD_QUEUE_FORMAT_PM4 3537 ? KFD_IOC_QUEUE_TYPE_COMPUTE 3538 : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; 3539 case KFD_QUEUE_TYPE_SDMA: 3540 return KFD_IOC_QUEUE_TYPE_SDMA; 3541 case KFD_QUEUE_TYPE_SDMA_XGMI: 3542 return KFD_IOC_QUEUE_TYPE_SDMA_XGMI; 3543 default: 3544 WARN_ONCE(true, "queue type not recognized!"); 3545 return 0xffffffff; 3546 }; 3547 } 3548 3549 void set_queue_snapshot_entry(struct queue *q, 3550 uint64_t exception_clear_mask, 3551 struct kfd_queue_snapshot_entry *qss_entry) 3552 { 3553 qss_entry->ring_base_address = q->properties.queue_address; 3554 qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr; 3555 qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr; 3556 qss_entry->ctx_save_restore_address = 3557 q->properties.ctx_save_restore_area_address; 3558 qss_entry->ctx_save_restore_area_size = 3559 q->properties.ctx_save_restore_area_size; 3560 qss_entry->exception_status = q->properties.exception_status; 3561 qss_entry->queue_id = q->properties.queue_id; 3562 qss_entry->gpu_id = q->device->id; 3563 qss_entry->ring_size = (uint32_t)q->properties.queue_size; 3564 qss_entry->queue_type = set_queue_type_for_user(&q->properties); 3565 q->properties.exception_status &= ~exception_clear_mask; 3566 } 3567 3568 int debug_lock_and_unmap(struct device_queue_manager *dqm) 3569 { 3570 struct device *dev = dqm->dev->adev->dev; 3571 int r; 3572 3573 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3574 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3575 return -EINVAL; 3576 } 3577 3578 if (!kfd_dbg_is_per_vmid_supported(dqm->dev)) 3579 return 0; 3580 3581 dqm_lock(dqm); 3582 3583 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false); 3584 if (r) 3585 dqm_unlock(dqm); 3586 3587 return r; 3588 } 3589 3590 int debug_map_and_unlock(struct device_queue_manager *dqm) 3591 { 3592 struct device *dev = dqm->dev->adev->dev; 3593 int r; 3594 3595 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3596 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3597 return -EINVAL; 3598 } 3599 3600 if (!kfd_dbg_is_per_vmid_supported(dqm->dev)) 3601 return 0; 3602 3603 r = map_queues_cpsch(dqm); 3604 3605 dqm_unlock(dqm); 3606 3607 return r; 3608 } 3609 3610 int debug_refresh_runlist(struct device_queue_manager *dqm) 3611 { 3612 int r = debug_lock_and_unmap(dqm); 3613 3614 if (r) 3615 return r; 3616 3617 return debug_map_and_unlock(dqm); 3618 } 3619 3620 bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, 3621 struct qcm_process_device *qpd, 3622 int doorbell_off, u32 *queue_format) 3623 { 3624 struct queue *q; 3625 bool r = false; 3626 3627 if (!queue_format) 3628 return r; 3629 3630 dqm_lock(dqm); 3631 3632 list_for_each_entry(q, &qpd->queues_list, list) { 3633 if (q->properties.doorbell_off == doorbell_off) { 3634 *queue_format = q->properties.format; 3635 r = true; 3636 goto out; 3637 } 3638 } 3639 3640 out: 3641 dqm_unlock(dqm); 3642 return r; 3643 } 3644 #if defined(CONFIG_DEBUG_FS) 3645 3646 static void seq_reg_dump(struct seq_file *m, 3647 uint32_t (*dump)[2], uint32_t n_regs) 3648 { 3649 uint32_t i, count; 3650 3651 for (i = 0, count = 0; i < n_regs; i++) { 3652 if (count == 0 || 3653 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { 3654 seq_printf(m, "%s %08x: %08x", 3655 i ? "\n" : "", 3656 dump[i][0], dump[i][1]); 3657 count = 7; 3658 } else { 3659 seq_printf(m, " %08x", dump[i][1]); 3660 count--; 3661 } 3662 } 3663 3664 seq_puts(m, "\n"); 3665 } 3666 3667 int dqm_debugfs_hqds(struct seq_file *m, void *data) 3668 { 3669 struct device_queue_manager *dqm = data; 3670 uint32_t xcc_mask = dqm->dev->xcc_mask; 3671 uint32_t (*dump)[2], n_regs; 3672 int pipe, queue; 3673 int r = 0, xcc_id; 3674 uint32_t sdma_engine_start; 3675 3676 if (!dqm->sched_running) { 3677 seq_puts(m, " Device is stopped\n"); 3678 return 0; 3679 } 3680 3681 for_each_inst(xcc_id, xcc_mask) { 3682 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 3683 KFD_CIK_HIQ_PIPE, 3684 KFD_CIK_HIQ_QUEUE, &dump, 3685 &n_regs, xcc_id); 3686 if (!r) { 3687 seq_printf( 3688 m, 3689 " Inst %d, HIQ on MEC %d Pipe %d Queue %d\n", 3690 xcc_id, 3691 KFD_CIK_HIQ_PIPE / get_pipes_per_mec(dqm) + 1, 3692 KFD_CIK_HIQ_PIPE % get_pipes_per_mec(dqm), 3693 KFD_CIK_HIQ_QUEUE); 3694 seq_reg_dump(m, dump, n_regs); 3695 3696 kfree(dump); 3697 } 3698 3699 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 3700 int pipe_offset = pipe * get_queues_per_pipe(dqm); 3701 3702 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) { 3703 if (!test_bit(pipe_offset + queue, 3704 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 3705 continue; 3706 3707 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 3708 pipe, queue, 3709 &dump, &n_regs, 3710 xcc_id); 3711 if (r) 3712 break; 3713 3714 seq_printf(m, 3715 " Inst %d, CP Pipe %d, Queue %d\n", 3716 xcc_id, pipe, queue); 3717 seq_reg_dump(m, dump, n_regs); 3718 3719 kfree(dump); 3720 } 3721 } 3722 } 3723 3724 sdma_engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 3725 for (pipe = sdma_engine_start; 3726 pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm)); 3727 pipe++) { 3728 for (queue = 0; 3729 queue < dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 3730 queue++) { 3731 r = dqm->dev->kfd2kgd->hqd_sdma_dump( 3732 dqm->dev->adev, pipe, queue, &dump, &n_regs); 3733 if (r) 3734 break; 3735 3736 seq_printf(m, " SDMA Engine %d, RLC %d\n", 3737 pipe, queue); 3738 seq_reg_dump(m, dump, n_regs); 3739 3740 kfree(dump); 3741 } 3742 } 3743 3744 return r; 3745 } 3746 3747 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm) 3748 { 3749 int r = 0; 3750 3751 dqm_lock(dqm); 3752 r = pm_debugfs_hang_hws(&dqm->packet_mgr); 3753 if (r) { 3754 dqm_unlock(dqm); 3755 return r; 3756 } 3757 dqm->active_runlist = true; 3758 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 3759 0, USE_DEFAULT_GRACE_PERIOD); 3760 dqm_unlock(dqm); 3761 3762 return r; 3763 } 3764 3765 #endif 3766