1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/ratelimit.h> 26 #include <linux/printk.h> 27 #include <linux/slab.h> 28 #include <linux/list.h> 29 #include <linux/types.h> 30 #include <linux/bitops.h> 31 #include <linux/sched.h> 32 #include "kfd_priv.h" 33 #include "kfd_device_queue_manager.h" 34 #include "kfd_mqd_manager.h" 35 #include "cik_regs.h" 36 #include "kfd_kernel_queue.h" 37 #include "amdgpu_amdkfd.h" 38 39 /* Size of the per-pipe EOP queue */ 40 #define CIK_HPD_EOP_BYTES_LOG2 11 41 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) 42 43 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, 44 u32 pasid, unsigned int vmid); 45 46 static int execute_queues_cpsch(struct device_queue_manager *dqm, 47 enum kfd_unmap_queues_filter filter, 48 uint32_t filter_param); 49 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 50 enum kfd_unmap_queues_filter filter, 51 uint32_t filter_param, bool reset); 52 53 static int map_queues_cpsch(struct device_queue_manager *dqm); 54 55 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 56 struct queue *q); 57 58 static inline void deallocate_hqd(struct device_queue_manager *dqm, 59 struct queue *q); 60 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q); 61 static int allocate_sdma_queue(struct device_queue_manager *dqm, 62 struct queue *q, const uint32_t *restore_sdma_id); 63 static void kfd_process_hw_exception(struct work_struct *work); 64 65 static inline 66 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) 67 { 68 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI) 69 return KFD_MQD_TYPE_SDMA; 70 return KFD_MQD_TYPE_CP; 71 } 72 73 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) 74 { 75 int i; 76 int pipe_offset = (mec * dqm->dev->shared_resources.num_pipe_per_mec 77 + pipe) * dqm->dev->shared_resources.num_queue_per_pipe; 78 79 /* queue is available for KFD usage if bit is 1 */ 80 for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i) 81 if (test_bit(pipe_offset + i, 82 dqm->dev->shared_resources.cp_queue_bitmap)) 83 return true; 84 return false; 85 } 86 87 unsigned int get_cp_queues_num(struct device_queue_manager *dqm) 88 { 89 return bitmap_weight(dqm->dev->shared_resources.cp_queue_bitmap, 90 KGD_MAX_QUEUES); 91 } 92 93 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) 94 { 95 return dqm->dev->shared_resources.num_queue_per_pipe; 96 } 97 98 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) 99 { 100 return dqm->dev->shared_resources.num_pipe_per_mec; 101 } 102 103 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm) 104 { 105 return kfd_get_num_sdma_engines(dqm->dev) + 106 kfd_get_num_xgmi_sdma_engines(dqm->dev); 107 } 108 109 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm) 110 { 111 return kfd_get_num_sdma_engines(dqm->dev) * 112 dqm->dev->device_info.num_sdma_queues_per_engine; 113 } 114 115 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm) 116 { 117 return kfd_get_num_xgmi_sdma_engines(dqm->dev) * 118 dqm->dev->device_info.num_sdma_queues_per_engine; 119 } 120 121 void program_sh_mem_settings(struct device_queue_manager *dqm, 122 struct qcm_process_device *qpd) 123 { 124 return dqm->dev->kfd2kgd->program_sh_mem_settings( 125 dqm->dev->adev, qpd->vmid, 126 qpd->sh_mem_config, 127 qpd->sh_mem_ape1_base, 128 qpd->sh_mem_ape1_limit, 129 qpd->sh_mem_bases); 130 } 131 132 static void increment_queue_count(struct device_queue_manager *dqm, 133 enum kfd_queue_type type) 134 { 135 dqm->active_queue_count++; 136 if (type == KFD_QUEUE_TYPE_COMPUTE || type == KFD_QUEUE_TYPE_DIQ) 137 dqm->active_cp_queue_count++; 138 } 139 140 static void decrement_queue_count(struct device_queue_manager *dqm, 141 enum kfd_queue_type type) 142 { 143 dqm->active_queue_count--; 144 if (type == KFD_QUEUE_TYPE_COMPUTE || type == KFD_QUEUE_TYPE_DIQ) 145 dqm->active_cp_queue_count--; 146 } 147 148 /* 149 * Allocate a doorbell ID to this queue. 150 * If doorbell_id is passed in, make sure requested ID is valid then allocate it. 151 */ 152 static int allocate_doorbell(struct qcm_process_device *qpd, 153 struct queue *q, 154 uint32_t const *restore_id) 155 { 156 struct kfd_dev *dev = qpd->dqm->dev; 157 158 if (!KFD_IS_SOC15(dev)) { 159 /* On pre-SOC15 chips we need to use the queue ID to 160 * preserve the user mode ABI. 161 */ 162 163 if (restore_id && *restore_id != q->properties.queue_id) 164 return -EINVAL; 165 166 q->doorbell_id = q->properties.queue_id; 167 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 168 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 169 /* For SDMA queues on SOC15 with 8-byte doorbell, use static 170 * doorbell assignments based on the engine and queue id. 171 * The doobell index distance between RLC (2*i) and (2*i+1) 172 * for a SDMA engine is 512. 173 */ 174 175 uint32_t *idx_offset = dev->shared_resources.sdma_doorbell_idx; 176 uint32_t valid_id = idx_offset[q->properties.sdma_engine_id] 177 + (q->properties.sdma_queue_id & 1) 178 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET 179 + (q->properties.sdma_queue_id >> 1); 180 181 if (restore_id && *restore_id != valid_id) 182 return -EINVAL; 183 q->doorbell_id = valid_id; 184 } else { 185 /* For CP queues on SOC15 */ 186 if (restore_id) { 187 /* make sure that ID is free */ 188 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap)) 189 return -EINVAL; 190 191 q->doorbell_id = *restore_id; 192 } else { 193 /* or reserve a free doorbell ID */ 194 unsigned int found; 195 196 found = find_first_zero_bit(qpd->doorbell_bitmap, 197 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 198 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 199 pr_debug("No doorbells available"); 200 return -EBUSY; 201 } 202 set_bit(found, qpd->doorbell_bitmap); 203 q->doorbell_id = found; 204 } 205 } 206 207 q->properties.doorbell_off = 208 kfd_get_doorbell_dw_offset_in_bar(dev, qpd_to_pdd(qpd), 209 q->doorbell_id); 210 return 0; 211 } 212 213 static void deallocate_doorbell(struct qcm_process_device *qpd, 214 struct queue *q) 215 { 216 unsigned int old; 217 struct kfd_dev *dev = qpd->dqm->dev; 218 219 if (!KFD_IS_SOC15(dev) || 220 q->properties.type == KFD_QUEUE_TYPE_SDMA || 221 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 222 return; 223 224 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap); 225 WARN_ON(!old); 226 } 227 228 static void program_trap_handler_settings(struct device_queue_manager *dqm, 229 struct qcm_process_device *qpd) 230 { 231 if (dqm->dev->kfd2kgd->program_trap_handler_settings) 232 dqm->dev->kfd2kgd->program_trap_handler_settings( 233 dqm->dev->adev, qpd->vmid, 234 qpd->tba_addr, qpd->tma_addr); 235 } 236 237 static int allocate_vmid(struct device_queue_manager *dqm, 238 struct qcm_process_device *qpd, 239 struct queue *q) 240 { 241 int allocated_vmid = -1, i; 242 243 for (i = dqm->dev->vm_info.first_vmid_kfd; 244 i <= dqm->dev->vm_info.last_vmid_kfd; i++) { 245 if (!dqm->vmid_pasid[i]) { 246 allocated_vmid = i; 247 break; 248 } 249 } 250 251 if (allocated_vmid < 0) { 252 pr_err("no more vmid to allocate\n"); 253 return -ENOSPC; 254 } 255 256 pr_debug("vmid allocated: %d\n", allocated_vmid); 257 258 dqm->vmid_pasid[allocated_vmid] = q->process->pasid; 259 260 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid); 261 262 qpd->vmid = allocated_vmid; 263 q->properties.vmid = allocated_vmid; 264 265 program_sh_mem_settings(dqm, qpd); 266 267 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->cwsr_enabled) 268 program_trap_handler_settings(dqm, qpd); 269 270 /* qpd->page_table_base is set earlier when register_process() 271 * is called, i.e. when the first queue is created. 272 */ 273 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev, 274 qpd->vmid, 275 qpd->page_table_base); 276 /* invalidate the VM context after pasid and vmid mapping is set up */ 277 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 278 279 if (dqm->dev->kfd2kgd->set_scratch_backing_va) 280 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev, 281 qpd->sh_hidden_private_base, qpd->vmid); 282 283 return 0; 284 } 285 286 static int flush_texture_cache_nocpsch(struct kfd_dev *kdev, 287 struct qcm_process_device *qpd) 288 { 289 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf; 290 int ret; 291 292 if (!qpd->ib_kaddr) 293 return -ENOMEM; 294 295 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr); 296 if (ret) 297 return ret; 298 299 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid, 300 qpd->ib_base, (uint32_t *)qpd->ib_kaddr, 301 pmf->release_mem_size / sizeof(uint32_t)); 302 } 303 304 static void deallocate_vmid(struct device_queue_manager *dqm, 305 struct qcm_process_device *qpd, 306 struct queue *q) 307 { 308 /* On GFX v7, CP doesn't flush TC at dequeue */ 309 if (q->device->adev->asic_type == CHIP_HAWAII) 310 if (flush_texture_cache_nocpsch(q->device, qpd)) 311 pr_err("Failed to flush TC\n"); 312 313 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 314 315 /* Release the vmid mapping */ 316 set_pasid_vmid_mapping(dqm, 0, qpd->vmid); 317 dqm->vmid_pasid[qpd->vmid] = 0; 318 319 qpd->vmid = 0; 320 q->properties.vmid = 0; 321 } 322 323 static int create_queue_nocpsch(struct device_queue_manager *dqm, 324 struct queue *q, 325 struct qcm_process_device *qpd, 326 const struct kfd_criu_queue_priv_data *qd, 327 const void *restore_mqd, const void *restore_ctl_stack) 328 { 329 struct mqd_manager *mqd_mgr; 330 int retval; 331 332 dqm_lock(dqm); 333 334 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 335 pr_warn("Can't create new usermode queue because %d queues were already created\n", 336 dqm->total_queue_count); 337 retval = -EPERM; 338 goto out_unlock; 339 } 340 341 if (list_empty(&qpd->queues_list)) { 342 retval = allocate_vmid(dqm, qpd, q); 343 if (retval) 344 goto out_unlock; 345 } 346 q->properties.vmid = qpd->vmid; 347 /* 348 * Eviction state logic: mark all queues as evicted, even ones 349 * not currently active. Restoring inactive queues later only 350 * updates the is_evicted flag but is a no-op otherwise. 351 */ 352 q->properties.is_evicted = !!qpd->evicted; 353 354 q->properties.tba_addr = qpd->tba_addr; 355 q->properties.tma_addr = qpd->tma_addr; 356 357 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 358 q->properties.type)]; 359 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { 360 retval = allocate_hqd(dqm, q); 361 if (retval) 362 goto deallocate_vmid; 363 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", 364 q->pipe, q->queue); 365 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 366 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 367 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 368 if (retval) 369 goto deallocate_vmid; 370 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 371 } 372 373 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 374 if (retval) 375 goto out_deallocate_hqd; 376 377 /* Temporarily release dqm lock to avoid a circular lock dependency */ 378 dqm_unlock(dqm); 379 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 380 dqm_lock(dqm); 381 382 if (!q->mqd_mem_obj) { 383 retval = -ENOMEM; 384 goto out_deallocate_doorbell; 385 } 386 387 if (qd) 388 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 389 &q->properties, restore_mqd, restore_ctl_stack, 390 qd->ctl_stack_size); 391 else 392 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 393 &q->gart_mqd_addr, &q->properties); 394 395 if (q->properties.is_active) { 396 if (!dqm->sched_running) { 397 WARN_ONCE(1, "Load non-HWS mqd while stopped\n"); 398 goto add_queue_to_list; 399 } 400 401 if (WARN(q->process->mm != current->mm, 402 "should only run in user thread")) 403 retval = -EFAULT; 404 else 405 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 406 q->queue, &q->properties, current->mm); 407 if (retval) 408 goto out_free_mqd; 409 } 410 411 add_queue_to_list: 412 list_add(&q->list, &qpd->queues_list); 413 qpd->queue_count++; 414 if (q->properties.is_active) 415 increment_queue_count(dqm, q->properties.type); 416 417 /* 418 * Unconditionally increment this counter, regardless of the queue's 419 * type or whether the queue is active. 420 */ 421 dqm->total_queue_count++; 422 pr_debug("Total of %d queues are accountable so far\n", 423 dqm->total_queue_count); 424 goto out_unlock; 425 426 out_free_mqd: 427 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 428 out_deallocate_doorbell: 429 deallocate_doorbell(qpd, q); 430 out_deallocate_hqd: 431 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 432 deallocate_hqd(dqm, q); 433 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 434 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 435 deallocate_sdma_queue(dqm, q); 436 deallocate_vmid: 437 if (list_empty(&qpd->queues_list)) 438 deallocate_vmid(dqm, qpd, q); 439 out_unlock: 440 dqm_unlock(dqm); 441 return retval; 442 } 443 444 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) 445 { 446 bool set; 447 int pipe, bit, i; 448 449 set = false; 450 451 for (pipe = dqm->next_pipe_to_allocate, i = 0; 452 i < get_pipes_per_mec(dqm); 453 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { 454 455 if (!is_pipe_enabled(dqm, 0, pipe)) 456 continue; 457 458 if (dqm->allocated_queues[pipe] != 0) { 459 bit = ffs(dqm->allocated_queues[pipe]) - 1; 460 dqm->allocated_queues[pipe] &= ~(1 << bit); 461 q->pipe = pipe; 462 q->queue = bit; 463 set = true; 464 break; 465 } 466 } 467 468 if (!set) 469 return -EBUSY; 470 471 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); 472 /* horizontal hqd allocation */ 473 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); 474 475 return 0; 476 } 477 478 static inline void deallocate_hqd(struct device_queue_manager *dqm, 479 struct queue *q) 480 { 481 dqm->allocated_queues[q->pipe] |= (1 << q->queue); 482 } 483 484 #define SQ_IND_CMD_CMD_KILL 0x00000003 485 #define SQ_IND_CMD_MODE_BROADCAST 0x00000001 486 487 static int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p) 488 { 489 int status = 0; 490 unsigned int vmid; 491 uint16_t queried_pasid; 492 union SQ_CMD_BITS reg_sq_cmd; 493 union GRBM_GFX_INDEX_BITS reg_gfx_index; 494 struct kfd_process_device *pdd; 495 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd; 496 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd; 497 498 reg_sq_cmd.u32All = 0; 499 reg_gfx_index.u32All = 0; 500 501 pr_debug("Killing all process wavefronts\n"); 502 503 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING .. 504 * ATC_VMID15_PASID_MAPPING 505 * to check which VMID the current process is mapped to. 506 */ 507 508 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) { 509 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info 510 (dev->adev, vmid, &queried_pasid); 511 512 if (status && queried_pasid == p->pasid) { 513 pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n", 514 vmid, p->pasid); 515 break; 516 } 517 } 518 519 if (vmid > last_vmid_to_scan) { 520 pr_err("Didn't find vmid for pasid 0x%x\n", p->pasid); 521 return -EFAULT; 522 } 523 524 /* taking the VMID for that process on the safe way using PDD */ 525 pdd = kfd_get_process_device_data(dev, p); 526 if (!pdd) 527 return -EFAULT; 528 529 reg_gfx_index.bits.sh_broadcast_writes = 1; 530 reg_gfx_index.bits.se_broadcast_writes = 1; 531 reg_gfx_index.bits.instance_broadcast_writes = 1; 532 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; 533 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL; 534 reg_sq_cmd.bits.vm_id = vmid; 535 536 dev->kfd2kgd->wave_control_execute(dev->adev, 537 reg_gfx_index.u32All, 538 reg_sq_cmd.u32All); 539 540 return 0; 541 } 542 543 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked 544 * to avoid asynchronized access 545 */ 546 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, 547 struct qcm_process_device *qpd, 548 struct queue *q) 549 { 550 int retval; 551 struct mqd_manager *mqd_mgr; 552 553 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 554 q->properties.type)]; 555 556 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 557 deallocate_hqd(dqm, q); 558 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 559 deallocate_sdma_queue(dqm, q); 560 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 561 deallocate_sdma_queue(dqm, q); 562 else { 563 pr_debug("q->properties.type %d is invalid\n", 564 q->properties.type); 565 return -EINVAL; 566 } 567 dqm->total_queue_count--; 568 569 deallocate_doorbell(qpd, q); 570 571 if (!dqm->sched_running) { 572 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n"); 573 return 0; 574 } 575 576 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 577 KFD_PREEMPT_TYPE_WAVEFRONT_RESET, 578 KFD_UNMAP_LATENCY_MS, 579 q->pipe, q->queue); 580 if (retval == -ETIME) 581 qpd->reset_wavefronts = true; 582 583 list_del(&q->list); 584 if (list_empty(&qpd->queues_list)) { 585 if (qpd->reset_wavefronts) { 586 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n", 587 dqm->dev); 588 /* dbgdev_wave_reset_wavefronts has to be called before 589 * deallocate_vmid(), i.e. when vmid is still in use. 590 */ 591 dbgdev_wave_reset_wavefronts(dqm->dev, 592 qpd->pqm->process); 593 qpd->reset_wavefronts = false; 594 } 595 596 deallocate_vmid(dqm, qpd, q); 597 } 598 qpd->queue_count--; 599 if (q->properties.is_active) { 600 decrement_queue_count(dqm, q->properties.type); 601 if (q->properties.is_gws) { 602 dqm->gws_queue_count--; 603 qpd->mapped_gws_queue = false; 604 } 605 } 606 607 return retval; 608 } 609 610 static int destroy_queue_nocpsch(struct device_queue_manager *dqm, 611 struct qcm_process_device *qpd, 612 struct queue *q) 613 { 614 int retval; 615 uint64_t sdma_val = 0; 616 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 617 struct mqd_manager *mqd_mgr = 618 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 619 620 /* Get the SDMA queue stats */ 621 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 622 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 623 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 624 &sdma_val); 625 if (retval) 626 pr_err("Failed to read SDMA queue counter for queue: %d\n", 627 q->properties.queue_id); 628 } 629 630 dqm_lock(dqm); 631 retval = destroy_queue_nocpsch_locked(dqm, qpd, q); 632 if (!retval) 633 pdd->sdma_past_activity_counter += sdma_val; 634 dqm_unlock(dqm); 635 636 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 637 638 return retval; 639 } 640 641 static int update_queue(struct device_queue_manager *dqm, struct queue *q, 642 struct mqd_update_info *minfo) 643 { 644 int retval = 0; 645 struct mqd_manager *mqd_mgr; 646 struct kfd_process_device *pdd; 647 bool prev_active = false; 648 649 dqm_lock(dqm); 650 pdd = kfd_get_process_device_data(q->device, q->process); 651 if (!pdd) { 652 retval = -ENODEV; 653 goto out_unlock; 654 } 655 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 656 q->properties.type)]; 657 658 /* Save previous activity state for counters */ 659 prev_active = q->properties.is_active; 660 661 /* Make sure the queue is unmapped before updating the MQD */ 662 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 663 retval = unmap_queues_cpsch(dqm, 664 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false); 665 if (retval) { 666 pr_err("unmap queue failed\n"); 667 goto out_unlock; 668 } 669 } else if (prev_active && 670 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 671 q->properties.type == KFD_QUEUE_TYPE_SDMA || 672 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 673 674 if (!dqm->sched_running) { 675 WARN_ONCE(1, "Update non-HWS queue while stopped\n"); 676 goto out_unlock; 677 } 678 679 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 680 (dqm->dev->cwsr_enabled ? 681 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 682 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 683 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 684 if (retval) { 685 pr_err("destroy mqd failed\n"); 686 goto out_unlock; 687 } 688 } 689 690 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo); 691 692 /* 693 * check active state vs. the previous state and modify 694 * counter accordingly. map_queues_cpsch uses the 695 * dqm->active_queue_count to determine whether a new runlist must be 696 * uploaded. 697 */ 698 if (q->properties.is_active && !prev_active) 699 increment_queue_count(dqm, q->properties.type); 700 else if (!q->properties.is_active && prev_active) 701 decrement_queue_count(dqm, q->properties.type); 702 703 if (q->gws && !q->properties.is_gws) { 704 if (q->properties.is_active) { 705 dqm->gws_queue_count++; 706 pdd->qpd.mapped_gws_queue = true; 707 } 708 q->properties.is_gws = true; 709 } else if (!q->gws && q->properties.is_gws) { 710 if (q->properties.is_active) { 711 dqm->gws_queue_count--; 712 pdd->qpd.mapped_gws_queue = false; 713 } 714 q->properties.is_gws = false; 715 } 716 717 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) 718 retval = map_queues_cpsch(dqm); 719 else if (q->properties.is_active && 720 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 721 q->properties.type == KFD_QUEUE_TYPE_SDMA || 722 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 723 if (WARN(q->process->mm != current->mm, 724 "should only run in user thread")) 725 retval = -EFAULT; 726 else 727 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, 728 q->pipe, q->queue, 729 &q->properties, current->mm); 730 } 731 732 out_unlock: 733 dqm_unlock(dqm); 734 return retval; 735 } 736 737 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm, 738 struct qcm_process_device *qpd) 739 { 740 struct queue *q; 741 struct mqd_manager *mqd_mgr; 742 struct kfd_process_device *pdd; 743 int retval, ret = 0; 744 745 dqm_lock(dqm); 746 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 747 goto out; 748 749 pdd = qpd_to_pdd(qpd); 750 pr_debug_ratelimited("Evicting PASID 0x%x queues\n", 751 pdd->process->pasid); 752 753 pdd->last_evict_timestamp = get_jiffies_64(); 754 /* Mark all queues as evicted. Deactivate all active queues on 755 * the qpd. 756 */ 757 list_for_each_entry(q, &qpd->queues_list, list) { 758 q->properties.is_evicted = true; 759 if (!q->properties.is_active) 760 continue; 761 762 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 763 q->properties.type)]; 764 q->properties.is_active = false; 765 decrement_queue_count(dqm, q->properties.type); 766 if (q->properties.is_gws) { 767 dqm->gws_queue_count--; 768 qpd->mapped_gws_queue = false; 769 } 770 771 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n")) 772 continue; 773 774 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 775 (dqm->dev->cwsr_enabled ? 776 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 777 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 778 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 779 if (retval && !ret) 780 /* Return the first error, but keep going to 781 * maintain a consistent eviction state 782 */ 783 ret = retval; 784 } 785 786 out: 787 dqm_unlock(dqm); 788 return ret; 789 } 790 791 static int evict_process_queues_cpsch(struct device_queue_manager *dqm, 792 struct qcm_process_device *qpd) 793 { 794 struct queue *q; 795 struct kfd_process_device *pdd; 796 int retval = 0; 797 798 dqm_lock(dqm); 799 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 800 goto out; 801 802 pdd = qpd_to_pdd(qpd); 803 pr_debug_ratelimited("Evicting PASID 0x%x queues\n", 804 pdd->process->pasid); 805 806 /* Mark all queues as evicted. Deactivate all active queues on 807 * the qpd. 808 */ 809 list_for_each_entry(q, &qpd->queues_list, list) { 810 q->properties.is_evicted = true; 811 if (!q->properties.is_active) 812 continue; 813 814 q->properties.is_active = false; 815 decrement_queue_count(dqm, q->properties.type); 816 } 817 pdd->last_evict_timestamp = get_jiffies_64(); 818 retval = execute_queues_cpsch(dqm, 819 qpd->is_debug ? 820 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : 821 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 822 823 out: 824 dqm_unlock(dqm); 825 return retval; 826 } 827 828 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, 829 struct qcm_process_device *qpd) 830 { 831 struct mm_struct *mm = NULL; 832 struct queue *q; 833 struct mqd_manager *mqd_mgr; 834 struct kfd_process_device *pdd; 835 uint64_t pd_base; 836 uint64_t eviction_duration; 837 int retval, ret = 0; 838 839 pdd = qpd_to_pdd(qpd); 840 /* Retrieve PD base */ 841 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 842 843 dqm_lock(dqm); 844 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 845 goto out; 846 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 847 qpd->evicted--; 848 goto out; 849 } 850 851 pr_debug_ratelimited("Restoring PASID 0x%x queues\n", 852 pdd->process->pasid); 853 854 /* Update PD Base in QPD */ 855 qpd->page_table_base = pd_base; 856 pr_debug("Updated PD address to 0x%llx\n", pd_base); 857 858 if (!list_empty(&qpd->queues_list)) { 859 dqm->dev->kfd2kgd->set_vm_context_page_table_base( 860 dqm->dev->adev, 861 qpd->vmid, 862 qpd->page_table_base); 863 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); 864 } 865 866 /* Take a safe reference to the mm_struct, which may otherwise 867 * disappear even while the kfd_process is still referenced. 868 */ 869 mm = get_task_mm(pdd->process->lead_thread); 870 if (!mm) { 871 ret = -EFAULT; 872 goto out; 873 } 874 875 /* Remove the eviction flags. Activate queues that are not 876 * inactive for other reasons. 877 */ 878 list_for_each_entry(q, &qpd->queues_list, list) { 879 q->properties.is_evicted = false; 880 if (!QUEUE_IS_ACTIVE(q->properties)) 881 continue; 882 883 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 884 q->properties.type)]; 885 q->properties.is_active = true; 886 increment_queue_count(dqm, q->properties.type); 887 if (q->properties.is_gws) { 888 dqm->gws_queue_count++; 889 qpd->mapped_gws_queue = true; 890 } 891 892 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n")) 893 continue; 894 895 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 896 q->queue, &q->properties, mm); 897 if (retval && !ret) 898 /* Return the first error, but keep going to 899 * maintain a consistent eviction state 900 */ 901 ret = retval; 902 } 903 qpd->evicted = 0; 904 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 905 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 906 out: 907 if (mm) 908 mmput(mm); 909 dqm_unlock(dqm); 910 return ret; 911 } 912 913 static int restore_process_queues_cpsch(struct device_queue_manager *dqm, 914 struct qcm_process_device *qpd) 915 { 916 struct queue *q; 917 struct kfd_process_device *pdd; 918 uint64_t pd_base; 919 uint64_t eviction_duration; 920 int retval = 0; 921 922 pdd = qpd_to_pdd(qpd); 923 /* Retrieve PD base */ 924 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 925 926 dqm_lock(dqm); 927 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 928 goto out; 929 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 930 qpd->evicted--; 931 goto out; 932 } 933 934 pr_debug_ratelimited("Restoring PASID 0x%x queues\n", 935 pdd->process->pasid); 936 937 /* Update PD Base in QPD */ 938 qpd->page_table_base = pd_base; 939 pr_debug("Updated PD address to 0x%llx\n", pd_base); 940 941 /* activate all active queues on the qpd */ 942 list_for_each_entry(q, &qpd->queues_list, list) { 943 q->properties.is_evicted = false; 944 if (!QUEUE_IS_ACTIVE(q->properties)) 945 continue; 946 947 q->properties.is_active = true; 948 increment_queue_count(dqm, q->properties.type); 949 } 950 retval = execute_queues_cpsch(dqm, 951 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 952 qpd->evicted = 0; 953 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 954 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 955 out: 956 dqm_unlock(dqm); 957 return retval; 958 } 959 960 static int register_process(struct device_queue_manager *dqm, 961 struct qcm_process_device *qpd) 962 { 963 struct device_process_node *n; 964 struct kfd_process_device *pdd; 965 uint64_t pd_base; 966 int retval; 967 968 n = kzalloc(sizeof(*n), GFP_KERNEL); 969 if (!n) 970 return -ENOMEM; 971 972 n->qpd = qpd; 973 974 pdd = qpd_to_pdd(qpd); 975 /* Retrieve PD base */ 976 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 977 978 dqm_lock(dqm); 979 list_add(&n->list, &dqm->queues); 980 981 /* Update PD Base in QPD */ 982 qpd->page_table_base = pd_base; 983 pr_debug("Updated PD address to 0x%llx\n", pd_base); 984 985 retval = dqm->asic_ops.update_qpd(dqm, qpd); 986 987 dqm->processes_count++; 988 989 dqm_unlock(dqm); 990 991 /* Outside the DQM lock because under the DQM lock we can't do 992 * reclaim or take other locks that others hold while reclaiming. 993 */ 994 kfd_inc_compute_active(dqm->dev); 995 996 return retval; 997 } 998 999 static int unregister_process(struct device_queue_manager *dqm, 1000 struct qcm_process_device *qpd) 1001 { 1002 int retval; 1003 struct device_process_node *cur, *next; 1004 1005 pr_debug("qpd->queues_list is %s\n", 1006 list_empty(&qpd->queues_list) ? "empty" : "not empty"); 1007 1008 retval = 0; 1009 dqm_lock(dqm); 1010 1011 list_for_each_entry_safe(cur, next, &dqm->queues, list) { 1012 if (qpd == cur->qpd) { 1013 list_del(&cur->list); 1014 kfree(cur); 1015 dqm->processes_count--; 1016 goto out; 1017 } 1018 } 1019 /* qpd not found in dqm list */ 1020 retval = 1; 1021 out: 1022 dqm_unlock(dqm); 1023 1024 /* Outside the DQM lock because under the DQM lock we can't do 1025 * reclaim or take other locks that others hold while reclaiming. 1026 */ 1027 if (!retval) 1028 kfd_dec_compute_active(dqm->dev); 1029 1030 return retval; 1031 } 1032 1033 static int 1034 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid, 1035 unsigned int vmid) 1036 { 1037 return dqm->dev->kfd2kgd->set_pasid_vmid_mapping( 1038 dqm->dev->adev, pasid, vmid); 1039 } 1040 1041 static void init_interrupts(struct device_queue_manager *dqm) 1042 { 1043 unsigned int i; 1044 1045 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) 1046 if (is_pipe_enabled(dqm, 0, i)) 1047 dqm->dev->kfd2kgd->init_interrupts(dqm->dev->adev, i); 1048 } 1049 1050 static int initialize_nocpsch(struct device_queue_manager *dqm) 1051 { 1052 int pipe, queue; 1053 1054 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1055 1056 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), 1057 sizeof(unsigned int), GFP_KERNEL); 1058 if (!dqm->allocated_queues) 1059 return -ENOMEM; 1060 1061 mutex_init(&dqm->lock_hidden); 1062 INIT_LIST_HEAD(&dqm->queues); 1063 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0; 1064 dqm->active_cp_queue_count = 0; 1065 dqm->gws_queue_count = 0; 1066 1067 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 1068 int pipe_offset = pipe * get_queues_per_pipe(dqm); 1069 1070 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) 1071 if (test_bit(pipe_offset + queue, 1072 dqm->dev->shared_resources.cp_queue_bitmap)) 1073 dqm->allocated_queues[pipe] |= 1 << queue; 1074 } 1075 1076 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid)); 1077 1078 dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm)); 1079 dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm)); 1080 1081 return 0; 1082 } 1083 1084 static void uninitialize(struct device_queue_manager *dqm) 1085 { 1086 int i; 1087 1088 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0); 1089 1090 kfree(dqm->allocated_queues); 1091 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) 1092 kfree(dqm->mqd_mgrs[i]); 1093 mutex_destroy(&dqm->lock_hidden); 1094 } 1095 1096 static int start_nocpsch(struct device_queue_manager *dqm) 1097 { 1098 int r = 0; 1099 1100 pr_info("SW scheduler is used"); 1101 init_interrupts(dqm); 1102 1103 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1104 r = pm_init(&dqm->packet_mgr, dqm); 1105 if (!r) 1106 dqm->sched_running = true; 1107 1108 return r; 1109 } 1110 1111 static int stop_nocpsch(struct device_queue_manager *dqm) 1112 { 1113 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1114 pm_uninit(&dqm->packet_mgr, false); 1115 dqm->sched_running = false; 1116 1117 return 0; 1118 } 1119 1120 static void pre_reset(struct device_queue_manager *dqm) 1121 { 1122 dqm_lock(dqm); 1123 dqm->is_resetting = true; 1124 dqm_unlock(dqm); 1125 } 1126 1127 static int allocate_sdma_queue(struct device_queue_manager *dqm, 1128 struct queue *q, const uint32_t *restore_sdma_id) 1129 { 1130 int bit; 1131 1132 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1133 if (dqm->sdma_bitmap == 0) { 1134 pr_err("No more SDMA queue to allocate\n"); 1135 return -ENOMEM; 1136 } 1137 1138 if (restore_sdma_id) { 1139 /* Re-use existing sdma_id */ 1140 if (!(dqm->sdma_bitmap & (1ULL << *restore_sdma_id))) { 1141 pr_err("SDMA queue already in use\n"); 1142 return -EBUSY; 1143 } 1144 dqm->sdma_bitmap &= ~(1ULL << *restore_sdma_id); 1145 q->sdma_id = *restore_sdma_id; 1146 } else { 1147 /* Find first available sdma_id */ 1148 bit = __ffs64(dqm->sdma_bitmap); 1149 dqm->sdma_bitmap &= ~(1ULL << bit); 1150 q->sdma_id = bit; 1151 } 1152 1153 q->properties.sdma_engine_id = q->sdma_id % 1154 kfd_get_num_sdma_engines(dqm->dev); 1155 q->properties.sdma_queue_id = q->sdma_id / 1156 kfd_get_num_sdma_engines(dqm->dev); 1157 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1158 if (dqm->xgmi_sdma_bitmap == 0) { 1159 pr_err("No more XGMI SDMA queue to allocate\n"); 1160 return -ENOMEM; 1161 } 1162 if (restore_sdma_id) { 1163 /* Re-use existing sdma_id */ 1164 if (!(dqm->xgmi_sdma_bitmap & (1ULL << *restore_sdma_id))) { 1165 pr_err("SDMA queue already in use\n"); 1166 return -EBUSY; 1167 } 1168 dqm->xgmi_sdma_bitmap &= ~(1ULL << *restore_sdma_id); 1169 q->sdma_id = *restore_sdma_id; 1170 } else { 1171 bit = __ffs64(dqm->xgmi_sdma_bitmap); 1172 dqm->xgmi_sdma_bitmap &= ~(1ULL << bit); 1173 q->sdma_id = bit; 1174 } 1175 /* sdma_engine_id is sdma id including 1176 * both PCIe-optimized SDMAs and XGMI- 1177 * optimized SDMAs. The calculation below 1178 * assumes the first N engines are always 1179 * PCIe-optimized ones 1180 */ 1181 q->properties.sdma_engine_id = 1182 kfd_get_num_sdma_engines(dqm->dev) + 1183 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev); 1184 q->properties.sdma_queue_id = q->sdma_id / 1185 kfd_get_num_xgmi_sdma_engines(dqm->dev); 1186 } 1187 1188 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); 1189 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); 1190 1191 return 0; 1192 } 1193 1194 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 1195 struct queue *q) 1196 { 1197 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1198 if (q->sdma_id >= get_num_sdma_queues(dqm)) 1199 return; 1200 dqm->sdma_bitmap |= (1ULL << q->sdma_id); 1201 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1202 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm)) 1203 return; 1204 dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id); 1205 } 1206 } 1207 1208 /* 1209 * Device Queue Manager implementation for cp scheduler 1210 */ 1211 1212 static int set_sched_resources(struct device_queue_manager *dqm) 1213 { 1214 int i, mec; 1215 struct scheduling_resources res; 1216 1217 res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap; 1218 1219 res.queue_mask = 0; 1220 for (i = 0; i < KGD_MAX_QUEUES; ++i) { 1221 mec = (i / dqm->dev->shared_resources.num_queue_per_pipe) 1222 / dqm->dev->shared_resources.num_pipe_per_mec; 1223 1224 if (!test_bit(i, dqm->dev->shared_resources.cp_queue_bitmap)) 1225 continue; 1226 1227 /* only acquire queues from the first MEC */ 1228 if (mec > 0) 1229 continue; 1230 1231 /* This situation may be hit in the future if a new HW 1232 * generation exposes more than 64 queues. If so, the 1233 * definition of res.queue_mask needs updating 1234 */ 1235 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { 1236 pr_err("Invalid queue enabled by amdgpu: %d\n", i); 1237 break; 1238 } 1239 1240 res.queue_mask |= 1ull 1241 << amdgpu_queue_mask_bit_to_set_resource_bit( 1242 dqm->dev->adev, i); 1243 } 1244 res.gws_mask = ~0ull; 1245 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; 1246 1247 pr_debug("Scheduling resources:\n" 1248 "vmid mask: 0x%8X\n" 1249 "queue mask: 0x%8llX\n", 1250 res.vmid_mask, res.queue_mask); 1251 1252 return pm_send_set_resources(&dqm->packet_mgr, &res); 1253 } 1254 1255 static int initialize_cpsch(struct device_queue_manager *dqm) 1256 { 1257 uint64_t num_sdma_queues; 1258 uint64_t num_xgmi_sdma_queues; 1259 1260 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1261 1262 mutex_init(&dqm->lock_hidden); 1263 INIT_LIST_HEAD(&dqm->queues); 1264 dqm->active_queue_count = dqm->processes_count = 0; 1265 dqm->active_cp_queue_count = 0; 1266 dqm->gws_queue_count = 0; 1267 dqm->active_runlist = false; 1268 1269 num_sdma_queues = get_num_sdma_queues(dqm); 1270 if (num_sdma_queues >= BITS_PER_TYPE(dqm->sdma_bitmap)) 1271 dqm->sdma_bitmap = ULLONG_MAX; 1272 else 1273 dqm->sdma_bitmap = (BIT_ULL(num_sdma_queues) - 1); 1274 1275 num_xgmi_sdma_queues = get_num_xgmi_sdma_queues(dqm); 1276 if (num_xgmi_sdma_queues >= BITS_PER_TYPE(dqm->xgmi_sdma_bitmap)) 1277 dqm->xgmi_sdma_bitmap = ULLONG_MAX; 1278 else 1279 dqm->xgmi_sdma_bitmap = (BIT_ULL(num_xgmi_sdma_queues) - 1); 1280 1281 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception); 1282 1283 return 0; 1284 } 1285 1286 static int start_cpsch(struct device_queue_manager *dqm) 1287 { 1288 int retval; 1289 1290 retval = 0; 1291 1292 dqm_lock(dqm); 1293 retval = pm_init(&dqm->packet_mgr, dqm); 1294 if (retval) 1295 goto fail_packet_manager_init; 1296 1297 retval = set_sched_resources(dqm); 1298 if (retval) 1299 goto fail_set_sched_resources; 1300 1301 pr_debug("Allocating fence memory\n"); 1302 1303 /* allocate fence memory on the gart */ 1304 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), 1305 &dqm->fence_mem); 1306 1307 if (retval) 1308 goto fail_allocate_vidmem; 1309 1310 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr; 1311 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; 1312 1313 init_interrupts(dqm); 1314 1315 /* clear hang status when driver try to start the hw scheduler */ 1316 dqm->is_hws_hang = false; 1317 dqm->is_resetting = false; 1318 dqm->sched_running = true; 1319 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1320 dqm_unlock(dqm); 1321 1322 return 0; 1323 fail_allocate_vidmem: 1324 fail_set_sched_resources: 1325 pm_uninit(&dqm->packet_mgr, false); 1326 fail_packet_manager_init: 1327 dqm_unlock(dqm); 1328 return retval; 1329 } 1330 1331 static int stop_cpsch(struct device_queue_manager *dqm) 1332 { 1333 bool hanging; 1334 1335 dqm_lock(dqm); 1336 if (!dqm->sched_running) { 1337 dqm_unlock(dqm); 1338 return 0; 1339 } 1340 1341 if (!dqm->is_hws_hang) 1342 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, false); 1343 hanging = dqm->is_hws_hang || dqm->is_resetting; 1344 dqm->sched_running = false; 1345 1346 pm_release_ib(&dqm->packet_mgr); 1347 1348 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 1349 pm_uninit(&dqm->packet_mgr, hanging); 1350 dqm_unlock(dqm); 1351 1352 return 0; 1353 } 1354 1355 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, 1356 struct kernel_queue *kq, 1357 struct qcm_process_device *qpd) 1358 { 1359 dqm_lock(dqm); 1360 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1361 pr_warn("Can't create new kernel queue because %d queues were already created\n", 1362 dqm->total_queue_count); 1363 dqm_unlock(dqm); 1364 return -EPERM; 1365 } 1366 1367 /* 1368 * Unconditionally increment this counter, regardless of the queue's 1369 * type or whether the queue is active. 1370 */ 1371 dqm->total_queue_count++; 1372 pr_debug("Total of %d queues are accountable so far\n", 1373 dqm->total_queue_count); 1374 1375 list_add(&kq->list, &qpd->priv_queue_list); 1376 increment_queue_count(dqm, kq->queue->properties.type); 1377 qpd->is_debug = true; 1378 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1379 dqm_unlock(dqm); 1380 1381 return 0; 1382 } 1383 1384 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, 1385 struct kernel_queue *kq, 1386 struct qcm_process_device *qpd) 1387 { 1388 dqm_lock(dqm); 1389 list_del(&kq->list); 1390 decrement_queue_count(dqm, kq->queue->properties.type); 1391 qpd->is_debug = false; 1392 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); 1393 /* 1394 * Unconditionally decrement this counter, regardless of the queue's 1395 * type. 1396 */ 1397 dqm->total_queue_count--; 1398 pr_debug("Total of %d queues are accountable so far\n", 1399 dqm->total_queue_count); 1400 dqm_unlock(dqm); 1401 } 1402 1403 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, 1404 struct qcm_process_device *qpd, 1405 const struct kfd_criu_queue_priv_data *qd, 1406 const void *restore_mqd, const void *restore_ctl_stack) 1407 { 1408 int retval; 1409 struct mqd_manager *mqd_mgr; 1410 1411 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1412 pr_warn("Can't create new usermode queue because %d queues were already created\n", 1413 dqm->total_queue_count); 1414 retval = -EPERM; 1415 goto out; 1416 } 1417 1418 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1419 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1420 dqm_lock(dqm); 1421 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 1422 dqm_unlock(dqm); 1423 if (retval) 1424 goto out; 1425 } 1426 1427 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 1428 if (retval) 1429 goto out_deallocate_sdma_queue; 1430 1431 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1432 q->properties.type)]; 1433 1434 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1435 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 1436 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 1437 q->properties.tba_addr = qpd->tba_addr; 1438 q->properties.tma_addr = qpd->tma_addr; 1439 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 1440 if (!q->mqd_mem_obj) { 1441 retval = -ENOMEM; 1442 goto out_deallocate_doorbell; 1443 } 1444 1445 dqm_lock(dqm); 1446 /* 1447 * Eviction state logic: mark all queues as evicted, even ones 1448 * not currently active. Restoring inactive queues later only 1449 * updates the is_evicted flag but is a no-op otherwise. 1450 */ 1451 q->properties.is_evicted = !!qpd->evicted; 1452 1453 if (qd) 1454 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 1455 &q->properties, restore_mqd, restore_ctl_stack, 1456 qd->ctl_stack_size); 1457 else 1458 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 1459 &q->gart_mqd_addr, &q->properties); 1460 1461 list_add(&q->list, &qpd->queues_list); 1462 qpd->queue_count++; 1463 1464 if (q->properties.is_active) { 1465 increment_queue_count(dqm, q->properties.type); 1466 1467 execute_queues_cpsch(dqm, 1468 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1469 } 1470 1471 /* 1472 * Unconditionally increment this counter, regardless of the queue's 1473 * type or whether the queue is active. 1474 */ 1475 dqm->total_queue_count++; 1476 1477 pr_debug("Total of %d queues are accountable so far\n", 1478 dqm->total_queue_count); 1479 1480 dqm_unlock(dqm); 1481 return retval; 1482 1483 out_deallocate_doorbell: 1484 deallocate_doorbell(qpd, q); 1485 out_deallocate_sdma_queue: 1486 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1487 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1488 dqm_lock(dqm); 1489 deallocate_sdma_queue(dqm, q); 1490 dqm_unlock(dqm); 1491 } 1492 out: 1493 return retval; 1494 } 1495 1496 int amdkfd_fence_wait_timeout(uint64_t *fence_addr, 1497 uint64_t fence_value, 1498 unsigned int timeout_ms) 1499 { 1500 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; 1501 1502 while (*fence_addr != fence_value) { 1503 if (time_after(jiffies, end_jiffies)) { 1504 pr_err("qcm fence wait loop timeout expired\n"); 1505 /* In HWS case, this is used to halt the driver thread 1506 * in order not to mess up CP states before doing 1507 * scandumps for FW debugging. 1508 */ 1509 while (halt_if_hws_hang) 1510 schedule(); 1511 1512 return -ETIME; 1513 } 1514 schedule(); 1515 } 1516 1517 return 0; 1518 } 1519 1520 /* dqm->lock mutex has to be locked before calling this function */ 1521 static int map_queues_cpsch(struct device_queue_manager *dqm) 1522 { 1523 int retval; 1524 1525 if (!dqm->sched_running) 1526 return 0; 1527 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0) 1528 return 0; 1529 if (dqm->active_runlist) 1530 return 0; 1531 1532 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues); 1533 pr_debug("%s sent runlist\n", __func__); 1534 if (retval) { 1535 pr_err("failed to execute runlist\n"); 1536 return retval; 1537 } 1538 dqm->active_runlist = true; 1539 1540 return retval; 1541 } 1542 1543 /* dqm->lock mutex has to be locked before calling this function */ 1544 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 1545 enum kfd_unmap_queues_filter filter, 1546 uint32_t filter_param, bool reset) 1547 { 1548 int retval = 0; 1549 struct mqd_manager *mqd_mgr; 1550 1551 if (!dqm->sched_running) 1552 return 0; 1553 if (dqm->is_hws_hang || dqm->is_resetting) 1554 return -EIO; 1555 if (!dqm->active_runlist) 1556 return retval; 1557 1558 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset); 1559 if (retval) 1560 return retval; 1561 1562 *dqm->fence_addr = KFD_FENCE_INIT; 1563 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, 1564 KFD_FENCE_COMPLETED); 1565 /* should be timed out */ 1566 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, 1567 queue_preemption_timeout_ms); 1568 if (retval) { 1569 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n"); 1570 dqm->is_hws_hang = true; 1571 /* It's possible we're detecting a HWS hang in the 1572 * middle of a GPU reset. No need to schedule another 1573 * reset in this case. 1574 */ 1575 if (!dqm->is_resetting) 1576 schedule_work(&dqm->hw_exception_work); 1577 return retval; 1578 } 1579 1580 /* In the current MEC firmware implementation, if compute queue 1581 * doesn't response to the preemption request in time, HIQ will 1582 * abandon the unmap request without returning any timeout error 1583 * to driver. Instead, MEC firmware will log the doorbell of the 1584 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields. 1585 * To make sure the queue unmap was successful, driver need to 1586 * check those fields 1587 */ 1588 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; 1589 if (mqd_mgr->read_doorbell_id(dqm->packet_mgr.priv_queue->queue->mqd)) { 1590 pr_err("HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n"); 1591 while (halt_if_hws_hang) 1592 schedule(); 1593 return -ETIME; 1594 } 1595 1596 pm_release_ib(&dqm->packet_mgr); 1597 dqm->active_runlist = false; 1598 1599 return retval; 1600 } 1601 1602 /* only for compute queue */ 1603 static int reset_queues_cpsch(struct device_queue_manager *dqm, 1604 uint16_t pasid) 1605 { 1606 int retval; 1607 1608 dqm_lock(dqm); 1609 1610 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID, 1611 pasid, true); 1612 1613 dqm_unlock(dqm); 1614 return retval; 1615 } 1616 1617 /* dqm->lock mutex has to be locked before calling this function */ 1618 static int execute_queues_cpsch(struct device_queue_manager *dqm, 1619 enum kfd_unmap_queues_filter filter, 1620 uint32_t filter_param) 1621 { 1622 int retval; 1623 1624 if (dqm->is_hws_hang) 1625 return -EIO; 1626 retval = unmap_queues_cpsch(dqm, filter, filter_param, false); 1627 if (retval) 1628 return retval; 1629 1630 return map_queues_cpsch(dqm); 1631 } 1632 1633 static int destroy_queue_cpsch(struct device_queue_manager *dqm, 1634 struct qcm_process_device *qpd, 1635 struct queue *q) 1636 { 1637 int retval; 1638 struct mqd_manager *mqd_mgr; 1639 uint64_t sdma_val = 0; 1640 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 1641 1642 /* Get the SDMA queue stats */ 1643 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 1644 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1645 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 1646 &sdma_val); 1647 if (retval) 1648 pr_err("Failed to read SDMA queue counter for queue: %d\n", 1649 q->properties.queue_id); 1650 } 1651 1652 retval = 0; 1653 1654 /* remove queue from list to prevent rescheduling after preemption */ 1655 dqm_lock(dqm); 1656 1657 if (qpd->is_debug) { 1658 /* 1659 * error, currently we do not allow to destroy a queue 1660 * of a currently debugged process 1661 */ 1662 retval = -EBUSY; 1663 goto failed_try_destroy_debugged_queue; 1664 1665 } 1666 1667 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1668 q->properties.type)]; 1669 1670 deallocate_doorbell(qpd, q); 1671 1672 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 1673 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1674 deallocate_sdma_queue(dqm, q); 1675 pdd->sdma_past_activity_counter += sdma_val; 1676 } 1677 1678 list_del(&q->list); 1679 qpd->queue_count--; 1680 if (q->properties.is_active) { 1681 decrement_queue_count(dqm, q->properties.type); 1682 retval = execute_queues_cpsch(dqm, 1683 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1684 if (retval == -ETIME) 1685 qpd->reset_wavefronts = true; 1686 if (q->properties.is_gws) { 1687 dqm->gws_queue_count--; 1688 qpd->mapped_gws_queue = false; 1689 } 1690 } 1691 1692 /* 1693 * Unconditionally decrement this counter, regardless of the queue's 1694 * type 1695 */ 1696 dqm->total_queue_count--; 1697 pr_debug("Total of %d queues are accountable so far\n", 1698 dqm->total_queue_count); 1699 1700 dqm_unlock(dqm); 1701 1702 /* Do free_mqd after dqm_unlock(dqm) to avoid circular locking */ 1703 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1704 1705 return retval; 1706 1707 failed_try_destroy_debugged_queue: 1708 1709 dqm_unlock(dqm); 1710 return retval; 1711 } 1712 1713 /* 1714 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to 1715 * stay in user mode. 1716 */ 1717 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL 1718 /* APE1 limit is inclusive and 64K aligned. */ 1719 #define APE1_LIMIT_ALIGNMENT 0xFFFF 1720 1721 static bool set_cache_memory_policy(struct device_queue_manager *dqm, 1722 struct qcm_process_device *qpd, 1723 enum cache_policy default_policy, 1724 enum cache_policy alternate_policy, 1725 void __user *alternate_aperture_base, 1726 uint64_t alternate_aperture_size) 1727 { 1728 bool retval = true; 1729 1730 if (!dqm->asic_ops.set_cache_memory_policy) 1731 return retval; 1732 1733 dqm_lock(dqm); 1734 1735 if (alternate_aperture_size == 0) { 1736 /* base > limit disables APE1 */ 1737 qpd->sh_mem_ape1_base = 1; 1738 qpd->sh_mem_ape1_limit = 0; 1739 } else { 1740 /* 1741 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]}, 1742 * SH_MEM_APE1_BASE[31:0], 0x0000 } 1743 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]}, 1744 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF } 1745 * Verify that the base and size parameters can be 1746 * represented in this format and convert them. 1747 * Additionally restrict APE1 to user-mode addresses. 1748 */ 1749 1750 uint64_t base = (uintptr_t)alternate_aperture_base; 1751 uint64_t limit = base + alternate_aperture_size - 1; 1752 1753 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || 1754 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) { 1755 retval = false; 1756 goto out; 1757 } 1758 1759 qpd->sh_mem_ape1_base = base >> 16; 1760 qpd->sh_mem_ape1_limit = limit >> 16; 1761 } 1762 1763 retval = dqm->asic_ops.set_cache_memory_policy( 1764 dqm, 1765 qpd, 1766 default_policy, 1767 alternate_policy, 1768 alternate_aperture_base, 1769 alternate_aperture_size); 1770 1771 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) 1772 program_sh_mem_settings(dqm, qpd); 1773 1774 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", 1775 qpd->sh_mem_config, qpd->sh_mem_ape1_base, 1776 qpd->sh_mem_ape1_limit); 1777 1778 out: 1779 dqm_unlock(dqm); 1780 return retval; 1781 } 1782 1783 static int process_termination_nocpsch(struct device_queue_manager *dqm, 1784 struct qcm_process_device *qpd) 1785 { 1786 struct queue *q; 1787 struct device_process_node *cur, *next_dpn; 1788 int retval = 0; 1789 bool found = false; 1790 1791 dqm_lock(dqm); 1792 1793 /* Clear all user mode queues */ 1794 while (!list_empty(&qpd->queues_list)) { 1795 struct mqd_manager *mqd_mgr; 1796 int ret; 1797 1798 q = list_first_entry(&qpd->queues_list, struct queue, list); 1799 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1800 q->properties.type)]; 1801 ret = destroy_queue_nocpsch_locked(dqm, qpd, q); 1802 if (ret) 1803 retval = ret; 1804 dqm_unlock(dqm); 1805 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1806 dqm_lock(dqm); 1807 } 1808 1809 /* Unregister process */ 1810 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 1811 if (qpd == cur->qpd) { 1812 list_del(&cur->list); 1813 kfree(cur); 1814 dqm->processes_count--; 1815 found = true; 1816 break; 1817 } 1818 } 1819 1820 dqm_unlock(dqm); 1821 1822 /* Outside the DQM lock because under the DQM lock we can't do 1823 * reclaim or take other locks that others hold while reclaiming. 1824 */ 1825 if (found) 1826 kfd_dec_compute_active(dqm->dev); 1827 1828 return retval; 1829 } 1830 1831 static int get_wave_state(struct device_queue_manager *dqm, 1832 struct queue *q, 1833 void __user *ctl_stack, 1834 u32 *ctl_stack_used_size, 1835 u32 *save_area_used_size) 1836 { 1837 struct mqd_manager *mqd_mgr; 1838 1839 dqm_lock(dqm); 1840 1841 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 1842 1843 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || 1844 q->properties.is_active || !q->device->cwsr_enabled || 1845 !mqd_mgr->get_wave_state) { 1846 dqm_unlock(dqm); 1847 return -EINVAL; 1848 } 1849 1850 dqm_unlock(dqm); 1851 1852 /* 1853 * get_wave_state is outside the dqm lock to prevent circular locking 1854 * and the queue should be protected against destruction by the process 1855 * lock. 1856 */ 1857 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack, 1858 ctl_stack_used_size, save_area_used_size); 1859 } 1860 1861 static void get_queue_checkpoint_info(struct device_queue_manager *dqm, 1862 const struct queue *q, 1863 u32 *mqd_size, 1864 u32 *ctl_stack_size) 1865 { 1866 struct mqd_manager *mqd_mgr; 1867 enum KFD_MQD_TYPE mqd_type = 1868 get_mqd_type_from_queue_type(q->properties.type); 1869 1870 dqm_lock(dqm); 1871 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 1872 *mqd_size = mqd_mgr->mqd_size; 1873 *ctl_stack_size = 0; 1874 1875 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info) 1876 mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size); 1877 1878 dqm_unlock(dqm); 1879 } 1880 1881 static int checkpoint_mqd(struct device_queue_manager *dqm, 1882 const struct queue *q, 1883 void *mqd, 1884 void *ctl_stack) 1885 { 1886 struct mqd_manager *mqd_mgr; 1887 int r = 0; 1888 enum KFD_MQD_TYPE mqd_type = 1889 get_mqd_type_from_queue_type(q->properties.type); 1890 1891 dqm_lock(dqm); 1892 1893 if (q->properties.is_active || !q->device->cwsr_enabled) { 1894 r = -EINVAL; 1895 goto dqm_unlock; 1896 } 1897 1898 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 1899 if (!mqd_mgr->checkpoint_mqd) { 1900 r = -EOPNOTSUPP; 1901 goto dqm_unlock; 1902 } 1903 1904 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack); 1905 1906 dqm_unlock: 1907 dqm_unlock(dqm); 1908 return r; 1909 } 1910 1911 static int process_termination_cpsch(struct device_queue_manager *dqm, 1912 struct qcm_process_device *qpd) 1913 { 1914 int retval; 1915 struct queue *q; 1916 struct kernel_queue *kq, *kq_next; 1917 struct mqd_manager *mqd_mgr; 1918 struct device_process_node *cur, *next_dpn; 1919 enum kfd_unmap_queues_filter filter = 1920 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; 1921 bool found = false; 1922 1923 retval = 0; 1924 1925 dqm_lock(dqm); 1926 1927 /* Clean all kernel queues */ 1928 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) { 1929 list_del(&kq->list); 1930 decrement_queue_count(dqm, kq->queue->properties.type); 1931 qpd->is_debug = false; 1932 dqm->total_queue_count--; 1933 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES; 1934 } 1935 1936 /* Clear all user mode queues */ 1937 list_for_each_entry(q, &qpd->queues_list, list) { 1938 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 1939 deallocate_sdma_queue(dqm, q); 1940 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 1941 deallocate_sdma_queue(dqm, q); 1942 1943 if (q->properties.is_active) { 1944 decrement_queue_count(dqm, q->properties.type); 1945 if (q->properties.is_gws) { 1946 dqm->gws_queue_count--; 1947 qpd->mapped_gws_queue = false; 1948 } 1949 } 1950 1951 dqm->total_queue_count--; 1952 } 1953 1954 /* Unregister process */ 1955 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 1956 if (qpd == cur->qpd) { 1957 list_del(&cur->list); 1958 kfree(cur); 1959 dqm->processes_count--; 1960 found = true; 1961 break; 1962 } 1963 } 1964 1965 retval = execute_queues_cpsch(dqm, filter, 0); 1966 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) { 1967 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev); 1968 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process); 1969 qpd->reset_wavefronts = false; 1970 } 1971 1972 /* Lastly, free mqd resources. 1973 * Do free_mqd() after dqm_unlock to avoid circular locking. 1974 */ 1975 while (!list_empty(&qpd->queues_list)) { 1976 q = list_first_entry(&qpd->queues_list, struct queue, list); 1977 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1978 q->properties.type)]; 1979 list_del(&q->list); 1980 qpd->queue_count--; 1981 dqm_unlock(dqm); 1982 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1983 dqm_lock(dqm); 1984 } 1985 dqm_unlock(dqm); 1986 1987 /* Outside the DQM lock because under the DQM lock we can't do 1988 * reclaim or take other locks that others hold while reclaiming. 1989 */ 1990 if (found) 1991 kfd_dec_compute_active(dqm->dev); 1992 1993 return retval; 1994 } 1995 1996 static int init_mqd_managers(struct device_queue_manager *dqm) 1997 { 1998 int i, j; 1999 struct mqd_manager *mqd_mgr; 2000 2001 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) { 2002 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev); 2003 if (!mqd_mgr) { 2004 pr_err("mqd manager [%d] initialization failed\n", i); 2005 goto out_free; 2006 } 2007 dqm->mqd_mgrs[i] = mqd_mgr; 2008 } 2009 2010 return 0; 2011 2012 out_free: 2013 for (j = 0; j < i; j++) { 2014 kfree(dqm->mqd_mgrs[j]); 2015 dqm->mqd_mgrs[j] = NULL; 2016 } 2017 2018 return -ENOMEM; 2019 } 2020 2021 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/ 2022 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) 2023 { 2024 int retval; 2025 struct kfd_dev *dev = dqm->dev; 2026 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd; 2027 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * 2028 get_num_all_sdma_engines(dqm) * 2029 dev->device_info.num_sdma_queues_per_engine + 2030 dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size; 2031 2032 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size, 2033 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), 2034 (void *)&(mem_obj->cpu_ptr), false); 2035 2036 return retval; 2037 } 2038 2039 struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) 2040 { 2041 struct device_queue_manager *dqm; 2042 2043 pr_debug("Loading device queue manager\n"); 2044 2045 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL); 2046 if (!dqm) 2047 return NULL; 2048 2049 switch (dev->adev->asic_type) { 2050 /* HWS is not available on Hawaii. */ 2051 case CHIP_HAWAII: 2052 /* HWS depends on CWSR for timely dequeue. CWSR is not 2053 * available on Tonga. 2054 * 2055 * FIXME: This argument also applies to Kaveri. 2056 */ 2057 case CHIP_TONGA: 2058 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS; 2059 break; 2060 default: 2061 dqm->sched_policy = sched_policy; 2062 break; 2063 } 2064 2065 dqm->dev = dev; 2066 switch (dqm->sched_policy) { 2067 case KFD_SCHED_POLICY_HWS: 2068 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: 2069 /* initialize dqm for cp scheduling */ 2070 dqm->ops.create_queue = create_queue_cpsch; 2071 dqm->ops.initialize = initialize_cpsch; 2072 dqm->ops.start = start_cpsch; 2073 dqm->ops.stop = stop_cpsch; 2074 dqm->ops.pre_reset = pre_reset; 2075 dqm->ops.destroy_queue = destroy_queue_cpsch; 2076 dqm->ops.update_queue = update_queue; 2077 dqm->ops.register_process = register_process; 2078 dqm->ops.unregister_process = unregister_process; 2079 dqm->ops.uninitialize = uninitialize; 2080 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; 2081 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; 2082 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 2083 dqm->ops.process_termination = process_termination_cpsch; 2084 dqm->ops.evict_process_queues = evict_process_queues_cpsch; 2085 dqm->ops.restore_process_queues = restore_process_queues_cpsch; 2086 dqm->ops.get_wave_state = get_wave_state; 2087 dqm->ops.reset_queues = reset_queues_cpsch; 2088 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 2089 dqm->ops.checkpoint_mqd = checkpoint_mqd; 2090 break; 2091 case KFD_SCHED_POLICY_NO_HWS: 2092 /* initialize dqm for no cp scheduling */ 2093 dqm->ops.start = start_nocpsch; 2094 dqm->ops.stop = stop_nocpsch; 2095 dqm->ops.pre_reset = pre_reset; 2096 dqm->ops.create_queue = create_queue_nocpsch; 2097 dqm->ops.destroy_queue = destroy_queue_nocpsch; 2098 dqm->ops.update_queue = update_queue; 2099 dqm->ops.register_process = register_process; 2100 dqm->ops.unregister_process = unregister_process; 2101 dqm->ops.initialize = initialize_nocpsch; 2102 dqm->ops.uninitialize = uninitialize; 2103 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 2104 dqm->ops.process_termination = process_termination_nocpsch; 2105 dqm->ops.evict_process_queues = evict_process_queues_nocpsch; 2106 dqm->ops.restore_process_queues = 2107 restore_process_queues_nocpsch; 2108 dqm->ops.get_wave_state = get_wave_state; 2109 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 2110 dqm->ops.checkpoint_mqd = checkpoint_mqd; 2111 break; 2112 default: 2113 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy); 2114 goto out_free; 2115 } 2116 2117 switch (dev->adev->asic_type) { 2118 case CHIP_CARRIZO: 2119 device_queue_manager_init_vi(&dqm->asic_ops); 2120 break; 2121 2122 case CHIP_KAVERI: 2123 device_queue_manager_init_cik(&dqm->asic_ops); 2124 break; 2125 2126 case CHIP_HAWAII: 2127 device_queue_manager_init_cik_hawaii(&dqm->asic_ops); 2128 break; 2129 2130 case CHIP_TONGA: 2131 case CHIP_FIJI: 2132 case CHIP_POLARIS10: 2133 case CHIP_POLARIS11: 2134 case CHIP_POLARIS12: 2135 case CHIP_VEGAM: 2136 device_queue_manager_init_vi_tonga(&dqm->asic_ops); 2137 break; 2138 2139 default: 2140 if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1)) 2141 device_queue_manager_init_v10_navi10(&dqm->asic_ops); 2142 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) 2143 device_queue_manager_init_v9(&dqm->asic_ops); 2144 else { 2145 WARN(1, "Unexpected ASIC family %u", 2146 dev->adev->asic_type); 2147 goto out_free; 2148 } 2149 } 2150 2151 if (init_mqd_managers(dqm)) 2152 goto out_free; 2153 2154 if (allocate_hiq_sdma_mqd(dqm)) { 2155 pr_err("Failed to allocate hiq sdma mqd trunk buffer\n"); 2156 goto out_free; 2157 } 2158 2159 if (!dqm->ops.initialize(dqm)) 2160 return dqm; 2161 2162 out_free: 2163 kfree(dqm); 2164 return NULL; 2165 } 2166 2167 static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev, 2168 struct kfd_mem_obj *mqd) 2169 { 2170 WARN(!mqd, "No hiq sdma mqd trunk to free"); 2171 2172 amdgpu_amdkfd_free_gtt_mem(dev->adev, mqd->gtt_mem); 2173 } 2174 2175 void device_queue_manager_uninit(struct device_queue_manager *dqm) 2176 { 2177 dqm->ops.uninitialize(dqm); 2178 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd); 2179 kfree(dqm); 2180 } 2181 2182 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid) 2183 { 2184 struct kfd_process_device *pdd; 2185 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); 2186 int ret = 0; 2187 2188 if (!p) 2189 return -EINVAL; 2190 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 2191 pdd = kfd_get_process_device_data(dqm->dev, p); 2192 if (pdd) 2193 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd); 2194 kfd_unref_process(p); 2195 2196 return ret; 2197 } 2198 2199 static void kfd_process_hw_exception(struct work_struct *work) 2200 { 2201 struct device_queue_manager *dqm = container_of(work, 2202 struct device_queue_manager, hw_exception_work); 2203 amdgpu_amdkfd_gpu_reset(dqm->dev->adev); 2204 } 2205 2206 #if defined(CONFIG_DEBUG_FS) 2207 2208 static void seq_reg_dump(struct seq_file *m, 2209 uint32_t (*dump)[2], uint32_t n_regs) 2210 { 2211 uint32_t i, count; 2212 2213 for (i = 0, count = 0; i < n_regs; i++) { 2214 if (count == 0 || 2215 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { 2216 seq_printf(m, "%s %08x: %08x", 2217 i ? "\n" : "", 2218 dump[i][0], dump[i][1]); 2219 count = 7; 2220 } else { 2221 seq_printf(m, " %08x", dump[i][1]); 2222 count--; 2223 } 2224 } 2225 2226 seq_puts(m, "\n"); 2227 } 2228 2229 int dqm_debugfs_hqds(struct seq_file *m, void *data) 2230 { 2231 struct device_queue_manager *dqm = data; 2232 uint32_t (*dump)[2], n_regs; 2233 int pipe, queue; 2234 int r = 0; 2235 2236 if (!dqm->sched_running) { 2237 seq_puts(m, " Device is stopped\n"); 2238 return 0; 2239 } 2240 2241 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 2242 KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE, 2243 &dump, &n_regs); 2244 if (!r) { 2245 seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n", 2246 KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1, 2247 KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm), 2248 KFD_CIK_HIQ_QUEUE); 2249 seq_reg_dump(m, dump, n_regs); 2250 2251 kfree(dump); 2252 } 2253 2254 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 2255 int pipe_offset = pipe * get_queues_per_pipe(dqm); 2256 2257 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) { 2258 if (!test_bit(pipe_offset + queue, 2259 dqm->dev->shared_resources.cp_queue_bitmap)) 2260 continue; 2261 2262 r = dqm->dev->kfd2kgd->hqd_dump( 2263 dqm->dev->adev, pipe, queue, &dump, &n_regs); 2264 if (r) 2265 break; 2266 2267 seq_printf(m, " CP Pipe %d, Queue %d\n", 2268 pipe, queue); 2269 seq_reg_dump(m, dump, n_regs); 2270 2271 kfree(dump); 2272 } 2273 } 2274 2275 for (pipe = 0; pipe < get_num_all_sdma_engines(dqm); pipe++) { 2276 for (queue = 0; 2277 queue < dqm->dev->device_info.num_sdma_queues_per_engine; 2278 queue++) { 2279 r = dqm->dev->kfd2kgd->hqd_sdma_dump( 2280 dqm->dev->adev, pipe, queue, &dump, &n_regs); 2281 if (r) 2282 break; 2283 2284 seq_printf(m, " SDMA Engine %d, RLC %d\n", 2285 pipe, queue); 2286 seq_reg_dump(m, dump, n_regs); 2287 2288 kfree(dump); 2289 } 2290 } 2291 2292 return r; 2293 } 2294 2295 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm) 2296 { 2297 int r = 0; 2298 2299 dqm_lock(dqm); 2300 r = pm_debugfs_hang_hws(&dqm->packet_mgr); 2301 if (r) { 2302 dqm_unlock(dqm); 2303 return r; 2304 } 2305 dqm->active_runlist = true; 2306 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); 2307 dqm_unlock(dqm); 2308 2309 return r; 2310 } 2311 2312 #endif 2313