1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/ratelimit.h> 26 #include <linux/printk.h> 27 #include <linux/slab.h> 28 #include <linux/list.h> 29 #include <linux/types.h> 30 #include <linux/bitops.h> 31 #include <linux/sched.h> 32 #include "kfd_priv.h" 33 #include "kfd_device_queue_manager.h" 34 #include "kfd_mqd_manager.h" 35 #include "cik_regs.h" 36 #include "kfd_kernel_queue.h" 37 #include "amdgpu_amdkfd.h" 38 #include "amdgpu_reset.h" 39 #include "amdgpu_sdma.h" 40 #include "amdgpu_ring.h" 41 #include "amdgpu_mes.h" 42 #include "kfd_debug.h" 43 44 /* Size of the per-pipe EOP queue */ 45 #define CIK_HPD_EOP_BYTES_LOG2 11 46 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) 47 /* See unmap_queues_cpsch() */ 48 #define USE_DEFAULT_GRACE_PERIOD 0xffffffff 49 50 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, 51 u32 pasid, unsigned int vmid); 52 53 static int execute_queues_cpsch(struct device_queue_manager *dqm, 54 enum kfd_unmap_queues_filter filter, 55 uint32_t filter_param, 56 uint32_t grace_period); 57 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 58 enum kfd_unmap_queues_filter filter, 59 uint32_t filter_param, 60 uint32_t grace_period, 61 bool reset); 62 63 static int map_queues_cpsch(struct device_queue_manager *dqm); 64 65 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 66 struct queue *q); 67 68 static inline void deallocate_hqd(struct device_queue_manager *dqm, 69 struct queue *q); 70 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q); 71 static int allocate_sdma_queue(struct device_queue_manager *dqm, 72 struct queue *q, const uint32_t *restore_sdma_id); 73 74 static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma); 75 static struct queue *find_queue_by_doorbell_offset(struct device_queue_manager *dqm, 76 u32 doorbell_offset); 77 static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q, 78 struct qcm_process_device *qpd); 79 static int reset_queues_mes(struct device_queue_manager *dqm, struct queue *q); 80 81 static inline 82 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) 83 { 84 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI) 85 return KFD_MQD_TYPE_SDMA; 86 return KFD_MQD_TYPE_CP; 87 } 88 89 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) 90 { 91 int i; 92 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec 93 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe; 94 95 /* queue is available for KFD usage if bit is 1 */ 96 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i) 97 if (test_bit(pipe_offset + i, 98 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 99 return true; 100 return false; 101 } 102 103 unsigned int get_cp_queues_num(struct device_queue_manager *dqm) 104 { 105 return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap, 106 AMDGPU_MAX_QUEUES); 107 } 108 109 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) 110 { 111 return dqm->dev->kfd->shared_resources.num_queue_per_pipe; 112 } 113 114 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) 115 { 116 return dqm->dev->kfd->shared_resources.num_pipe_per_mec; 117 } 118 119 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm) 120 { 121 return kfd_get_num_sdma_engines(dqm->dev) + 122 kfd_get_num_xgmi_sdma_engines(dqm->dev); 123 } 124 125 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm) 126 { 127 return kfd_get_num_sdma_engines(dqm->dev) * 128 dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 129 } 130 131 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm) 132 { 133 return kfd_get_num_xgmi_sdma_engines(dqm->dev) * 134 dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 135 } 136 137 static void init_sdma_bitmaps(struct device_queue_manager *dqm) 138 { 139 bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES); 140 bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm)); 141 142 bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES); 143 bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm)); 144 145 /* Mask out the reserved queues */ 146 bitmap_clear(dqm->sdma_bitmap, 0, kfd_get_num_sdma_engines(dqm->dev) * 147 dqm->dev->kfd->device_info.num_reserved_sdma_queues_per_engine); 148 bitmap_clear(dqm->xgmi_sdma_bitmap, 0, kfd_get_num_xgmi_sdma_engines(dqm->dev) * 149 dqm->dev->kfd->device_info.num_reserved_sdma_queues_per_engine); 150 } 151 152 void program_sh_mem_settings(struct device_queue_manager *dqm, 153 struct qcm_process_device *qpd) 154 { 155 uint32_t xcc_mask = dqm->dev->xcc_mask; 156 int xcc_id; 157 158 for_each_inst(xcc_id, xcc_mask) 159 dqm->dev->kfd2kgd->program_sh_mem_settings( 160 dqm->dev->adev, qpd->vmid, qpd->sh_mem_config, 161 qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit, 162 qpd->sh_mem_bases, xcc_id); 163 } 164 165 static void kfd_hws_hang(struct device_queue_manager *dqm) 166 { 167 struct device_process_node *cur; 168 struct qcm_process_device *qpd; 169 struct queue *q; 170 171 /* Mark all device queues as reset. */ 172 list_for_each_entry(cur, &dqm->queues, list) { 173 qpd = cur->qpd; 174 list_for_each_entry(q, &qpd->queues_list, list) { 175 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 176 177 pdd->has_reset_queue = true; 178 } 179 } 180 181 /* 182 * Issue a GPU reset if HWS is unresponsive 183 */ 184 amdgpu_amdkfd_gpu_reset(dqm->dev->adev); 185 } 186 187 static int convert_to_amdgpu_ring_type(int queue_type) 188 { 189 int amdgpu_ring_type; 190 191 switch (queue_type) { 192 case KFD_QUEUE_TYPE_COMPUTE: 193 amdgpu_ring_type = AMDGPU_RING_TYPE_COMPUTE; 194 break; 195 case KFD_QUEUE_TYPE_SDMA: 196 amdgpu_ring_type = AMDGPU_RING_TYPE_SDMA; 197 break; 198 default: 199 WARN(1, "Invalid queue type %d", queue_type); 200 amdgpu_ring_type = -EINVAL; 201 break; 202 } 203 204 return amdgpu_ring_type; 205 } 206 207 static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, 208 struct qcm_process_device *qpd) 209 { 210 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 211 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 212 struct mes_add_queue_input queue_input; 213 int r, queue_type; 214 uint64_t wptr_addr_off; 215 216 if (!dqm->sched_running || dqm->sched_halt) 217 return 0; 218 if (!down_read_trylock(&adev->reset_domain->sem)) 219 return -EIO; 220 221 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 222 queue_input.process_id = pdd->pasid; 223 queue_input.page_table_base_addr = qpd->page_table_base; 224 queue_input.process_va_start = 0; 225 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 226 /* MES unit for quantum is 100ns */ 227 queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */ 228 queue_input.process_context_addr = pdd->proc_ctx_gpu_addr; 229 queue_input.process_context_array_index = pdd->proc_ctx_array_index; 230 queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */ 231 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 232 queue_input.gang_context_array_index = q->gang_ctx_array_index; 233 queue_input.inprocess_gang_priority = q->properties.priority; 234 queue_input.gang_global_priority_level = 235 AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 236 queue_input.doorbell_offset = q->properties.doorbell_off; 237 queue_input.mqd_addr = q->gart_mqd_addr; 238 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; 239 240 wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1); 241 queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q->properties.wptr_bo) + wptr_addr_off; 242 243 queue_input.is_kfd_process = 1; 244 queue_input.is_aql_queue = (q->properties.format == KFD_QUEUE_FORMAT_AQL); 245 queue_input.queue_size = q->properties.queue_size >> 2; 246 247 queue_input.paging = false; 248 queue_input.tba_addr = qpd->tba_addr; 249 queue_input.tma_addr = qpd->tma_addr; 250 queue_input.trap_en = !kfd_dbg_has_cwsr_workaround(q->device); 251 queue_input.skip_process_ctx_clear = 252 qpd->pqm->process->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED && 253 (qpd->pqm->process->debug_trap_enabled || 254 kfd_dbg_has_ttmps_always_setup(q->device)); 255 256 queue_type = convert_to_amdgpu_ring_type(q->properties.type); 257 if (queue_type < 0) { 258 dev_err(adev->dev, "Queue type not supported with MES, queue:%d\n", 259 q->properties.type); 260 up_read(&adev->reset_domain->sem); 261 return -EINVAL; 262 } 263 queue_input.queue_type = (uint32_t)queue_type; 264 265 queue_input.exclusively_scheduled = q->properties.is_gws; 266 queue_input.sh_mem_config_data = qpd->sh_mem_config; 267 queue_input.vm_cntx_cntl = qpd->vm_cntx_cntl; 268 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; 269 270 amdgpu_mes_lock(&adev->mes); 271 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 272 amdgpu_mes_unlock(&adev->mes); 273 up_read(&adev->reset_domain->sem); 274 if (r) { 275 dev_err(adev->dev, "failed to add hardware queue to MES, doorbell=0x%x\n", 276 q->properties.doorbell_off); 277 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); 278 kfd_hws_hang(dqm); 279 } 280 281 return r; 282 } 283 284 static int remove_queue_mes_on_reset_option(struct device_queue_manager *dqm, struct queue *q, 285 struct qcm_process_device *qpd, 286 bool is_for_reset, 287 bool flush_mes_queue) 288 { 289 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 290 int r; 291 struct mes_remove_queue_input queue_input; 292 293 /* queue was already removed during reset */ 294 if (q->properties.is_reset) 295 return 0; 296 297 if (!dqm->sched_running || dqm->sched_halt) 298 return 0; 299 if (!down_read_trylock(&adev->reset_domain->sem)) 300 return -EIO; 301 302 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 303 queue_input.doorbell_offset = q->properties.doorbell_off; 304 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 305 queue_input.queue_type = convert_to_amdgpu_ring_type(q->properties.type); 306 queue_input.remove_queue_after_reset = flush_mes_queue; 307 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; 308 queue_input.gang_context_array_index = q->gang_ctx_array_index; 309 310 amdgpu_mes_lock(&adev->mes); 311 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 312 amdgpu_mes_unlock(&adev->mes); 313 up_read(&adev->reset_domain->sem); 314 315 /* If is_for_reset set, it is a mes internal cleanup */ 316 if (!r || is_for_reset) 317 return r; 318 319 /* remove_hw_queue failure indicates a queue hang. reset the queue */ 320 r = reset_queues_mes(dqm, q); 321 if (r && amdgpu_gpu_recovery) { 322 dev_err(adev->dev, "failed to remove queue from MES, doorbell=0x%x\n", 323 q->properties.doorbell_off); 324 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); 325 kfd_hws_hang(dqm); 326 } 327 328 return r; 329 } 330 331 static void set_perfcount(struct device_queue_manager *dqm, int enable) 332 { 333 struct device_process_node *cur; 334 struct qcm_process_device *qpd; 335 struct queue *q; 336 struct mqd_update_info minfo = { 0 }; 337 338 if (!dqm) 339 return; 340 341 minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : 342 UPDATE_FLAG_PERFCOUNT_DISABLE); 343 dqm_lock(dqm); 344 list_for_each_entry(cur, &dqm->queues, list) { 345 qpd = cur->qpd; 346 list_for_each_entry(q, &qpd->queues_list, list) { 347 pqm_update_mqd(qpd->pqm, q->properties.queue_id, 348 &minfo); 349 } 350 } 351 dqm_unlock(dqm); 352 } 353 354 static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, 355 struct qcm_process_device *qpd) 356 { 357 return remove_queue_mes_on_reset_option(dqm, q, qpd, false, false); 358 } 359 360 static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) 361 { 362 struct device_process_node *cur; 363 struct device *dev = dqm->dev->adev->dev; 364 struct qcm_process_device *qpd; 365 struct queue *q; 366 int retval = 0; 367 368 list_for_each_entry(cur, &dqm->queues, list) { 369 qpd = cur->qpd; 370 list_for_each_entry(q, &qpd->queues_list, list) { 371 if (q->properties.is_active) { 372 retval = remove_queue_mes(dqm, q, qpd); 373 if (retval) { 374 dev_err(dev, "%s: Failed to remove queue %d for dev %d", 375 __func__, 376 q->properties.queue_id, 377 dqm->dev->id); 378 return retval; 379 } 380 } 381 } 382 } 383 384 return retval; 385 } 386 387 static int add_all_kfd_queues_mes(struct device_queue_manager *dqm) 388 { 389 struct device_process_node *cur; 390 struct device *dev = dqm->dev->adev->dev; 391 struct qcm_process_device *qpd; 392 struct queue *q; 393 int retval = 0; 394 395 list_for_each_entry(cur, &dqm->queues, list) { 396 qpd = cur->qpd; 397 list_for_each_entry(q, &qpd->queues_list, list) { 398 if (!q->properties.is_active) 399 continue; 400 retval = add_queue_mes(dqm, q, qpd); 401 if (retval) { 402 dev_err(dev, "%s: Failed to add queue %d for dev %d", 403 __func__, 404 q->properties.queue_id, 405 dqm->dev->id); 406 return retval; 407 } 408 } 409 } 410 411 return retval; 412 } 413 414 static int reset_queue_mes(struct device_queue_manager *dqm, struct queue *q, 415 int queue_type, int pipe, int queue, unsigned int db) 416 { 417 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 418 struct kfd_process_device *pdd; 419 bool use_mmio = adev->gfx.mec.use_mmio_for_reset; 420 int r; 421 422 pdd = kfd_get_process_device_data(q->device, q->process); 423 if (!pdd) 424 return -ENODEV; 425 426 if (use_mmio) 427 r = amdgpu_mes_reset_queue_mmio(adev, queue_type, 0, 1, pipe, queue, 428 ffs(dqm->dev->xcc_mask) - 1); 429 else 430 r = amdgpu_mes_reset_user_queue(adev, queue_type, db, 431 ffs(dqm->dev->xcc_mask) - 1); 432 if (r) 433 return r; 434 /* Proceed remove_queue with reset=true */ 435 remove_queue_mes_on_reset_option(dqm, q, &pdd->qpd, true, true); 436 set_queue_as_reset(dqm, q, &pdd->qpd); 437 return 0; 438 } 439 440 int kfd_reset_queue_mes(struct device_queue_manager *dqm, int queue_type, 441 int pipe, int queue, unsigned int db) 442 { 443 struct queue *q; 444 445 q = find_queue_by_doorbell_offset(dqm, db); 446 if (!q) 447 return 0; 448 return reset_queue_mes(dqm, q, queue_type, pipe, queue, db); 449 } 450 451 static int reset_queues_mes(struct device_queue_manager *dqm, struct queue *q) 452 { 453 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 454 struct drm_wedge_task_info *info = NULL; 455 struct amdgpu_task_info *ti = NULL; 456 struct kfd_process_device *pdd; 457 unsigned int num_hung = 0; 458 int r = 0; 459 struct mes_remove_queue_input queue_input; 460 461 if (!amdgpu_mes_queue_reset_by_mes_supported(adev)) { 462 r = -ENOTRECOVERABLE; 463 goto fail; 464 } 465 466 /* reset should be used only in dqm locked queue reset */ 467 if (WARN_ON(dqm->detect_hang_count > 0)) 468 return 0; 469 470 if (!amdgpu_gpu_recovery) { 471 r = -ENOTRECOVERABLE; 472 goto fail; 473 } 474 475 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 476 queue_input.doorbell_offset = q->properties.doorbell_off; 477 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 478 queue_input.queue_type = convert_to_amdgpu_ring_type(q->properties.type); 479 queue_input.remove_queue_after_reset = false; 480 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; 481 /* pass the known bad queue info to the reset function */ 482 r = amdgpu_gfx_reset_mes_compute(adev, NULL, NULL, NULL, &num_hung, &queue_input); 483 if (r) 484 goto fail; 485 pdd = kfd_get_process_device_data(q->device, q->process); 486 if (pdd) { 487 ti = amdgpu_vm_get_task_info_pasid(adev, pdd->pasid); 488 if (ti) { 489 amdgpu_vm_print_task_info(adev, ti); 490 info = &ti->task; 491 } 492 } 493 494 dqm->detect_hang_count = num_hung; 495 /* When MES doesn't detect any queue hang, no reset happens. Don't signal reset 496 * event. 497 */ 498 if (dqm->detect_hang_count) { 499 kfd_signal_reset_event(dqm->dev); 500 if (pdd && pdd->has_reset_queue) { 501 atomic_inc(&adev->gpu_reset_counter); 502 drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, info); 503 } 504 } 505 amdgpu_vm_put_task_info(ti); 506 507 fail: 508 dqm->detect_hang_count = 0; 509 return r; 510 } 511 512 static void increment_queue_count(struct device_queue_manager *dqm, 513 struct qcm_process_device *qpd, 514 struct queue *q) 515 { 516 dqm->active_queue_count++; 517 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 518 dqm->active_cp_queue_count++; 519 520 if (q->properties.is_gws) { 521 dqm->gws_queue_count++; 522 qpd->mapped_gws_queue = true; 523 } 524 } 525 526 static void decrement_queue_count(struct device_queue_manager *dqm, 527 struct qcm_process_device *qpd, 528 struct queue *q) 529 { 530 dqm->active_queue_count--; 531 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 532 dqm->active_cp_queue_count--; 533 534 if (q->properties.is_gws) { 535 dqm->gws_queue_count--; 536 qpd->mapped_gws_queue = false; 537 } 538 } 539 540 /* 541 * Allocate a doorbell ID to this queue. 542 * If doorbell_id is passed in, make sure requested ID is valid then allocate it. 543 */ 544 static int allocate_doorbell(struct qcm_process_device *qpd, 545 struct queue *q, 546 uint32_t const *restore_id) 547 { 548 struct kfd_node *dev = qpd->dqm->dev; 549 550 if (!KFD_IS_SOC15(dev)) { 551 /* On pre-SOC15 chips we need to use the queue ID to 552 * preserve the user mode ABI. 553 */ 554 555 if (restore_id && *restore_id != q->properties.queue_id) 556 return -EINVAL; 557 558 q->doorbell_id = q->properties.queue_id; 559 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 560 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 561 /* For SDMA queues on SOC15 with 8-byte doorbell, use static 562 * doorbell assignments based on the engine and queue id. 563 * The doobell index distance between RLC (2*i) and (2*i+1) 564 * for a SDMA engine is 512. 565 */ 566 567 uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx; 568 569 /* 570 * q->properties.sdma_engine_id corresponds to the virtual 571 * sdma engine number. However, for doorbell allocation, 572 * we need the physical sdma engine id in order to get the 573 * correct doorbell offset. 574 */ 575 uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id * 576 get_num_all_sdma_engines(qpd->dqm) + 577 q->properties.sdma_engine_id] 578 + (q->properties.sdma_queue_id & 1) 579 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET 580 + (q->properties.sdma_queue_id >> 1); 581 582 if (restore_id && *restore_id != valid_id) 583 return -EINVAL; 584 q->doorbell_id = valid_id; 585 } else { 586 /* For CP queues on SOC15 */ 587 if (restore_id) { 588 if (*restore_id >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 589 return -EINVAL; 590 591 /* make sure that ID is free */ 592 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap)) 593 return -EINVAL; 594 595 q->doorbell_id = *restore_id; 596 } else { 597 /* or reserve a free doorbell ID */ 598 unsigned int found; 599 600 found = find_first_zero_bit(qpd->doorbell_bitmap, 601 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 602 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 603 pr_debug("No doorbells available"); 604 return -EBUSY; 605 } 606 set_bit(found, qpd->doorbell_bitmap); 607 q->doorbell_id = found; 608 } 609 } 610 611 q->properties.doorbell_off = amdgpu_doorbell_index_on_bar(dev->adev, 612 qpd->proc_doorbells, 613 q->doorbell_id, 614 dev->kfd->device_info.doorbell_size); 615 return 0; 616 } 617 618 static void deallocate_doorbell(struct qcm_process_device *qpd, 619 struct queue *q) 620 { 621 unsigned int old; 622 struct kfd_node *dev = qpd->dqm->dev; 623 624 if (!KFD_IS_SOC15(dev) || 625 q->properties.type == KFD_QUEUE_TYPE_SDMA || 626 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 627 return; 628 629 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap); 630 WARN_ON(!old); 631 } 632 633 static void program_trap_handler_settings(struct device_queue_manager *dqm, 634 struct qcm_process_device *qpd) 635 { 636 uint32_t xcc_mask = dqm->dev->xcc_mask; 637 int xcc_id; 638 639 if (dqm->dev->kfd2kgd->program_trap_handler_settings) 640 for_each_inst(xcc_id, xcc_mask) 641 dqm->dev->kfd2kgd->program_trap_handler_settings( 642 dqm->dev->adev, qpd->vmid, qpd->tba_addr, 643 qpd->tma_addr, xcc_id); 644 } 645 646 static int allocate_vmid(struct device_queue_manager *dqm, 647 struct qcm_process_device *qpd, 648 struct queue *q) 649 { 650 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 651 struct device *dev = dqm->dev->adev->dev; 652 int allocated_vmid = -1, i; 653 654 for (i = dqm->dev->vm_info.first_vmid_kfd; 655 i <= dqm->dev->vm_info.last_vmid_kfd; i++) { 656 if (!dqm->vmid_pasid[i]) { 657 allocated_vmid = i; 658 break; 659 } 660 } 661 662 if (allocated_vmid < 0) { 663 dev_err(dev, "no more vmid to allocate\n"); 664 return -ENOSPC; 665 } 666 667 pr_debug("vmid allocated: %d\n", allocated_vmid); 668 669 dqm->vmid_pasid[allocated_vmid] = pdd->pasid; 670 671 set_pasid_vmid_mapping(dqm, pdd->pasid, allocated_vmid); 672 673 qpd->vmid = allocated_vmid; 674 q->properties.vmid = allocated_vmid; 675 676 program_sh_mem_settings(dqm, qpd); 677 678 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->kfd->cwsr_enabled) 679 program_trap_handler_settings(dqm, qpd); 680 681 /* qpd->page_table_base is set earlier when register_process() 682 * is called, i.e. when the first queue is created. 683 */ 684 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev, 685 qpd->vmid, 686 qpd->page_table_base); 687 /* invalidate the VM context after pasid and vmid mapping is set up */ 688 kfd_flush_tlb(qpd_to_pdd(qpd)); 689 690 if (dqm->dev->kfd2kgd->set_scratch_backing_va) 691 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev, 692 qpd->sh_hidden_private_base, qpd->vmid); 693 694 return 0; 695 } 696 697 static int flush_texture_cache_nocpsch(struct kfd_node *kdev, 698 struct qcm_process_device *qpd) 699 { 700 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf; 701 int ret; 702 703 if (!qpd->ib_kaddr) 704 return -ENOMEM; 705 706 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr); 707 if (ret) 708 return ret; 709 710 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid, 711 qpd->ib_base, (uint32_t *)qpd->ib_kaddr, 712 pmf->release_mem_size / sizeof(uint32_t)); 713 } 714 715 static void deallocate_vmid(struct device_queue_manager *dqm, 716 struct qcm_process_device *qpd, 717 struct queue *q) 718 { 719 struct device *dev = dqm->dev->adev->dev; 720 721 /* On GFX v7, CP doesn't flush TC at dequeue */ 722 if (q->device->adev->asic_type == CHIP_HAWAII) 723 if (flush_texture_cache_nocpsch(q->device, qpd)) 724 dev_err(dev, "Failed to flush TC\n"); 725 726 kfd_flush_tlb(qpd_to_pdd(qpd)); 727 728 /* Release the vmid mapping */ 729 set_pasid_vmid_mapping(dqm, 0, qpd->vmid); 730 dqm->vmid_pasid[qpd->vmid] = 0; 731 732 qpd->vmid = 0; 733 q->properties.vmid = 0; 734 } 735 736 static int create_queue_nocpsch(struct device_queue_manager *dqm, 737 struct queue *q, 738 struct qcm_process_device *qpd, 739 const struct kfd_criu_queue_priv_data *qd, 740 const void *restore_mqd, const void *restore_ctl_stack) 741 { 742 struct mqd_manager *mqd_mgr; 743 int retval; 744 745 dqm_lock(dqm); 746 747 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 748 pr_warn("Can't create new usermode queue because %d queues were already created\n", 749 dqm->total_queue_count); 750 retval = -EPERM; 751 goto out_unlock; 752 } 753 754 if (list_empty(&qpd->queues_list)) { 755 retval = allocate_vmid(dqm, qpd, q); 756 if (retval) 757 goto out_unlock; 758 } 759 q->properties.vmid = qpd->vmid; 760 /* 761 * Eviction state logic: mark all queues as evicted, even ones 762 * not currently active. Restoring inactive queues later only 763 * updates the is_evicted flag but is a no-op otherwise. 764 */ 765 q->properties.is_evicted = !!qpd->evicted; 766 767 q->properties.tba_addr = qpd->tba_addr; 768 q->properties.tma_addr = qpd->tma_addr; 769 770 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 771 q->properties.type)]; 772 if (qd && !mqd_mgr->restore_mqd) { 773 pr_debug("restore_mqd not implemented for queue type %d\n", 774 q->properties.type); 775 retval = -EOPNOTSUPP; 776 goto deallocate_vmid; 777 } 778 779 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { 780 retval = allocate_hqd(dqm, q); 781 if (retval) 782 goto deallocate_vmid; 783 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", 784 q->pipe, q->queue); 785 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 786 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 787 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 788 if (retval) 789 goto deallocate_vmid; 790 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 791 } 792 793 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 794 if (retval) 795 goto out_deallocate_hqd; 796 797 /* Temporarily release dqm lock to avoid a circular lock dependency */ 798 dqm_unlock(dqm); 799 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); 800 dqm_lock(dqm); 801 802 if (!q->mqd_mem_obj) { 803 retval = -ENOMEM; 804 goto out_deallocate_doorbell; 805 } 806 807 if (qd) 808 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 809 &q->properties, restore_mqd, restore_ctl_stack, 810 qd->ctl_stack_size); 811 else 812 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 813 &q->gart_mqd_addr, &q->properties); 814 815 if (q->properties.is_active) { 816 if (!dqm->sched_running) { 817 WARN_ONCE(1, "Load non-HWS mqd while stopped\n"); 818 goto add_queue_to_list; 819 } 820 821 if (WARN(q->process->mm != current->mm, 822 "should only run in user thread")) 823 retval = -EFAULT; 824 else 825 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 826 q->queue, &q->properties, current->mm); 827 if (retval) 828 goto out_free_mqd; 829 } 830 831 add_queue_to_list: 832 list_add(&q->list, &qpd->queues_list); 833 qpd->queue_count++; 834 if (q->properties.is_active) 835 increment_queue_count(dqm, qpd, q); 836 837 /* 838 * Unconditionally increment this counter, regardless of the queue's 839 * type or whether the queue is active. 840 */ 841 dqm->total_queue_count++; 842 pr_debug("Total of %d queues are accountable so far\n", 843 dqm->total_queue_count); 844 goto out_unlock; 845 846 out_free_mqd: 847 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 848 out_deallocate_doorbell: 849 deallocate_doorbell(qpd, q); 850 out_deallocate_hqd: 851 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 852 deallocate_hqd(dqm, q); 853 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 854 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 855 deallocate_sdma_queue(dqm, q); 856 deallocate_vmid: 857 if (list_empty(&qpd->queues_list)) 858 deallocate_vmid(dqm, qpd, q); 859 out_unlock: 860 dqm_unlock(dqm); 861 return retval; 862 } 863 864 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) 865 { 866 bool set; 867 int pipe, bit, i; 868 869 set = false; 870 871 for (pipe = dqm->next_pipe_to_allocate, i = 0; 872 i < get_pipes_per_mec(dqm); 873 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { 874 875 if (!is_pipe_enabled(dqm, 0, pipe)) 876 continue; 877 878 if (dqm->allocated_queues[pipe] != 0) { 879 bit = ffs(dqm->allocated_queues[pipe]) - 1; 880 dqm->allocated_queues[pipe] &= ~(1 << bit); 881 q->pipe = pipe; 882 q->queue = bit; 883 set = true; 884 break; 885 } 886 } 887 888 if (!set) 889 return -EBUSY; 890 891 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); 892 /* horizontal hqd allocation */ 893 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); 894 895 return 0; 896 } 897 898 static inline void deallocate_hqd(struct device_queue_manager *dqm, 899 struct queue *q) 900 { 901 dqm->allocated_queues[q->pipe] |= (1 << q->queue); 902 } 903 904 #define SQ_IND_CMD_CMD_KILL 0x00000003 905 #define SQ_IND_CMD_MODE_BROADCAST 0x00000001 906 907 static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process *p) 908 { 909 int status = 0; 910 unsigned int vmid; 911 uint16_t queried_pasid; 912 union SQ_CMD_BITS reg_sq_cmd; 913 union GRBM_GFX_INDEX_BITS reg_gfx_index; 914 struct kfd_process_device *pdd; 915 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd; 916 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd; 917 uint32_t xcc_mask = dev->xcc_mask; 918 int xcc_id; 919 920 reg_sq_cmd.u32All = 0; 921 reg_gfx_index.u32All = 0; 922 923 pr_debug("Killing all process wavefronts\n"); 924 925 if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) { 926 dev_err(dev->adev->dev, "no vmid pasid mapping supported\n"); 927 return -EOPNOTSUPP; 928 } 929 930 /* taking the VMID for that process on the safe way using PDD */ 931 pdd = kfd_get_process_device_data(dev, p); 932 if (!pdd) 933 return -EFAULT; 934 935 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING .. 936 * ATC_VMID15_PASID_MAPPING 937 * to check which VMID the current process is mapped to. 938 */ 939 940 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) { 941 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info 942 (dev->adev, vmid, &queried_pasid); 943 944 if (status && queried_pasid == pdd->pasid) { 945 pr_debug("Killing wave fronts of vmid %d and process pid %d\n", 946 vmid, p->lead_thread->pid); 947 break; 948 } 949 } 950 951 if (vmid > last_vmid_to_scan) { 952 dev_err(dev->adev->dev, "Didn't find vmid for process pid %d\n", 953 p->lead_thread->pid); 954 return -EFAULT; 955 } 956 957 reg_gfx_index.bits.sh_broadcast_writes = 1; 958 reg_gfx_index.bits.se_broadcast_writes = 1; 959 reg_gfx_index.bits.instance_broadcast_writes = 1; 960 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; 961 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL; 962 reg_sq_cmd.bits.vm_id = vmid; 963 964 for_each_inst(xcc_id, xcc_mask) 965 dev->kfd2kgd->wave_control_execute( 966 dev->adev, reg_gfx_index.u32All, 967 reg_sq_cmd.u32All, xcc_id); 968 969 return 0; 970 } 971 972 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked 973 * to avoid asynchronized access 974 */ 975 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, 976 struct qcm_process_device *qpd, 977 struct queue *q) 978 { 979 int retval; 980 struct mqd_manager *mqd_mgr; 981 982 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 983 984 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 985 deallocate_hqd(dqm, q); 986 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 987 deallocate_sdma_queue(dqm, q); 988 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 989 deallocate_sdma_queue(dqm, q); 990 else { 991 pr_debug("q->properties.type %d is invalid\n", 992 q->properties.type); 993 return -EINVAL; 994 } 995 dqm->total_queue_count--; 996 997 deallocate_doorbell(qpd, q); 998 999 if (!dqm->sched_running) { 1000 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n"); 1001 return 0; 1002 } 1003 1004 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 1005 KFD_PREEMPT_TYPE_WAVEFRONT_RESET, 1006 KFD_UNMAP_LATENCY_MS, 1007 q->pipe, q->queue); 1008 if (retval == -ETIME) 1009 qpd->reset_wavefronts = true; 1010 1011 list_del(&q->list); 1012 if (list_empty(&qpd->queues_list)) { 1013 if (qpd->reset_wavefronts) { 1014 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n", 1015 dqm->dev); 1016 /* dbgdev_wave_reset_wavefronts has to be called before 1017 * deallocate_vmid(), i.e. when vmid is still in use. 1018 */ 1019 dbgdev_wave_reset_wavefronts(dqm->dev, 1020 qpd->pqm->process); 1021 qpd->reset_wavefronts = false; 1022 } 1023 1024 deallocate_vmid(dqm, qpd, q); 1025 } 1026 qpd->queue_count--; 1027 if (q->properties.is_active) 1028 decrement_queue_count(dqm, qpd, q); 1029 1030 return retval; 1031 } 1032 1033 static int destroy_queue_nocpsch(struct device_queue_manager *dqm, 1034 struct qcm_process_device *qpd, 1035 struct queue *q) 1036 { 1037 int retval; 1038 uint64_t sdma_val = 0; 1039 struct device *dev = dqm->dev->adev->dev; 1040 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 1041 struct mqd_manager *mqd_mgr = 1042 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 1043 1044 /* Get the SDMA queue stats */ 1045 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 1046 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1047 if (dqm->dev->kfd2kgd->hqd_sdma_get_counter) 1048 retval = dqm->dev->kfd2kgd->hqd_sdma_get_counter( 1049 dqm->dev->adev, q->mqd, 1050 dqm->dev->kfd->device_info.num_sdma_queues_per_engine, 1051 &sdma_val); 1052 else 1053 retval = read_sdma_queue_counter( 1054 (uint64_t __user *)q->properties.read_ptr, 1055 &sdma_val); 1056 if (retval) 1057 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n", 1058 q->properties.queue_id); 1059 } 1060 1061 dqm_lock(dqm); 1062 retval = destroy_queue_nocpsch_locked(dqm, qpd, q); 1063 if (!retval) 1064 pdd->sdma_past_activity_counter += sdma_val; 1065 dqm_unlock(dqm); 1066 1067 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1068 1069 return retval; 1070 } 1071 1072 static int update_queue(struct device_queue_manager *dqm, struct queue *q, 1073 struct mqd_update_info *minfo) 1074 { 1075 int retval = 0; 1076 struct device *dev = dqm->dev->adev->dev; 1077 struct mqd_manager *mqd_mgr; 1078 struct kfd_process_device *pdd; 1079 bool prev_active = false; 1080 1081 dqm_lock(dqm); 1082 pdd = kfd_get_process_device_data(q->device, q->process); 1083 if (!pdd) { 1084 retval = -ENODEV; 1085 goto out_unlock; 1086 } 1087 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1088 q->properties.type)]; 1089 1090 /* Save previous activity state for counters */ 1091 prev_active = q->properties.is_active; 1092 1093 /* Make sure the queue is unmapped before updating the MQD */ 1094 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 1095 if (!dqm->dev->kfd->shared_resources.enable_mes) 1096 retval = unmap_queues_cpsch(dqm, 1097 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false); 1098 else if (prev_active) 1099 retval = remove_queue_mes(dqm, q, &pdd->qpd); 1100 1101 /* queue is reset so inaccessable */ 1102 if (pdd->has_reset_queue) { 1103 retval = -EACCES; 1104 goto out_unlock; 1105 } 1106 1107 if (retval) { 1108 dev_err(dev, "unmap queue failed\n"); 1109 goto out_unlock; 1110 } 1111 } else if (prev_active && 1112 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 1113 q->properties.type == KFD_QUEUE_TYPE_SDMA || 1114 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1115 1116 if (!dqm->sched_running) { 1117 WARN_ONCE(1, "Update non-HWS queue while stopped\n"); 1118 goto out_unlock; 1119 } 1120 1121 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 1122 (dqm->dev->kfd->cwsr_enabled ? 1123 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 1124 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 1125 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 1126 if (retval) { 1127 dev_err(dev, "destroy mqd failed\n"); 1128 goto out_unlock; 1129 } 1130 } 1131 1132 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo); 1133 1134 /* 1135 * check active state vs. the previous state and modify 1136 * counter accordingly. map_queues_cpsch uses the 1137 * dqm->active_queue_count to determine whether a new runlist must be 1138 * uploaded. 1139 */ 1140 if (q->properties.is_active && !prev_active) { 1141 increment_queue_count(dqm, &pdd->qpd, q); 1142 } else if (!q->properties.is_active && prev_active) { 1143 decrement_queue_count(dqm, &pdd->qpd, q); 1144 } else if (q->gws && !q->properties.is_gws) { 1145 if (q->properties.is_active) { 1146 dqm->gws_queue_count++; 1147 pdd->qpd.mapped_gws_queue = true; 1148 } 1149 q->properties.is_gws = true; 1150 } else if (!q->gws && q->properties.is_gws) { 1151 if (q->properties.is_active) { 1152 dqm->gws_queue_count--; 1153 pdd->qpd.mapped_gws_queue = false; 1154 } 1155 q->properties.is_gws = false; 1156 } 1157 1158 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 1159 if (!dqm->dev->kfd->shared_resources.enable_mes) 1160 retval = map_queues_cpsch(dqm); 1161 else if (q->properties.is_active) 1162 retval = add_queue_mes(dqm, q, &pdd->qpd); 1163 } else if (q->properties.is_active && 1164 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 1165 q->properties.type == KFD_QUEUE_TYPE_SDMA || 1166 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1167 if (WARN(q->process->mm != current->mm, 1168 "should only run in user thread")) 1169 retval = -EFAULT; 1170 else 1171 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, 1172 q->pipe, q->queue, 1173 &q->properties, current->mm); 1174 } 1175 1176 out_unlock: 1177 dqm_unlock(dqm); 1178 return retval; 1179 } 1180 1181 /* suspend_single_queue does not lock the dqm like the 1182 * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should 1183 * lock the dqm before calling, and unlock after calling. 1184 * 1185 * The reason we don't lock the dqm is because this function may be 1186 * called on multiple queues in a loop, so rather than locking/unlocking 1187 * multiple times, we will just keep the dqm locked for all of the calls. 1188 */ 1189 static int suspend_single_queue(struct device_queue_manager *dqm, 1190 struct kfd_process_device *pdd, 1191 struct queue *q) 1192 { 1193 bool is_new; 1194 1195 if (q->properties.is_suspended) 1196 return 0; 1197 1198 pr_debug("Suspending process pid %d queue [%i]\n", 1199 pdd->process->lead_thread->pid, 1200 q->properties.queue_id); 1201 1202 is_new = q->properties.exception_status & KFD_EC_MASK(EC_QUEUE_NEW); 1203 1204 if (is_new || q->properties.is_being_destroyed) { 1205 pr_debug("Suspend: skip %s queue id %i\n", 1206 is_new ? "new" : "destroyed", 1207 q->properties.queue_id); 1208 return -EBUSY; 1209 } 1210 1211 q->properties.is_suspended = true; 1212 if (q->properties.is_active) { 1213 if (dqm->dev->kfd->shared_resources.enable_mes) { 1214 int r = remove_queue_mes(dqm, q, &pdd->qpd); 1215 1216 if (r) 1217 return r; 1218 } 1219 1220 decrement_queue_count(dqm, &pdd->qpd, q); 1221 q->properties.is_active = false; 1222 } 1223 1224 return 0; 1225 } 1226 1227 /* resume_single_queue does not lock the dqm like the functions 1228 * restore_process_queues_cpsch or restore_process_queues_nocpsch. You should 1229 * lock the dqm before calling, and unlock after calling. 1230 * 1231 * The reason we don't lock the dqm is because this function may be 1232 * called on multiple queues in a loop, so rather than locking/unlocking 1233 * multiple times, we will just keep the dqm locked for all of the calls. 1234 */ 1235 static int resume_single_queue(struct device_queue_manager *dqm, 1236 struct qcm_process_device *qpd, 1237 struct queue *q) 1238 { 1239 struct kfd_process_device *pdd; 1240 1241 if (!q->properties.is_suspended) 1242 return 0; 1243 1244 pdd = qpd_to_pdd(qpd); 1245 1246 pr_debug("Restoring from suspend process pid %d queue [%i]\n", 1247 pdd->process->lead_thread->pid, 1248 q->properties.queue_id); 1249 1250 q->properties.is_suspended = false; 1251 1252 if (QUEUE_IS_ACTIVE(q->properties)) { 1253 if (dqm->dev->kfd->shared_resources.enable_mes) { 1254 int r = add_queue_mes(dqm, q, &pdd->qpd); 1255 1256 if (r) 1257 return r; 1258 } 1259 1260 q->properties.is_active = true; 1261 increment_queue_count(dqm, qpd, q); 1262 } 1263 1264 return 0; 1265 } 1266 1267 /* Unpin the MQD BO at S4 suspend so it is evicted into the hibernation image; 1268 * dqm_repin_mqd_bo() pins it back on resume. Gated on adev->in_s4 so runtime 1269 * eviction is untouched. 1270 */ 1271 static void dqm_evict_mqd_bo(struct device_queue_manager *dqm, struct queue *q) 1272 { 1273 struct mqd_manager *mqd_mgr; 1274 struct amdgpu_bo *bo; 1275 1276 if (!dqm->dev->adev->in_s4) 1277 return; 1278 if (!mqd_on_vram(dqm->dev->adev)) 1279 return; 1280 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE) 1281 return; 1282 if (!q->mqd_mem_obj || !q->mqd_mem_obj->mem) 1283 return; 1284 1285 /* Without update_mqd_gpu_addr() the MQD self-address cannot be fixed up 1286 * after a repin, so skip eviction (with a warning) instead of faulting. 1287 */ 1288 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 1289 if (!mqd_mgr->update_mqd_gpu_addr) { 1290 dev_warn_once(dqm->dev->adev->dev, 1291 "MQD is in VRAM but update_mqd_gpu_addr is not implemented; skipping hibernation eviction\n"); 1292 return; 1293 } 1294 1295 bo = q->mqd_mem_obj->mem; 1296 if (amdgpu_bo_reserve(bo, false)) 1297 return; 1298 1299 amdgpu_bo_unpin(bo); 1300 amdgpu_bo_unreserve(bo); 1301 q->mqd = NULL; 1302 q->needs_mqd_repin = true; 1303 } 1304 1305 /* Repin the MQD BO to VRAM and refresh the cached mapping and GPU addresses. 1306 * Used both on resume and when a queue is destroyed before resume has repinned 1307 * it. A no-op unless a repin is owed (needs_mqd_repin set). 1308 */ 1309 static int dqm_repin_mqd_bo(struct device_queue_manager *dqm, struct queue *q) 1310 { 1311 struct mqd_manager *mqd_mgr; 1312 struct amdgpu_bo *bo; 1313 void *cpu_ptr; 1314 int r; 1315 1316 if (!q->needs_mqd_repin) 1317 return 0; 1318 if (!q->mqd_mem_obj || !q->mqd_mem_obj->mem) 1319 return 0; 1320 1321 bo = q->mqd_mem_obj->mem; 1322 r = amdgpu_bo_reserve(bo, false); 1323 if (r) 1324 return r; 1325 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM); 1326 if (r) { 1327 amdgpu_bo_unreserve(bo); 1328 dev_err(dqm->dev->adev->dev, 1329 "Failed to repin MQD of queue %d to VRAM: %d\n", 1330 q->properties.queue_id, r); 1331 return r; 1332 } 1333 /* The BO may have moved; refresh the kernel mapping and gpu address. */ 1334 amdgpu_bo_kunmap(bo); 1335 r = amdgpu_bo_kmap(bo, &cpu_ptr); 1336 amdgpu_bo_unreserve(bo); 1337 if (r) { 1338 dev_err(dqm->dev->adev->dev, 1339 "Failed to remap MQD of queue %d: %d\n", 1340 q->properties.queue_id, r); 1341 return r; 1342 } 1343 1344 q->mqd_mem_obj->cpu_ptr = cpu_ptr; 1345 q->mqd_mem_obj->gpu_addr = amdgpu_bo_gpu_offset(bo); 1346 q->gart_mqd_addr = q->mqd_mem_obj->gpu_addr; 1347 q->mqd = cpu_ptr; 1348 1349 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1350 q->properties.type)]; 1351 if (mqd_mgr->update_mqd_gpu_addr) 1352 mqd_mgr->update_mqd_gpu_addr(mqd_mgr, q->mqd, 1353 q->mqd_mem_obj, 1354 &q->properties); 1355 1356 q->needs_mqd_repin = false; 1357 return 0; 1358 } 1359 1360 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm, 1361 struct qcm_process_device *qpd) 1362 { 1363 struct queue *q; 1364 struct mqd_manager *mqd_mgr; 1365 struct kfd_process_device *pdd; 1366 int retval, ret = 0; 1367 1368 dqm_lock(dqm); 1369 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 1370 goto out; 1371 1372 pdd = qpd_to_pdd(qpd); 1373 pr_debug_ratelimited("Evicting process pid %d queues\n", 1374 pdd->process->lead_thread->pid); 1375 1376 pdd->last_evict_timestamp = get_jiffies_64(); 1377 /* Mark all queues as evicted. Deactivate all active queues on 1378 * the qpd. 1379 */ 1380 list_for_each_entry(q, &qpd->queues_list, list) { 1381 q->properties.is_evicted = true; 1382 if (!q->properties.is_active) 1383 continue; 1384 1385 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1386 q->properties.type)]; 1387 q->properties.is_active = false; 1388 decrement_queue_count(dqm, qpd, q); 1389 1390 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n")) 1391 continue; 1392 1393 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 1394 (dqm->dev->kfd->cwsr_enabled ? 1395 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 1396 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 1397 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 1398 if (retval && !ret) 1399 /* Return the first error, but keep going to 1400 * maintain a consistent eviction state 1401 */ 1402 ret = retval; 1403 } 1404 1405 out: 1406 dqm_unlock(dqm); 1407 return ret; 1408 } 1409 1410 static int evict_process_queues_cpsch(struct device_queue_manager *dqm, 1411 struct qcm_process_device *qpd) 1412 { 1413 struct queue *q; 1414 struct device *dev = dqm->dev->adev->dev; 1415 struct kfd_process_device *pdd; 1416 int retval = 0; 1417 1418 dqm_lock(dqm); 1419 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 1420 goto out; 1421 1422 pdd = qpd_to_pdd(qpd); 1423 1424 /* The debugger creates processes that temporarily have not acquired 1425 * all VMs for all devices and has no VMs itself. 1426 * Skip queue eviction on process eviction. 1427 */ 1428 if (!pdd->drm_priv) 1429 goto out; 1430 1431 pr_debug_ratelimited("Evicting process pid %d queues\n", 1432 pdd->process->lead_thread->pid); 1433 1434 if (dqm->dev->kfd->shared_resources.enable_mes) 1435 pdd->last_evict_timestamp = get_jiffies_64(); 1436 1437 /* Mark all queues as evicted. Deactivate all active queues on 1438 * the qpd. 1439 */ 1440 list_for_each_entry(q, &qpd->queues_list, list) { 1441 q->properties.is_evicted = true; 1442 if (!q->properties.is_active) 1443 continue; 1444 1445 q->properties.is_active = false; 1446 decrement_queue_count(dqm, qpd, q); 1447 1448 if (dqm->dev->kfd->shared_resources.enable_mes) { 1449 retval = remove_queue_mes(dqm, q, qpd); 1450 if (retval) { 1451 dev_err(dev, "Failed to evict queue %d\n", 1452 q->properties.queue_id); 1453 goto out; 1454 } 1455 } 1456 1457 dqm_evict_mqd_bo(dqm, q); 1458 } 1459 1460 /* 1461 * Heavy-weight TLB flush after MES removes queues to ensure 1462 * in-flight memory accesses complete before memory is freed/migrated. 1463 * HWS does this automatically, MES does not. 1464 */ 1465 if (dqm->dev->kfd->shared_resources.enable_mes) 1466 kfd_flush_tlb(pdd); 1467 1468 if (!dqm->dev->kfd->shared_resources.enable_mes) { 1469 pdd->last_evict_timestamp = get_jiffies_64(); 1470 retval = execute_queues_cpsch(dqm, 1471 qpd->is_debug ? 1472 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : 1473 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 1474 USE_DEFAULT_GRACE_PERIOD); 1475 } 1476 1477 out: 1478 dqm_unlock(dqm); 1479 return retval; 1480 } 1481 1482 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, 1483 struct qcm_process_device *qpd) 1484 { 1485 struct mm_struct *mm = NULL; 1486 struct queue *q; 1487 struct mqd_manager *mqd_mgr; 1488 struct kfd_process_device *pdd; 1489 uint64_t pd_base; 1490 uint64_t eviction_duration; 1491 int retval, ret = 0; 1492 1493 pdd = qpd_to_pdd(qpd); 1494 /* Retrieve PD base */ 1495 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1496 1497 dqm_lock(dqm); 1498 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 1499 goto out; 1500 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 1501 qpd->evicted--; 1502 goto out; 1503 } 1504 1505 pr_debug_ratelimited("Restoring process pid %d queues\n", 1506 pdd->process->lead_thread->pid); 1507 1508 /* Update PD Base in QPD */ 1509 qpd->page_table_base = pd_base; 1510 pr_debug("Updated PD address to 0x%llx\n", pd_base); 1511 1512 if (!list_empty(&qpd->queues_list)) { 1513 dqm->dev->kfd2kgd->set_vm_context_page_table_base( 1514 dqm->dev->adev, 1515 qpd->vmid, 1516 qpd->page_table_base); 1517 kfd_flush_tlb(pdd); 1518 } 1519 1520 /* Take a safe reference to the mm_struct, which may otherwise 1521 * disappear even while the kfd_process is still referenced. 1522 */ 1523 mm = get_task_mm(pdd->process->lead_thread); 1524 if (!mm) { 1525 ret = -EFAULT; 1526 goto out; 1527 } 1528 1529 /* Remove the eviction flags. Activate queues that are not 1530 * inactive for other reasons. 1531 */ 1532 list_for_each_entry(q, &qpd->queues_list, list) { 1533 q->properties.is_evicted = false; 1534 if (!QUEUE_IS_ACTIVE(q->properties)) 1535 continue; 1536 1537 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1538 q->properties.type)]; 1539 q->properties.is_active = true; 1540 increment_queue_count(dqm, qpd, q); 1541 1542 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n")) 1543 continue; 1544 1545 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 1546 q->queue, &q->properties, mm); 1547 if (retval && !ret) 1548 /* Return the first error, but keep going to 1549 * maintain a consistent eviction state 1550 */ 1551 ret = retval; 1552 } 1553 qpd->evicted = 0; 1554 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 1555 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 1556 out: 1557 if (mm) 1558 mmput(mm); 1559 dqm_unlock(dqm); 1560 return ret; 1561 } 1562 1563 static int restore_process_queues_cpsch(struct device_queue_manager *dqm, 1564 struct qcm_process_device *qpd) 1565 { 1566 struct queue *q; 1567 struct device *dev = dqm->dev->adev->dev; 1568 struct kfd_process_device *pdd; 1569 uint64_t eviction_duration; 1570 int retval = 0; 1571 1572 pdd = qpd_to_pdd(qpd); 1573 1574 dqm_lock(dqm); 1575 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 1576 goto out; 1577 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 1578 qpd->evicted--; 1579 goto out; 1580 } 1581 1582 /* The debugger creates processes that temporarily have not acquired 1583 * all VMs for all devices and has no VMs itself. 1584 * Skip queue restore on process restore. 1585 */ 1586 if (!pdd->drm_priv) 1587 goto vm_not_acquired; 1588 1589 pr_debug_ratelimited("Restoring process pid %d queues\n", 1590 pdd->process->lead_thread->pid); 1591 1592 /* Update PD Base in QPD */ 1593 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1594 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base); 1595 1596 /* activate all active queues on the qpd */ 1597 list_for_each_entry(q, &qpd->queues_list, list) { 1598 q->properties.is_evicted = false; 1599 if (!QUEUE_IS_ACTIVE(q->properties)) 1600 continue; 1601 1602 q->properties.is_active = true; 1603 increment_queue_count(dqm, &pdd->qpd, q); 1604 1605 retval = dqm_repin_mqd_bo(dqm, q); 1606 if (retval) { 1607 dev_err(dev, "Failed to repin MQD for queue %d\n", 1608 q->properties.queue_id); 1609 goto out; 1610 } 1611 1612 if (dqm->dev->kfd->shared_resources.enable_mes) { 1613 retval = add_queue_mes(dqm, q, qpd); 1614 if (retval) { 1615 dev_err(dev, "Failed to restore queue %d\n", 1616 q->properties.queue_id); 1617 goto out; 1618 } 1619 } 1620 } 1621 if (!dqm->dev->kfd->shared_resources.enable_mes) 1622 retval = execute_queues_cpsch(dqm, 1623 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1624 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 1625 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 1626 vm_not_acquired: 1627 qpd->evicted = 0; 1628 out: 1629 dqm_unlock(dqm); 1630 return retval; 1631 } 1632 1633 static int register_process(struct device_queue_manager *dqm, 1634 struct qcm_process_device *qpd) 1635 { 1636 struct device_process_node *n; 1637 struct kfd_process_device *pdd; 1638 uint64_t pd_base; 1639 int retval; 1640 1641 n = kzalloc_obj(*n); 1642 if (!n) 1643 return -ENOMEM; 1644 1645 n->qpd = qpd; 1646 1647 pdd = qpd_to_pdd(qpd); 1648 /* Retrieve PD base */ 1649 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1650 1651 dqm_lock(dqm); 1652 list_add(&n->list, &dqm->queues); 1653 1654 /* Update PD Base in QPD */ 1655 qpd->page_table_base = pd_base; 1656 pr_debug("Updated PD address to 0x%llx\n", pd_base); 1657 1658 retval = dqm->asic_ops.update_qpd(dqm, qpd); 1659 1660 dqm->processes_count++; 1661 1662 dqm_unlock(dqm); 1663 1664 /* Outside the DQM lock because under the DQM lock we can't do 1665 * reclaim or take other locks that others hold while reclaiming. 1666 */ 1667 kfd_inc_compute_active(dqm->dev); 1668 1669 return retval; 1670 } 1671 1672 static int unregister_process(struct device_queue_manager *dqm, 1673 struct qcm_process_device *qpd) 1674 { 1675 int retval = 0; 1676 struct device_process_node *cur, *next; 1677 1678 pr_debug("qpd->queues_list is %s\n", 1679 list_empty(&qpd->queues_list) ? "empty" : "not empty"); 1680 1681 dqm_lock(dqm); 1682 1683 list_for_each_entry_safe(cur, next, &dqm->queues, list) { 1684 if (qpd == cur->qpd) { 1685 list_del(&cur->list); 1686 kfree(cur); 1687 dqm->processes_count--; 1688 goto out; 1689 } 1690 } 1691 /* qpd not found in dqm list */ 1692 retval = 1; 1693 out: 1694 dqm_unlock(dqm); 1695 1696 /* Outside the DQM lock because under the DQM lock we can't do 1697 * reclaim or take other locks that others hold while reclaiming. 1698 */ 1699 if (!retval) 1700 kfd_dec_compute_active(dqm->dev); 1701 1702 return retval; 1703 } 1704 1705 static int 1706 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid, 1707 unsigned int vmid) 1708 { 1709 uint32_t xcc_mask = dqm->dev->xcc_mask; 1710 int xcc_id, ret = 0; 1711 1712 for_each_inst(xcc_id, xcc_mask) { 1713 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping( 1714 dqm->dev->adev, pasid, vmid, xcc_id); 1715 if (ret) 1716 break; 1717 } 1718 1719 return ret; 1720 } 1721 1722 static void init_interrupts(struct device_queue_manager *dqm) 1723 { 1724 uint32_t xcc_mask = dqm->dev->xcc_mask; 1725 unsigned int i, xcc_id; 1726 1727 for_each_inst(xcc_id, xcc_mask) { 1728 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) { 1729 if (is_pipe_enabled(dqm, 0, i)) { 1730 dqm->dev->kfd2kgd->init_interrupts( 1731 dqm->dev->adev, i, xcc_id); 1732 } 1733 } 1734 } 1735 } 1736 1737 static int initialize_nocpsch(struct device_queue_manager *dqm) 1738 { 1739 int pipe, queue; 1740 1741 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1742 1743 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), 1744 sizeof(unsigned int), GFP_KERNEL); 1745 if (!dqm->allocated_queues) 1746 return -ENOMEM; 1747 1748 mutex_init(&dqm->lock_hidden); 1749 INIT_LIST_HEAD(&dqm->queues); 1750 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0; 1751 dqm->active_cp_queue_count = 0; 1752 dqm->gws_queue_count = 0; 1753 1754 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 1755 int pipe_offset = pipe * get_queues_per_pipe(dqm); 1756 1757 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) 1758 if (test_bit(pipe_offset + queue, 1759 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 1760 dqm->allocated_queues[pipe] |= 1 << queue; 1761 } 1762 1763 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid)); 1764 1765 init_sdma_bitmaps(dqm); 1766 1767 return 0; 1768 } 1769 1770 static void uninitialize(struct device_queue_manager *dqm) 1771 { 1772 int i; 1773 1774 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0); 1775 1776 kfree(dqm->allocated_queues); 1777 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) 1778 kfree(dqm->mqd_mgrs[i]); 1779 mutex_destroy(&dqm->lock_hidden); 1780 } 1781 1782 static int start_nocpsch(struct device_queue_manager *dqm) 1783 { 1784 int r = 0; 1785 1786 pr_info("SW scheduler is used"); 1787 init_interrupts(dqm); 1788 1789 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1790 r = pm_init(&dqm->packet_mgr, dqm); 1791 if (!r) 1792 dqm->sched_running = true; 1793 1794 return r; 1795 } 1796 1797 static int stop_nocpsch(struct device_queue_manager *dqm) 1798 { 1799 dqm_lock(dqm); 1800 if (!dqm->sched_running) { 1801 dqm_unlock(dqm); 1802 return 0; 1803 } 1804 1805 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1806 pm_uninit(&dqm->packet_mgr); 1807 dqm->sched_running = false; 1808 dqm_unlock(dqm); 1809 1810 return 0; 1811 } 1812 1813 static int allocate_sdma_queue(struct device_queue_manager *dqm, 1814 struct queue *q, const uint32_t *restore_sdma_id) 1815 { 1816 struct device *dev = dqm->dev->adev->dev; 1817 int bit; 1818 1819 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1820 if (bitmap_empty(dqm->sdma_bitmap, get_num_sdma_queues(dqm))) { 1821 dev_warn(dev, "No more SDMA queue to allocate (%d total queues)\n", 1822 get_num_sdma_queues(dqm)); 1823 return -ENOMEM; 1824 } 1825 1826 if (restore_sdma_id) { 1827 if (*restore_sdma_id >= get_num_sdma_queues(dqm)) 1828 return -EINVAL; 1829 1830 /* Re-use existing sdma_id */ 1831 if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) { 1832 dev_err(dev, "SDMA queue already in use\n"); 1833 return -EBUSY; 1834 } 1835 clear_bit(*restore_sdma_id, dqm->sdma_bitmap); 1836 q->sdma_id = *restore_sdma_id; 1837 } else { 1838 /* Find first available sdma_id */ 1839 bit = find_first_bit(dqm->sdma_bitmap, 1840 get_num_sdma_queues(dqm)); 1841 clear_bit(bit, dqm->sdma_bitmap); 1842 q->sdma_id = bit; 1843 } 1844 1845 q->properties.sdma_engine_id = 1846 q->sdma_id % kfd_get_num_sdma_engines(dqm->dev); 1847 q->properties.sdma_queue_id = q->sdma_id / 1848 kfd_get_num_sdma_engines(dqm->dev); 1849 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1850 if (bitmap_empty(dqm->xgmi_sdma_bitmap, get_num_xgmi_sdma_queues(dqm))) { 1851 dev_warn(dev, "No more XGMI SDMA queue to allocate (%d total queues)\n", 1852 get_num_xgmi_sdma_queues(dqm)); 1853 return -ENOMEM; 1854 } 1855 if (restore_sdma_id) { 1856 if (*restore_sdma_id >= get_num_xgmi_sdma_queues(dqm)) 1857 return -EINVAL; 1858 1859 /* Re-use existing sdma_id */ 1860 if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) { 1861 dev_err(dev, "SDMA queue already in use\n"); 1862 return -EBUSY; 1863 } 1864 clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap); 1865 q->sdma_id = *restore_sdma_id; 1866 } else { 1867 bit = find_first_bit(dqm->xgmi_sdma_bitmap, 1868 get_num_xgmi_sdma_queues(dqm)); 1869 clear_bit(bit, dqm->xgmi_sdma_bitmap); 1870 q->sdma_id = bit; 1871 } 1872 /* sdma_engine_id is sdma id including 1873 * both PCIe-optimized SDMAs and XGMI- 1874 * optimized SDMAs. The calculation below 1875 * assumes the first N engines are always 1876 * PCIe-optimized ones 1877 */ 1878 q->properties.sdma_engine_id = 1879 kfd_get_num_sdma_engines(dqm->dev) + 1880 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev); 1881 q->properties.sdma_queue_id = q->sdma_id / 1882 kfd_get_num_xgmi_sdma_engines(dqm->dev); 1883 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 1884 int i, num_queues, num_engines, eng_offset = 0, start_engine; 1885 bool free_bit_found = false, is_xgmi = false; 1886 1887 if (q->properties.sdma_engine_id < kfd_get_num_sdma_engines(dqm->dev)) { 1888 num_queues = get_num_sdma_queues(dqm); 1889 num_engines = kfd_get_num_sdma_engines(dqm->dev); 1890 q->properties.type = KFD_QUEUE_TYPE_SDMA; 1891 } else { 1892 num_queues = get_num_xgmi_sdma_queues(dqm); 1893 num_engines = kfd_get_num_xgmi_sdma_engines(dqm->dev); 1894 eng_offset = kfd_get_num_sdma_engines(dqm->dev); 1895 q->properties.type = KFD_QUEUE_TYPE_SDMA_XGMI; 1896 is_xgmi = true; 1897 } 1898 1899 /* Scan available bit based on target engine ID. */ 1900 start_engine = q->properties.sdma_engine_id - eng_offset; 1901 for (i = start_engine; i < num_queues; i += num_engines) { 1902 1903 if (!test_bit(i, is_xgmi ? dqm->xgmi_sdma_bitmap : dqm->sdma_bitmap)) 1904 continue; 1905 1906 clear_bit(i, is_xgmi ? dqm->xgmi_sdma_bitmap : dqm->sdma_bitmap); 1907 q->sdma_id = i; 1908 q->properties.sdma_queue_id = q->sdma_id / num_engines; 1909 free_bit_found = true; 1910 break; 1911 } 1912 1913 if (!free_bit_found) { 1914 dev_warn(dev, "No more SDMA queue to allocate for target ID %i (%d total queues)\n", 1915 q->properties.sdma_engine_id, num_queues); 1916 return -ENOMEM; 1917 } 1918 } 1919 1920 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); 1921 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); 1922 1923 return 0; 1924 } 1925 1926 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 1927 struct queue *q) 1928 { 1929 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1930 if (q->sdma_id >= get_num_sdma_queues(dqm)) 1931 return; 1932 set_bit(q->sdma_id, dqm->sdma_bitmap); 1933 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1934 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm)) 1935 return; 1936 set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap); 1937 } 1938 } 1939 1940 /* 1941 * Device Queue Manager implementation for cp scheduler 1942 */ 1943 1944 static int set_sched_resources(struct device_queue_manager *dqm) 1945 { 1946 int i, mec; 1947 struct scheduling_resources res; 1948 struct device *dev = dqm->dev->adev->dev; 1949 1950 res.vmid_mask = dqm->dev->compute_vmid_bitmap; 1951 1952 res.queue_mask = 0; 1953 for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) { 1954 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) 1955 / dqm->dev->kfd->shared_resources.num_pipe_per_mec; 1956 1957 if (!test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 1958 continue; 1959 1960 /* only acquire queues from the first MEC */ 1961 if (mec > 0) 1962 continue; 1963 1964 /* This situation may be hit in the future if a new HW 1965 * generation exposes more than 64 queues. If so, the 1966 * definition of res.queue_mask needs updating 1967 */ 1968 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { 1969 dev_err(dev, "Invalid queue enabled by amdgpu: %d\n", i); 1970 break; 1971 } 1972 1973 res.queue_mask |= 1ull 1974 << amdgpu_queue_mask_bit_to_set_resource_bit( 1975 dqm->dev->adev, i); 1976 } 1977 res.gws_mask = ~0ull; 1978 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; 1979 1980 pr_debug("Scheduling resources:\n" 1981 "vmid mask: 0x%8X\n" 1982 "queue mask: 0x%8llX\n", 1983 res.vmid_mask, res.queue_mask); 1984 1985 return pm_send_set_resources(&dqm->packet_mgr, &res); 1986 } 1987 1988 static int initialize_cpsch(struct device_queue_manager *dqm) 1989 { 1990 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1991 1992 mutex_init(&dqm->lock_hidden); 1993 INIT_LIST_HEAD(&dqm->queues); 1994 dqm->active_queue_count = dqm->processes_count = 0; 1995 dqm->active_cp_queue_count = 0; 1996 dqm->gws_queue_count = 0; 1997 dqm->active_runlist = false; 1998 dqm->trap_debug_vmid = 0; 1999 2000 init_sdma_bitmaps(dqm); 2001 2002 update_dqm_wait_times(dqm); 2003 return 0; 2004 } 2005 2006 /* halt_cpsch: 2007 * Unmap queues so the schedule doesn't continue remaining jobs in the queue. 2008 * Then set dqm->sched_halt so queues don't map to runlist until unhalt_cpsch 2009 * is called. 2010 */ 2011 static int halt_cpsch(struct device_queue_manager *dqm) 2012 { 2013 int ret = 0; 2014 2015 dqm_lock(dqm); 2016 if (!dqm->sched_running) { 2017 dqm_unlock(dqm); 2018 return 0; 2019 } 2020 2021 WARN_ONCE(dqm->sched_halt, "Scheduling is already on halt\n"); 2022 2023 if (!dqm->is_hws_hang) { 2024 if (!dqm->dev->kfd->shared_resources.enable_mes) 2025 ret = unmap_queues_cpsch(dqm, 2026 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 2027 USE_DEFAULT_GRACE_PERIOD, false); 2028 else 2029 ret = remove_all_kfd_queues_mes(dqm); 2030 } 2031 dqm->sched_halt = true; 2032 dqm_unlock(dqm); 2033 2034 return ret; 2035 } 2036 2037 /* unhalt_cpsch 2038 * Unset dqm->sched_halt and map queues back to runlist 2039 */ 2040 static int unhalt_cpsch(struct device_queue_manager *dqm) 2041 { 2042 int ret = 0; 2043 struct amdgpu_device *adev = dqm->dev->adev; 2044 2045 dqm_lock(dqm); 2046 if (!dqm->sched_running || !dqm->sched_halt) { 2047 dev_dbg(adev->dev, "Scheduling is not on halt.\n"); 2048 dqm_unlock(dqm); 2049 return 0; 2050 } 2051 dqm->sched_halt = false; 2052 if (!dqm->dev->kfd->shared_resources.enable_mes) 2053 ret = execute_queues_cpsch(dqm, 2054 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 2055 0, USE_DEFAULT_GRACE_PERIOD); 2056 else 2057 ret = add_all_kfd_queues_mes(dqm); 2058 2059 dqm_unlock(dqm); 2060 2061 return ret; 2062 } 2063 2064 static int start_cpsch(struct device_queue_manager *dqm) 2065 { 2066 struct device *dev = dqm->dev->adev->dev; 2067 int retval, num_hw_queue_slots; 2068 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 2069 int hung_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev); 2070 int hqd_info_size = adev->mes.hung_queue_hqd_info_offset; 2071 2072 dqm_lock(dqm); 2073 2074 if (!dqm->dev->kfd->shared_resources.enable_mes) { 2075 retval = pm_init(&dqm->packet_mgr, dqm); 2076 if (retval) 2077 goto fail_packet_manager_init; 2078 2079 retval = set_sched_resources(dqm); 2080 if (retval) 2081 goto fail_set_sched_resources; 2082 } 2083 pr_debug("Allocating fence memory\n"); 2084 2085 /* allocate fence memory on the gart */ 2086 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), 2087 &dqm->fence_mem); 2088 2089 if (retval) 2090 goto fail_allocate_vidmem; 2091 2092 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr; 2093 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; 2094 2095 init_interrupts(dqm); 2096 2097 /* clear hang status when driver try to start the hw scheduler */ 2098 dqm->sched_running = true; 2099 2100 if (!dqm->dev->kfd->shared_resources.enable_mes) { 2101 if (pm_config_dequeue_wait_counts(&dqm->packet_mgr, 2102 KFD_DEQUEUE_WAIT_INIT, 0 /* unused */)) 2103 dev_err(dev, "Setting optimized dequeue wait failed. Using default values\n"); 2104 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 2105 } 2106 2107 /* setup per-queue reset detection buffer */ 2108 num_hw_queue_slots = dqm->dev->kfd->shared_resources.num_queue_per_pipe * 2109 dqm->dev->kfd->shared_resources.num_pipe_per_mec * 2110 NUM_XCC(dqm->dev->xcc_mask); 2111 2112 dqm->detect_hang_info_size = num_hw_queue_slots * sizeof(struct dqm_detect_hang_info); 2113 dqm->detect_hang_info = kzalloc(dqm->detect_hang_info_size, GFP_KERNEL); 2114 2115 if (!dqm->detect_hang_info) { 2116 retval = -ENOMEM; 2117 goto fail_detect_hang_buffer; 2118 } 2119 2120 dqm->hung_db_array = kzalloc(hung_array_size * sizeof(u32), GFP_KERNEL); 2121 dqm->hqd_info = kzalloc( 2122 hqd_info_size * sizeof(struct amdgpu_mes_hung_queue_hqd_info), 2123 GFP_KERNEL); 2124 2125 dqm_unlock(dqm); 2126 2127 return 0; 2128 fail_detect_hang_buffer: 2129 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 2130 fail_allocate_vidmem: 2131 fail_set_sched_resources: 2132 if (!dqm->dev->kfd->shared_resources.enable_mes) 2133 pm_uninit(&dqm->packet_mgr); 2134 fail_packet_manager_init: 2135 dqm_unlock(dqm); 2136 return retval; 2137 } 2138 2139 static int stop_cpsch(struct device_queue_manager *dqm) 2140 { 2141 int ret = 0; 2142 2143 dqm_lock(dqm); 2144 if (!dqm->sched_running) { 2145 dqm_unlock(dqm); 2146 return 0; 2147 } 2148 2149 if (!dqm->dev->kfd->shared_resources.enable_mes) 2150 ret = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 2151 0, USE_DEFAULT_GRACE_PERIOD, false); 2152 else 2153 ret = remove_all_kfd_queues_mes(dqm); 2154 2155 dqm->sched_running = false; 2156 2157 if (!dqm->dev->kfd->shared_resources.enable_mes) 2158 pm_release_ib(&dqm->packet_mgr); 2159 2160 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 2161 if (!dqm->dev->kfd->shared_resources.enable_mes) 2162 pm_uninit(&dqm->packet_mgr); 2163 kfree(dqm->detect_hang_info); 2164 dqm->detect_hang_info = NULL; 2165 kfree(dqm->hung_db_array); 2166 kfree(dqm->hqd_info); 2167 2168 dqm_unlock(dqm); 2169 2170 return ret; 2171 } 2172 2173 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, 2174 struct kernel_queue *kq, 2175 struct qcm_process_device *qpd) 2176 { 2177 dqm_lock(dqm); 2178 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 2179 pr_warn("Can't create new kernel queue because %d queues were already created\n", 2180 dqm->total_queue_count); 2181 dqm_unlock(dqm); 2182 return -EPERM; 2183 } 2184 2185 /* 2186 * Unconditionally increment this counter, regardless of the queue's 2187 * type or whether the queue is active. 2188 */ 2189 dqm->total_queue_count++; 2190 pr_debug("Total of %d queues are accountable so far\n", 2191 dqm->total_queue_count); 2192 2193 list_add(&kq->list, &qpd->priv_queue_list); 2194 increment_queue_count(dqm, qpd, kq->queue); 2195 qpd->is_debug = true; 2196 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 2197 USE_DEFAULT_GRACE_PERIOD); 2198 dqm_unlock(dqm); 2199 2200 return 0; 2201 } 2202 2203 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, 2204 struct kernel_queue *kq, 2205 struct qcm_process_device *qpd) 2206 { 2207 dqm_lock(dqm); 2208 list_del(&kq->list); 2209 decrement_queue_count(dqm, qpd, kq->queue); 2210 qpd->is_debug = false; 2211 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 2212 USE_DEFAULT_GRACE_PERIOD); 2213 /* 2214 * Unconditionally decrement this counter, regardless of the queue's 2215 * type. 2216 */ 2217 dqm->total_queue_count--; 2218 pr_debug("Total of %d queues are accountable so far\n", 2219 dqm->total_queue_count); 2220 dqm_unlock(dqm); 2221 } 2222 2223 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, 2224 struct qcm_process_device *qpd, 2225 const struct kfd_criu_queue_priv_data *qd, 2226 const void *restore_mqd, const void *restore_ctl_stack) 2227 { 2228 int retval; 2229 struct mqd_manager *mqd_mgr; 2230 2231 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 2232 pr_warn("Can't create new usermode queue because %d queues were already created\n", 2233 dqm->total_queue_count); 2234 retval = -EPERM; 2235 goto out; 2236 } 2237 2238 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 2239 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI || 2240 q->properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 2241 dqm_lock(dqm); 2242 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 2243 dqm_unlock(dqm); 2244 if (retval) 2245 goto out; 2246 } 2247 2248 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 2249 if (retval) 2250 goto out_deallocate_sdma_queue; 2251 2252 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2253 q->properties.type)]; 2254 if (qd && !mqd_mgr->restore_mqd) { 2255 pr_debug("restore_mqd not implemented for queue type %d\n", 2256 q->properties.type); 2257 retval = -EOPNOTSUPP; 2258 goto out_deallocate_doorbell; 2259 } 2260 2261 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 2262 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 2263 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 2264 q->properties.tba_addr = qpd->tba_addr; 2265 q->properties.tma_addr = qpd->tma_addr; 2266 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); 2267 if (!q->mqd_mem_obj) { 2268 retval = -ENOMEM; 2269 goto out_deallocate_doorbell; 2270 } 2271 2272 dqm_lock(dqm); 2273 /* 2274 * Eviction state logic: mark all queues as evicted, even ones 2275 * not currently active. Restoring inactive queues later only 2276 * updates the is_evicted flag but is a no-op otherwise. 2277 */ 2278 q->properties.is_evicted = !!qpd->evicted; 2279 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled && 2280 kfd_dbg_has_cwsr_workaround(q->device); 2281 2282 if (qd) 2283 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 2284 &q->properties, restore_mqd, restore_ctl_stack, 2285 qd->ctl_stack_size); 2286 else 2287 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 2288 &q->gart_mqd_addr, &q->properties); 2289 2290 list_add(&q->list, &qpd->queues_list); 2291 qpd->queue_count++; 2292 2293 if (q->properties.is_active) { 2294 increment_queue_count(dqm, qpd, q); 2295 2296 if (!dqm->dev->kfd->shared_resources.enable_mes) 2297 retval = execute_queues_cpsch(dqm, 2298 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 2299 else 2300 retval = add_queue_mes(dqm, q, qpd); 2301 if (retval) 2302 goto cleanup_queue; 2303 } 2304 2305 /* 2306 * Unconditionally increment this counter, regardless of the queue's 2307 * type or whether the queue is active. 2308 */ 2309 dqm->total_queue_count++; 2310 2311 pr_debug("Total of %d queues are accountable so far\n", 2312 dqm->total_queue_count); 2313 2314 dqm_unlock(dqm); 2315 return retval; 2316 2317 cleanup_queue: 2318 qpd->queue_count--; 2319 list_del(&q->list); 2320 if (q->properties.is_active) 2321 decrement_queue_count(dqm, qpd, q); 2322 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2323 dqm_unlock(dqm); 2324 out_deallocate_doorbell: 2325 deallocate_doorbell(qpd, q); 2326 out_deallocate_sdma_queue: 2327 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 2328 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 2329 dqm_lock(dqm); 2330 deallocate_sdma_queue(dqm, q); 2331 dqm_unlock(dqm); 2332 } 2333 out: 2334 return retval; 2335 } 2336 2337 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, 2338 uint64_t fence_value, 2339 unsigned int timeout_ms) 2340 { 2341 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; 2342 struct device *dev = dqm->dev->adev->dev; 2343 uint64_t *fence_addr = dqm->fence_addr; 2344 2345 while (*fence_addr != fence_value) { 2346 /* Fatal err detected, this response won't come */ 2347 if (amdgpu_amdkfd_is_fed(dqm->dev->adev) || 2348 amdgpu_in_reset(dqm->dev->adev)) 2349 return -EIO; 2350 2351 if (time_after(jiffies, end_jiffies)) { 2352 dev_err(dev, "qcm fence wait loop timeout expired\n"); 2353 /* In HWS case, this is used to halt the driver thread 2354 * in order not to mess up CP states before doing 2355 * scandumps for FW debugging. 2356 */ 2357 while (halt_if_hws_hang) 2358 schedule(); 2359 2360 return -ETIME; 2361 } 2362 schedule(); 2363 } 2364 2365 return 0; 2366 } 2367 2368 /* dqm->lock mutex has to be locked before calling this function */ 2369 static int map_queues_cpsch(struct device_queue_manager *dqm) 2370 { 2371 struct device *dev = dqm->dev->adev->dev; 2372 int retval; 2373 2374 if (!dqm->sched_running || dqm->sched_halt) 2375 return 0; 2376 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0) 2377 return 0; 2378 if (dqm->active_runlist) 2379 return 0; 2380 2381 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues); 2382 pr_debug("%s sent runlist\n", __func__); 2383 if (retval) { 2384 dev_err(dev, "failed to execute runlist\n"); 2385 return retval; 2386 } 2387 dqm->active_runlist = true; 2388 2389 return retval; 2390 } 2391 2392 static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q, 2393 struct qcm_process_device *qpd) 2394 { 2395 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 2396 2397 dev_err(dqm->dev->adev->dev, "queue id 0x%0x at pasid %d is reset\n", 2398 q->properties.queue_id, pdd->process->lead_thread->pid); 2399 2400 pdd->has_reset_queue = true; 2401 q->properties.is_reset = true; 2402 if (q->properties.is_active) { 2403 q->properties.is_active = false; 2404 decrement_queue_count(dqm, qpd, q); 2405 } 2406 } 2407 2408 static int detect_queue_hang(struct device_queue_manager *dqm) 2409 { 2410 int i; 2411 2412 /* detect should be used only in dqm locked queue reset */ 2413 if (WARN_ON(dqm->detect_hang_count > 0)) 2414 return 0; 2415 2416 memset(dqm->detect_hang_info, 0, dqm->detect_hang_info_size); 2417 2418 for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) { 2419 uint32_t mec, pipe, queue; 2420 int xcc_id; 2421 2422 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) 2423 / dqm->dev->kfd->shared_resources.num_pipe_per_mec; 2424 2425 if (mec || !test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 2426 continue; 2427 2428 amdgpu_queue_mask_bit_to_mec_queue(dqm->dev->adev, i, &mec, &pipe, &queue); 2429 2430 for_each_inst(xcc_id, dqm->dev->xcc_mask) { 2431 uint64_t queue_addr = dqm->dev->kfd2kgd->hqd_get_pq_addr( 2432 dqm->dev->adev, pipe, queue, xcc_id); 2433 struct dqm_detect_hang_info hang_info; 2434 2435 if (!queue_addr) 2436 continue; 2437 2438 hang_info.pipe_id = pipe; 2439 hang_info.queue_id = queue; 2440 hang_info.xcc_id = xcc_id; 2441 hang_info.queue_address = queue_addr; 2442 2443 dqm->detect_hang_info[dqm->detect_hang_count] = hang_info; 2444 dqm->detect_hang_count++; 2445 } 2446 } 2447 2448 return dqm->detect_hang_count; 2449 } 2450 2451 static struct queue *find_queue_by_address(struct device_queue_manager *dqm, uint64_t queue_address) 2452 { 2453 struct device_process_node *cur; 2454 struct qcm_process_device *qpd; 2455 struct queue *q; 2456 2457 list_for_each_entry(cur, &dqm->queues, list) { 2458 qpd = cur->qpd; 2459 list_for_each_entry(q, &qpd->queues_list, list) { 2460 if (queue_address == q->properties.queue_address) 2461 return q; 2462 } 2463 } 2464 2465 return NULL; 2466 } 2467 2468 static struct queue *find_queue_by_doorbell_offset(struct device_queue_manager *dqm, u32 doorbell_offset) 2469 { 2470 struct device_process_node *cur; 2471 struct qcm_process_device *qpd; 2472 struct queue *q; 2473 2474 list_for_each_entry(cur, &dqm->queues, list) { 2475 qpd = cur->qpd; 2476 list_for_each_entry(q, &qpd->queues_list, list) { 2477 if (doorbell_offset == q->properties.doorbell_off) 2478 return q; 2479 } 2480 } 2481 2482 return NULL; 2483 } 2484 2485 static int reset_hung_queues(struct device_queue_manager *dqm) 2486 { 2487 int r = 0, reset_count = 0, i; 2488 2489 if (!dqm->detect_hang_info || dqm->is_hws_hang) 2490 return -EIO; 2491 2492 /* assume dqm locked. */ 2493 if (!detect_queue_hang(dqm)) 2494 return -ENOTRECOVERABLE; 2495 2496 for (i = 0; i < dqm->detect_hang_count; i++) { 2497 struct dqm_detect_hang_info hang_info = dqm->detect_hang_info[i]; 2498 struct queue *q = find_queue_by_address(dqm, hang_info.queue_address); 2499 struct kfd_process_device *pdd; 2500 uint64_t queue_addr = 0; 2501 2502 if (!q) { 2503 r = -ENOTRECOVERABLE; 2504 goto reset_fail; 2505 } 2506 2507 pdd = kfd_get_process_device_data(dqm->dev, q->process); 2508 if (!pdd) { 2509 r = -ENOTRECOVERABLE; 2510 goto reset_fail; 2511 } 2512 2513 queue_addr = dqm->dev->kfd2kgd->hqd_reset(dqm->dev->adev, 2514 hang_info.pipe_id, hang_info.queue_id, hang_info.xcc_id, 2515 KFD_UNMAP_LATENCY_MS); 2516 2517 /* either reset failed or we reset an unexpected queue. */ 2518 if (queue_addr != q->properties.queue_address) { 2519 r = -ENOTRECOVERABLE; 2520 goto reset_fail; 2521 } 2522 2523 set_queue_as_reset(dqm, q, &pdd->qpd); 2524 reset_count++; 2525 } 2526 2527 if (reset_count == dqm->detect_hang_count) 2528 kfd_signal_reset_event(dqm->dev); 2529 else 2530 r = -ENOTRECOVERABLE; 2531 2532 reset_fail: 2533 dqm->detect_hang_count = 0; 2534 2535 return r; 2536 } 2537 2538 static bool sdma_has_hang(struct device_queue_manager *dqm) 2539 { 2540 int engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 2541 int engine_end = engine_start + get_num_all_sdma_engines(dqm); 2542 int num_queues_per_eng = dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 2543 int i, j; 2544 2545 for (i = engine_start; i < engine_end; i++) { 2546 for (j = 0; j < num_queues_per_eng; j++) { 2547 if (!dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j)) 2548 continue; 2549 2550 return true; 2551 } 2552 } 2553 2554 return false; 2555 } 2556 2557 static bool set_sdma_queue_as_reset(struct device_queue_manager *dqm, 2558 uint32_t doorbell_off) 2559 { 2560 struct device_process_node *cur; 2561 struct qcm_process_device *qpd; 2562 struct queue *q; 2563 2564 list_for_each_entry(cur, &dqm->queues, list) { 2565 qpd = cur->qpd; 2566 list_for_each_entry(q, &qpd->queues_list, list) { 2567 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA || 2568 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) && 2569 q->properties.doorbell_off == doorbell_off) { 2570 set_queue_as_reset(dqm, q, qpd); 2571 return true; 2572 } 2573 } 2574 } 2575 2576 return false; 2577 } 2578 2579 static int reset_hung_queues_sdma(struct device_queue_manager *dqm) 2580 { 2581 int engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 2582 int engine_end = engine_start + get_num_all_sdma_engines(dqm); 2583 int num_queues_per_eng = dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 2584 int r = 0, i, j; 2585 2586 if (dqm->is_hws_hang) 2587 return -EIO; 2588 2589 /* Scan for hung HW queues and reset engine. */ 2590 dqm->detect_hang_count = 0; 2591 for (i = engine_start; i < engine_end; i++) { 2592 for (j = 0; j < num_queues_per_eng; j++) { 2593 uint32_t doorbell_off = 2594 dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j); 2595 2596 if (!doorbell_off) 2597 continue; 2598 2599 /* Reset engine and check. */ 2600 if (amdgpu_sdma_reset_engine(dqm->dev->adev, i, false) || 2601 dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j) || 2602 !set_sdma_queue_as_reset(dqm, doorbell_off)) { 2603 r = -ENOTRECOVERABLE; 2604 goto reset_fail; 2605 } 2606 2607 /* Should only expect one queue active per engine */ 2608 dqm->detect_hang_count++; 2609 break; 2610 } 2611 } 2612 2613 /* Signal process reset */ 2614 if (dqm->detect_hang_count) 2615 kfd_signal_reset_event(dqm->dev); 2616 else 2617 r = -ENOTRECOVERABLE; 2618 2619 reset_fail: 2620 dqm->detect_hang_count = 0; 2621 2622 return r; 2623 } 2624 2625 static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma) 2626 { 2627 struct amdgpu_device *adev = dqm->dev->adev; 2628 2629 while (halt_if_hws_hang) 2630 schedule(); 2631 2632 if (adev->debug_disable_gpu_ring_reset) { 2633 dev_info_once(adev->dev, 2634 "%s queue hung, but ring reset disabled", 2635 is_sdma ? "sdma" : "compute"); 2636 2637 return -EPERM; 2638 } 2639 if (!amdgpu_gpu_recovery) 2640 return -ENOTRECOVERABLE; 2641 2642 return is_sdma ? reset_hung_queues_sdma(dqm) : reset_hung_queues(dqm); 2643 } 2644 2645 /* dqm->lock mutex has to be locked before calling this function 2646 * 2647 * @grace_period: If USE_DEFAULT_GRACE_PERIOD then default wait time 2648 * for context switch latency. Lower values are used by debugger 2649 * since context switching are triggered at high frequency. 2650 * This is configured by setting CP_IQ_WAIT_TIME2.SCH_WAVE 2651 * 2652 */ 2653 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 2654 enum kfd_unmap_queues_filter filter, 2655 uint32_t filter_param, 2656 uint32_t grace_period, 2657 bool reset) 2658 { 2659 struct device *dev = dqm->dev->adev->dev; 2660 struct mqd_manager *mqd_mgr; 2661 int retval; 2662 2663 if (!dqm->sched_running) 2664 return 0; 2665 if (!dqm->active_runlist) 2666 return 0; 2667 if (!down_read_trylock(&dqm->dev->adev->reset_domain->sem)) 2668 return -EIO; 2669 2670 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 2671 retval = pm_config_dequeue_wait_counts(&dqm->packet_mgr, 2672 KFD_DEQUEUE_WAIT_SET_SCH_WAVE, grace_period); 2673 if (retval) 2674 goto out; 2675 } 2676 2677 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset); 2678 if (retval) 2679 goto out; 2680 2681 *dqm->fence_addr = KFD_FENCE_INIT; 2682 mb(); 2683 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, 2684 KFD_FENCE_COMPLETED); 2685 /* should be timed out */ 2686 retval = amdkfd_fence_wait_timeout(dqm, KFD_FENCE_COMPLETED, 2687 queue_preemption_timeout_ms); 2688 if (retval) { 2689 dev_err(dev, "The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n"); 2690 kfd_hws_hang(dqm); 2691 goto out; 2692 } 2693 2694 /* In the current MEC firmware implementation, if compute queue 2695 * doesn't response to the preemption request in time, HIQ will 2696 * abandon the unmap request without returning any timeout error 2697 * to driver. Instead, MEC firmware will log the doorbell of the 2698 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields. 2699 * To make sure the queue unmap was successful, driver need to 2700 * check those fields 2701 */ 2702 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; 2703 if (mqd_mgr->check_preemption_failed(mqd_mgr, dqm->packet_mgr.priv_queue->queue->mqd) && 2704 reset_queues_on_hws_hang(dqm, false)) 2705 goto reset_fail; 2706 2707 /* Check for SDMA hang and attempt SDMA reset */ 2708 if (sdma_has_hang(dqm) && reset_queues_on_hws_hang(dqm, true)) 2709 goto reset_fail; 2710 2711 /* We need to reset the grace period value for this device */ 2712 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 2713 if (pm_config_dequeue_wait_counts(&dqm->packet_mgr, 2714 KFD_DEQUEUE_WAIT_RESET, 0 /* unused */)) 2715 dev_err(dev, "Failed to reset grace period\n"); 2716 } 2717 2718 pm_release_ib(&dqm->packet_mgr); 2719 dqm->active_runlist = false; 2720 out: 2721 up_read(&dqm->dev->adev->reset_domain->sem); 2722 return retval; 2723 2724 reset_fail: 2725 dqm->is_hws_hang = true; 2726 kfd_hws_hang(dqm); 2727 up_read(&dqm->dev->adev->reset_domain->sem); 2728 return -ETIME; 2729 } 2730 2731 /* only for compute queue */ 2732 static int reset_queues_cpsch(struct device_queue_manager *dqm, uint16_t pasid) 2733 { 2734 int retval; 2735 2736 dqm_lock(dqm); 2737 2738 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID, 2739 pasid, USE_DEFAULT_GRACE_PERIOD, true); 2740 2741 dqm_unlock(dqm); 2742 return retval; 2743 } 2744 2745 /* dqm->lock mutex has to be locked before calling this function */ 2746 static int execute_queues_cpsch(struct device_queue_manager *dqm, 2747 enum kfd_unmap_queues_filter filter, 2748 uint32_t filter_param, 2749 uint32_t grace_period) 2750 { 2751 int retval; 2752 2753 if (!down_read_trylock(&dqm->dev->adev->reset_domain->sem)) 2754 return -EIO; 2755 retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false); 2756 if (!retval) 2757 retval = map_queues_cpsch(dqm); 2758 up_read(&dqm->dev->adev->reset_domain->sem); 2759 return retval; 2760 } 2761 2762 static int wait_on_destroy_queue(struct device_queue_manager *dqm, 2763 struct queue *q) 2764 { 2765 struct kfd_process_device *pdd = kfd_get_process_device_data(q->device, 2766 q->process); 2767 int ret = 0; 2768 2769 if (WARN_ON(!pdd)) 2770 return ret; 2771 2772 if (pdd->qpd.is_debug) 2773 return ret; 2774 2775 if (q->properties.is_being_destroyed) 2776 return -EBUSY; 2777 2778 q->properties.is_being_destroyed = true; 2779 2780 if (pdd->process->debug_trap_enabled && q->properties.is_suspended) { 2781 dqm_unlock(dqm); 2782 mutex_unlock(&q->process->mutex); 2783 ret = wait_event_interruptible(dqm->destroy_wait, 2784 !q->properties.is_suspended); 2785 2786 mutex_lock(&q->process->mutex); 2787 dqm_lock(dqm); 2788 } 2789 2790 if (ret) 2791 q->properties.is_being_destroyed = false; 2792 2793 return ret; 2794 } 2795 2796 static int destroy_queue_cpsch(struct device_queue_manager *dqm, 2797 struct qcm_process_device *qpd, 2798 struct queue *q) 2799 { 2800 int retval; 2801 struct mqd_manager *mqd_mgr; 2802 uint64_t sdma_val = 0; 2803 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 2804 struct device *dev = dqm->dev->adev->dev; 2805 2806 /* Get the SDMA queue stats */ 2807 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 2808 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 2809 if (dqm->dev->kfd2kgd->hqd_sdma_get_counter) 2810 retval = dqm->dev->kfd2kgd->hqd_sdma_get_counter( 2811 dqm->dev->adev, q->mqd, 2812 dqm->dev->kfd->device_info.num_sdma_queues_per_engine, 2813 &sdma_val); 2814 else 2815 retval = read_sdma_queue_counter( 2816 (uint64_t __user *)q->properties.read_ptr, 2817 &sdma_val); 2818 2819 if (retval) 2820 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n", 2821 q->properties.queue_id); 2822 } 2823 2824 /* remove queue from list to prevent rescheduling after preemption */ 2825 dqm_lock(dqm); 2826 2827 retval = wait_on_destroy_queue(dqm, q); 2828 2829 if (retval) { 2830 dqm_unlock(dqm); 2831 return retval; 2832 } 2833 2834 if (qpd->is_debug) { 2835 /* 2836 * error, currently we do not allow to destroy a queue 2837 * of a currently debugged process 2838 */ 2839 retval = -EBUSY; 2840 goto failed_try_destroy_debugged_queue; 2841 2842 } 2843 2844 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2845 q->properties.type)]; 2846 2847 deallocate_doorbell(qpd, q); 2848 2849 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 2850 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 2851 deallocate_sdma_queue(dqm, q); 2852 pdd->sdma_past_activity_counter += sdma_val; 2853 } 2854 2855 if (q->properties.is_active) { 2856 decrement_queue_count(dqm, qpd, q); 2857 q->properties.is_active = false; 2858 if (!dqm->dev->kfd->shared_resources.enable_mes) { 2859 retval = execute_queues_cpsch(dqm, 2860 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 2861 USE_DEFAULT_GRACE_PERIOD); 2862 if (retval == -ETIME) 2863 qpd->reset_wavefronts = true; 2864 } else { 2865 retval = remove_queue_mes(dqm, q, qpd); 2866 } 2867 } 2868 list_del(&q->list); 2869 qpd->queue_count--; 2870 2871 /* 2872 * Unconditionally decrement this counter, regardless of the queue's 2873 * type 2874 */ 2875 dqm->total_queue_count--; 2876 pr_debug("Total of %d queues are accountable so far\n", 2877 dqm->total_queue_count); 2878 2879 dqm_unlock(dqm); 2880 2881 /* 2882 * Do free_mqd and raise delete event after dqm_unlock(dqm) to avoid 2883 * circular locking 2884 */ 2885 kfd_dbg_ev_raise(KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE), 2886 qpd->pqm->process, q->device, 2887 -1, false, NULL, 0); 2888 2889 /* Repin the MQD BO if still evicted for hibernation, before it is freed. */ 2890 dqm_repin_mqd_bo(dqm, q); 2891 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2892 2893 return retval; 2894 2895 failed_try_destroy_debugged_queue: 2896 q->properties.is_being_destroyed = false; 2897 dqm_unlock(dqm); 2898 return retval; 2899 } 2900 2901 static bool set_cache_memory_policy(struct device_queue_manager *dqm, 2902 struct qcm_process_device *qpd, 2903 enum cache_policy default_policy, 2904 enum cache_policy alternate_policy, 2905 void __user *alternate_aperture_base, 2906 uint64_t alternate_aperture_size, 2907 u32 misc_process_properties) 2908 { 2909 bool retval = true; 2910 2911 if (!dqm->asic_ops.set_cache_memory_policy) 2912 return retval; 2913 2914 dqm_lock(dqm); 2915 2916 retval = dqm->asic_ops.set_cache_memory_policy( 2917 dqm, 2918 qpd, 2919 default_policy, 2920 alternate_policy, 2921 alternate_aperture_base, 2922 alternate_aperture_size, 2923 misc_process_properties); 2924 2925 if (retval) 2926 goto out; 2927 2928 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) 2929 program_sh_mem_settings(dqm, qpd); 2930 2931 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", 2932 qpd->sh_mem_config, qpd->sh_mem_ape1_base, 2933 qpd->sh_mem_ape1_limit); 2934 2935 out: 2936 dqm_unlock(dqm); 2937 return retval; 2938 } 2939 2940 static int process_termination_nocpsch(struct device_queue_manager *dqm, 2941 struct qcm_process_device *qpd) 2942 { 2943 struct queue *q; 2944 struct device_process_node *cur, *next_dpn; 2945 int retval = 0; 2946 bool found = false; 2947 2948 dqm_lock(dqm); 2949 2950 /* Clear all user mode queues */ 2951 while (!list_empty(&qpd->queues_list)) { 2952 struct mqd_manager *mqd_mgr; 2953 int ret; 2954 2955 q = list_first_entry(&qpd->queues_list, struct queue, list); 2956 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2957 q->properties.type)]; 2958 ret = destroy_queue_nocpsch_locked(dqm, qpd, q); 2959 if (ret) 2960 retval = ret; 2961 dqm_unlock(dqm); 2962 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2963 dqm_lock(dqm); 2964 } 2965 2966 /* Unregister process */ 2967 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 2968 if (qpd == cur->qpd) { 2969 list_del(&cur->list); 2970 kfree(cur); 2971 dqm->processes_count--; 2972 found = true; 2973 break; 2974 } 2975 } 2976 2977 dqm_unlock(dqm); 2978 2979 /* Outside the DQM lock because under the DQM lock we can't do 2980 * reclaim or take other locks that others hold while reclaiming. 2981 */ 2982 if (found) 2983 kfd_dec_compute_active(dqm->dev); 2984 2985 return retval; 2986 } 2987 2988 static int get_wave_state(struct device_queue_manager *dqm, 2989 struct queue *q, 2990 void __user *ctl_stack, 2991 u32 *ctl_stack_used_size, 2992 u32 *save_area_used_size) 2993 { 2994 struct mqd_manager *mqd_mgr; 2995 2996 dqm_lock(dqm); 2997 2998 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 2999 3000 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || 3001 q->properties.is_active || !q->device->kfd->cwsr_enabled || 3002 !mqd_mgr->get_wave_state) { 3003 dqm_unlock(dqm); 3004 return -EINVAL; 3005 } 3006 3007 dqm_unlock(dqm); 3008 3009 /* 3010 * get_wave_state is outside the dqm lock to prevent circular locking 3011 * and the queue should be protected against destruction by the process 3012 * lock. 3013 */ 3014 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, &q->properties, 3015 ctl_stack, ctl_stack_used_size, save_area_used_size); 3016 } 3017 3018 static int get_queue_checkpoint_info(struct device_queue_manager *dqm, 3019 const struct queue *q, 3020 u32 *mqd_size, 3021 u32 *ctl_stack_size) 3022 { 3023 struct mqd_manager *mqd_mgr; 3024 enum KFD_MQD_TYPE mqd_type = 3025 get_mqd_type_from_queue_type(q->properties.type); 3026 int ret = 0; 3027 3028 dqm_lock(dqm); 3029 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 3030 *mqd_size = mqd_mgr->mqd_size * NUM_XCC(mqd_mgr->dev->xcc_mask); 3031 *ctl_stack_size = 0; 3032 3033 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info) 3034 ret = mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size); 3035 3036 dqm_unlock(dqm); 3037 3038 return ret; 3039 } 3040 3041 static int checkpoint_mqd(struct device_queue_manager *dqm, 3042 const struct queue *q, 3043 void *mqd, 3044 void *ctl_stack) 3045 { 3046 struct mqd_manager *mqd_mgr; 3047 int r = 0; 3048 enum KFD_MQD_TYPE mqd_type = 3049 get_mqd_type_from_queue_type(q->properties.type); 3050 3051 dqm_lock(dqm); 3052 3053 if (q->properties.is_active || !q->device->kfd->cwsr_enabled) { 3054 r = -EINVAL; 3055 goto dqm_unlock; 3056 } 3057 3058 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 3059 if (!mqd_mgr->checkpoint_mqd) { 3060 r = -EOPNOTSUPP; 3061 goto dqm_unlock; 3062 } 3063 3064 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack); 3065 3066 dqm_unlock: 3067 dqm_unlock(dqm); 3068 return r; 3069 } 3070 3071 static int process_termination_cpsch(struct device_queue_manager *dqm, 3072 struct qcm_process_device *qpd) 3073 { 3074 int retval = 0; 3075 struct queue *q; 3076 struct device *dev = dqm->dev->adev->dev; 3077 struct kernel_queue *kq, *kq_next; 3078 struct mqd_manager *mqd_mgr; 3079 struct device_process_node *cur, *next_dpn; 3080 enum kfd_unmap_queues_filter filter = 3081 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; 3082 bool found = false; 3083 3084 dqm_lock(dqm); 3085 3086 /* Clean all kernel queues */ 3087 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) { 3088 list_del(&kq->list); 3089 decrement_queue_count(dqm, qpd, kq->queue); 3090 qpd->is_debug = false; 3091 dqm->total_queue_count--; 3092 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES; 3093 } 3094 3095 /* Clear all user mode queues */ 3096 list_for_each_entry(q, &qpd->queues_list, list) { 3097 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 3098 deallocate_sdma_queue(dqm, q); 3099 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 3100 deallocate_sdma_queue(dqm, q); 3101 3102 if (q->properties.is_active) { 3103 decrement_queue_count(dqm, qpd, q); 3104 3105 if (dqm->dev->kfd->shared_resources.enable_mes) { 3106 retval = remove_queue_mes(dqm, q, qpd); 3107 if (retval) 3108 dev_err(dev, "Failed to remove queue %d\n", 3109 q->properties.queue_id); 3110 } 3111 } 3112 3113 dqm->total_queue_count--; 3114 } 3115 3116 /* Unregister process */ 3117 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 3118 if (qpd == cur->qpd) { 3119 list_del(&cur->list); 3120 kfree(cur); 3121 dqm->processes_count--; 3122 found = true; 3123 break; 3124 } 3125 } 3126 3127 if (!dqm->dev->kfd->shared_resources.enable_mes) 3128 retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD); 3129 3130 if ((retval || qpd->reset_wavefronts) && 3131 down_read_trylock(&dqm->dev->adev->reset_domain->sem)) { 3132 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev); 3133 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process); 3134 qpd->reset_wavefronts = false; 3135 up_read(&dqm->dev->adev->reset_domain->sem); 3136 } 3137 3138 /* Lastly, free mqd resources. 3139 * Do free_mqd() after dqm_unlock to avoid circular locking. 3140 */ 3141 while (!list_empty(&qpd->queues_list)) { 3142 q = list_first_entry(&qpd->queues_list, struct queue, list); 3143 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 3144 q->properties.type)]; 3145 list_del(&q->list); 3146 qpd->queue_count--; 3147 dqm_unlock(dqm); 3148 /* Repin the MQD BO if still evicted for hibernation, before free. */ 3149 dqm_repin_mqd_bo(dqm, q); 3150 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 3151 dqm_lock(dqm); 3152 } 3153 dqm_unlock(dqm); 3154 3155 /* Outside the DQM lock because under the DQM lock we can't do 3156 * reclaim or take other locks that others hold while reclaiming. 3157 */ 3158 if (found) 3159 kfd_dec_compute_active(dqm->dev); 3160 3161 return retval; 3162 } 3163 3164 static int init_mqd_managers(struct device_queue_manager *dqm) 3165 { 3166 int i, j; 3167 struct device *dev = dqm->dev->adev->dev; 3168 struct mqd_manager *mqd_mgr; 3169 3170 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) { 3171 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev); 3172 if (!mqd_mgr) { 3173 dev_err(dev, "mqd manager [%d] initialization failed\n", i); 3174 goto out_free; 3175 } 3176 dqm->mqd_mgrs[i] = mqd_mgr; 3177 } 3178 3179 return 0; 3180 3181 out_free: 3182 for (j = 0; j < i; j++) { 3183 kfree(dqm->mqd_mgrs[j]); 3184 dqm->mqd_mgrs[j] = NULL; 3185 } 3186 3187 return -ENOMEM; 3188 } 3189 3190 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/ 3191 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) 3192 { 3193 int retval; 3194 struct kfd_node *dev = dqm->dev; 3195 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd; 3196 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * 3197 get_num_all_sdma_engines(dqm) * 3198 dev->kfd->device_info.num_sdma_queues_per_engine + 3199 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size * 3200 NUM_XCC(dqm->dev->xcc_mask)); 3201 3202 retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, size, 3203 AMDGPU_GEM_DOMAIN_GTT, 3204 &(mem_obj->mem), &(mem_obj->gpu_addr), 3205 (void *)&(mem_obj->cpu_ptr), false); 3206 3207 return retval; 3208 } 3209 3210 static void deallocate_hiq_sdma_mqd(struct kfd_node *dev, 3211 struct kfd_mem_obj *mqd) 3212 { 3213 WARN(!mqd, "No hiq sdma mqd trunk to free"); 3214 3215 amdgpu_amdkfd_free_kernel_mem(dev->adev, &mqd->mem); 3216 } 3217 3218 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) 3219 { 3220 struct device_queue_manager *dqm; 3221 int i; 3222 3223 pr_debug("Loading device queue manager\n"); 3224 3225 dqm = kzalloc_obj(*dqm); 3226 if (!dqm) 3227 return NULL; 3228 3229 switch (dev->adev->asic_type) { 3230 /* HWS is not available on Hawaii. */ 3231 case CHIP_HAWAII: 3232 /* HWS depends on CWSR for timely dequeue. CWSR is not 3233 * available on Tonga. 3234 * 3235 * FIXME: This argument also applies to Kaveri. 3236 */ 3237 case CHIP_TONGA: 3238 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS; 3239 break; 3240 default: 3241 dqm->sched_policy = sched_policy; 3242 break; 3243 } 3244 3245 dqm->dev = dev; 3246 switch (dqm->sched_policy) { 3247 case KFD_SCHED_POLICY_HWS: 3248 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: 3249 /* initialize dqm for cp scheduling */ 3250 dqm->ops.create_queue = create_queue_cpsch; 3251 dqm->ops.initialize = initialize_cpsch; 3252 dqm->ops.start = start_cpsch; 3253 dqm->ops.stop = stop_cpsch; 3254 dqm->ops.halt = halt_cpsch; 3255 dqm->ops.unhalt = unhalt_cpsch; 3256 dqm->ops.destroy_queue = destroy_queue_cpsch; 3257 dqm->ops.update_queue = update_queue; 3258 dqm->ops.register_process = register_process; 3259 dqm->ops.unregister_process = unregister_process; 3260 dqm->ops.uninitialize = uninitialize; 3261 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; 3262 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; 3263 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 3264 dqm->ops.process_termination = process_termination_cpsch; 3265 dqm->ops.evict_process_queues = evict_process_queues_cpsch; 3266 dqm->ops.restore_process_queues = restore_process_queues_cpsch; 3267 dqm->ops.get_wave_state = get_wave_state; 3268 dqm->ops.reset_queues = reset_queues_cpsch; 3269 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 3270 dqm->ops.checkpoint_mqd = checkpoint_mqd; 3271 dqm->ops.set_perfcount = set_perfcount; 3272 break; 3273 case KFD_SCHED_POLICY_NO_HWS: 3274 /* initialize dqm for no cp scheduling */ 3275 dqm->ops.start = start_nocpsch; 3276 dqm->ops.stop = stop_nocpsch; 3277 dqm->ops.create_queue = create_queue_nocpsch; 3278 dqm->ops.destroy_queue = destroy_queue_nocpsch; 3279 dqm->ops.update_queue = update_queue; 3280 dqm->ops.register_process = register_process; 3281 dqm->ops.unregister_process = unregister_process; 3282 dqm->ops.initialize = initialize_nocpsch; 3283 dqm->ops.uninitialize = uninitialize; 3284 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 3285 dqm->ops.process_termination = process_termination_nocpsch; 3286 dqm->ops.evict_process_queues = evict_process_queues_nocpsch; 3287 dqm->ops.restore_process_queues = 3288 restore_process_queues_nocpsch; 3289 dqm->ops.get_wave_state = get_wave_state; 3290 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 3291 dqm->ops.checkpoint_mqd = checkpoint_mqd; 3292 dqm->ops.set_perfcount = set_perfcount; 3293 break; 3294 default: 3295 dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); 3296 goto out_free; 3297 } 3298 3299 switch (dev->adev->asic_type) { 3300 case CHIP_KAVERI: 3301 case CHIP_HAWAII: 3302 device_queue_manager_init_cik(&dqm->asic_ops); 3303 break; 3304 3305 case CHIP_CARRIZO: 3306 case CHIP_TONGA: 3307 case CHIP_FIJI: 3308 case CHIP_POLARIS10: 3309 case CHIP_POLARIS11: 3310 case CHIP_POLARIS12: 3311 case CHIP_VEGAM: 3312 device_queue_manager_init_vi(&dqm->asic_ops); 3313 break; 3314 3315 default: 3316 if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 1, 0)) 3317 device_queue_manager_init_v12_1(&dqm->asic_ops); 3318 else if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 0, 0)) 3319 device_queue_manager_init_v12(&dqm->asic_ops); 3320 else if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0)) 3321 device_queue_manager_init_v11(&dqm->asic_ops); 3322 else if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1)) 3323 device_queue_manager_init_v10(&dqm->asic_ops); 3324 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) 3325 device_queue_manager_init_v9(&dqm->asic_ops); 3326 else { 3327 WARN(1, "Unexpected ASIC family %u", 3328 dev->adev->asic_type); 3329 goto out_free; 3330 } 3331 } 3332 3333 if (init_mqd_managers(dqm)) 3334 goto out_free; 3335 3336 if (!dev->kfd->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) { 3337 dev_err(dev->adev->dev, "Failed to allocate hiq sdma mqd trunk buffer\n"); 3338 goto out_free; 3339 } 3340 3341 if (!dqm->ops.initialize(dqm)) { 3342 init_waitqueue_head(&dqm->destroy_wait); 3343 return dqm; 3344 } 3345 3346 if (!dev->kfd->shared_resources.enable_mes) 3347 deallocate_hiq_sdma_mqd(dev, &dqm->hiq_sdma_mqd); 3348 3349 out_free: 3350 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) 3351 kfree(dqm->mqd_mgrs[i]); 3352 3353 kfree(dqm); 3354 return NULL; 3355 } 3356 3357 void device_queue_manager_uninit(struct device_queue_manager *dqm) 3358 { 3359 dqm->ops.stop(dqm); 3360 dqm->ops.uninitialize(dqm); 3361 if (!dqm->dev->kfd->shared_resources.enable_mes) 3362 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd); 3363 kfree(dqm); 3364 } 3365 3366 /* bad queue notified by interrupt from CP */ 3367 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id) 3368 { 3369 struct kfd_process_device *pdd = NULL; 3370 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, &pdd); 3371 struct device_queue_manager *dqm = knode->dqm; 3372 struct qcm_process_device *qpd; 3373 struct queue *q = NULL; 3374 int ret = 0; 3375 3376 if (!pdd) 3377 return -EINVAL; 3378 3379 dqm_lock(dqm); 3380 3381 if (pdd) { 3382 qpd = &pdd->qpd; 3383 3384 list_for_each_entry(q, &qpd->queues_list, list) { 3385 if (q->doorbell_id == doorbell_id && q->properties.is_active) { 3386 reset_queues_mes(dqm, q); 3387 q->properties.is_evicted = true; 3388 q->properties.is_active = false; 3389 decrement_queue_count(dqm, qpd, q); 3390 break; 3391 } 3392 } 3393 } 3394 3395 dqm_unlock(dqm); 3396 kfd_unref_process(p); 3397 return ret; 3398 } 3399 3400 int kfd_evict_process_device(struct kfd_process_device *pdd) 3401 { 3402 struct device_queue_manager *dqm; 3403 struct kfd_process *p; 3404 3405 p = pdd->process; 3406 dqm = pdd->dev->dqm; 3407 3408 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 3409 3410 return dqm->ops.evict_process_queues(dqm, &pdd->qpd); 3411 } 3412 3413 int reserve_debug_trap_vmid(struct device_queue_manager *dqm, 3414 struct qcm_process_device *qpd) 3415 { 3416 int r; 3417 struct device *dev = dqm->dev->adev->dev; 3418 int updated_vmid_mask; 3419 3420 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3421 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3422 return -EINVAL; 3423 } 3424 3425 dqm_lock(dqm); 3426 3427 if (dqm->trap_debug_vmid != 0) { 3428 dev_err(dev, "Trap debug id already reserved\n"); 3429 r = -EBUSY; 3430 goto out_unlock; 3431 } 3432 3433 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 3434 USE_DEFAULT_GRACE_PERIOD, false); 3435 if (r) 3436 goto out_unlock; 3437 3438 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap; 3439 updated_vmid_mask &= ~(1 << dqm->dev->vm_info.last_vmid_kfd); 3440 3441 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask; 3442 dqm->trap_debug_vmid = dqm->dev->vm_info.last_vmid_kfd; 3443 r = set_sched_resources(dqm); 3444 if (r) 3445 goto out_unlock; 3446 3447 r = map_queues_cpsch(dqm); 3448 if (r) 3449 goto out_unlock; 3450 3451 pr_debug("Reserved VMID for trap debug: %i\n", dqm->trap_debug_vmid); 3452 3453 out_unlock: 3454 dqm_unlock(dqm); 3455 return r; 3456 } 3457 3458 /* 3459 * Releases vmid for the trap debugger 3460 */ 3461 int release_debug_trap_vmid(struct device_queue_manager *dqm, 3462 struct qcm_process_device *qpd) 3463 { 3464 struct device *dev = dqm->dev->adev->dev; 3465 int r; 3466 int updated_vmid_mask; 3467 uint32_t trap_debug_vmid; 3468 3469 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3470 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3471 return -EINVAL; 3472 } 3473 3474 dqm_lock(dqm); 3475 trap_debug_vmid = dqm->trap_debug_vmid; 3476 if (dqm->trap_debug_vmid == 0) { 3477 dev_err(dev, "Trap debug id is not reserved\n"); 3478 r = -EINVAL; 3479 goto out_unlock; 3480 } 3481 3482 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 3483 USE_DEFAULT_GRACE_PERIOD, false); 3484 if (r) 3485 goto out_unlock; 3486 3487 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap; 3488 updated_vmid_mask |= (1 << dqm->dev->vm_info.last_vmid_kfd); 3489 3490 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask; 3491 dqm->trap_debug_vmid = 0; 3492 r = set_sched_resources(dqm); 3493 if (r) 3494 goto out_unlock; 3495 3496 r = map_queues_cpsch(dqm); 3497 if (r) 3498 goto out_unlock; 3499 3500 pr_debug("Released VMID for trap debug: %i\n", trap_debug_vmid); 3501 3502 out_unlock: 3503 dqm_unlock(dqm); 3504 return r; 3505 } 3506 3507 #define QUEUE_NOT_FOUND -1 3508 /* invalidate queue operation in array */ 3509 static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids) 3510 { 3511 int i; 3512 3513 for (i = 0; i < num_queues; i++) 3514 queue_ids[i] |= KFD_DBG_QUEUE_INVALID_MASK; 3515 } 3516 3517 /* find queue index in array */ 3518 static int q_array_get_index(unsigned int queue_id, 3519 uint32_t num_queues, 3520 uint32_t *queue_ids) 3521 { 3522 int i; 3523 3524 for (i = 0; i < num_queues; i++) 3525 if (queue_id == (queue_ids[i] & ~KFD_DBG_QUEUE_INVALID_MASK)) 3526 return i; 3527 3528 return QUEUE_NOT_FOUND; 3529 } 3530 3531 struct copy_context_work_handler_workarea { 3532 struct work_struct copy_context_work; 3533 struct kfd_process *p; 3534 }; 3535 3536 static void copy_context_work_handler(struct work_struct *work) 3537 { 3538 struct copy_context_work_handler_workarea *workarea; 3539 struct mqd_manager *mqd_mgr; 3540 struct queue *q; 3541 struct mm_struct *mm; 3542 struct kfd_process *p; 3543 uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size; 3544 int i; 3545 3546 workarea = container_of(work, 3547 struct copy_context_work_handler_workarea, 3548 copy_context_work); 3549 3550 p = workarea->p; 3551 mm = get_task_mm(p->lead_thread); 3552 3553 if (!mm) 3554 return; 3555 3556 kthread_use_mm(mm); 3557 for (i = 0; i < p->n_pdds; i++) { 3558 struct kfd_process_device *pdd = p->pdds[i]; 3559 struct device_queue_manager *dqm = pdd->dev->dqm; 3560 struct qcm_process_device *qpd = &pdd->qpd; 3561 3562 list_for_each_entry(q, &qpd->queues_list, list) { 3563 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE) 3564 continue; 3565 3566 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 3567 3568 /* We ignore the return value from get_wave_state 3569 * because 3570 * i) right now, it always returns 0, and 3571 * ii) if we hit an error, we would continue to the 3572 * next queue anyway. 3573 */ 3574 mqd_mgr->get_wave_state(mqd_mgr, 3575 q->mqd, 3576 &q->properties, 3577 (void __user *) q->properties.ctx_save_restore_area_address, 3578 &tmp_ctl_stack_used_size, 3579 &tmp_save_area_used_size); 3580 } 3581 } 3582 kthread_unuse_mm(mm); 3583 mmput(mm); 3584 } 3585 3586 static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array) 3587 { 3588 if (!usr_queue_id_array) 3589 return num_queues ? ERR_PTR(-EINVAL) : NULL; 3590 3591 if (num_queues > KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 3592 return ERR_PTR(-EINVAL); 3593 3594 return memdup_user(usr_queue_id_array, 3595 array_size(num_queues, sizeof(uint32_t))); 3596 } 3597 3598 int resume_queues(struct kfd_process *p, 3599 uint32_t num_queues, 3600 uint32_t *usr_queue_id_array) 3601 { 3602 uint32_t *queue_ids = NULL; 3603 int total_resumed = 0; 3604 int i; 3605 3606 if (usr_queue_id_array) { 3607 queue_ids = get_queue_ids(num_queues, usr_queue_id_array); 3608 3609 if (IS_ERR(queue_ids)) 3610 return PTR_ERR(queue_ids); 3611 3612 /* mask all queues as invalid. unmask per successful request */ 3613 q_array_invalidate(num_queues, queue_ids); 3614 } 3615 3616 for (i = 0; i < p->n_pdds; i++) { 3617 struct kfd_process_device *pdd = p->pdds[i]; 3618 struct device_queue_manager *dqm = pdd->dev->dqm; 3619 struct device *dev = dqm->dev->adev->dev; 3620 struct qcm_process_device *qpd = &pdd->qpd; 3621 struct queue *q; 3622 int r, per_device_resumed = 0; 3623 3624 dqm_lock(dqm); 3625 3626 /* unmask queues that resume or already resumed as valid */ 3627 list_for_each_entry(q, &qpd->queues_list, list) { 3628 int q_idx = QUEUE_NOT_FOUND; 3629 3630 if (queue_ids) 3631 q_idx = q_array_get_index( 3632 q->properties.queue_id, 3633 num_queues, 3634 queue_ids); 3635 3636 if (!queue_ids || q_idx != QUEUE_NOT_FOUND) { 3637 int err = resume_single_queue(dqm, &pdd->qpd, q); 3638 3639 if (queue_ids) { 3640 if (!err) { 3641 queue_ids[q_idx] &= 3642 ~KFD_DBG_QUEUE_INVALID_MASK; 3643 } else { 3644 queue_ids[q_idx] |= 3645 KFD_DBG_QUEUE_ERROR_MASK; 3646 break; 3647 } 3648 } 3649 3650 if (dqm->dev->kfd->shared_resources.enable_mes) { 3651 wake_up_all(&dqm->destroy_wait); 3652 if (!err) 3653 total_resumed++; 3654 } else { 3655 per_device_resumed++; 3656 } 3657 } 3658 } 3659 3660 if (!per_device_resumed) { 3661 dqm_unlock(dqm); 3662 continue; 3663 } 3664 3665 r = execute_queues_cpsch(dqm, 3666 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 3667 0, 3668 USE_DEFAULT_GRACE_PERIOD); 3669 if (r) { 3670 dev_err(dev, "Failed to resume process queues\n"); 3671 if (queue_ids) { 3672 list_for_each_entry(q, &qpd->queues_list, list) { 3673 int q_idx = q_array_get_index( 3674 q->properties.queue_id, 3675 num_queues, 3676 queue_ids); 3677 3678 /* mask queue as error on resume fail */ 3679 if (q_idx != QUEUE_NOT_FOUND) 3680 queue_ids[q_idx] |= 3681 KFD_DBG_QUEUE_ERROR_MASK; 3682 } 3683 } 3684 } else { 3685 wake_up_all(&dqm->destroy_wait); 3686 total_resumed += per_device_resumed; 3687 } 3688 3689 dqm_unlock(dqm); 3690 } 3691 3692 if (queue_ids) { 3693 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids, 3694 num_queues * sizeof(uint32_t))) 3695 pr_err("copy_to_user failed on queue resume\n"); 3696 3697 kfree(queue_ids); 3698 } 3699 3700 return total_resumed; 3701 } 3702 3703 int suspend_queues(struct kfd_process *p, 3704 uint32_t num_queues, 3705 uint32_t grace_period, 3706 uint64_t exception_clear_mask, 3707 uint32_t *usr_queue_id_array) 3708 { 3709 uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array); 3710 int total_suspended = 0; 3711 int i; 3712 3713 if (IS_ERR(queue_ids)) 3714 return PTR_ERR(queue_ids); 3715 3716 /* mask all queues as invalid. umask on successful request */ 3717 q_array_invalidate(num_queues, queue_ids); 3718 3719 for (i = 0; i < p->n_pdds; i++) { 3720 struct kfd_process_device *pdd = p->pdds[i]; 3721 struct device_queue_manager *dqm = pdd->dev->dqm; 3722 struct device *dev = dqm->dev->adev->dev; 3723 struct qcm_process_device *qpd = &pdd->qpd; 3724 struct queue *q; 3725 int r, per_device_suspended = 0; 3726 3727 mutex_lock(&p->event_mutex); 3728 dqm_lock(dqm); 3729 3730 /* unmask queues that suspend or already suspended */ 3731 list_for_each_entry(q, &qpd->queues_list, list) { 3732 int q_idx = q_array_get_index(q->properties.queue_id, 3733 num_queues, 3734 queue_ids); 3735 3736 if (q_idx != QUEUE_NOT_FOUND) { 3737 int err = suspend_single_queue(dqm, pdd, q); 3738 bool is_mes = dqm->dev->kfd->shared_resources.enable_mes; 3739 3740 if (!err) { 3741 queue_ids[q_idx] &= ~KFD_DBG_QUEUE_INVALID_MASK; 3742 if (exception_clear_mask && is_mes) 3743 q->properties.exception_status &= 3744 ~exception_clear_mask; 3745 3746 if (is_mes) 3747 total_suspended++; 3748 else 3749 per_device_suspended++; 3750 } else if (err != -EBUSY) { 3751 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 3752 break; 3753 } 3754 } 3755 } 3756 3757 if (!per_device_suspended) { 3758 dqm_unlock(dqm); 3759 mutex_unlock(&p->event_mutex); 3760 if (total_suspended) { 3761 amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev); 3762 /* Heavy-weight TLB flush after MES suspends queues */ 3763 kfd_flush_tlb(pdd); 3764 } 3765 continue; 3766 } 3767 3768 r = execute_queues_cpsch(dqm, 3769 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 3770 grace_period); 3771 3772 if (r) 3773 dev_err(dev, "Failed to suspend process queues.\n"); 3774 else 3775 total_suspended += per_device_suspended; 3776 3777 list_for_each_entry(q, &qpd->queues_list, list) { 3778 int q_idx = q_array_get_index(q->properties.queue_id, 3779 num_queues, queue_ids); 3780 3781 if (q_idx == QUEUE_NOT_FOUND) 3782 continue; 3783 3784 /* mask queue as error on suspend fail */ 3785 if (r) 3786 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 3787 else if (exception_clear_mask) 3788 q->properties.exception_status &= 3789 ~exception_clear_mask; 3790 } 3791 3792 dqm_unlock(dqm); 3793 mutex_unlock(&p->event_mutex); 3794 amdgpu_device_flush_hdp(dqm->dev->adev, NULL); 3795 } 3796 3797 if (total_suspended) { 3798 struct copy_context_work_handler_workarea copy_context_worker; 3799 3800 INIT_WORK_ONSTACK( 3801 ©_context_worker.copy_context_work, 3802 copy_context_work_handler); 3803 3804 copy_context_worker.p = p; 3805 3806 schedule_work(©_context_worker.copy_context_work); 3807 3808 3809 flush_work(©_context_worker.copy_context_work); 3810 destroy_work_on_stack(©_context_worker.copy_context_work); 3811 } 3812 3813 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids, 3814 num_queues * sizeof(uint32_t))) 3815 pr_err("copy_to_user failed on queue suspend\n"); 3816 3817 kfree(queue_ids); 3818 3819 return total_suspended; 3820 } 3821 3822 static uint32_t set_queue_type_for_user(struct queue_properties *q_props) 3823 { 3824 switch (q_props->type) { 3825 case KFD_QUEUE_TYPE_COMPUTE: 3826 return q_props->format == KFD_QUEUE_FORMAT_PM4 3827 ? KFD_IOC_QUEUE_TYPE_COMPUTE 3828 : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; 3829 case KFD_QUEUE_TYPE_SDMA: 3830 return KFD_IOC_QUEUE_TYPE_SDMA; 3831 case KFD_QUEUE_TYPE_SDMA_XGMI: 3832 return KFD_IOC_QUEUE_TYPE_SDMA_XGMI; 3833 default: 3834 WARN_ONCE(true, "queue type not recognized!"); 3835 return 0xffffffff; 3836 }; 3837 } 3838 3839 void set_queue_snapshot_entry(struct queue *q, 3840 uint64_t exception_clear_mask, 3841 struct kfd_queue_snapshot_entry *qss_entry) 3842 { 3843 qss_entry->ring_base_address = q->properties.queue_address; 3844 qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr; 3845 qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr; 3846 qss_entry->ctx_save_restore_address = 3847 q->properties.ctx_save_restore_area_address; 3848 qss_entry->ctx_save_restore_area_size = 3849 q->properties.ctx_save_restore_area_size; 3850 qss_entry->exception_status = q->properties.exception_status; 3851 qss_entry->queue_id = q->properties.queue_id; 3852 qss_entry->gpu_id = q->device->id; 3853 qss_entry->ring_size = (uint32_t)q->properties.queue_size; 3854 qss_entry->queue_type = set_queue_type_for_user(&q->properties); 3855 q->properties.exception_status &= ~exception_clear_mask; 3856 } 3857 3858 int debug_lock_and_unmap(struct device_queue_manager *dqm) 3859 { 3860 struct device *dev = dqm->dev->adev->dev; 3861 int r; 3862 3863 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3864 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3865 return -EINVAL; 3866 } 3867 3868 if (!kfd_dbg_is_per_vmid_supported(dqm->dev)) 3869 return 0; 3870 3871 dqm_lock(dqm); 3872 3873 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false); 3874 if (r) 3875 dqm_unlock(dqm); 3876 3877 return r; 3878 } 3879 3880 int debug_map_and_unlock(struct device_queue_manager *dqm) 3881 { 3882 struct device *dev = dqm->dev->adev->dev; 3883 int r; 3884 3885 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3886 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3887 return -EINVAL; 3888 } 3889 3890 if (!kfd_dbg_is_per_vmid_supported(dqm->dev)) 3891 return 0; 3892 3893 r = map_queues_cpsch(dqm); 3894 3895 dqm_unlock(dqm); 3896 3897 return r; 3898 } 3899 3900 int debug_refresh_runlist(struct device_queue_manager *dqm) 3901 { 3902 int r = debug_lock_and_unmap(dqm); 3903 3904 if (r) 3905 return r; 3906 3907 return debug_map_and_unlock(dqm); 3908 } 3909 3910 bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, 3911 struct qcm_process_device *qpd, 3912 int doorbell_off, u32 *queue_format) 3913 { 3914 struct queue *q; 3915 bool r = false; 3916 3917 if (!queue_format) 3918 return r; 3919 3920 dqm_lock(dqm); 3921 3922 list_for_each_entry(q, &qpd->queues_list, list) { 3923 if (q->properties.doorbell_off == doorbell_off) { 3924 *queue_format = q->properties.format; 3925 r = true; 3926 goto out; 3927 } 3928 } 3929 3930 out: 3931 dqm_unlock(dqm); 3932 return r; 3933 } 3934 3935 size_t mqd_size_from_queue_type(struct device_queue_manager *dqm, enum kfd_queue_type type) 3936 { 3937 return dqm->mqd_mgrs[get_mqd_type_from_queue_type(type)]->mqd_size; 3938 } 3939 3940 #if defined(CONFIG_DEBUG_FS) 3941 3942 static void seq_reg_dump(struct seq_file *m, 3943 uint32_t (*dump)[2], uint32_t n_regs) 3944 { 3945 uint32_t i, count; 3946 3947 for (i = 0, count = 0; i < n_regs; i++) { 3948 if (count == 0 || 3949 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { 3950 seq_printf(m, "%s %08x: %08x", 3951 i ? "\n" : "", 3952 dump[i][0], dump[i][1]); 3953 count = 7; 3954 } else { 3955 seq_printf(m, " %08x", dump[i][1]); 3956 count--; 3957 } 3958 } 3959 3960 seq_puts(m, "\n"); 3961 } 3962 3963 int dqm_debugfs_hqds(struct seq_file *m, void *data) 3964 { 3965 struct device_queue_manager *dqm = data; 3966 uint32_t xcc_mask = dqm->dev->xcc_mask; 3967 uint32_t (*dump)[2], n_regs; 3968 int pipe, queue; 3969 int r = 0, xcc_id; 3970 uint32_t sdma_engine_start; 3971 3972 if (!dqm->sched_running) { 3973 seq_puts(m, " Device is stopped\n"); 3974 return 0; 3975 } 3976 3977 for_each_inst(xcc_id, xcc_mask) { 3978 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 3979 KFD_CIK_HIQ_PIPE, 3980 KFD_CIK_HIQ_QUEUE, &dump, 3981 &n_regs, xcc_id); 3982 if (!r) { 3983 seq_printf( 3984 m, 3985 " Inst %d, HIQ on MEC %d Pipe %d Queue %d\n", 3986 xcc_id, 3987 KFD_CIK_HIQ_PIPE / get_pipes_per_mec(dqm) + 1, 3988 KFD_CIK_HIQ_PIPE % get_pipes_per_mec(dqm), 3989 KFD_CIK_HIQ_QUEUE); 3990 seq_reg_dump(m, dump, n_regs); 3991 3992 kfree(dump); 3993 } 3994 3995 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 3996 int pipe_offset = pipe * get_queues_per_pipe(dqm); 3997 3998 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) { 3999 if (!test_bit(pipe_offset + queue, 4000 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 4001 continue; 4002 4003 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 4004 pipe, queue, 4005 &dump, &n_regs, 4006 xcc_id); 4007 if (r) 4008 break; 4009 4010 seq_printf(m, 4011 " Inst %d, CP Pipe %d, Queue %d\n", 4012 xcc_id, pipe, queue); 4013 seq_reg_dump(m, dump, n_regs); 4014 4015 kfree(dump); 4016 } 4017 } 4018 } 4019 4020 sdma_engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 4021 for (pipe = sdma_engine_start; 4022 pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm)); 4023 pipe++) { 4024 for (queue = 0; 4025 queue < dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 4026 queue++) { 4027 r = dqm->dev->kfd2kgd->hqd_sdma_dump( 4028 dqm->dev->adev, pipe, queue, &dump, &n_regs); 4029 if (r) 4030 break; 4031 4032 seq_printf(m, " SDMA Engine %d, RLC %d\n", 4033 pipe, queue); 4034 seq_reg_dump(m, dump, n_regs); 4035 4036 kfree(dump); 4037 } 4038 } 4039 4040 return r; 4041 } 4042 4043 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm) 4044 { 4045 int r = 0; 4046 4047 dqm_lock(dqm); 4048 r = pm_debugfs_hang_hws(&dqm->packet_mgr); 4049 if (r) { 4050 dqm_unlock(dqm); 4051 return r; 4052 } 4053 dqm->active_runlist = true; 4054 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 4055 0, USE_DEFAULT_GRACE_PERIOD); 4056 dqm_unlock(dqm); 4057 4058 return r; 4059 } 4060 4061 #endif 4062