1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/ratelimit.h> 26 #include <linux/printk.h> 27 #include <linux/slab.h> 28 #include <linux/list.h> 29 #include <linux/types.h> 30 #include <linux/bitops.h> 31 #include <linux/sched.h> 32 #include "kfd_priv.h" 33 #include "kfd_device_queue_manager.h" 34 #include "kfd_mqd_manager.h" 35 #include "cik_regs.h" 36 #include "kfd_kernel_queue.h" 37 #include "amdgpu_amdkfd.h" 38 #include "amdgpu_reset.h" 39 #include "amdgpu_sdma.h" 40 #include "amdgpu_ring.h" 41 #include "amdgpu_mes.h" 42 #include "kfd_debug.h" 43 44 /* Size of the per-pipe EOP queue */ 45 #define CIK_HPD_EOP_BYTES_LOG2 11 46 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) 47 /* See unmap_queues_cpsch() */ 48 #define USE_DEFAULT_GRACE_PERIOD 0xffffffff 49 50 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, 51 u32 pasid, unsigned int vmid); 52 53 static int execute_queues_cpsch(struct device_queue_manager *dqm, 54 enum kfd_unmap_queues_filter filter, 55 uint32_t filter_param, 56 uint32_t grace_period); 57 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 58 enum kfd_unmap_queues_filter filter, 59 uint32_t filter_param, 60 uint32_t grace_period, 61 bool reset); 62 63 static int map_queues_cpsch(struct device_queue_manager *dqm); 64 65 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 66 struct queue *q); 67 68 static inline void deallocate_hqd(struct device_queue_manager *dqm, 69 struct queue *q); 70 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q); 71 static int allocate_sdma_queue(struct device_queue_manager *dqm, 72 struct queue *q, const uint32_t *restore_sdma_id); 73 74 static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma); 75 static struct queue *find_queue_by_doorbell_offset(struct device_queue_manager *dqm, 76 u32 doorbell_offset); 77 static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q, 78 struct qcm_process_device *qpd); 79 static int reset_queues_mes(struct device_queue_manager *dqm, struct queue *q); 80 81 static inline 82 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) 83 { 84 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI) 85 return KFD_MQD_TYPE_SDMA; 86 return KFD_MQD_TYPE_CP; 87 } 88 89 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) 90 { 91 int i; 92 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec 93 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe; 94 95 /* queue is available for KFD usage if bit is 1 */ 96 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i) 97 if (test_bit(pipe_offset + i, 98 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 99 return true; 100 return false; 101 } 102 103 unsigned int get_cp_queues_num(struct device_queue_manager *dqm) 104 { 105 return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap, 106 AMDGPU_MAX_QUEUES); 107 } 108 109 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) 110 { 111 return dqm->dev->kfd->shared_resources.num_queue_per_pipe; 112 } 113 114 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) 115 { 116 return dqm->dev->kfd->shared_resources.num_pipe_per_mec; 117 } 118 119 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm) 120 { 121 return kfd_get_num_sdma_engines(dqm->dev) + 122 kfd_get_num_xgmi_sdma_engines(dqm->dev); 123 } 124 125 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm) 126 { 127 return kfd_get_num_sdma_engines(dqm->dev) * 128 dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 129 } 130 131 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm) 132 { 133 return kfd_get_num_xgmi_sdma_engines(dqm->dev) * 134 dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 135 } 136 137 static void init_sdma_bitmaps(struct device_queue_manager *dqm) 138 { 139 bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES); 140 bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm)); 141 142 bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES); 143 bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm)); 144 145 /* Mask out the reserved queues */ 146 bitmap_clear(dqm->sdma_bitmap, 0, kfd_get_num_sdma_engines(dqm->dev) * 147 dqm->dev->kfd->device_info.num_reserved_sdma_queues_per_engine); 148 bitmap_clear(dqm->xgmi_sdma_bitmap, 0, kfd_get_num_xgmi_sdma_engines(dqm->dev) * 149 dqm->dev->kfd->device_info.num_reserved_sdma_queues_per_engine); 150 } 151 152 void program_sh_mem_settings(struct device_queue_manager *dqm, 153 struct qcm_process_device *qpd) 154 { 155 uint32_t xcc_mask = dqm->dev->xcc_mask; 156 int xcc_id; 157 158 for_each_inst(xcc_id, xcc_mask) 159 dqm->dev->kfd2kgd->program_sh_mem_settings( 160 dqm->dev->adev, qpd->vmid, qpd->sh_mem_config, 161 qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit, 162 qpd->sh_mem_bases, xcc_id); 163 } 164 165 static void kfd_hws_hang(struct device_queue_manager *dqm) 166 { 167 struct device_process_node *cur; 168 struct qcm_process_device *qpd; 169 struct queue *q; 170 171 /* Mark all device queues as reset. */ 172 list_for_each_entry(cur, &dqm->queues, list) { 173 qpd = cur->qpd; 174 list_for_each_entry(q, &qpd->queues_list, list) { 175 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 176 177 pdd->has_reset_queue = true; 178 } 179 } 180 181 /* 182 * Issue a GPU reset if HWS is unresponsive 183 */ 184 amdgpu_amdkfd_gpu_reset(dqm->dev->adev); 185 } 186 187 static int convert_to_amdgpu_ring_type(int queue_type) 188 { 189 int amdgpu_ring_type; 190 191 switch (queue_type) { 192 case KFD_QUEUE_TYPE_COMPUTE: 193 amdgpu_ring_type = AMDGPU_RING_TYPE_COMPUTE; 194 break; 195 case KFD_QUEUE_TYPE_SDMA: 196 amdgpu_ring_type = AMDGPU_RING_TYPE_SDMA; 197 break; 198 default: 199 WARN(1, "Invalid queue type %d", queue_type); 200 amdgpu_ring_type = -EINVAL; 201 break; 202 } 203 204 return amdgpu_ring_type; 205 } 206 207 static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, 208 struct qcm_process_device *qpd) 209 { 210 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 211 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 212 struct mes_add_queue_input queue_input; 213 int r, queue_type; 214 uint64_t wptr_addr_off; 215 216 if (!dqm->sched_running || dqm->sched_halt) 217 return 0; 218 if (!down_read_trylock(&adev->reset_domain->sem)) 219 return -EIO; 220 221 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 222 queue_input.process_id = pdd->pasid; 223 queue_input.page_table_base_addr = qpd->page_table_base; 224 queue_input.process_va_start = 0; 225 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 226 /* MES unit for quantum is 100ns */ 227 queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */ 228 queue_input.process_context_addr = pdd->proc_ctx_gpu_addr; 229 queue_input.process_context_array_index = pdd->proc_ctx_array_index; 230 queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */ 231 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 232 queue_input.gang_context_array_index = q->gang_ctx_array_index; 233 queue_input.inprocess_gang_priority = q->properties.priority; 234 queue_input.gang_global_priority_level = 235 AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 236 queue_input.doorbell_offset = q->properties.doorbell_off; 237 queue_input.mqd_addr = q->gart_mqd_addr; 238 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; 239 240 wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1); 241 queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q->properties.wptr_bo) + wptr_addr_off; 242 243 queue_input.is_kfd_process = 1; 244 queue_input.is_aql_queue = (q->properties.format == KFD_QUEUE_FORMAT_AQL); 245 queue_input.queue_size = q->properties.queue_size >> 2; 246 247 queue_input.paging = false; 248 queue_input.tba_addr = qpd->tba_addr; 249 queue_input.tma_addr = qpd->tma_addr; 250 queue_input.trap_en = !kfd_dbg_has_cwsr_workaround(q->device); 251 queue_input.skip_process_ctx_clear = 252 qpd->pqm->process->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED && 253 (qpd->pqm->process->debug_trap_enabled || 254 kfd_dbg_has_ttmps_always_setup(q->device)); 255 256 queue_type = convert_to_amdgpu_ring_type(q->properties.type); 257 if (queue_type < 0) { 258 dev_err(adev->dev, "Queue type not supported with MES, queue:%d\n", 259 q->properties.type); 260 up_read(&adev->reset_domain->sem); 261 return -EINVAL; 262 } 263 queue_input.queue_type = (uint32_t)queue_type; 264 265 queue_input.exclusively_scheduled = q->properties.is_gws; 266 queue_input.sh_mem_config_data = qpd->sh_mem_config; 267 queue_input.vm_cntx_cntl = qpd->vm_cntx_cntl; 268 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; 269 270 amdgpu_mes_lock(&adev->mes); 271 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 272 amdgpu_mes_unlock(&adev->mes); 273 up_read(&adev->reset_domain->sem); 274 if (r) { 275 dev_err(adev->dev, "failed to add hardware queue to MES, doorbell=0x%x\n", 276 q->properties.doorbell_off); 277 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); 278 kfd_hws_hang(dqm); 279 } 280 281 return r; 282 } 283 284 static int remove_queue_mes_on_reset_option(struct device_queue_manager *dqm, struct queue *q, 285 struct qcm_process_device *qpd, 286 bool is_for_reset, 287 bool flush_mes_queue) 288 { 289 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 290 int r; 291 struct mes_remove_queue_input queue_input; 292 293 /* queue was already removed during reset */ 294 if (q->properties.is_reset) 295 return 0; 296 297 if (!dqm->sched_running || dqm->sched_halt) 298 return 0; 299 if (!down_read_trylock(&adev->reset_domain->sem)) 300 return -EIO; 301 302 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 303 queue_input.doorbell_offset = q->properties.doorbell_off; 304 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 305 queue_input.queue_type = convert_to_amdgpu_ring_type(q->properties.type); 306 queue_input.remove_queue_after_reset = flush_mes_queue; 307 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; 308 queue_input.gang_context_array_index = q->gang_ctx_array_index; 309 310 amdgpu_mes_lock(&adev->mes); 311 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 312 amdgpu_mes_unlock(&adev->mes); 313 up_read(&adev->reset_domain->sem); 314 315 /* If is_for_reset set, it is a mes internal cleanup */ 316 if (!r || is_for_reset) 317 return r; 318 319 /* remove_hw_queue failure indicates a queue hang. reset the queue */ 320 r = reset_queues_mes(dqm, q); 321 if (r && amdgpu_gpu_recovery) { 322 dev_err(adev->dev, "failed to remove queue from MES, doorbell=0x%x\n", 323 q->properties.doorbell_off); 324 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); 325 kfd_hws_hang(dqm); 326 } 327 328 return r; 329 } 330 331 static void set_perfcount(struct device_queue_manager *dqm, int enable) 332 { 333 struct device_process_node *cur; 334 struct qcm_process_device *qpd; 335 struct queue *q; 336 struct mqd_update_info minfo = { 0 }; 337 338 if (!dqm) 339 return; 340 341 minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : 342 UPDATE_FLAG_PERFCOUNT_DISABLE); 343 dqm_lock(dqm); 344 list_for_each_entry(cur, &dqm->queues, list) { 345 qpd = cur->qpd; 346 list_for_each_entry(q, &qpd->queues_list, list) { 347 pqm_update_mqd(qpd->pqm, q->properties.queue_id, 348 &minfo); 349 } 350 } 351 dqm_unlock(dqm); 352 } 353 354 static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, 355 struct qcm_process_device *qpd) 356 { 357 return remove_queue_mes_on_reset_option(dqm, q, qpd, false, false); 358 } 359 360 static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) 361 { 362 struct device_process_node *cur; 363 struct device *dev = dqm->dev->adev->dev; 364 struct qcm_process_device *qpd; 365 struct queue *q; 366 int retval = 0; 367 368 list_for_each_entry(cur, &dqm->queues, list) { 369 qpd = cur->qpd; 370 list_for_each_entry(q, &qpd->queues_list, list) { 371 if (q->properties.is_active) { 372 retval = remove_queue_mes(dqm, q, qpd); 373 if (retval) { 374 dev_err(dev, "%s: Failed to remove queue %d for dev %d", 375 __func__, 376 q->properties.queue_id, 377 dqm->dev->id); 378 return retval; 379 } 380 } 381 } 382 } 383 384 return retval; 385 } 386 387 static int add_all_kfd_queues_mes(struct device_queue_manager *dqm) 388 { 389 struct device_process_node *cur; 390 struct device *dev = dqm->dev->adev->dev; 391 struct qcm_process_device *qpd; 392 struct queue *q; 393 int retval = 0; 394 395 list_for_each_entry(cur, &dqm->queues, list) { 396 qpd = cur->qpd; 397 list_for_each_entry(q, &qpd->queues_list, list) { 398 if (!q->properties.is_active) 399 continue; 400 retval = add_queue_mes(dqm, q, qpd); 401 if (retval) { 402 dev_err(dev, "%s: Failed to add queue %d for dev %d", 403 __func__, 404 q->properties.queue_id, 405 dqm->dev->id); 406 return retval; 407 } 408 } 409 } 410 411 return retval; 412 } 413 414 static int reset_queue_mes(struct device_queue_manager *dqm, struct queue *q, 415 int queue_type, int pipe, int queue, unsigned int db) 416 { 417 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 418 struct kfd_process_device *pdd; 419 bool use_mmio = adev->gfx.mec.use_mmio_for_reset; 420 int r; 421 422 pdd = kfd_get_process_device_data(q->device, q->process); 423 if (!pdd) 424 return -ENODEV; 425 426 if (use_mmio) 427 r = amdgpu_mes_reset_queue_mmio(adev, queue_type, 0, 1, pipe, queue, 428 ffs(dqm->dev->xcc_mask) - 1); 429 else 430 r = amdgpu_mes_reset_user_queue(adev, queue_type, db, 431 ffs(dqm->dev->xcc_mask) - 1); 432 if (r) 433 return r; 434 /* Proceed remove_queue with reset=true */ 435 remove_queue_mes_on_reset_option(dqm, q, &pdd->qpd, true, true); 436 set_queue_as_reset(dqm, q, &pdd->qpd); 437 return 0; 438 } 439 440 int kfd_reset_queue_mes(struct device_queue_manager *dqm, int queue_type, 441 int pipe, int queue, unsigned int db) 442 { 443 struct queue *q; 444 445 q = find_queue_by_doorbell_offset(dqm, db); 446 if (!q) 447 return 0; 448 return reset_queue_mes(dqm, q, queue_type, pipe, queue, db); 449 } 450 451 static int reset_queues_mes(struct device_queue_manager *dqm, struct queue *q) 452 { 453 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 454 struct drm_wedge_task_info *info = NULL; 455 struct amdgpu_task_info *ti = NULL; 456 struct kfd_process_device *pdd; 457 unsigned int num_hung = 0; 458 int r = 0; 459 struct mes_remove_queue_input queue_input; 460 461 if (!amdgpu_mes_queue_reset_by_mes_supported(adev)) { 462 r = -ENOTRECOVERABLE; 463 goto fail; 464 } 465 466 /* reset should be used only in dqm locked queue reset */ 467 if (WARN_ON(dqm->detect_hang_count > 0)) 468 return 0; 469 470 if (!amdgpu_gpu_recovery) { 471 r = -ENOTRECOVERABLE; 472 goto fail; 473 } 474 475 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 476 queue_input.doorbell_offset = q->properties.doorbell_off; 477 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 478 queue_input.queue_type = convert_to_amdgpu_ring_type(q->properties.type); 479 queue_input.remove_queue_after_reset = false; 480 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; 481 /* pass the known bad queue info to the reset function */ 482 r = amdgpu_gfx_reset_mes_compute(adev, NULL, NULL, NULL, &num_hung, &queue_input); 483 if (r) 484 goto fail; 485 pdd = kfd_get_process_device_data(q->device, q->process); 486 if (pdd) { 487 ti = amdgpu_vm_get_task_info_pasid(adev, pdd->pasid); 488 if (ti) { 489 amdgpu_vm_print_task_info(adev, ti); 490 info = &ti->task; 491 } 492 } 493 494 dqm->detect_hang_count = num_hung; 495 /* When MES doesn't detect any queue hang, no reset happens. Don't signal reset 496 * event. 497 */ 498 if (dqm->detect_hang_count) { 499 kfd_signal_reset_event(dqm->dev); 500 if (pdd && pdd->has_reset_queue) { 501 atomic_inc(&adev->gpu_reset_counter); 502 drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, info); 503 } 504 } 505 amdgpu_vm_put_task_info(ti); 506 507 fail: 508 dqm->detect_hang_count = 0; 509 return r; 510 } 511 512 static void increment_queue_count(struct device_queue_manager *dqm, 513 struct qcm_process_device *qpd, 514 struct queue *q) 515 { 516 dqm->active_queue_count++; 517 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 518 dqm->active_cp_queue_count++; 519 520 if (q->properties.is_gws) { 521 dqm->gws_queue_count++; 522 qpd->mapped_gws_queue = true; 523 } 524 } 525 526 static void decrement_queue_count(struct device_queue_manager *dqm, 527 struct qcm_process_device *qpd, 528 struct queue *q) 529 { 530 dqm->active_queue_count--; 531 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 532 dqm->active_cp_queue_count--; 533 534 if (q->properties.is_gws) { 535 dqm->gws_queue_count--; 536 qpd->mapped_gws_queue = false; 537 } 538 } 539 540 /* 541 * Allocate a doorbell ID to this queue. 542 * If doorbell_id is passed in, make sure requested ID is valid then allocate it. 543 */ 544 static int allocate_doorbell(struct qcm_process_device *qpd, 545 struct queue *q, 546 uint32_t const *restore_id) 547 { 548 struct kfd_node *dev = qpd->dqm->dev; 549 550 if (!KFD_IS_SOC15(dev)) { 551 /* On pre-SOC15 chips we need to use the queue ID to 552 * preserve the user mode ABI. 553 */ 554 555 if (restore_id && *restore_id != q->properties.queue_id) 556 return -EINVAL; 557 558 q->doorbell_id = q->properties.queue_id; 559 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 560 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 561 /* For SDMA queues on SOC15 with 8-byte doorbell, use static 562 * doorbell assignments based on the engine and queue id. 563 * The doobell index distance between RLC (2*i) and (2*i+1) 564 * for a SDMA engine is 512. 565 */ 566 567 uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx; 568 569 /* 570 * q->properties.sdma_engine_id corresponds to the virtual 571 * sdma engine number. However, for doorbell allocation, 572 * we need the physical sdma engine id in order to get the 573 * correct doorbell offset. 574 */ 575 uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id * 576 get_num_all_sdma_engines(qpd->dqm) + 577 q->properties.sdma_engine_id] 578 + (q->properties.sdma_queue_id & 1) 579 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET 580 + (q->properties.sdma_queue_id >> 1); 581 582 if (restore_id && *restore_id != valid_id) 583 return -EINVAL; 584 q->doorbell_id = valid_id; 585 } else { 586 /* For CP queues on SOC15 */ 587 if (restore_id) { 588 if (*restore_id >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 589 return -EINVAL; 590 591 /* make sure that ID is free */ 592 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap)) 593 return -EINVAL; 594 595 q->doorbell_id = *restore_id; 596 } else { 597 /* or reserve a free doorbell ID */ 598 unsigned int found; 599 600 found = find_first_zero_bit(qpd->doorbell_bitmap, 601 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 602 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 603 pr_debug("No doorbells available"); 604 return -EBUSY; 605 } 606 set_bit(found, qpd->doorbell_bitmap); 607 q->doorbell_id = found; 608 } 609 } 610 611 q->properties.doorbell_off = amdgpu_doorbell_index_on_bar(dev->adev, 612 qpd->proc_doorbells, 613 q->doorbell_id, 614 dev->kfd->device_info.doorbell_size); 615 return 0; 616 } 617 618 static void deallocate_doorbell(struct qcm_process_device *qpd, 619 struct queue *q) 620 { 621 unsigned int old; 622 struct kfd_node *dev = qpd->dqm->dev; 623 624 if (!KFD_IS_SOC15(dev) || 625 q->properties.type == KFD_QUEUE_TYPE_SDMA || 626 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 627 return; 628 629 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap); 630 WARN_ON(!old); 631 } 632 633 static void program_trap_handler_settings(struct device_queue_manager *dqm, 634 struct qcm_process_device *qpd) 635 { 636 uint32_t xcc_mask = dqm->dev->xcc_mask; 637 int xcc_id; 638 639 if (dqm->dev->kfd2kgd->program_trap_handler_settings) 640 for_each_inst(xcc_id, xcc_mask) 641 dqm->dev->kfd2kgd->program_trap_handler_settings( 642 dqm->dev->adev, qpd->vmid, qpd->tba_addr, 643 qpd->tma_addr, xcc_id); 644 } 645 646 static int allocate_vmid(struct device_queue_manager *dqm, 647 struct qcm_process_device *qpd, 648 struct queue *q) 649 { 650 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 651 struct device *dev = dqm->dev->adev->dev; 652 int allocated_vmid = -1, i; 653 654 for (i = dqm->dev->vm_info.first_vmid_kfd; 655 i <= dqm->dev->vm_info.last_vmid_kfd; i++) { 656 if (!dqm->vmid_pasid[i]) { 657 allocated_vmid = i; 658 break; 659 } 660 } 661 662 if (allocated_vmid < 0) { 663 dev_err(dev, "no more vmid to allocate\n"); 664 return -ENOSPC; 665 } 666 667 pr_debug("vmid allocated: %d\n", allocated_vmid); 668 669 dqm->vmid_pasid[allocated_vmid] = pdd->pasid; 670 671 set_pasid_vmid_mapping(dqm, pdd->pasid, allocated_vmid); 672 673 qpd->vmid = allocated_vmid; 674 q->properties.vmid = allocated_vmid; 675 676 program_sh_mem_settings(dqm, qpd); 677 678 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->kfd->cwsr_enabled) 679 program_trap_handler_settings(dqm, qpd); 680 681 /* qpd->page_table_base is set earlier when register_process() 682 * is called, i.e. when the first queue is created. 683 */ 684 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev, 685 qpd->vmid, 686 qpd->page_table_base); 687 /* invalidate the VM context after pasid and vmid mapping is set up */ 688 kfd_flush_tlb(qpd_to_pdd(qpd)); 689 690 if (dqm->dev->kfd2kgd->set_scratch_backing_va) 691 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev, 692 qpd->sh_hidden_private_base, qpd->vmid); 693 694 return 0; 695 } 696 697 static int flush_texture_cache_nocpsch(struct kfd_node *kdev, 698 struct qcm_process_device *qpd) 699 { 700 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf; 701 int ret; 702 703 if (!qpd->ib_kaddr) 704 return -ENOMEM; 705 706 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr); 707 if (ret) 708 return ret; 709 710 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid, 711 qpd->ib_base, (uint32_t *)qpd->ib_kaddr, 712 pmf->release_mem_size / sizeof(uint32_t)); 713 } 714 715 static void deallocate_vmid(struct device_queue_manager *dqm, 716 struct qcm_process_device *qpd, 717 struct queue *q) 718 { 719 struct device *dev = dqm->dev->adev->dev; 720 721 /* On GFX v7, CP doesn't flush TC at dequeue */ 722 if (q->device->adev->asic_type == CHIP_HAWAII) 723 if (flush_texture_cache_nocpsch(q->device, qpd)) 724 dev_err(dev, "Failed to flush TC\n"); 725 726 kfd_flush_tlb(qpd_to_pdd(qpd)); 727 728 /* Release the vmid mapping */ 729 set_pasid_vmid_mapping(dqm, 0, qpd->vmid); 730 dqm->vmid_pasid[qpd->vmid] = 0; 731 732 qpd->vmid = 0; 733 q->properties.vmid = 0; 734 } 735 736 static int create_queue_nocpsch(struct device_queue_manager *dqm, 737 struct queue *q, 738 struct qcm_process_device *qpd, 739 const struct kfd_criu_queue_priv_data *qd, 740 const void *restore_mqd, const void *restore_ctl_stack) 741 { 742 struct mqd_manager *mqd_mgr; 743 int retval; 744 745 dqm_lock(dqm); 746 747 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 748 pr_warn("Can't create new usermode queue because %d queues were already created\n", 749 dqm->total_queue_count); 750 retval = -EPERM; 751 goto out_unlock; 752 } 753 754 if (list_empty(&qpd->queues_list)) { 755 retval = allocate_vmid(dqm, qpd, q); 756 if (retval) 757 goto out_unlock; 758 } 759 q->properties.vmid = qpd->vmid; 760 /* 761 * Eviction state logic: mark all queues as evicted, even ones 762 * not currently active. Restoring inactive queues later only 763 * updates the is_evicted flag but is a no-op otherwise. 764 */ 765 q->properties.is_evicted = !!qpd->evicted; 766 767 q->properties.tba_addr = qpd->tba_addr; 768 q->properties.tma_addr = qpd->tma_addr; 769 770 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 771 q->properties.type)]; 772 if (qd && !mqd_mgr->restore_mqd) { 773 pr_debug("restore_mqd not implemented for this GPU\n"); 774 retval = -EOPNOTSUPP; 775 goto deallocate_vmid; 776 } 777 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { 778 retval = allocate_hqd(dqm, q); 779 if (retval) 780 goto deallocate_vmid; 781 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", 782 q->pipe, q->queue); 783 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 784 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 785 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 786 if (retval) 787 goto deallocate_vmid; 788 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 789 } 790 791 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 792 if (retval) 793 goto out_deallocate_hqd; 794 795 /* Temporarily release dqm lock to avoid a circular lock dependency */ 796 dqm_unlock(dqm); 797 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); 798 dqm_lock(dqm); 799 800 if (!q->mqd_mem_obj) { 801 retval = -ENOMEM; 802 goto out_deallocate_doorbell; 803 } 804 805 if (qd) 806 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 807 &q->properties, restore_mqd, restore_ctl_stack, 808 qd->ctl_stack_size); 809 else 810 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 811 &q->gart_mqd_addr, &q->properties); 812 813 if (q->properties.is_active) { 814 if (!dqm->sched_running) { 815 WARN_ONCE(1, "Load non-HWS mqd while stopped\n"); 816 goto add_queue_to_list; 817 } 818 819 if (WARN(q->process->mm != current->mm, 820 "should only run in user thread")) 821 retval = -EFAULT; 822 else 823 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 824 q->queue, &q->properties, current->mm); 825 if (retval) 826 goto out_free_mqd; 827 } 828 829 add_queue_to_list: 830 list_add(&q->list, &qpd->queues_list); 831 qpd->queue_count++; 832 if (q->properties.is_active) 833 increment_queue_count(dqm, qpd, q); 834 835 /* 836 * Unconditionally increment this counter, regardless of the queue's 837 * type or whether the queue is active. 838 */ 839 dqm->total_queue_count++; 840 pr_debug("Total of %d queues are accountable so far\n", 841 dqm->total_queue_count); 842 goto out_unlock; 843 844 out_free_mqd: 845 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 846 out_deallocate_doorbell: 847 deallocate_doorbell(qpd, q); 848 out_deallocate_hqd: 849 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 850 deallocate_hqd(dqm, q); 851 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 852 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 853 deallocate_sdma_queue(dqm, q); 854 deallocate_vmid: 855 if (list_empty(&qpd->queues_list)) 856 deallocate_vmid(dqm, qpd, q); 857 out_unlock: 858 dqm_unlock(dqm); 859 return retval; 860 } 861 862 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) 863 { 864 bool set; 865 int pipe, bit, i; 866 867 set = false; 868 869 for (pipe = dqm->next_pipe_to_allocate, i = 0; 870 i < get_pipes_per_mec(dqm); 871 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { 872 873 if (!is_pipe_enabled(dqm, 0, pipe)) 874 continue; 875 876 if (dqm->allocated_queues[pipe] != 0) { 877 bit = ffs(dqm->allocated_queues[pipe]) - 1; 878 dqm->allocated_queues[pipe] &= ~(1 << bit); 879 q->pipe = pipe; 880 q->queue = bit; 881 set = true; 882 break; 883 } 884 } 885 886 if (!set) 887 return -EBUSY; 888 889 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); 890 /* horizontal hqd allocation */ 891 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); 892 893 return 0; 894 } 895 896 static inline void deallocate_hqd(struct device_queue_manager *dqm, 897 struct queue *q) 898 { 899 dqm->allocated_queues[q->pipe] |= (1 << q->queue); 900 } 901 902 #define SQ_IND_CMD_CMD_KILL 0x00000003 903 #define SQ_IND_CMD_MODE_BROADCAST 0x00000001 904 905 static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process *p) 906 { 907 int status = 0; 908 unsigned int vmid; 909 uint16_t queried_pasid; 910 union SQ_CMD_BITS reg_sq_cmd; 911 union GRBM_GFX_INDEX_BITS reg_gfx_index; 912 struct kfd_process_device *pdd; 913 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd; 914 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd; 915 uint32_t xcc_mask = dev->xcc_mask; 916 int xcc_id; 917 918 reg_sq_cmd.u32All = 0; 919 reg_gfx_index.u32All = 0; 920 921 pr_debug("Killing all process wavefronts\n"); 922 923 if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) { 924 dev_err(dev->adev->dev, "no vmid pasid mapping supported\n"); 925 return -EOPNOTSUPP; 926 } 927 928 /* taking the VMID for that process on the safe way using PDD */ 929 pdd = kfd_get_process_device_data(dev, p); 930 if (!pdd) 931 return -EFAULT; 932 933 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING .. 934 * ATC_VMID15_PASID_MAPPING 935 * to check which VMID the current process is mapped to. 936 */ 937 938 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) { 939 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info 940 (dev->adev, vmid, &queried_pasid); 941 942 if (status && queried_pasid == pdd->pasid) { 943 pr_debug("Killing wave fronts of vmid %d and process pid %d\n", 944 vmid, p->lead_thread->pid); 945 break; 946 } 947 } 948 949 if (vmid > last_vmid_to_scan) { 950 dev_err(dev->adev->dev, "Didn't find vmid for process pid %d\n", 951 p->lead_thread->pid); 952 return -EFAULT; 953 } 954 955 reg_gfx_index.bits.sh_broadcast_writes = 1; 956 reg_gfx_index.bits.se_broadcast_writes = 1; 957 reg_gfx_index.bits.instance_broadcast_writes = 1; 958 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; 959 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL; 960 reg_sq_cmd.bits.vm_id = vmid; 961 962 for_each_inst(xcc_id, xcc_mask) 963 dev->kfd2kgd->wave_control_execute( 964 dev->adev, reg_gfx_index.u32All, 965 reg_sq_cmd.u32All, xcc_id); 966 967 return 0; 968 } 969 970 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked 971 * to avoid asynchronized access 972 */ 973 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, 974 struct qcm_process_device *qpd, 975 struct queue *q) 976 { 977 int retval; 978 struct mqd_manager *mqd_mgr; 979 980 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 981 982 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 983 deallocate_hqd(dqm, q); 984 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 985 deallocate_sdma_queue(dqm, q); 986 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 987 deallocate_sdma_queue(dqm, q); 988 else { 989 pr_debug("q->properties.type %d is invalid\n", 990 q->properties.type); 991 return -EINVAL; 992 } 993 dqm->total_queue_count--; 994 995 deallocate_doorbell(qpd, q); 996 997 if (!dqm->sched_running) { 998 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n"); 999 return 0; 1000 } 1001 1002 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 1003 KFD_PREEMPT_TYPE_WAVEFRONT_RESET, 1004 KFD_UNMAP_LATENCY_MS, 1005 q->pipe, q->queue); 1006 if (retval == -ETIME) 1007 qpd->reset_wavefronts = true; 1008 1009 list_del(&q->list); 1010 if (list_empty(&qpd->queues_list)) { 1011 if (qpd->reset_wavefronts) { 1012 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n", 1013 dqm->dev); 1014 /* dbgdev_wave_reset_wavefronts has to be called before 1015 * deallocate_vmid(), i.e. when vmid is still in use. 1016 */ 1017 dbgdev_wave_reset_wavefronts(dqm->dev, 1018 qpd->pqm->process); 1019 qpd->reset_wavefronts = false; 1020 } 1021 1022 deallocate_vmid(dqm, qpd, q); 1023 } 1024 qpd->queue_count--; 1025 if (q->properties.is_active) 1026 decrement_queue_count(dqm, qpd, q); 1027 1028 return retval; 1029 } 1030 1031 static int destroy_queue_nocpsch(struct device_queue_manager *dqm, 1032 struct qcm_process_device *qpd, 1033 struct queue *q) 1034 { 1035 int retval; 1036 uint64_t sdma_val = 0; 1037 struct device *dev = dqm->dev->adev->dev; 1038 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 1039 struct mqd_manager *mqd_mgr = 1040 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 1041 1042 /* Get the SDMA queue stats */ 1043 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 1044 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1045 if (dqm->dev->kfd2kgd->hqd_sdma_get_counter) 1046 retval = dqm->dev->kfd2kgd->hqd_sdma_get_counter( 1047 dqm->dev->adev, q->mqd, 1048 dqm->dev->kfd->device_info.num_sdma_queues_per_engine, 1049 &sdma_val); 1050 else 1051 retval = read_sdma_queue_counter( 1052 (uint64_t __user *)q->properties.read_ptr, 1053 &sdma_val); 1054 if (retval) 1055 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n", 1056 q->properties.queue_id); 1057 } 1058 1059 dqm_lock(dqm); 1060 retval = destroy_queue_nocpsch_locked(dqm, qpd, q); 1061 if (!retval) 1062 pdd->sdma_past_activity_counter += sdma_val; 1063 dqm_unlock(dqm); 1064 1065 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1066 1067 return retval; 1068 } 1069 1070 static int update_queue(struct device_queue_manager *dqm, struct queue *q, 1071 struct mqd_update_info *minfo) 1072 { 1073 int retval = 0; 1074 struct device *dev = dqm->dev->adev->dev; 1075 struct mqd_manager *mqd_mgr; 1076 struct kfd_process_device *pdd; 1077 bool prev_active = false; 1078 1079 dqm_lock(dqm); 1080 pdd = kfd_get_process_device_data(q->device, q->process); 1081 if (!pdd) { 1082 retval = -ENODEV; 1083 goto out_unlock; 1084 } 1085 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1086 q->properties.type)]; 1087 1088 /* Save previous activity state for counters */ 1089 prev_active = q->properties.is_active; 1090 1091 /* Make sure the queue is unmapped before updating the MQD */ 1092 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 1093 if (!dqm->dev->kfd->shared_resources.enable_mes) 1094 retval = unmap_queues_cpsch(dqm, 1095 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false); 1096 else if (prev_active) 1097 retval = remove_queue_mes(dqm, q, &pdd->qpd); 1098 1099 /* queue is reset so inaccessable */ 1100 if (pdd->has_reset_queue) { 1101 retval = -EACCES; 1102 goto out_unlock; 1103 } 1104 1105 if (retval) { 1106 dev_err(dev, "unmap queue failed\n"); 1107 goto out_unlock; 1108 } 1109 } else if (prev_active && 1110 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 1111 q->properties.type == KFD_QUEUE_TYPE_SDMA || 1112 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1113 1114 if (!dqm->sched_running) { 1115 WARN_ONCE(1, "Update non-HWS queue while stopped\n"); 1116 goto out_unlock; 1117 } 1118 1119 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 1120 (dqm->dev->kfd->cwsr_enabled ? 1121 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 1122 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 1123 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 1124 if (retval) { 1125 dev_err(dev, "destroy mqd failed\n"); 1126 goto out_unlock; 1127 } 1128 } 1129 1130 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo); 1131 1132 /* 1133 * check active state vs. the previous state and modify 1134 * counter accordingly. map_queues_cpsch uses the 1135 * dqm->active_queue_count to determine whether a new runlist must be 1136 * uploaded. 1137 */ 1138 if (q->properties.is_active && !prev_active) { 1139 increment_queue_count(dqm, &pdd->qpd, q); 1140 } else if (!q->properties.is_active && prev_active) { 1141 decrement_queue_count(dqm, &pdd->qpd, q); 1142 } else if (q->gws && !q->properties.is_gws) { 1143 if (q->properties.is_active) { 1144 dqm->gws_queue_count++; 1145 pdd->qpd.mapped_gws_queue = true; 1146 } 1147 q->properties.is_gws = true; 1148 } else if (!q->gws && q->properties.is_gws) { 1149 if (q->properties.is_active) { 1150 dqm->gws_queue_count--; 1151 pdd->qpd.mapped_gws_queue = false; 1152 } 1153 q->properties.is_gws = false; 1154 } 1155 1156 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 1157 if (!dqm->dev->kfd->shared_resources.enable_mes) 1158 retval = map_queues_cpsch(dqm); 1159 else if (q->properties.is_active) 1160 retval = add_queue_mes(dqm, q, &pdd->qpd); 1161 } else if (q->properties.is_active && 1162 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 1163 q->properties.type == KFD_QUEUE_TYPE_SDMA || 1164 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1165 if (WARN(q->process->mm != current->mm, 1166 "should only run in user thread")) 1167 retval = -EFAULT; 1168 else 1169 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, 1170 q->pipe, q->queue, 1171 &q->properties, current->mm); 1172 } 1173 1174 out_unlock: 1175 dqm_unlock(dqm); 1176 return retval; 1177 } 1178 1179 /* suspend_single_queue does not lock the dqm like the 1180 * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should 1181 * lock the dqm before calling, and unlock after calling. 1182 * 1183 * The reason we don't lock the dqm is because this function may be 1184 * called on multiple queues in a loop, so rather than locking/unlocking 1185 * multiple times, we will just keep the dqm locked for all of the calls. 1186 */ 1187 static int suspend_single_queue(struct device_queue_manager *dqm, 1188 struct kfd_process_device *pdd, 1189 struct queue *q) 1190 { 1191 bool is_new; 1192 1193 if (q->properties.is_suspended) 1194 return 0; 1195 1196 pr_debug("Suspending process pid %d queue [%i]\n", 1197 pdd->process->lead_thread->pid, 1198 q->properties.queue_id); 1199 1200 is_new = q->properties.exception_status & KFD_EC_MASK(EC_QUEUE_NEW); 1201 1202 if (is_new || q->properties.is_being_destroyed) { 1203 pr_debug("Suspend: skip %s queue id %i\n", 1204 is_new ? "new" : "destroyed", 1205 q->properties.queue_id); 1206 return -EBUSY; 1207 } 1208 1209 q->properties.is_suspended = true; 1210 if (q->properties.is_active) { 1211 if (dqm->dev->kfd->shared_resources.enable_mes) { 1212 int r = remove_queue_mes(dqm, q, &pdd->qpd); 1213 1214 if (r) 1215 return r; 1216 } 1217 1218 decrement_queue_count(dqm, &pdd->qpd, q); 1219 q->properties.is_active = false; 1220 } 1221 1222 return 0; 1223 } 1224 1225 /* resume_single_queue does not lock the dqm like the functions 1226 * restore_process_queues_cpsch or restore_process_queues_nocpsch. You should 1227 * lock the dqm before calling, and unlock after calling. 1228 * 1229 * The reason we don't lock the dqm is because this function may be 1230 * called on multiple queues in a loop, so rather than locking/unlocking 1231 * multiple times, we will just keep the dqm locked for all of the calls. 1232 */ 1233 static int resume_single_queue(struct device_queue_manager *dqm, 1234 struct qcm_process_device *qpd, 1235 struct queue *q) 1236 { 1237 struct kfd_process_device *pdd; 1238 1239 if (!q->properties.is_suspended) 1240 return 0; 1241 1242 pdd = qpd_to_pdd(qpd); 1243 1244 pr_debug("Restoring from suspend process pid %d queue [%i]\n", 1245 pdd->process->lead_thread->pid, 1246 q->properties.queue_id); 1247 1248 q->properties.is_suspended = false; 1249 1250 if (QUEUE_IS_ACTIVE(q->properties)) { 1251 if (dqm->dev->kfd->shared_resources.enable_mes) { 1252 int r = add_queue_mes(dqm, q, &pdd->qpd); 1253 1254 if (r) 1255 return r; 1256 } 1257 1258 q->properties.is_active = true; 1259 increment_queue_count(dqm, qpd, q); 1260 } 1261 1262 return 0; 1263 } 1264 1265 /* Unpin the MQD BO at S4 suspend so it is evicted into the hibernation image; 1266 * dqm_repin_mqd_bo() pins it back on resume. Gated on adev->in_s4 so runtime 1267 * eviction is untouched. 1268 */ 1269 static void dqm_evict_mqd_bo(struct device_queue_manager *dqm, struct queue *q) 1270 { 1271 struct mqd_manager *mqd_mgr; 1272 struct amdgpu_bo *bo; 1273 1274 if (!dqm->dev->adev->in_s4) 1275 return; 1276 if (!mqd_on_vram(dqm->dev->adev)) 1277 return; 1278 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE) 1279 return; 1280 if (!q->mqd_mem_obj || !q->mqd_mem_obj->mem) 1281 return; 1282 1283 /* Without update_mqd_gpu_addr() the MQD self-address cannot be fixed up 1284 * after a repin, so skip eviction (with a warning) instead of faulting. 1285 */ 1286 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 1287 if (!mqd_mgr->update_mqd_gpu_addr) { 1288 dev_warn_once(dqm->dev->adev->dev, 1289 "MQD is in VRAM but update_mqd_gpu_addr is not implemented; skipping hibernation eviction\n"); 1290 return; 1291 } 1292 1293 bo = q->mqd_mem_obj->mem; 1294 if (amdgpu_bo_reserve(bo, false)) 1295 return; 1296 1297 amdgpu_bo_unpin(bo); 1298 amdgpu_bo_unreserve(bo); 1299 q->mqd = NULL; 1300 q->needs_mqd_repin = true; 1301 } 1302 1303 /* Repin the MQD BO to VRAM and refresh the cached mapping and GPU addresses. 1304 * Used both on resume and when a queue is destroyed before resume has repinned 1305 * it. A no-op unless a repin is owed (needs_mqd_repin set). 1306 */ 1307 static int dqm_repin_mqd_bo(struct device_queue_manager *dqm, struct queue *q) 1308 { 1309 struct mqd_manager *mqd_mgr; 1310 struct amdgpu_bo *bo; 1311 void *cpu_ptr; 1312 int r; 1313 1314 if (!q->needs_mqd_repin) 1315 return 0; 1316 if (!q->mqd_mem_obj || !q->mqd_mem_obj->mem) 1317 return 0; 1318 1319 bo = q->mqd_mem_obj->mem; 1320 r = amdgpu_bo_reserve(bo, false); 1321 if (r) 1322 return r; 1323 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM); 1324 if (r) { 1325 amdgpu_bo_unreserve(bo); 1326 dev_err(dqm->dev->adev->dev, 1327 "Failed to repin MQD of queue %d to VRAM: %d\n", 1328 q->properties.queue_id, r); 1329 return r; 1330 } 1331 /* The BO may have moved; refresh the kernel mapping and gpu address. */ 1332 amdgpu_bo_kunmap(bo); 1333 r = amdgpu_bo_kmap(bo, &cpu_ptr); 1334 amdgpu_bo_unreserve(bo); 1335 if (r) { 1336 dev_err(dqm->dev->adev->dev, 1337 "Failed to remap MQD of queue %d: %d\n", 1338 q->properties.queue_id, r); 1339 return r; 1340 } 1341 1342 q->mqd_mem_obj->cpu_ptr = cpu_ptr; 1343 q->mqd_mem_obj->gpu_addr = amdgpu_bo_gpu_offset(bo); 1344 q->gart_mqd_addr = q->mqd_mem_obj->gpu_addr; 1345 q->mqd = cpu_ptr; 1346 1347 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1348 q->properties.type)]; 1349 if (mqd_mgr->update_mqd_gpu_addr) 1350 mqd_mgr->update_mqd_gpu_addr(mqd_mgr, q->mqd, 1351 q->mqd_mem_obj, 1352 &q->properties); 1353 1354 q->needs_mqd_repin = false; 1355 return 0; 1356 } 1357 1358 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm, 1359 struct qcm_process_device *qpd) 1360 { 1361 struct queue *q; 1362 struct mqd_manager *mqd_mgr; 1363 struct kfd_process_device *pdd; 1364 int retval, ret = 0; 1365 1366 dqm_lock(dqm); 1367 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 1368 goto out; 1369 1370 pdd = qpd_to_pdd(qpd); 1371 pr_debug_ratelimited("Evicting process pid %d queues\n", 1372 pdd->process->lead_thread->pid); 1373 1374 pdd->last_evict_timestamp = get_jiffies_64(); 1375 /* Mark all queues as evicted. Deactivate all active queues on 1376 * the qpd. 1377 */ 1378 list_for_each_entry(q, &qpd->queues_list, list) { 1379 q->properties.is_evicted = true; 1380 if (!q->properties.is_active) 1381 continue; 1382 1383 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1384 q->properties.type)]; 1385 q->properties.is_active = false; 1386 decrement_queue_count(dqm, qpd, q); 1387 1388 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n")) 1389 continue; 1390 1391 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 1392 (dqm->dev->kfd->cwsr_enabled ? 1393 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 1394 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 1395 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 1396 if (retval && !ret) 1397 /* Return the first error, but keep going to 1398 * maintain a consistent eviction state 1399 */ 1400 ret = retval; 1401 } 1402 1403 out: 1404 dqm_unlock(dqm); 1405 return ret; 1406 } 1407 1408 static int evict_process_queues_cpsch(struct device_queue_manager *dqm, 1409 struct qcm_process_device *qpd) 1410 { 1411 struct queue *q; 1412 struct device *dev = dqm->dev->adev->dev; 1413 struct kfd_process_device *pdd; 1414 int retval = 0; 1415 1416 dqm_lock(dqm); 1417 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 1418 goto out; 1419 1420 pdd = qpd_to_pdd(qpd); 1421 1422 /* The debugger creates processes that temporarily have not acquired 1423 * all VMs for all devices and has no VMs itself. 1424 * Skip queue eviction on process eviction. 1425 */ 1426 if (!pdd->drm_priv) 1427 goto out; 1428 1429 pr_debug_ratelimited("Evicting process pid %d queues\n", 1430 pdd->process->lead_thread->pid); 1431 1432 if (dqm->dev->kfd->shared_resources.enable_mes) 1433 pdd->last_evict_timestamp = get_jiffies_64(); 1434 1435 /* Mark all queues as evicted. Deactivate all active queues on 1436 * the qpd. 1437 */ 1438 list_for_each_entry(q, &qpd->queues_list, list) { 1439 q->properties.is_evicted = true; 1440 if (!q->properties.is_active) 1441 continue; 1442 1443 q->properties.is_active = false; 1444 decrement_queue_count(dqm, qpd, q); 1445 1446 if (dqm->dev->kfd->shared_resources.enable_mes) { 1447 retval = remove_queue_mes(dqm, q, qpd); 1448 if (retval) { 1449 dev_err(dev, "Failed to evict queue %d\n", 1450 q->properties.queue_id); 1451 goto out; 1452 } 1453 } 1454 1455 dqm_evict_mqd_bo(dqm, q); 1456 } 1457 1458 /* 1459 * Heavy-weight TLB flush after MES removes queues to ensure 1460 * in-flight memory accesses complete before memory is freed/migrated. 1461 * HWS does this automatically, MES does not. 1462 */ 1463 if (dqm->dev->kfd->shared_resources.enable_mes) 1464 kfd_flush_tlb(pdd); 1465 1466 if (!dqm->dev->kfd->shared_resources.enable_mes) { 1467 pdd->last_evict_timestamp = get_jiffies_64(); 1468 retval = execute_queues_cpsch(dqm, 1469 qpd->is_debug ? 1470 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : 1471 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 1472 USE_DEFAULT_GRACE_PERIOD); 1473 } 1474 1475 out: 1476 dqm_unlock(dqm); 1477 return retval; 1478 } 1479 1480 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, 1481 struct qcm_process_device *qpd) 1482 { 1483 struct mm_struct *mm = NULL; 1484 struct queue *q; 1485 struct mqd_manager *mqd_mgr; 1486 struct kfd_process_device *pdd; 1487 uint64_t pd_base; 1488 uint64_t eviction_duration; 1489 int retval, ret = 0; 1490 1491 pdd = qpd_to_pdd(qpd); 1492 /* Retrieve PD base */ 1493 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1494 1495 dqm_lock(dqm); 1496 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 1497 goto out; 1498 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 1499 qpd->evicted--; 1500 goto out; 1501 } 1502 1503 pr_debug_ratelimited("Restoring process pid %d queues\n", 1504 pdd->process->lead_thread->pid); 1505 1506 /* Update PD Base in QPD */ 1507 qpd->page_table_base = pd_base; 1508 pr_debug("Updated PD address to 0x%llx\n", pd_base); 1509 1510 if (!list_empty(&qpd->queues_list)) { 1511 dqm->dev->kfd2kgd->set_vm_context_page_table_base( 1512 dqm->dev->adev, 1513 qpd->vmid, 1514 qpd->page_table_base); 1515 kfd_flush_tlb(pdd); 1516 } 1517 1518 /* Take a safe reference to the mm_struct, which may otherwise 1519 * disappear even while the kfd_process is still referenced. 1520 */ 1521 mm = get_task_mm(pdd->process->lead_thread); 1522 if (!mm) { 1523 ret = -EFAULT; 1524 goto out; 1525 } 1526 1527 /* Remove the eviction flags. Activate queues that are not 1528 * inactive for other reasons. 1529 */ 1530 list_for_each_entry(q, &qpd->queues_list, list) { 1531 q->properties.is_evicted = false; 1532 if (!QUEUE_IS_ACTIVE(q->properties)) 1533 continue; 1534 1535 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1536 q->properties.type)]; 1537 q->properties.is_active = true; 1538 increment_queue_count(dqm, qpd, q); 1539 1540 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n")) 1541 continue; 1542 1543 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 1544 q->queue, &q->properties, mm); 1545 if (retval && !ret) 1546 /* Return the first error, but keep going to 1547 * maintain a consistent eviction state 1548 */ 1549 ret = retval; 1550 } 1551 qpd->evicted = 0; 1552 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 1553 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 1554 out: 1555 if (mm) 1556 mmput(mm); 1557 dqm_unlock(dqm); 1558 return ret; 1559 } 1560 1561 static int restore_process_queues_cpsch(struct device_queue_manager *dqm, 1562 struct qcm_process_device *qpd) 1563 { 1564 struct queue *q; 1565 struct device *dev = dqm->dev->adev->dev; 1566 struct kfd_process_device *pdd; 1567 uint64_t eviction_duration; 1568 int retval = 0; 1569 1570 pdd = qpd_to_pdd(qpd); 1571 1572 dqm_lock(dqm); 1573 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 1574 goto out; 1575 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 1576 qpd->evicted--; 1577 goto out; 1578 } 1579 1580 /* The debugger creates processes that temporarily have not acquired 1581 * all VMs for all devices and has no VMs itself. 1582 * Skip queue restore on process restore. 1583 */ 1584 if (!pdd->drm_priv) 1585 goto vm_not_acquired; 1586 1587 pr_debug_ratelimited("Restoring process pid %d queues\n", 1588 pdd->process->lead_thread->pid); 1589 1590 /* Update PD Base in QPD */ 1591 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1592 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base); 1593 1594 /* activate all active queues on the qpd */ 1595 list_for_each_entry(q, &qpd->queues_list, list) { 1596 q->properties.is_evicted = false; 1597 if (!QUEUE_IS_ACTIVE(q->properties)) 1598 continue; 1599 1600 q->properties.is_active = true; 1601 increment_queue_count(dqm, &pdd->qpd, q); 1602 1603 retval = dqm_repin_mqd_bo(dqm, q); 1604 if (retval) { 1605 dev_err(dev, "Failed to repin MQD for queue %d\n", 1606 q->properties.queue_id); 1607 goto out; 1608 } 1609 1610 if (dqm->dev->kfd->shared_resources.enable_mes) { 1611 retval = add_queue_mes(dqm, q, qpd); 1612 if (retval) { 1613 dev_err(dev, "Failed to restore queue %d\n", 1614 q->properties.queue_id); 1615 goto out; 1616 } 1617 } 1618 } 1619 if (!dqm->dev->kfd->shared_resources.enable_mes) 1620 retval = execute_queues_cpsch(dqm, 1621 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1622 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 1623 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 1624 vm_not_acquired: 1625 qpd->evicted = 0; 1626 out: 1627 dqm_unlock(dqm); 1628 return retval; 1629 } 1630 1631 static int register_process(struct device_queue_manager *dqm, 1632 struct qcm_process_device *qpd) 1633 { 1634 struct device_process_node *n; 1635 struct kfd_process_device *pdd; 1636 uint64_t pd_base; 1637 int retval; 1638 1639 n = kzalloc_obj(*n); 1640 if (!n) 1641 return -ENOMEM; 1642 1643 n->qpd = qpd; 1644 1645 pdd = qpd_to_pdd(qpd); 1646 /* Retrieve PD base */ 1647 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1648 1649 dqm_lock(dqm); 1650 list_add(&n->list, &dqm->queues); 1651 1652 /* Update PD Base in QPD */ 1653 qpd->page_table_base = pd_base; 1654 pr_debug("Updated PD address to 0x%llx\n", pd_base); 1655 1656 retval = dqm->asic_ops.update_qpd(dqm, qpd); 1657 1658 dqm->processes_count++; 1659 1660 dqm_unlock(dqm); 1661 1662 /* Outside the DQM lock because under the DQM lock we can't do 1663 * reclaim or take other locks that others hold while reclaiming. 1664 */ 1665 kfd_inc_compute_active(dqm->dev); 1666 1667 return retval; 1668 } 1669 1670 static int unregister_process(struct device_queue_manager *dqm, 1671 struct qcm_process_device *qpd) 1672 { 1673 int retval = 0; 1674 struct device_process_node *cur, *next; 1675 1676 pr_debug("qpd->queues_list is %s\n", 1677 list_empty(&qpd->queues_list) ? "empty" : "not empty"); 1678 1679 dqm_lock(dqm); 1680 1681 list_for_each_entry_safe(cur, next, &dqm->queues, list) { 1682 if (qpd == cur->qpd) { 1683 list_del(&cur->list); 1684 kfree(cur); 1685 dqm->processes_count--; 1686 goto out; 1687 } 1688 } 1689 /* qpd not found in dqm list */ 1690 retval = 1; 1691 out: 1692 dqm_unlock(dqm); 1693 1694 /* Outside the DQM lock because under the DQM lock we can't do 1695 * reclaim or take other locks that others hold while reclaiming. 1696 */ 1697 if (!retval) 1698 kfd_dec_compute_active(dqm->dev); 1699 1700 return retval; 1701 } 1702 1703 static int 1704 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid, 1705 unsigned int vmid) 1706 { 1707 uint32_t xcc_mask = dqm->dev->xcc_mask; 1708 int xcc_id, ret = 0; 1709 1710 for_each_inst(xcc_id, xcc_mask) { 1711 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping( 1712 dqm->dev->adev, pasid, vmid, xcc_id); 1713 if (ret) 1714 break; 1715 } 1716 1717 return ret; 1718 } 1719 1720 static void init_interrupts(struct device_queue_manager *dqm) 1721 { 1722 uint32_t xcc_mask = dqm->dev->xcc_mask; 1723 unsigned int i, xcc_id; 1724 1725 for_each_inst(xcc_id, xcc_mask) { 1726 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) { 1727 if (is_pipe_enabled(dqm, 0, i)) { 1728 dqm->dev->kfd2kgd->init_interrupts( 1729 dqm->dev->adev, i, xcc_id); 1730 } 1731 } 1732 } 1733 } 1734 1735 static int initialize_nocpsch(struct device_queue_manager *dqm) 1736 { 1737 int pipe, queue; 1738 1739 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1740 1741 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), 1742 sizeof(unsigned int), GFP_KERNEL); 1743 if (!dqm->allocated_queues) 1744 return -ENOMEM; 1745 1746 mutex_init(&dqm->lock_hidden); 1747 INIT_LIST_HEAD(&dqm->queues); 1748 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0; 1749 dqm->active_cp_queue_count = 0; 1750 dqm->gws_queue_count = 0; 1751 1752 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 1753 int pipe_offset = pipe * get_queues_per_pipe(dqm); 1754 1755 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) 1756 if (test_bit(pipe_offset + queue, 1757 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 1758 dqm->allocated_queues[pipe] |= 1 << queue; 1759 } 1760 1761 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid)); 1762 1763 init_sdma_bitmaps(dqm); 1764 1765 return 0; 1766 } 1767 1768 static void uninitialize(struct device_queue_manager *dqm) 1769 { 1770 int i; 1771 1772 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0); 1773 1774 kfree(dqm->allocated_queues); 1775 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) 1776 kfree(dqm->mqd_mgrs[i]); 1777 mutex_destroy(&dqm->lock_hidden); 1778 } 1779 1780 static int start_nocpsch(struct device_queue_manager *dqm) 1781 { 1782 int r = 0; 1783 1784 pr_info("SW scheduler is used"); 1785 init_interrupts(dqm); 1786 1787 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1788 r = pm_init(&dqm->packet_mgr, dqm); 1789 if (!r) 1790 dqm->sched_running = true; 1791 1792 return r; 1793 } 1794 1795 static int stop_nocpsch(struct device_queue_manager *dqm) 1796 { 1797 dqm_lock(dqm); 1798 if (!dqm->sched_running) { 1799 dqm_unlock(dqm); 1800 return 0; 1801 } 1802 1803 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1804 pm_uninit(&dqm->packet_mgr); 1805 dqm->sched_running = false; 1806 dqm_unlock(dqm); 1807 1808 return 0; 1809 } 1810 1811 static int allocate_sdma_queue(struct device_queue_manager *dqm, 1812 struct queue *q, const uint32_t *restore_sdma_id) 1813 { 1814 struct device *dev = dqm->dev->adev->dev; 1815 int bit; 1816 1817 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1818 if (bitmap_empty(dqm->sdma_bitmap, get_num_sdma_queues(dqm))) { 1819 dev_warn(dev, "No more SDMA queue to allocate (%d total queues)\n", 1820 get_num_sdma_queues(dqm)); 1821 return -ENOMEM; 1822 } 1823 1824 if (restore_sdma_id) { 1825 if (*restore_sdma_id >= get_num_sdma_queues(dqm)) 1826 return -EINVAL; 1827 1828 /* Re-use existing sdma_id */ 1829 if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) { 1830 dev_err(dev, "SDMA queue already in use\n"); 1831 return -EBUSY; 1832 } 1833 clear_bit(*restore_sdma_id, dqm->sdma_bitmap); 1834 q->sdma_id = *restore_sdma_id; 1835 } else { 1836 /* Find first available sdma_id */ 1837 bit = find_first_bit(dqm->sdma_bitmap, 1838 get_num_sdma_queues(dqm)); 1839 clear_bit(bit, dqm->sdma_bitmap); 1840 q->sdma_id = bit; 1841 } 1842 1843 q->properties.sdma_engine_id = 1844 q->sdma_id % kfd_get_num_sdma_engines(dqm->dev); 1845 q->properties.sdma_queue_id = q->sdma_id / 1846 kfd_get_num_sdma_engines(dqm->dev); 1847 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1848 if (bitmap_empty(dqm->xgmi_sdma_bitmap, get_num_xgmi_sdma_queues(dqm))) { 1849 dev_warn(dev, "No more XGMI SDMA queue to allocate (%d total queues)\n", 1850 get_num_xgmi_sdma_queues(dqm)); 1851 return -ENOMEM; 1852 } 1853 if (restore_sdma_id) { 1854 if (*restore_sdma_id >= get_num_xgmi_sdma_queues(dqm)) 1855 return -EINVAL; 1856 1857 /* Re-use existing sdma_id */ 1858 if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) { 1859 dev_err(dev, "SDMA queue already in use\n"); 1860 return -EBUSY; 1861 } 1862 clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap); 1863 q->sdma_id = *restore_sdma_id; 1864 } else { 1865 bit = find_first_bit(dqm->xgmi_sdma_bitmap, 1866 get_num_xgmi_sdma_queues(dqm)); 1867 clear_bit(bit, dqm->xgmi_sdma_bitmap); 1868 q->sdma_id = bit; 1869 } 1870 /* sdma_engine_id is sdma id including 1871 * both PCIe-optimized SDMAs and XGMI- 1872 * optimized SDMAs. The calculation below 1873 * assumes the first N engines are always 1874 * PCIe-optimized ones 1875 */ 1876 q->properties.sdma_engine_id = 1877 kfd_get_num_sdma_engines(dqm->dev) + 1878 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev); 1879 q->properties.sdma_queue_id = q->sdma_id / 1880 kfd_get_num_xgmi_sdma_engines(dqm->dev); 1881 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 1882 int i, num_queues, num_engines, eng_offset = 0, start_engine; 1883 bool free_bit_found = false, is_xgmi = false; 1884 1885 if (q->properties.sdma_engine_id < kfd_get_num_sdma_engines(dqm->dev)) { 1886 num_queues = get_num_sdma_queues(dqm); 1887 num_engines = kfd_get_num_sdma_engines(dqm->dev); 1888 q->properties.type = KFD_QUEUE_TYPE_SDMA; 1889 } else { 1890 num_queues = get_num_xgmi_sdma_queues(dqm); 1891 num_engines = kfd_get_num_xgmi_sdma_engines(dqm->dev); 1892 eng_offset = kfd_get_num_sdma_engines(dqm->dev); 1893 q->properties.type = KFD_QUEUE_TYPE_SDMA_XGMI; 1894 is_xgmi = true; 1895 } 1896 1897 /* Scan available bit based on target engine ID. */ 1898 start_engine = q->properties.sdma_engine_id - eng_offset; 1899 for (i = start_engine; i < num_queues; i += num_engines) { 1900 1901 if (!test_bit(i, is_xgmi ? dqm->xgmi_sdma_bitmap : dqm->sdma_bitmap)) 1902 continue; 1903 1904 clear_bit(i, is_xgmi ? dqm->xgmi_sdma_bitmap : dqm->sdma_bitmap); 1905 q->sdma_id = i; 1906 q->properties.sdma_queue_id = q->sdma_id / num_engines; 1907 free_bit_found = true; 1908 break; 1909 } 1910 1911 if (!free_bit_found) { 1912 dev_warn(dev, "No more SDMA queue to allocate for target ID %i (%d total queues)\n", 1913 q->properties.sdma_engine_id, num_queues); 1914 return -ENOMEM; 1915 } 1916 } 1917 1918 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); 1919 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); 1920 1921 return 0; 1922 } 1923 1924 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 1925 struct queue *q) 1926 { 1927 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1928 if (q->sdma_id >= get_num_sdma_queues(dqm)) 1929 return; 1930 set_bit(q->sdma_id, dqm->sdma_bitmap); 1931 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1932 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm)) 1933 return; 1934 set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap); 1935 } 1936 } 1937 1938 /* 1939 * Device Queue Manager implementation for cp scheduler 1940 */ 1941 1942 static int set_sched_resources(struct device_queue_manager *dqm) 1943 { 1944 int i, mec; 1945 struct scheduling_resources res; 1946 struct device *dev = dqm->dev->adev->dev; 1947 1948 res.vmid_mask = dqm->dev->compute_vmid_bitmap; 1949 1950 res.queue_mask = 0; 1951 for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) { 1952 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) 1953 / dqm->dev->kfd->shared_resources.num_pipe_per_mec; 1954 1955 if (!test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 1956 continue; 1957 1958 /* only acquire queues from the first MEC */ 1959 if (mec > 0) 1960 continue; 1961 1962 /* This situation may be hit in the future if a new HW 1963 * generation exposes more than 64 queues. If so, the 1964 * definition of res.queue_mask needs updating 1965 */ 1966 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { 1967 dev_err(dev, "Invalid queue enabled by amdgpu: %d\n", i); 1968 break; 1969 } 1970 1971 res.queue_mask |= 1ull 1972 << amdgpu_queue_mask_bit_to_set_resource_bit( 1973 dqm->dev->adev, i); 1974 } 1975 res.gws_mask = ~0ull; 1976 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; 1977 1978 pr_debug("Scheduling resources:\n" 1979 "vmid mask: 0x%8X\n" 1980 "queue mask: 0x%8llX\n", 1981 res.vmid_mask, res.queue_mask); 1982 1983 return pm_send_set_resources(&dqm->packet_mgr, &res); 1984 } 1985 1986 static int initialize_cpsch(struct device_queue_manager *dqm) 1987 { 1988 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1989 1990 mutex_init(&dqm->lock_hidden); 1991 INIT_LIST_HEAD(&dqm->queues); 1992 dqm->active_queue_count = dqm->processes_count = 0; 1993 dqm->active_cp_queue_count = 0; 1994 dqm->gws_queue_count = 0; 1995 dqm->active_runlist = false; 1996 dqm->trap_debug_vmid = 0; 1997 1998 init_sdma_bitmaps(dqm); 1999 2000 update_dqm_wait_times(dqm); 2001 return 0; 2002 } 2003 2004 /* halt_cpsch: 2005 * Unmap queues so the schedule doesn't continue remaining jobs in the queue. 2006 * Then set dqm->sched_halt so queues don't map to runlist until unhalt_cpsch 2007 * is called. 2008 */ 2009 static int halt_cpsch(struct device_queue_manager *dqm) 2010 { 2011 int ret = 0; 2012 2013 dqm_lock(dqm); 2014 if (!dqm->sched_running) { 2015 dqm_unlock(dqm); 2016 return 0; 2017 } 2018 2019 WARN_ONCE(dqm->sched_halt, "Scheduling is already on halt\n"); 2020 2021 if (!dqm->is_hws_hang) { 2022 if (!dqm->dev->kfd->shared_resources.enable_mes) 2023 ret = unmap_queues_cpsch(dqm, 2024 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 2025 USE_DEFAULT_GRACE_PERIOD, false); 2026 else 2027 ret = remove_all_kfd_queues_mes(dqm); 2028 } 2029 dqm->sched_halt = true; 2030 dqm_unlock(dqm); 2031 2032 return ret; 2033 } 2034 2035 /* unhalt_cpsch 2036 * Unset dqm->sched_halt and map queues back to runlist 2037 */ 2038 static int unhalt_cpsch(struct device_queue_manager *dqm) 2039 { 2040 int ret = 0; 2041 struct amdgpu_device *adev = dqm->dev->adev; 2042 2043 dqm_lock(dqm); 2044 if (!dqm->sched_running || !dqm->sched_halt) { 2045 dev_dbg(adev->dev, "Scheduling is not on halt.\n"); 2046 dqm_unlock(dqm); 2047 return 0; 2048 } 2049 dqm->sched_halt = false; 2050 if (!dqm->dev->kfd->shared_resources.enable_mes) 2051 ret = execute_queues_cpsch(dqm, 2052 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 2053 0, USE_DEFAULT_GRACE_PERIOD); 2054 else 2055 ret = add_all_kfd_queues_mes(dqm); 2056 2057 dqm_unlock(dqm); 2058 2059 return ret; 2060 } 2061 2062 static int start_cpsch(struct device_queue_manager *dqm) 2063 { 2064 struct device *dev = dqm->dev->adev->dev; 2065 int retval, num_hw_queue_slots; 2066 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 2067 int hung_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev); 2068 int hqd_info_size = adev->mes.hung_queue_hqd_info_offset; 2069 2070 dqm_lock(dqm); 2071 2072 if (!dqm->dev->kfd->shared_resources.enable_mes) { 2073 retval = pm_init(&dqm->packet_mgr, dqm); 2074 if (retval) 2075 goto fail_packet_manager_init; 2076 2077 retval = set_sched_resources(dqm); 2078 if (retval) 2079 goto fail_set_sched_resources; 2080 } 2081 pr_debug("Allocating fence memory\n"); 2082 2083 /* allocate fence memory on the gart */ 2084 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), 2085 &dqm->fence_mem); 2086 2087 if (retval) 2088 goto fail_allocate_vidmem; 2089 2090 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr; 2091 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; 2092 2093 init_interrupts(dqm); 2094 2095 /* clear hang status when driver try to start the hw scheduler */ 2096 dqm->sched_running = true; 2097 2098 if (!dqm->dev->kfd->shared_resources.enable_mes) { 2099 if (pm_config_dequeue_wait_counts(&dqm->packet_mgr, 2100 KFD_DEQUEUE_WAIT_INIT, 0 /* unused */)) 2101 dev_err(dev, "Setting optimized dequeue wait failed. Using default values\n"); 2102 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 2103 } 2104 2105 /* setup per-queue reset detection buffer */ 2106 num_hw_queue_slots = dqm->dev->kfd->shared_resources.num_queue_per_pipe * 2107 dqm->dev->kfd->shared_resources.num_pipe_per_mec * 2108 NUM_XCC(dqm->dev->xcc_mask); 2109 2110 dqm->detect_hang_info_size = num_hw_queue_slots * sizeof(struct dqm_detect_hang_info); 2111 dqm->detect_hang_info = kzalloc(dqm->detect_hang_info_size, GFP_KERNEL); 2112 2113 if (!dqm->detect_hang_info) { 2114 retval = -ENOMEM; 2115 goto fail_detect_hang_buffer; 2116 } 2117 2118 dqm->hung_db_array = kzalloc(hung_array_size * sizeof(u32), GFP_KERNEL); 2119 dqm->hqd_info = kzalloc( 2120 hqd_info_size * sizeof(struct amdgpu_mes_hung_queue_hqd_info), 2121 GFP_KERNEL); 2122 2123 dqm_unlock(dqm); 2124 2125 return 0; 2126 fail_detect_hang_buffer: 2127 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 2128 fail_allocate_vidmem: 2129 fail_set_sched_resources: 2130 if (!dqm->dev->kfd->shared_resources.enable_mes) 2131 pm_uninit(&dqm->packet_mgr); 2132 fail_packet_manager_init: 2133 dqm_unlock(dqm); 2134 return retval; 2135 } 2136 2137 static int stop_cpsch(struct device_queue_manager *dqm) 2138 { 2139 int ret = 0; 2140 2141 dqm_lock(dqm); 2142 if (!dqm->sched_running) { 2143 dqm_unlock(dqm); 2144 return 0; 2145 } 2146 2147 if (!dqm->dev->kfd->shared_resources.enable_mes) 2148 ret = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 2149 0, USE_DEFAULT_GRACE_PERIOD, false); 2150 else 2151 ret = remove_all_kfd_queues_mes(dqm); 2152 2153 dqm->sched_running = false; 2154 2155 if (!dqm->dev->kfd->shared_resources.enable_mes) 2156 pm_release_ib(&dqm->packet_mgr); 2157 2158 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 2159 if (!dqm->dev->kfd->shared_resources.enable_mes) 2160 pm_uninit(&dqm->packet_mgr); 2161 kfree(dqm->detect_hang_info); 2162 dqm->detect_hang_info = NULL; 2163 kfree(dqm->hung_db_array); 2164 kfree(dqm->hqd_info); 2165 2166 dqm_unlock(dqm); 2167 2168 return ret; 2169 } 2170 2171 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, 2172 struct kernel_queue *kq, 2173 struct qcm_process_device *qpd) 2174 { 2175 dqm_lock(dqm); 2176 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 2177 pr_warn("Can't create new kernel queue because %d queues were already created\n", 2178 dqm->total_queue_count); 2179 dqm_unlock(dqm); 2180 return -EPERM; 2181 } 2182 2183 /* 2184 * Unconditionally increment this counter, regardless of the queue's 2185 * type or whether the queue is active. 2186 */ 2187 dqm->total_queue_count++; 2188 pr_debug("Total of %d queues are accountable so far\n", 2189 dqm->total_queue_count); 2190 2191 list_add(&kq->list, &qpd->priv_queue_list); 2192 increment_queue_count(dqm, qpd, kq->queue); 2193 qpd->is_debug = true; 2194 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 2195 USE_DEFAULT_GRACE_PERIOD); 2196 dqm_unlock(dqm); 2197 2198 return 0; 2199 } 2200 2201 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, 2202 struct kernel_queue *kq, 2203 struct qcm_process_device *qpd) 2204 { 2205 dqm_lock(dqm); 2206 list_del(&kq->list); 2207 decrement_queue_count(dqm, qpd, kq->queue); 2208 qpd->is_debug = false; 2209 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 2210 USE_DEFAULT_GRACE_PERIOD); 2211 /* 2212 * Unconditionally decrement this counter, regardless of the queue's 2213 * type. 2214 */ 2215 dqm->total_queue_count--; 2216 pr_debug("Total of %d queues are accountable so far\n", 2217 dqm->total_queue_count); 2218 dqm_unlock(dqm); 2219 } 2220 2221 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, 2222 struct qcm_process_device *qpd, 2223 const struct kfd_criu_queue_priv_data *qd, 2224 const void *restore_mqd, const void *restore_ctl_stack) 2225 { 2226 int retval; 2227 struct mqd_manager *mqd_mgr; 2228 2229 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 2230 pr_warn("Can't create new usermode queue because %d queues were already created\n", 2231 dqm->total_queue_count); 2232 retval = -EPERM; 2233 goto out; 2234 } 2235 2236 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 2237 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI || 2238 q->properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 2239 dqm_lock(dqm); 2240 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 2241 dqm_unlock(dqm); 2242 if (retval) 2243 goto out; 2244 } 2245 2246 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 2247 if (retval) 2248 goto out_deallocate_sdma_queue; 2249 2250 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2251 q->properties.type)]; 2252 if (qd && !mqd_mgr->restore_mqd) { 2253 pr_debug("restore_mqd not implemented for this GPU\n"); 2254 retval = -EOPNOTSUPP; 2255 goto out_deallocate_doorbell; 2256 } 2257 2258 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 2259 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 2260 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 2261 q->properties.tba_addr = qpd->tba_addr; 2262 q->properties.tma_addr = qpd->tma_addr; 2263 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); 2264 if (!q->mqd_mem_obj) { 2265 retval = -ENOMEM; 2266 goto out_deallocate_doorbell; 2267 } 2268 2269 dqm_lock(dqm); 2270 /* 2271 * Eviction state logic: mark all queues as evicted, even ones 2272 * not currently active. Restoring inactive queues later only 2273 * updates the is_evicted flag but is a no-op otherwise. 2274 */ 2275 q->properties.is_evicted = !!qpd->evicted; 2276 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled && 2277 kfd_dbg_has_cwsr_workaround(q->device); 2278 2279 if (qd) 2280 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 2281 &q->properties, restore_mqd, restore_ctl_stack, 2282 qd->ctl_stack_size); 2283 else 2284 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 2285 &q->gart_mqd_addr, &q->properties); 2286 2287 list_add(&q->list, &qpd->queues_list); 2288 qpd->queue_count++; 2289 2290 if (q->properties.is_active) { 2291 increment_queue_count(dqm, qpd, q); 2292 2293 if (!dqm->dev->kfd->shared_resources.enable_mes) 2294 retval = execute_queues_cpsch(dqm, 2295 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 2296 else 2297 retval = add_queue_mes(dqm, q, qpd); 2298 if (retval) 2299 goto cleanup_queue; 2300 } 2301 2302 /* 2303 * Unconditionally increment this counter, regardless of the queue's 2304 * type or whether the queue is active. 2305 */ 2306 dqm->total_queue_count++; 2307 2308 pr_debug("Total of %d queues are accountable so far\n", 2309 dqm->total_queue_count); 2310 2311 dqm_unlock(dqm); 2312 return retval; 2313 2314 cleanup_queue: 2315 qpd->queue_count--; 2316 list_del(&q->list); 2317 if (q->properties.is_active) 2318 decrement_queue_count(dqm, qpd, q); 2319 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2320 dqm_unlock(dqm); 2321 out_deallocate_doorbell: 2322 deallocate_doorbell(qpd, q); 2323 out_deallocate_sdma_queue: 2324 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 2325 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 2326 dqm_lock(dqm); 2327 deallocate_sdma_queue(dqm, q); 2328 dqm_unlock(dqm); 2329 } 2330 out: 2331 return retval; 2332 } 2333 2334 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, 2335 uint64_t fence_value, 2336 unsigned int timeout_ms) 2337 { 2338 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; 2339 struct device *dev = dqm->dev->adev->dev; 2340 uint64_t *fence_addr = dqm->fence_addr; 2341 2342 while (*fence_addr != fence_value) { 2343 /* Fatal err detected, this response won't come */ 2344 if (amdgpu_amdkfd_is_fed(dqm->dev->adev) || 2345 amdgpu_in_reset(dqm->dev->adev)) 2346 return -EIO; 2347 2348 if (time_after(jiffies, end_jiffies)) { 2349 dev_err(dev, "qcm fence wait loop timeout expired\n"); 2350 /* In HWS case, this is used to halt the driver thread 2351 * in order not to mess up CP states before doing 2352 * scandumps for FW debugging. 2353 */ 2354 while (halt_if_hws_hang) 2355 schedule(); 2356 2357 return -ETIME; 2358 } 2359 schedule(); 2360 } 2361 2362 return 0; 2363 } 2364 2365 /* dqm->lock mutex has to be locked before calling this function */ 2366 static int map_queues_cpsch(struct device_queue_manager *dqm) 2367 { 2368 struct device *dev = dqm->dev->adev->dev; 2369 int retval; 2370 2371 if (!dqm->sched_running || dqm->sched_halt) 2372 return 0; 2373 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0) 2374 return 0; 2375 if (dqm->active_runlist) 2376 return 0; 2377 2378 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues); 2379 pr_debug("%s sent runlist\n", __func__); 2380 if (retval) { 2381 dev_err(dev, "failed to execute runlist\n"); 2382 return retval; 2383 } 2384 dqm->active_runlist = true; 2385 2386 return retval; 2387 } 2388 2389 static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q, 2390 struct qcm_process_device *qpd) 2391 { 2392 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 2393 2394 dev_err(dqm->dev->adev->dev, "queue id 0x%0x at pasid %d is reset\n", 2395 q->properties.queue_id, pdd->process->lead_thread->pid); 2396 2397 pdd->has_reset_queue = true; 2398 q->properties.is_reset = true; 2399 if (q->properties.is_active) { 2400 q->properties.is_active = false; 2401 decrement_queue_count(dqm, qpd, q); 2402 } 2403 } 2404 2405 static int detect_queue_hang(struct device_queue_manager *dqm) 2406 { 2407 int i; 2408 2409 /* detect should be used only in dqm locked queue reset */ 2410 if (WARN_ON(dqm->detect_hang_count > 0)) 2411 return 0; 2412 2413 memset(dqm->detect_hang_info, 0, dqm->detect_hang_info_size); 2414 2415 for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) { 2416 uint32_t mec, pipe, queue; 2417 int xcc_id; 2418 2419 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) 2420 / dqm->dev->kfd->shared_resources.num_pipe_per_mec; 2421 2422 if (mec || !test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 2423 continue; 2424 2425 amdgpu_queue_mask_bit_to_mec_queue(dqm->dev->adev, i, &mec, &pipe, &queue); 2426 2427 for_each_inst(xcc_id, dqm->dev->xcc_mask) { 2428 uint64_t queue_addr = dqm->dev->kfd2kgd->hqd_get_pq_addr( 2429 dqm->dev->adev, pipe, queue, xcc_id); 2430 struct dqm_detect_hang_info hang_info; 2431 2432 if (!queue_addr) 2433 continue; 2434 2435 hang_info.pipe_id = pipe; 2436 hang_info.queue_id = queue; 2437 hang_info.xcc_id = xcc_id; 2438 hang_info.queue_address = queue_addr; 2439 2440 dqm->detect_hang_info[dqm->detect_hang_count] = hang_info; 2441 dqm->detect_hang_count++; 2442 } 2443 } 2444 2445 return dqm->detect_hang_count; 2446 } 2447 2448 static struct queue *find_queue_by_address(struct device_queue_manager *dqm, uint64_t queue_address) 2449 { 2450 struct device_process_node *cur; 2451 struct qcm_process_device *qpd; 2452 struct queue *q; 2453 2454 list_for_each_entry(cur, &dqm->queues, list) { 2455 qpd = cur->qpd; 2456 list_for_each_entry(q, &qpd->queues_list, list) { 2457 if (queue_address == q->properties.queue_address) 2458 return q; 2459 } 2460 } 2461 2462 return NULL; 2463 } 2464 2465 static struct queue *find_queue_by_doorbell_offset(struct device_queue_manager *dqm, u32 doorbell_offset) 2466 { 2467 struct device_process_node *cur; 2468 struct qcm_process_device *qpd; 2469 struct queue *q; 2470 2471 list_for_each_entry(cur, &dqm->queues, list) { 2472 qpd = cur->qpd; 2473 list_for_each_entry(q, &qpd->queues_list, list) { 2474 if (doorbell_offset == q->properties.doorbell_off) 2475 return q; 2476 } 2477 } 2478 2479 return NULL; 2480 } 2481 2482 static int reset_hung_queues(struct device_queue_manager *dqm) 2483 { 2484 int r = 0, reset_count = 0, i; 2485 2486 if (!dqm->detect_hang_info || dqm->is_hws_hang) 2487 return -EIO; 2488 2489 /* assume dqm locked. */ 2490 if (!detect_queue_hang(dqm)) 2491 return -ENOTRECOVERABLE; 2492 2493 for (i = 0; i < dqm->detect_hang_count; i++) { 2494 struct dqm_detect_hang_info hang_info = dqm->detect_hang_info[i]; 2495 struct queue *q = find_queue_by_address(dqm, hang_info.queue_address); 2496 struct kfd_process_device *pdd; 2497 uint64_t queue_addr = 0; 2498 2499 if (!q) { 2500 r = -ENOTRECOVERABLE; 2501 goto reset_fail; 2502 } 2503 2504 pdd = kfd_get_process_device_data(dqm->dev, q->process); 2505 if (!pdd) { 2506 r = -ENOTRECOVERABLE; 2507 goto reset_fail; 2508 } 2509 2510 queue_addr = dqm->dev->kfd2kgd->hqd_reset(dqm->dev->adev, 2511 hang_info.pipe_id, hang_info.queue_id, hang_info.xcc_id, 2512 KFD_UNMAP_LATENCY_MS); 2513 2514 /* either reset failed or we reset an unexpected queue. */ 2515 if (queue_addr != q->properties.queue_address) { 2516 r = -ENOTRECOVERABLE; 2517 goto reset_fail; 2518 } 2519 2520 set_queue_as_reset(dqm, q, &pdd->qpd); 2521 reset_count++; 2522 } 2523 2524 if (reset_count == dqm->detect_hang_count) 2525 kfd_signal_reset_event(dqm->dev); 2526 else 2527 r = -ENOTRECOVERABLE; 2528 2529 reset_fail: 2530 dqm->detect_hang_count = 0; 2531 2532 return r; 2533 } 2534 2535 static bool sdma_has_hang(struct device_queue_manager *dqm) 2536 { 2537 int engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 2538 int engine_end = engine_start + get_num_all_sdma_engines(dqm); 2539 int num_queues_per_eng = dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 2540 int i, j; 2541 2542 for (i = engine_start; i < engine_end; i++) { 2543 for (j = 0; j < num_queues_per_eng; j++) { 2544 if (!dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j)) 2545 continue; 2546 2547 return true; 2548 } 2549 } 2550 2551 return false; 2552 } 2553 2554 static bool set_sdma_queue_as_reset(struct device_queue_manager *dqm, 2555 uint32_t doorbell_off) 2556 { 2557 struct device_process_node *cur; 2558 struct qcm_process_device *qpd; 2559 struct queue *q; 2560 2561 list_for_each_entry(cur, &dqm->queues, list) { 2562 qpd = cur->qpd; 2563 list_for_each_entry(q, &qpd->queues_list, list) { 2564 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA || 2565 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) && 2566 q->properties.doorbell_off == doorbell_off) { 2567 set_queue_as_reset(dqm, q, qpd); 2568 return true; 2569 } 2570 } 2571 } 2572 2573 return false; 2574 } 2575 2576 static int reset_hung_queues_sdma(struct device_queue_manager *dqm) 2577 { 2578 int engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 2579 int engine_end = engine_start + get_num_all_sdma_engines(dqm); 2580 int num_queues_per_eng = dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 2581 int r = 0, i, j; 2582 2583 if (dqm->is_hws_hang) 2584 return -EIO; 2585 2586 /* Scan for hung HW queues and reset engine. */ 2587 dqm->detect_hang_count = 0; 2588 for (i = engine_start; i < engine_end; i++) { 2589 for (j = 0; j < num_queues_per_eng; j++) { 2590 uint32_t doorbell_off = 2591 dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j); 2592 2593 if (!doorbell_off) 2594 continue; 2595 2596 /* Reset engine and check. */ 2597 if (amdgpu_sdma_reset_engine(dqm->dev->adev, i, false) || 2598 dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j) || 2599 !set_sdma_queue_as_reset(dqm, doorbell_off)) { 2600 r = -ENOTRECOVERABLE; 2601 goto reset_fail; 2602 } 2603 2604 /* Should only expect one queue active per engine */ 2605 dqm->detect_hang_count++; 2606 break; 2607 } 2608 } 2609 2610 /* Signal process reset */ 2611 if (dqm->detect_hang_count) 2612 kfd_signal_reset_event(dqm->dev); 2613 else 2614 r = -ENOTRECOVERABLE; 2615 2616 reset_fail: 2617 dqm->detect_hang_count = 0; 2618 2619 return r; 2620 } 2621 2622 static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma) 2623 { 2624 struct amdgpu_device *adev = dqm->dev->adev; 2625 2626 while (halt_if_hws_hang) 2627 schedule(); 2628 2629 if (adev->debug_disable_gpu_ring_reset) { 2630 dev_info_once(adev->dev, 2631 "%s queue hung, but ring reset disabled", 2632 is_sdma ? "sdma" : "compute"); 2633 2634 return -EPERM; 2635 } 2636 if (!amdgpu_gpu_recovery) 2637 return -ENOTRECOVERABLE; 2638 2639 return is_sdma ? reset_hung_queues_sdma(dqm) : reset_hung_queues(dqm); 2640 } 2641 2642 /* dqm->lock mutex has to be locked before calling this function 2643 * 2644 * @grace_period: If USE_DEFAULT_GRACE_PERIOD then default wait time 2645 * for context switch latency. Lower values are used by debugger 2646 * since context switching are triggered at high frequency. 2647 * This is configured by setting CP_IQ_WAIT_TIME2.SCH_WAVE 2648 * 2649 */ 2650 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 2651 enum kfd_unmap_queues_filter filter, 2652 uint32_t filter_param, 2653 uint32_t grace_period, 2654 bool reset) 2655 { 2656 struct device *dev = dqm->dev->adev->dev; 2657 struct mqd_manager *mqd_mgr; 2658 int retval; 2659 2660 if (!dqm->sched_running) 2661 return 0; 2662 if (!dqm->active_runlist) 2663 return 0; 2664 if (!down_read_trylock(&dqm->dev->adev->reset_domain->sem)) 2665 return -EIO; 2666 2667 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 2668 retval = pm_config_dequeue_wait_counts(&dqm->packet_mgr, 2669 KFD_DEQUEUE_WAIT_SET_SCH_WAVE, grace_period); 2670 if (retval) 2671 goto out; 2672 } 2673 2674 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset); 2675 if (retval) 2676 goto out; 2677 2678 *dqm->fence_addr = KFD_FENCE_INIT; 2679 mb(); 2680 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, 2681 KFD_FENCE_COMPLETED); 2682 /* should be timed out */ 2683 retval = amdkfd_fence_wait_timeout(dqm, KFD_FENCE_COMPLETED, 2684 queue_preemption_timeout_ms); 2685 if (retval) { 2686 dev_err(dev, "The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n"); 2687 kfd_hws_hang(dqm); 2688 goto out; 2689 } 2690 2691 /* In the current MEC firmware implementation, if compute queue 2692 * doesn't response to the preemption request in time, HIQ will 2693 * abandon the unmap request without returning any timeout error 2694 * to driver. Instead, MEC firmware will log the doorbell of the 2695 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields. 2696 * To make sure the queue unmap was successful, driver need to 2697 * check those fields 2698 */ 2699 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; 2700 if (mqd_mgr->check_preemption_failed(mqd_mgr, dqm->packet_mgr.priv_queue->queue->mqd) && 2701 reset_queues_on_hws_hang(dqm, false)) 2702 goto reset_fail; 2703 2704 /* Check for SDMA hang and attempt SDMA reset */ 2705 if (sdma_has_hang(dqm) && reset_queues_on_hws_hang(dqm, true)) 2706 goto reset_fail; 2707 2708 /* We need to reset the grace period value for this device */ 2709 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 2710 if (pm_config_dequeue_wait_counts(&dqm->packet_mgr, 2711 KFD_DEQUEUE_WAIT_RESET, 0 /* unused */)) 2712 dev_err(dev, "Failed to reset grace period\n"); 2713 } 2714 2715 pm_release_ib(&dqm->packet_mgr); 2716 dqm->active_runlist = false; 2717 out: 2718 up_read(&dqm->dev->adev->reset_domain->sem); 2719 return retval; 2720 2721 reset_fail: 2722 dqm->is_hws_hang = true; 2723 kfd_hws_hang(dqm); 2724 up_read(&dqm->dev->adev->reset_domain->sem); 2725 return -ETIME; 2726 } 2727 2728 /* only for compute queue */ 2729 static int reset_queues_cpsch(struct device_queue_manager *dqm, uint16_t pasid) 2730 { 2731 int retval; 2732 2733 dqm_lock(dqm); 2734 2735 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID, 2736 pasid, USE_DEFAULT_GRACE_PERIOD, true); 2737 2738 dqm_unlock(dqm); 2739 return retval; 2740 } 2741 2742 /* dqm->lock mutex has to be locked before calling this function */ 2743 static int execute_queues_cpsch(struct device_queue_manager *dqm, 2744 enum kfd_unmap_queues_filter filter, 2745 uint32_t filter_param, 2746 uint32_t grace_period) 2747 { 2748 int retval; 2749 2750 if (!down_read_trylock(&dqm->dev->adev->reset_domain->sem)) 2751 return -EIO; 2752 retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false); 2753 if (!retval) 2754 retval = map_queues_cpsch(dqm); 2755 up_read(&dqm->dev->adev->reset_domain->sem); 2756 return retval; 2757 } 2758 2759 static int wait_on_destroy_queue(struct device_queue_manager *dqm, 2760 struct queue *q) 2761 { 2762 struct kfd_process_device *pdd = kfd_get_process_device_data(q->device, 2763 q->process); 2764 int ret = 0; 2765 2766 if (WARN_ON(!pdd)) 2767 return ret; 2768 2769 if (pdd->qpd.is_debug) 2770 return ret; 2771 2772 if (q->properties.is_being_destroyed) 2773 return -EBUSY; 2774 2775 q->properties.is_being_destroyed = true; 2776 2777 if (pdd->process->debug_trap_enabled && q->properties.is_suspended) { 2778 dqm_unlock(dqm); 2779 mutex_unlock(&q->process->mutex); 2780 ret = wait_event_interruptible(dqm->destroy_wait, 2781 !q->properties.is_suspended); 2782 2783 mutex_lock(&q->process->mutex); 2784 dqm_lock(dqm); 2785 } 2786 2787 if (ret) 2788 q->properties.is_being_destroyed = false; 2789 2790 return ret; 2791 } 2792 2793 static int destroy_queue_cpsch(struct device_queue_manager *dqm, 2794 struct qcm_process_device *qpd, 2795 struct queue *q) 2796 { 2797 int retval; 2798 struct mqd_manager *mqd_mgr; 2799 uint64_t sdma_val = 0; 2800 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 2801 struct device *dev = dqm->dev->adev->dev; 2802 2803 /* Get the SDMA queue stats */ 2804 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 2805 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 2806 if (dqm->dev->kfd2kgd->hqd_sdma_get_counter) 2807 retval = dqm->dev->kfd2kgd->hqd_sdma_get_counter( 2808 dqm->dev->adev, q->mqd, 2809 dqm->dev->kfd->device_info.num_sdma_queues_per_engine, 2810 &sdma_val); 2811 else 2812 retval = read_sdma_queue_counter( 2813 (uint64_t __user *)q->properties.read_ptr, 2814 &sdma_val); 2815 2816 if (retval) 2817 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n", 2818 q->properties.queue_id); 2819 } 2820 2821 /* remove queue from list to prevent rescheduling after preemption */ 2822 dqm_lock(dqm); 2823 2824 retval = wait_on_destroy_queue(dqm, q); 2825 2826 if (retval) { 2827 dqm_unlock(dqm); 2828 return retval; 2829 } 2830 2831 if (qpd->is_debug) { 2832 /* 2833 * error, currently we do not allow to destroy a queue 2834 * of a currently debugged process 2835 */ 2836 retval = -EBUSY; 2837 goto failed_try_destroy_debugged_queue; 2838 2839 } 2840 2841 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2842 q->properties.type)]; 2843 2844 deallocate_doorbell(qpd, q); 2845 2846 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 2847 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 2848 deallocate_sdma_queue(dqm, q); 2849 pdd->sdma_past_activity_counter += sdma_val; 2850 } 2851 2852 if (q->properties.is_active) { 2853 decrement_queue_count(dqm, qpd, q); 2854 q->properties.is_active = false; 2855 if (!dqm->dev->kfd->shared_resources.enable_mes) { 2856 retval = execute_queues_cpsch(dqm, 2857 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 2858 USE_DEFAULT_GRACE_PERIOD); 2859 if (retval == -ETIME) 2860 qpd->reset_wavefronts = true; 2861 } else { 2862 retval = remove_queue_mes(dqm, q, qpd); 2863 } 2864 } 2865 list_del(&q->list); 2866 qpd->queue_count--; 2867 2868 /* 2869 * Unconditionally decrement this counter, regardless of the queue's 2870 * type 2871 */ 2872 dqm->total_queue_count--; 2873 pr_debug("Total of %d queues are accountable so far\n", 2874 dqm->total_queue_count); 2875 2876 dqm_unlock(dqm); 2877 2878 /* 2879 * Do free_mqd and raise delete event after dqm_unlock(dqm) to avoid 2880 * circular locking 2881 */ 2882 kfd_dbg_ev_raise(KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE), 2883 qpd->pqm->process, q->device, 2884 -1, false, NULL, 0); 2885 2886 /* Repin the MQD BO if still evicted for hibernation, before it is freed. */ 2887 dqm_repin_mqd_bo(dqm, q); 2888 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2889 2890 return retval; 2891 2892 failed_try_destroy_debugged_queue: 2893 q->properties.is_being_destroyed = false; 2894 dqm_unlock(dqm); 2895 return retval; 2896 } 2897 2898 static bool set_cache_memory_policy(struct device_queue_manager *dqm, 2899 struct qcm_process_device *qpd, 2900 enum cache_policy default_policy, 2901 enum cache_policy alternate_policy, 2902 void __user *alternate_aperture_base, 2903 uint64_t alternate_aperture_size, 2904 u32 misc_process_properties) 2905 { 2906 bool retval = true; 2907 2908 if (!dqm->asic_ops.set_cache_memory_policy) 2909 return retval; 2910 2911 dqm_lock(dqm); 2912 2913 retval = dqm->asic_ops.set_cache_memory_policy( 2914 dqm, 2915 qpd, 2916 default_policy, 2917 alternate_policy, 2918 alternate_aperture_base, 2919 alternate_aperture_size, 2920 misc_process_properties); 2921 2922 if (retval) 2923 goto out; 2924 2925 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) 2926 program_sh_mem_settings(dqm, qpd); 2927 2928 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", 2929 qpd->sh_mem_config, qpd->sh_mem_ape1_base, 2930 qpd->sh_mem_ape1_limit); 2931 2932 out: 2933 dqm_unlock(dqm); 2934 return retval; 2935 } 2936 2937 static int process_termination_nocpsch(struct device_queue_manager *dqm, 2938 struct qcm_process_device *qpd) 2939 { 2940 struct queue *q; 2941 struct device_process_node *cur, *next_dpn; 2942 int retval = 0; 2943 bool found = false; 2944 2945 dqm_lock(dqm); 2946 2947 /* Clear all user mode queues */ 2948 while (!list_empty(&qpd->queues_list)) { 2949 struct mqd_manager *mqd_mgr; 2950 int ret; 2951 2952 q = list_first_entry(&qpd->queues_list, struct queue, list); 2953 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2954 q->properties.type)]; 2955 ret = destroy_queue_nocpsch_locked(dqm, qpd, q); 2956 if (ret) 2957 retval = ret; 2958 dqm_unlock(dqm); 2959 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2960 dqm_lock(dqm); 2961 } 2962 2963 /* Unregister process */ 2964 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 2965 if (qpd == cur->qpd) { 2966 list_del(&cur->list); 2967 kfree(cur); 2968 dqm->processes_count--; 2969 found = true; 2970 break; 2971 } 2972 } 2973 2974 dqm_unlock(dqm); 2975 2976 /* Outside the DQM lock because under the DQM lock we can't do 2977 * reclaim or take other locks that others hold while reclaiming. 2978 */ 2979 if (found) 2980 kfd_dec_compute_active(dqm->dev); 2981 2982 return retval; 2983 } 2984 2985 static int get_wave_state(struct device_queue_manager *dqm, 2986 struct queue *q, 2987 void __user *ctl_stack, 2988 u32 *ctl_stack_used_size, 2989 u32 *save_area_used_size) 2990 { 2991 struct mqd_manager *mqd_mgr; 2992 2993 dqm_lock(dqm); 2994 2995 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 2996 2997 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || 2998 q->properties.is_active || !q->device->kfd->cwsr_enabled || 2999 !mqd_mgr->get_wave_state) { 3000 dqm_unlock(dqm); 3001 return -EINVAL; 3002 } 3003 3004 dqm_unlock(dqm); 3005 3006 /* 3007 * get_wave_state is outside the dqm lock to prevent circular locking 3008 * and the queue should be protected against destruction by the process 3009 * lock. 3010 */ 3011 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, &q->properties, 3012 ctl_stack, ctl_stack_used_size, save_area_used_size); 3013 } 3014 3015 static int get_queue_checkpoint_info(struct device_queue_manager *dqm, 3016 const struct queue *q, 3017 u32 *mqd_size, 3018 u32 *ctl_stack_size) 3019 { 3020 struct mqd_manager *mqd_mgr; 3021 enum KFD_MQD_TYPE mqd_type = 3022 get_mqd_type_from_queue_type(q->properties.type); 3023 int ret = 0; 3024 3025 dqm_lock(dqm); 3026 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 3027 *mqd_size = mqd_mgr->mqd_size * NUM_XCC(mqd_mgr->dev->xcc_mask); 3028 *ctl_stack_size = 0; 3029 3030 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info) 3031 ret = mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size); 3032 3033 dqm_unlock(dqm); 3034 3035 return ret; 3036 } 3037 3038 static int checkpoint_mqd(struct device_queue_manager *dqm, 3039 const struct queue *q, 3040 void *mqd, 3041 void *ctl_stack) 3042 { 3043 struct mqd_manager *mqd_mgr; 3044 int r = 0; 3045 enum KFD_MQD_TYPE mqd_type = 3046 get_mqd_type_from_queue_type(q->properties.type); 3047 3048 dqm_lock(dqm); 3049 3050 if (q->properties.is_active || !q->device->kfd->cwsr_enabled) { 3051 r = -EINVAL; 3052 goto dqm_unlock; 3053 } 3054 3055 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 3056 if (!mqd_mgr->checkpoint_mqd) { 3057 r = -EOPNOTSUPP; 3058 goto dqm_unlock; 3059 } 3060 3061 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack); 3062 3063 dqm_unlock: 3064 dqm_unlock(dqm); 3065 return r; 3066 } 3067 3068 static int process_termination_cpsch(struct device_queue_manager *dqm, 3069 struct qcm_process_device *qpd) 3070 { 3071 int retval = 0; 3072 struct queue *q; 3073 struct device *dev = dqm->dev->adev->dev; 3074 struct kernel_queue *kq, *kq_next; 3075 struct mqd_manager *mqd_mgr; 3076 struct device_process_node *cur, *next_dpn; 3077 enum kfd_unmap_queues_filter filter = 3078 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; 3079 bool found = false; 3080 3081 dqm_lock(dqm); 3082 3083 /* Clean all kernel queues */ 3084 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) { 3085 list_del(&kq->list); 3086 decrement_queue_count(dqm, qpd, kq->queue); 3087 qpd->is_debug = false; 3088 dqm->total_queue_count--; 3089 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES; 3090 } 3091 3092 /* Clear all user mode queues */ 3093 list_for_each_entry(q, &qpd->queues_list, list) { 3094 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 3095 deallocate_sdma_queue(dqm, q); 3096 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 3097 deallocate_sdma_queue(dqm, q); 3098 3099 if (q->properties.is_active) { 3100 decrement_queue_count(dqm, qpd, q); 3101 3102 if (dqm->dev->kfd->shared_resources.enable_mes) { 3103 retval = remove_queue_mes(dqm, q, qpd); 3104 if (retval) 3105 dev_err(dev, "Failed to remove queue %d\n", 3106 q->properties.queue_id); 3107 } 3108 } 3109 3110 dqm->total_queue_count--; 3111 } 3112 3113 /* Unregister process */ 3114 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 3115 if (qpd == cur->qpd) { 3116 list_del(&cur->list); 3117 kfree(cur); 3118 dqm->processes_count--; 3119 found = true; 3120 break; 3121 } 3122 } 3123 3124 if (!dqm->dev->kfd->shared_resources.enable_mes) 3125 retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD); 3126 3127 if ((retval || qpd->reset_wavefronts) && 3128 down_read_trylock(&dqm->dev->adev->reset_domain->sem)) { 3129 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev); 3130 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process); 3131 qpd->reset_wavefronts = false; 3132 up_read(&dqm->dev->adev->reset_domain->sem); 3133 } 3134 3135 /* Lastly, free mqd resources. 3136 * Do free_mqd() after dqm_unlock to avoid circular locking. 3137 */ 3138 while (!list_empty(&qpd->queues_list)) { 3139 q = list_first_entry(&qpd->queues_list, struct queue, list); 3140 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 3141 q->properties.type)]; 3142 list_del(&q->list); 3143 qpd->queue_count--; 3144 dqm_unlock(dqm); 3145 /* Repin the MQD BO if still evicted for hibernation, before free. */ 3146 dqm_repin_mqd_bo(dqm, q); 3147 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 3148 dqm_lock(dqm); 3149 } 3150 dqm_unlock(dqm); 3151 3152 /* Outside the DQM lock because under the DQM lock we can't do 3153 * reclaim or take other locks that others hold while reclaiming. 3154 */ 3155 if (found) 3156 kfd_dec_compute_active(dqm->dev); 3157 3158 return retval; 3159 } 3160 3161 static int init_mqd_managers(struct device_queue_manager *dqm) 3162 { 3163 int i, j; 3164 struct device *dev = dqm->dev->adev->dev; 3165 struct mqd_manager *mqd_mgr; 3166 3167 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) { 3168 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev); 3169 if (!mqd_mgr) { 3170 dev_err(dev, "mqd manager [%d] initialization failed\n", i); 3171 goto out_free; 3172 } 3173 dqm->mqd_mgrs[i] = mqd_mgr; 3174 } 3175 3176 return 0; 3177 3178 out_free: 3179 for (j = 0; j < i; j++) { 3180 kfree(dqm->mqd_mgrs[j]); 3181 dqm->mqd_mgrs[j] = NULL; 3182 } 3183 3184 return -ENOMEM; 3185 } 3186 3187 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/ 3188 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) 3189 { 3190 int retval; 3191 struct kfd_node *dev = dqm->dev; 3192 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd; 3193 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * 3194 get_num_all_sdma_engines(dqm) * 3195 dev->kfd->device_info.num_sdma_queues_per_engine + 3196 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size * 3197 NUM_XCC(dqm->dev->xcc_mask)); 3198 3199 retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, size, 3200 AMDGPU_GEM_DOMAIN_GTT, 3201 &(mem_obj->mem), &(mem_obj->gpu_addr), 3202 (void *)&(mem_obj->cpu_ptr), false); 3203 3204 return retval; 3205 } 3206 3207 static void deallocate_hiq_sdma_mqd(struct kfd_node *dev, 3208 struct kfd_mem_obj *mqd) 3209 { 3210 WARN(!mqd, "No hiq sdma mqd trunk to free"); 3211 3212 amdgpu_amdkfd_free_kernel_mem(dev->adev, &mqd->mem); 3213 } 3214 3215 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) 3216 { 3217 struct device_queue_manager *dqm; 3218 int i; 3219 3220 pr_debug("Loading device queue manager\n"); 3221 3222 dqm = kzalloc_obj(*dqm); 3223 if (!dqm) 3224 return NULL; 3225 3226 switch (dev->adev->asic_type) { 3227 /* HWS is not available on Hawaii. */ 3228 case CHIP_HAWAII: 3229 /* HWS depends on CWSR for timely dequeue. CWSR is not 3230 * available on Tonga. 3231 * 3232 * FIXME: This argument also applies to Kaveri. 3233 */ 3234 case CHIP_TONGA: 3235 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS; 3236 break; 3237 default: 3238 dqm->sched_policy = sched_policy; 3239 break; 3240 } 3241 3242 dqm->dev = dev; 3243 switch (dqm->sched_policy) { 3244 case KFD_SCHED_POLICY_HWS: 3245 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: 3246 /* initialize dqm for cp scheduling */ 3247 dqm->ops.create_queue = create_queue_cpsch; 3248 dqm->ops.initialize = initialize_cpsch; 3249 dqm->ops.start = start_cpsch; 3250 dqm->ops.stop = stop_cpsch; 3251 dqm->ops.halt = halt_cpsch; 3252 dqm->ops.unhalt = unhalt_cpsch; 3253 dqm->ops.destroy_queue = destroy_queue_cpsch; 3254 dqm->ops.update_queue = update_queue; 3255 dqm->ops.register_process = register_process; 3256 dqm->ops.unregister_process = unregister_process; 3257 dqm->ops.uninitialize = uninitialize; 3258 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; 3259 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; 3260 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 3261 dqm->ops.process_termination = process_termination_cpsch; 3262 dqm->ops.evict_process_queues = evict_process_queues_cpsch; 3263 dqm->ops.restore_process_queues = restore_process_queues_cpsch; 3264 dqm->ops.get_wave_state = get_wave_state; 3265 dqm->ops.reset_queues = reset_queues_cpsch; 3266 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 3267 dqm->ops.checkpoint_mqd = checkpoint_mqd; 3268 dqm->ops.set_perfcount = set_perfcount; 3269 break; 3270 case KFD_SCHED_POLICY_NO_HWS: 3271 /* initialize dqm for no cp scheduling */ 3272 dqm->ops.start = start_nocpsch; 3273 dqm->ops.stop = stop_nocpsch; 3274 dqm->ops.create_queue = create_queue_nocpsch; 3275 dqm->ops.destroy_queue = destroy_queue_nocpsch; 3276 dqm->ops.update_queue = update_queue; 3277 dqm->ops.register_process = register_process; 3278 dqm->ops.unregister_process = unregister_process; 3279 dqm->ops.initialize = initialize_nocpsch; 3280 dqm->ops.uninitialize = uninitialize; 3281 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 3282 dqm->ops.process_termination = process_termination_nocpsch; 3283 dqm->ops.evict_process_queues = evict_process_queues_nocpsch; 3284 dqm->ops.restore_process_queues = 3285 restore_process_queues_nocpsch; 3286 dqm->ops.get_wave_state = get_wave_state; 3287 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 3288 dqm->ops.checkpoint_mqd = checkpoint_mqd; 3289 dqm->ops.set_perfcount = set_perfcount; 3290 break; 3291 default: 3292 dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); 3293 goto out_free; 3294 } 3295 3296 switch (dev->adev->asic_type) { 3297 case CHIP_KAVERI: 3298 case CHIP_HAWAII: 3299 device_queue_manager_init_cik(&dqm->asic_ops); 3300 break; 3301 3302 case CHIP_CARRIZO: 3303 case CHIP_TONGA: 3304 case CHIP_FIJI: 3305 case CHIP_POLARIS10: 3306 case CHIP_POLARIS11: 3307 case CHIP_POLARIS12: 3308 case CHIP_VEGAM: 3309 device_queue_manager_init_vi(&dqm->asic_ops); 3310 break; 3311 3312 default: 3313 if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 1, 0)) 3314 device_queue_manager_init_v12_1(&dqm->asic_ops); 3315 else if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 0, 0)) 3316 device_queue_manager_init_v12(&dqm->asic_ops); 3317 else if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0)) 3318 device_queue_manager_init_v11(&dqm->asic_ops); 3319 else if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1)) 3320 device_queue_manager_init_v10(&dqm->asic_ops); 3321 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) 3322 device_queue_manager_init_v9(&dqm->asic_ops); 3323 else { 3324 WARN(1, "Unexpected ASIC family %u", 3325 dev->adev->asic_type); 3326 goto out_free; 3327 } 3328 } 3329 3330 if (init_mqd_managers(dqm)) 3331 goto out_free; 3332 3333 if (!dev->kfd->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) { 3334 dev_err(dev->adev->dev, "Failed to allocate hiq sdma mqd trunk buffer\n"); 3335 goto out_free; 3336 } 3337 3338 if (!dqm->ops.initialize(dqm)) { 3339 init_waitqueue_head(&dqm->destroy_wait); 3340 return dqm; 3341 } 3342 3343 if (!dev->kfd->shared_resources.enable_mes) 3344 deallocate_hiq_sdma_mqd(dev, &dqm->hiq_sdma_mqd); 3345 3346 out_free: 3347 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) 3348 kfree(dqm->mqd_mgrs[i]); 3349 3350 kfree(dqm); 3351 return NULL; 3352 } 3353 3354 void device_queue_manager_uninit(struct device_queue_manager *dqm) 3355 { 3356 dqm->ops.stop(dqm); 3357 dqm->ops.uninitialize(dqm); 3358 if (!dqm->dev->kfd->shared_resources.enable_mes) 3359 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd); 3360 kfree(dqm); 3361 } 3362 3363 /* bad queue notified by interrupt from CP */ 3364 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id) 3365 { 3366 struct kfd_process_device *pdd = NULL; 3367 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, &pdd); 3368 struct device_queue_manager *dqm = knode->dqm; 3369 struct qcm_process_device *qpd; 3370 struct queue *q = NULL; 3371 int ret = 0; 3372 3373 if (!pdd) 3374 return -EINVAL; 3375 3376 dqm_lock(dqm); 3377 3378 if (pdd) { 3379 qpd = &pdd->qpd; 3380 3381 list_for_each_entry(q, &qpd->queues_list, list) { 3382 if (q->doorbell_id == doorbell_id && q->properties.is_active) { 3383 reset_queues_mes(dqm, q); 3384 q->properties.is_evicted = true; 3385 q->properties.is_active = false; 3386 decrement_queue_count(dqm, qpd, q); 3387 break; 3388 } 3389 } 3390 } 3391 3392 dqm_unlock(dqm); 3393 kfd_unref_process(p); 3394 return ret; 3395 } 3396 3397 int kfd_evict_process_device(struct kfd_process_device *pdd) 3398 { 3399 struct device_queue_manager *dqm; 3400 struct kfd_process *p; 3401 3402 p = pdd->process; 3403 dqm = pdd->dev->dqm; 3404 3405 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 3406 3407 return dqm->ops.evict_process_queues(dqm, &pdd->qpd); 3408 } 3409 3410 int reserve_debug_trap_vmid(struct device_queue_manager *dqm, 3411 struct qcm_process_device *qpd) 3412 { 3413 int r; 3414 struct device *dev = dqm->dev->adev->dev; 3415 int updated_vmid_mask; 3416 3417 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3418 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3419 return -EINVAL; 3420 } 3421 3422 dqm_lock(dqm); 3423 3424 if (dqm->trap_debug_vmid != 0) { 3425 dev_err(dev, "Trap debug id already reserved\n"); 3426 r = -EBUSY; 3427 goto out_unlock; 3428 } 3429 3430 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 3431 USE_DEFAULT_GRACE_PERIOD, false); 3432 if (r) 3433 goto out_unlock; 3434 3435 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap; 3436 updated_vmid_mask &= ~(1 << dqm->dev->vm_info.last_vmid_kfd); 3437 3438 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask; 3439 dqm->trap_debug_vmid = dqm->dev->vm_info.last_vmid_kfd; 3440 r = set_sched_resources(dqm); 3441 if (r) 3442 goto out_unlock; 3443 3444 r = map_queues_cpsch(dqm); 3445 if (r) 3446 goto out_unlock; 3447 3448 pr_debug("Reserved VMID for trap debug: %i\n", dqm->trap_debug_vmid); 3449 3450 out_unlock: 3451 dqm_unlock(dqm); 3452 return r; 3453 } 3454 3455 /* 3456 * Releases vmid for the trap debugger 3457 */ 3458 int release_debug_trap_vmid(struct device_queue_manager *dqm, 3459 struct qcm_process_device *qpd) 3460 { 3461 struct device *dev = dqm->dev->adev->dev; 3462 int r; 3463 int updated_vmid_mask; 3464 uint32_t trap_debug_vmid; 3465 3466 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3467 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3468 return -EINVAL; 3469 } 3470 3471 dqm_lock(dqm); 3472 trap_debug_vmid = dqm->trap_debug_vmid; 3473 if (dqm->trap_debug_vmid == 0) { 3474 dev_err(dev, "Trap debug id is not reserved\n"); 3475 r = -EINVAL; 3476 goto out_unlock; 3477 } 3478 3479 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 3480 USE_DEFAULT_GRACE_PERIOD, false); 3481 if (r) 3482 goto out_unlock; 3483 3484 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap; 3485 updated_vmid_mask |= (1 << dqm->dev->vm_info.last_vmid_kfd); 3486 3487 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask; 3488 dqm->trap_debug_vmid = 0; 3489 r = set_sched_resources(dqm); 3490 if (r) 3491 goto out_unlock; 3492 3493 r = map_queues_cpsch(dqm); 3494 if (r) 3495 goto out_unlock; 3496 3497 pr_debug("Released VMID for trap debug: %i\n", trap_debug_vmid); 3498 3499 out_unlock: 3500 dqm_unlock(dqm); 3501 return r; 3502 } 3503 3504 #define QUEUE_NOT_FOUND -1 3505 /* invalidate queue operation in array */ 3506 static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids) 3507 { 3508 int i; 3509 3510 for (i = 0; i < num_queues; i++) 3511 queue_ids[i] |= KFD_DBG_QUEUE_INVALID_MASK; 3512 } 3513 3514 /* find queue index in array */ 3515 static int q_array_get_index(unsigned int queue_id, 3516 uint32_t num_queues, 3517 uint32_t *queue_ids) 3518 { 3519 int i; 3520 3521 for (i = 0; i < num_queues; i++) 3522 if (queue_id == (queue_ids[i] & ~KFD_DBG_QUEUE_INVALID_MASK)) 3523 return i; 3524 3525 return QUEUE_NOT_FOUND; 3526 } 3527 3528 struct copy_context_work_handler_workarea { 3529 struct work_struct copy_context_work; 3530 struct kfd_process *p; 3531 }; 3532 3533 static void copy_context_work_handler(struct work_struct *work) 3534 { 3535 struct copy_context_work_handler_workarea *workarea; 3536 struct mqd_manager *mqd_mgr; 3537 struct queue *q; 3538 struct mm_struct *mm; 3539 struct kfd_process *p; 3540 uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size; 3541 int i; 3542 3543 workarea = container_of(work, 3544 struct copy_context_work_handler_workarea, 3545 copy_context_work); 3546 3547 p = workarea->p; 3548 mm = get_task_mm(p->lead_thread); 3549 3550 if (!mm) 3551 return; 3552 3553 kthread_use_mm(mm); 3554 for (i = 0; i < p->n_pdds; i++) { 3555 struct kfd_process_device *pdd = p->pdds[i]; 3556 struct device_queue_manager *dqm = pdd->dev->dqm; 3557 struct qcm_process_device *qpd = &pdd->qpd; 3558 3559 list_for_each_entry(q, &qpd->queues_list, list) { 3560 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE) 3561 continue; 3562 3563 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 3564 3565 /* We ignore the return value from get_wave_state 3566 * because 3567 * i) right now, it always returns 0, and 3568 * ii) if we hit an error, we would continue to the 3569 * next queue anyway. 3570 */ 3571 mqd_mgr->get_wave_state(mqd_mgr, 3572 q->mqd, 3573 &q->properties, 3574 (void __user *) q->properties.ctx_save_restore_area_address, 3575 &tmp_ctl_stack_used_size, 3576 &tmp_save_area_used_size); 3577 } 3578 } 3579 kthread_unuse_mm(mm); 3580 mmput(mm); 3581 } 3582 3583 static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array) 3584 { 3585 if (!usr_queue_id_array) 3586 return num_queues ? ERR_PTR(-EINVAL) : NULL; 3587 3588 if (num_queues > KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 3589 return ERR_PTR(-EINVAL); 3590 3591 return memdup_user(usr_queue_id_array, 3592 array_size(num_queues, sizeof(uint32_t))); 3593 } 3594 3595 int resume_queues(struct kfd_process *p, 3596 uint32_t num_queues, 3597 uint32_t *usr_queue_id_array) 3598 { 3599 uint32_t *queue_ids = NULL; 3600 int total_resumed = 0; 3601 int i; 3602 3603 if (usr_queue_id_array) { 3604 queue_ids = get_queue_ids(num_queues, usr_queue_id_array); 3605 3606 if (IS_ERR(queue_ids)) 3607 return PTR_ERR(queue_ids); 3608 3609 /* mask all queues as invalid. unmask per successful request */ 3610 q_array_invalidate(num_queues, queue_ids); 3611 } 3612 3613 for (i = 0; i < p->n_pdds; i++) { 3614 struct kfd_process_device *pdd = p->pdds[i]; 3615 struct device_queue_manager *dqm = pdd->dev->dqm; 3616 struct device *dev = dqm->dev->adev->dev; 3617 struct qcm_process_device *qpd = &pdd->qpd; 3618 struct queue *q; 3619 int r, per_device_resumed = 0; 3620 3621 dqm_lock(dqm); 3622 3623 /* unmask queues that resume or already resumed as valid */ 3624 list_for_each_entry(q, &qpd->queues_list, list) { 3625 int q_idx = QUEUE_NOT_FOUND; 3626 3627 if (queue_ids) 3628 q_idx = q_array_get_index( 3629 q->properties.queue_id, 3630 num_queues, 3631 queue_ids); 3632 3633 if (!queue_ids || q_idx != QUEUE_NOT_FOUND) { 3634 int err = resume_single_queue(dqm, &pdd->qpd, q); 3635 3636 if (queue_ids) { 3637 if (!err) { 3638 queue_ids[q_idx] &= 3639 ~KFD_DBG_QUEUE_INVALID_MASK; 3640 } else { 3641 queue_ids[q_idx] |= 3642 KFD_DBG_QUEUE_ERROR_MASK; 3643 break; 3644 } 3645 } 3646 3647 if (dqm->dev->kfd->shared_resources.enable_mes) { 3648 wake_up_all(&dqm->destroy_wait); 3649 if (!err) 3650 total_resumed++; 3651 } else { 3652 per_device_resumed++; 3653 } 3654 } 3655 } 3656 3657 if (!per_device_resumed) { 3658 dqm_unlock(dqm); 3659 continue; 3660 } 3661 3662 r = execute_queues_cpsch(dqm, 3663 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 3664 0, 3665 USE_DEFAULT_GRACE_PERIOD); 3666 if (r) { 3667 dev_err(dev, "Failed to resume process queues\n"); 3668 if (queue_ids) { 3669 list_for_each_entry(q, &qpd->queues_list, list) { 3670 int q_idx = q_array_get_index( 3671 q->properties.queue_id, 3672 num_queues, 3673 queue_ids); 3674 3675 /* mask queue as error on resume fail */ 3676 if (q_idx != QUEUE_NOT_FOUND) 3677 queue_ids[q_idx] |= 3678 KFD_DBG_QUEUE_ERROR_MASK; 3679 } 3680 } 3681 } else { 3682 wake_up_all(&dqm->destroy_wait); 3683 total_resumed += per_device_resumed; 3684 } 3685 3686 dqm_unlock(dqm); 3687 } 3688 3689 if (queue_ids) { 3690 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids, 3691 num_queues * sizeof(uint32_t))) 3692 pr_err("copy_to_user failed on queue resume\n"); 3693 3694 kfree(queue_ids); 3695 } 3696 3697 return total_resumed; 3698 } 3699 3700 int suspend_queues(struct kfd_process *p, 3701 uint32_t num_queues, 3702 uint32_t grace_period, 3703 uint64_t exception_clear_mask, 3704 uint32_t *usr_queue_id_array) 3705 { 3706 uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array); 3707 int total_suspended = 0; 3708 int i; 3709 3710 if (IS_ERR(queue_ids)) 3711 return PTR_ERR(queue_ids); 3712 3713 /* mask all queues as invalid. umask on successful request */ 3714 q_array_invalidate(num_queues, queue_ids); 3715 3716 for (i = 0; i < p->n_pdds; i++) { 3717 struct kfd_process_device *pdd = p->pdds[i]; 3718 struct device_queue_manager *dqm = pdd->dev->dqm; 3719 struct device *dev = dqm->dev->adev->dev; 3720 struct qcm_process_device *qpd = &pdd->qpd; 3721 struct queue *q; 3722 int r, per_device_suspended = 0; 3723 3724 mutex_lock(&p->event_mutex); 3725 dqm_lock(dqm); 3726 3727 /* unmask queues that suspend or already suspended */ 3728 list_for_each_entry(q, &qpd->queues_list, list) { 3729 int q_idx = q_array_get_index(q->properties.queue_id, 3730 num_queues, 3731 queue_ids); 3732 3733 if (q_idx != QUEUE_NOT_FOUND) { 3734 int err = suspend_single_queue(dqm, pdd, q); 3735 bool is_mes = dqm->dev->kfd->shared_resources.enable_mes; 3736 3737 if (!err) { 3738 queue_ids[q_idx] &= ~KFD_DBG_QUEUE_INVALID_MASK; 3739 if (exception_clear_mask && is_mes) 3740 q->properties.exception_status &= 3741 ~exception_clear_mask; 3742 3743 if (is_mes) 3744 total_suspended++; 3745 else 3746 per_device_suspended++; 3747 } else if (err != -EBUSY) { 3748 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 3749 break; 3750 } 3751 } 3752 } 3753 3754 if (!per_device_suspended) { 3755 dqm_unlock(dqm); 3756 mutex_unlock(&p->event_mutex); 3757 if (total_suspended) { 3758 amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev); 3759 /* Heavy-weight TLB flush after MES suspends queues */ 3760 kfd_flush_tlb(pdd); 3761 } 3762 continue; 3763 } 3764 3765 r = execute_queues_cpsch(dqm, 3766 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 3767 grace_period); 3768 3769 if (r) 3770 dev_err(dev, "Failed to suspend process queues.\n"); 3771 else 3772 total_suspended += per_device_suspended; 3773 3774 list_for_each_entry(q, &qpd->queues_list, list) { 3775 int q_idx = q_array_get_index(q->properties.queue_id, 3776 num_queues, queue_ids); 3777 3778 if (q_idx == QUEUE_NOT_FOUND) 3779 continue; 3780 3781 /* mask queue as error on suspend fail */ 3782 if (r) 3783 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 3784 else if (exception_clear_mask) 3785 q->properties.exception_status &= 3786 ~exception_clear_mask; 3787 } 3788 3789 dqm_unlock(dqm); 3790 mutex_unlock(&p->event_mutex); 3791 amdgpu_device_flush_hdp(dqm->dev->adev, NULL); 3792 } 3793 3794 if (total_suspended) { 3795 struct copy_context_work_handler_workarea copy_context_worker; 3796 3797 INIT_WORK_ONSTACK( 3798 ©_context_worker.copy_context_work, 3799 copy_context_work_handler); 3800 3801 copy_context_worker.p = p; 3802 3803 schedule_work(©_context_worker.copy_context_work); 3804 3805 3806 flush_work(©_context_worker.copy_context_work); 3807 destroy_work_on_stack(©_context_worker.copy_context_work); 3808 } 3809 3810 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids, 3811 num_queues * sizeof(uint32_t))) 3812 pr_err("copy_to_user failed on queue suspend\n"); 3813 3814 kfree(queue_ids); 3815 3816 return total_suspended; 3817 } 3818 3819 static uint32_t set_queue_type_for_user(struct queue_properties *q_props) 3820 { 3821 switch (q_props->type) { 3822 case KFD_QUEUE_TYPE_COMPUTE: 3823 return q_props->format == KFD_QUEUE_FORMAT_PM4 3824 ? KFD_IOC_QUEUE_TYPE_COMPUTE 3825 : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; 3826 case KFD_QUEUE_TYPE_SDMA: 3827 return KFD_IOC_QUEUE_TYPE_SDMA; 3828 case KFD_QUEUE_TYPE_SDMA_XGMI: 3829 return KFD_IOC_QUEUE_TYPE_SDMA_XGMI; 3830 default: 3831 WARN_ONCE(true, "queue type not recognized!"); 3832 return 0xffffffff; 3833 }; 3834 } 3835 3836 void set_queue_snapshot_entry(struct queue *q, 3837 uint64_t exception_clear_mask, 3838 struct kfd_queue_snapshot_entry *qss_entry) 3839 { 3840 qss_entry->ring_base_address = q->properties.queue_address; 3841 qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr; 3842 qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr; 3843 qss_entry->ctx_save_restore_address = 3844 q->properties.ctx_save_restore_area_address; 3845 qss_entry->ctx_save_restore_area_size = 3846 q->properties.ctx_save_restore_area_size; 3847 qss_entry->exception_status = q->properties.exception_status; 3848 qss_entry->queue_id = q->properties.queue_id; 3849 qss_entry->gpu_id = q->device->id; 3850 qss_entry->ring_size = (uint32_t)q->properties.queue_size; 3851 qss_entry->queue_type = set_queue_type_for_user(&q->properties); 3852 q->properties.exception_status &= ~exception_clear_mask; 3853 } 3854 3855 int debug_lock_and_unmap(struct device_queue_manager *dqm) 3856 { 3857 struct device *dev = dqm->dev->adev->dev; 3858 int r; 3859 3860 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3861 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3862 return -EINVAL; 3863 } 3864 3865 if (!kfd_dbg_is_per_vmid_supported(dqm->dev)) 3866 return 0; 3867 3868 dqm_lock(dqm); 3869 3870 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false); 3871 if (r) 3872 dqm_unlock(dqm); 3873 3874 return r; 3875 } 3876 3877 int debug_map_and_unlock(struct device_queue_manager *dqm) 3878 { 3879 struct device *dev = dqm->dev->adev->dev; 3880 int r; 3881 3882 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3883 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy); 3884 return -EINVAL; 3885 } 3886 3887 if (!kfd_dbg_is_per_vmid_supported(dqm->dev)) 3888 return 0; 3889 3890 r = map_queues_cpsch(dqm); 3891 3892 dqm_unlock(dqm); 3893 3894 return r; 3895 } 3896 3897 int debug_refresh_runlist(struct device_queue_manager *dqm) 3898 { 3899 int r = debug_lock_and_unmap(dqm); 3900 3901 if (r) 3902 return r; 3903 3904 return debug_map_and_unlock(dqm); 3905 } 3906 3907 bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, 3908 struct qcm_process_device *qpd, 3909 int doorbell_off, u32 *queue_format) 3910 { 3911 struct queue *q; 3912 bool r = false; 3913 3914 if (!queue_format) 3915 return r; 3916 3917 dqm_lock(dqm); 3918 3919 list_for_each_entry(q, &qpd->queues_list, list) { 3920 if (q->properties.doorbell_off == doorbell_off) { 3921 *queue_format = q->properties.format; 3922 r = true; 3923 goto out; 3924 } 3925 } 3926 3927 out: 3928 dqm_unlock(dqm); 3929 return r; 3930 } 3931 3932 size_t mqd_size_from_queue_type(struct device_queue_manager *dqm, enum kfd_queue_type type) 3933 { 3934 return dqm->mqd_mgrs[get_mqd_type_from_queue_type(type)]->mqd_size; 3935 } 3936 3937 #if defined(CONFIG_DEBUG_FS) 3938 3939 static void seq_reg_dump(struct seq_file *m, 3940 uint32_t (*dump)[2], uint32_t n_regs) 3941 { 3942 uint32_t i, count; 3943 3944 for (i = 0, count = 0; i < n_regs; i++) { 3945 if (count == 0 || 3946 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { 3947 seq_printf(m, "%s %08x: %08x", 3948 i ? "\n" : "", 3949 dump[i][0], dump[i][1]); 3950 count = 7; 3951 } else { 3952 seq_printf(m, " %08x", dump[i][1]); 3953 count--; 3954 } 3955 } 3956 3957 seq_puts(m, "\n"); 3958 } 3959 3960 int dqm_debugfs_hqds(struct seq_file *m, void *data) 3961 { 3962 struct device_queue_manager *dqm = data; 3963 uint32_t xcc_mask = dqm->dev->xcc_mask; 3964 uint32_t (*dump)[2], n_regs; 3965 int pipe, queue; 3966 int r = 0, xcc_id; 3967 uint32_t sdma_engine_start; 3968 3969 if (!dqm->sched_running) { 3970 seq_puts(m, " Device is stopped\n"); 3971 return 0; 3972 } 3973 3974 for_each_inst(xcc_id, xcc_mask) { 3975 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 3976 KFD_CIK_HIQ_PIPE, 3977 KFD_CIK_HIQ_QUEUE, &dump, 3978 &n_regs, xcc_id); 3979 if (!r) { 3980 seq_printf( 3981 m, 3982 " Inst %d, HIQ on MEC %d Pipe %d Queue %d\n", 3983 xcc_id, 3984 KFD_CIK_HIQ_PIPE / get_pipes_per_mec(dqm) + 1, 3985 KFD_CIK_HIQ_PIPE % get_pipes_per_mec(dqm), 3986 KFD_CIK_HIQ_QUEUE); 3987 seq_reg_dump(m, dump, n_regs); 3988 3989 kfree(dump); 3990 } 3991 3992 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 3993 int pipe_offset = pipe * get_queues_per_pipe(dqm); 3994 3995 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) { 3996 if (!test_bit(pipe_offset + queue, 3997 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 3998 continue; 3999 4000 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 4001 pipe, queue, 4002 &dump, &n_regs, 4003 xcc_id); 4004 if (r) 4005 break; 4006 4007 seq_printf(m, 4008 " Inst %d, CP Pipe %d, Queue %d\n", 4009 xcc_id, pipe, queue); 4010 seq_reg_dump(m, dump, n_regs); 4011 4012 kfree(dump); 4013 } 4014 } 4015 } 4016 4017 sdma_engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 4018 for (pipe = sdma_engine_start; 4019 pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm)); 4020 pipe++) { 4021 for (queue = 0; 4022 queue < dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 4023 queue++) { 4024 r = dqm->dev->kfd2kgd->hqd_sdma_dump( 4025 dqm->dev->adev, pipe, queue, &dump, &n_regs); 4026 if (r) 4027 break; 4028 4029 seq_printf(m, " SDMA Engine %d, RLC %d\n", 4030 pipe, queue); 4031 seq_reg_dump(m, dump, n_regs); 4032 4033 kfree(dump); 4034 } 4035 } 4036 4037 return r; 4038 } 4039 4040 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm) 4041 { 4042 int r = 0; 4043 4044 dqm_lock(dqm); 4045 r = pm_debugfs_hang_hws(&dqm->packet_mgr); 4046 if (r) { 4047 dqm_unlock(dqm); 4048 return r; 4049 } 4050 dqm->active_runlist = true; 4051 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 4052 0, USE_DEFAULT_GRACE_PERIOD); 4053 dqm_unlock(dqm); 4054 4055 return r; 4056 } 4057 4058 #endif 4059