1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(4, 4, 5): 88 case IP_VERSION(4, 4, 4): 89 case IP_VERSION(5, 0, 0):/* NAVI10 */ 90 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 91 case IP_VERSION(5, 0, 2):/* NAVI14 */ 92 case IP_VERSION(5, 0, 5):/* NAVI12 */ 93 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 94 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 95 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 96 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 97 case IP_VERSION(6, 0, 0): 98 case IP_VERSION(6, 0, 1): 99 case IP_VERSION(6, 0, 2): 100 case IP_VERSION(6, 0, 3): 101 case IP_VERSION(6, 1, 0): 102 case IP_VERSION(6, 1, 1): 103 case IP_VERSION(6, 1, 2): 104 case IP_VERSION(6, 1, 3): 105 case IP_VERSION(7, 0, 0): 106 case IP_VERSION(7, 0, 1): 107 kfd->device_info.num_sdma_queues_per_engine = 8; 108 break; 109 default: 110 dev_warn(kfd_device, 111 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 112 sdma_version); 113 kfd->device_info.num_sdma_queues_per_engine = 8; 114 } 115 116 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 117 118 switch (sdma_version) { 119 case IP_VERSION(6, 0, 0): 120 case IP_VERSION(6, 0, 1): 121 case IP_VERSION(6, 0, 2): 122 case IP_VERSION(6, 0, 3): 123 case IP_VERSION(6, 1, 0): 124 case IP_VERSION(6, 1, 1): 125 case IP_VERSION(6, 1, 2): 126 case IP_VERSION(6, 1, 3): 127 case IP_VERSION(7, 0, 0): 128 case IP_VERSION(7, 0, 1): 129 /* Reserve 1 for paging and 1 for gfx */ 130 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 131 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 132 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 133 kfd->adev->sdma.num_instances * 134 kfd->device_info.num_reserved_sdma_queues_per_engine); 135 break; 136 default: 137 break; 138 } 139 } 140 141 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 142 { 143 uint32_t gc_version = KFD_GC_VERSION(kfd); 144 145 switch (gc_version) { 146 case IP_VERSION(9, 0, 1): /* VEGA10 */ 147 case IP_VERSION(9, 1, 0): /* RAVEN */ 148 case IP_VERSION(9, 2, 1): /* VEGA12 */ 149 case IP_VERSION(9, 2, 2): /* RAVEN */ 150 case IP_VERSION(9, 3, 0): /* RENOIR */ 151 case IP_VERSION(9, 4, 0): /* VEGA20 */ 152 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 153 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 154 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 155 break; 156 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 157 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 158 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */ 159 kfd->device_info.event_interrupt_class = 160 &event_interrupt_class_v9_4_3; 161 break; 162 case IP_VERSION(10, 3, 1): /* VANGOGH */ 163 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 164 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 165 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 166 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 167 case IP_VERSION(10, 1, 4): 168 case IP_VERSION(10, 1, 10): /* NAVI10 */ 169 case IP_VERSION(10, 1, 2): /* NAVI12 */ 170 case IP_VERSION(10, 1, 1): /* NAVI14 */ 171 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 172 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 173 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 174 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 175 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 176 break; 177 case IP_VERSION(11, 0, 0): 178 case IP_VERSION(11, 0, 1): 179 case IP_VERSION(11, 0, 2): 180 case IP_VERSION(11, 0, 3): 181 case IP_VERSION(11, 0, 4): 182 case IP_VERSION(11, 5, 0): 183 case IP_VERSION(11, 5, 1): 184 case IP_VERSION(11, 5, 2): 185 case IP_VERSION(11, 5, 3): 186 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 187 break; 188 case IP_VERSION(12, 0, 0): 189 case IP_VERSION(12, 0, 1): 190 /* GFX12_TODO: Change to v12 version. */ 191 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 192 break; 193 default: 194 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 195 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 196 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 197 } 198 } 199 200 static void kfd_device_info_init(struct kfd_dev *kfd, 201 bool vf, uint32_t gfx_target_version) 202 { 203 uint32_t gc_version = KFD_GC_VERSION(kfd); 204 uint32_t asic_type = kfd->adev->asic_type; 205 206 kfd->device_info.max_pasid_bits = 16; 207 kfd->device_info.max_no_of_hqd = 24; 208 kfd->device_info.num_of_watch_points = 4; 209 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 210 kfd->device_info.gfx_target_version = gfx_target_version; 211 212 if (KFD_IS_SOC15(kfd)) { 213 kfd->device_info.doorbell_size = 8; 214 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 215 kfd->device_info.supports_cwsr = true; 216 217 kfd_device_info_set_sdma_info(kfd); 218 219 kfd_device_info_set_event_interrupt_class(kfd); 220 221 if (gc_version < IP_VERSION(11, 0, 0)) { 222 /* Navi2x+, Navi1x+ */ 223 if (gc_version == IP_VERSION(10, 3, 6)) 224 kfd->device_info.no_atomic_fw_version = 14; 225 else if (gc_version == IP_VERSION(10, 3, 7)) 226 kfd->device_info.no_atomic_fw_version = 3; 227 else if (gc_version >= IP_VERSION(10, 3, 0)) 228 kfd->device_info.no_atomic_fw_version = 92; 229 else if (gc_version >= IP_VERSION(10, 1, 1)) 230 kfd->device_info.no_atomic_fw_version = 145; 231 232 /* Navi1x+ */ 233 if (gc_version >= IP_VERSION(10, 1, 1)) 234 kfd->device_info.needs_pci_atomics = true; 235 } else if (gc_version < IP_VERSION(12, 0, 0)) { 236 /* 237 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 238 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 239 * PCIe atomics support. 240 */ 241 kfd->device_info.needs_pci_atomics = true; 242 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 243 } else if (gc_version < IP_VERSION(13, 0, 0)) { 244 kfd->device_info.needs_pci_atomics = true; 245 kfd->device_info.no_atomic_fw_version = 2090; 246 } else { 247 kfd->device_info.needs_pci_atomics = true; 248 } 249 } else { 250 kfd->device_info.doorbell_size = 4; 251 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 252 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 253 kfd->device_info.num_sdma_queues_per_engine = 2; 254 255 if (asic_type != CHIP_KAVERI && 256 asic_type != CHIP_HAWAII && 257 asic_type != CHIP_TONGA) 258 kfd->device_info.supports_cwsr = true; 259 260 if (asic_type != CHIP_HAWAII && !vf) 261 kfd->device_info.needs_pci_atomics = true; 262 } 263 } 264 265 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 266 { 267 struct kfd_dev *kfd = NULL; 268 const struct kfd2kgd_calls *f2g = NULL; 269 uint32_t gfx_target_version = 0; 270 271 switch (adev->asic_type) { 272 #ifdef CONFIG_DRM_AMDGPU_CIK 273 case CHIP_KAVERI: 274 gfx_target_version = 70000; 275 if (!vf) 276 f2g = &gfx_v7_kfd2kgd; 277 break; 278 #endif 279 case CHIP_CARRIZO: 280 gfx_target_version = 80001; 281 if (!vf) 282 f2g = &gfx_v8_kfd2kgd; 283 break; 284 #ifdef CONFIG_DRM_AMDGPU_CIK 285 case CHIP_HAWAII: 286 gfx_target_version = 70001; 287 if (!amdgpu_exp_hw_support) 288 pr_info( 289 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 290 ); 291 else if (!vf) 292 f2g = &gfx_v7_kfd2kgd; 293 break; 294 #endif 295 case CHIP_TONGA: 296 gfx_target_version = 80002; 297 if (!vf) 298 f2g = &gfx_v8_kfd2kgd; 299 break; 300 case CHIP_FIJI: 301 case CHIP_POLARIS10: 302 gfx_target_version = 80003; 303 f2g = &gfx_v8_kfd2kgd; 304 break; 305 case CHIP_POLARIS11: 306 case CHIP_POLARIS12: 307 case CHIP_VEGAM: 308 gfx_target_version = 80003; 309 if (!vf) 310 f2g = &gfx_v8_kfd2kgd; 311 break; 312 default: 313 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 314 /* Vega 10 */ 315 case IP_VERSION(9, 0, 1): 316 gfx_target_version = 90000; 317 f2g = &gfx_v9_kfd2kgd; 318 break; 319 /* Raven */ 320 case IP_VERSION(9, 1, 0): 321 case IP_VERSION(9, 2, 2): 322 gfx_target_version = 90002; 323 if (!vf) 324 f2g = &gfx_v9_kfd2kgd; 325 break; 326 /* Vega12 */ 327 case IP_VERSION(9, 2, 1): 328 gfx_target_version = 90004; 329 if (!vf) 330 f2g = &gfx_v9_kfd2kgd; 331 break; 332 /* Renoir */ 333 case IP_VERSION(9, 3, 0): 334 gfx_target_version = 90012; 335 if (!vf) 336 f2g = &gfx_v9_kfd2kgd; 337 break; 338 /* Vega20 */ 339 case IP_VERSION(9, 4, 0): 340 gfx_target_version = 90006; 341 if (!vf) 342 f2g = &gfx_v9_kfd2kgd; 343 break; 344 /* Arcturus */ 345 case IP_VERSION(9, 4, 1): 346 gfx_target_version = 90008; 347 f2g = &arcturus_kfd2kgd; 348 break; 349 /* Aldebaran */ 350 case IP_VERSION(9, 4, 2): 351 gfx_target_version = 90010; 352 f2g = &aldebaran_kfd2kgd; 353 break; 354 case IP_VERSION(9, 4, 3): 355 gfx_target_version = adev->rev_id >= 1 ? 90402 356 : adev->flags & AMD_IS_APU ? 90400 357 : 90401; 358 f2g = &gc_9_4_3_kfd2kgd; 359 break; 360 case IP_VERSION(9, 4, 4): 361 gfx_target_version = 90402; 362 f2g = &gc_9_4_3_kfd2kgd; 363 break; 364 case IP_VERSION(9, 5, 0): 365 gfx_target_version = 90500; 366 f2g = &gc_9_4_3_kfd2kgd; 367 break; 368 /* Navi10 */ 369 case IP_VERSION(10, 1, 10): 370 gfx_target_version = 100100; 371 if (!vf) 372 f2g = &gfx_v10_kfd2kgd; 373 break; 374 /* Navi12 */ 375 case IP_VERSION(10, 1, 2): 376 gfx_target_version = 100101; 377 f2g = &gfx_v10_kfd2kgd; 378 break; 379 /* Navi14 */ 380 case IP_VERSION(10, 1, 1): 381 gfx_target_version = 100102; 382 if (!vf) 383 f2g = &gfx_v10_kfd2kgd; 384 break; 385 /* Cyan Skillfish */ 386 case IP_VERSION(10, 1, 3): 387 case IP_VERSION(10, 1, 4): 388 gfx_target_version = 100103; 389 if (!vf) 390 f2g = &gfx_v10_kfd2kgd; 391 break; 392 /* Sienna Cichlid */ 393 case IP_VERSION(10, 3, 0): 394 gfx_target_version = 100300; 395 f2g = &gfx_v10_3_kfd2kgd; 396 break; 397 /* Navy Flounder */ 398 case IP_VERSION(10, 3, 2): 399 gfx_target_version = 100301; 400 f2g = &gfx_v10_3_kfd2kgd; 401 break; 402 /* Van Gogh */ 403 case IP_VERSION(10, 3, 1): 404 gfx_target_version = 100303; 405 if (!vf) 406 f2g = &gfx_v10_3_kfd2kgd; 407 break; 408 /* Dimgrey Cavefish */ 409 case IP_VERSION(10, 3, 4): 410 gfx_target_version = 100302; 411 f2g = &gfx_v10_3_kfd2kgd; 412 break; 413 /* Beige Goby */ 414 case IP_VERSION(10, 3, 5): 415 gfx_target_version = 100304; 416 f2g = &gfx_v10_3_kfd2kgd; 417 break; 418 /* Yellow Carp */ 419 case IP_VERSION(10, 3, 3): 420 gfx_target_version = 100305; 421 if (!vf) 422 f2g = &gfx_v10_3_kfd2kgd; 423 break; 424 case IP_VERSION(10, 3, 6): 425 case IP_VERSION(10, 3, 7): 426 gfx_target_version = 100306; 427 if (!vf) 428 f2g = &gfx_v10_3_kfd2kgd; 429 break; 430 case IP_VERSION(11, 0, 0): 431 gfx_target_version = 110000; 432 f2g = &gfx_v11_kfd2kgd; 433 break; 434 case IP_VERSION(11, 0, 1): 435 case IP_VERSION(11, 0, 4): 436 gfx_target_version = 110003; 437 f2g = &gfx_v11_kfd2kgd; 438 break; 439 case IP_VERSION(11, 0, 2): 440 gfx_target_version = 110002; 441 f2g = &gfx_v11_kfd2kgd; 442 break; 443 case IP_VERSION(11, 0, 3): 444 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 445 gfx_target_version = 110001; 446 f2g = &gfx_v11_kfd2kgd; 447 break; 448 case IP_VERSION(11, 5, 0): 449 gfx_target_version = 110500; 450 f2g = &gfx_v11_kfd2kgd; 451 break; 452 case IP_VERSION(11, 5, 1): 453 gfx_target_version = 110501; 454 f2g = &gfx_v11_kfd2kgd; 455 break; 456 case IP_VERSION(11, 5, 2): 457 gfx_target_version = 110502; 458 f2g = &gfx_v11_kfd2kgd; 459 break; 460 case IP_VERSION(11, 5, 3): 461 gfx_target_version = 110503; 462 f2g = &gfx_v11_kfd2kgd; 463 break; 464 case IP_VERSION(12, 0, 0): 465 gfx_target_version = 120000; 466 f2g = &gfx_v12_kfd2kgd; 467 break; 468 case IP_VERSION(12, 0, 1): 469 gfx_target_version = 120001; 470 f2g = &gfx_v12_kfd2kgd; 471 break; 472 default: 473 break; 474 } 475 break; 476 } 477 478 if (!f2g) { 479 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 480 dev_info(kfd_device, 481 "GC IP %06x %s not supported in kfd\n", 482 amdgpu_ip_version(adev, GC_HWIP, 0), 483 vf ? "VF" : ""); 484 else 485 dev_info(kfd_device, "%s %s not supported in kfd\n", 486 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 487 return NULL; 488 } 489 490 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 491 if (!kfd) 492 return NULL; 493 494 kfd->adev = adev; 495 kfd_device_info_init(kfd, vf, gfx_target_version); 496 kfd->init_complete = false; 497 kfd->kfd2kgd = f2g; 498 atomic_set(&kfd->compute_profile, 0); 499 500 mutex_init(&kfd->doorbell_mutex); 501 502 ida_init(&kfd->doorbell_ida); 503 504 return kfd; 505 } 506 507 static void kfd_cwsr_init(struct kfd_dev *kfd) 508 { 509 if (cwsr_enable && kfd->device_info.supports_cwsr) { 510 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 511 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 512 > KFD_CWSR_TMA_OFFSET); 513 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 514 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 515 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 516 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 517 > KFD_CWSR_TMA_OFFSET); 518 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 519 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 520 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 521 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 522 > KFD_CWSR_TMA_OFFSET); 523 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 524 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 525 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 526 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 527 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 528 > KFD_CWSR_TMA_OFFSET); 529 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 530 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 531 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) { 532 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE); 533 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex; 534 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex); 535 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 536 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 537 > KFD_CWSR_TMA_OFFSET); 538 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 539 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 540 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 541 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 542 > KFD_CWSR_TMA_OFFSET); 543 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 544 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 545 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 546 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 547 > KFD_CWSR_TMA_OFFSET); 548 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 549 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 550 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 551 /* The gfx11 cwsr trap handler must fit inside a single 552 page. */ 553 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 554 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 555 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 556 } else { 557 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 558 > KFD_CWSR_TMA_OFFSET); 559 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 560 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 561 } 562 563 kfd->cwsr_enabled = true; 564 } 565 } 566 567 static int kfd_gws_init(struct kfd_node *node) 568 { 569 int ret = 0; 570 struct kfd_dev *kfd = node->kfd; 571 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 572 573 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 574 return 0; 575 576 if (hws_gws_support || (KFD_IS_SOC15(node) && 577 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 578 && kfd->mec2_fw_version >= 0x81b3) || 579 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 580 && kfd->mec2_fw_version >= 0x1b3) || 581 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 582 && kfd->mec2_fw_version >= 0x30) || 583 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 584 && kfd->mec2_fw_version >= 0x28) || 585 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 586 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 587 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) || 588 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 589 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 590 && kfd->mec2_fw_version >= 0x6b) || 591 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 592 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 593 && mes_rev >= 68)))) 594 ret = amdgpu_amdkfd_alloc_gws(node->adev, 595 node->adev->gds.gws_size, &node->gws); 596 597 return ret; 598 } 599 600 static void kfd_smi_init(struct kfd_node *dev) 601 { 602 INIT_LIST_HEAD(&dev->smi_clients); 603 spin_lock_init(&dev->smi_lock); 604 } 605 606 static int kfd_init_node(struct kfd_node *node) 607 { 608 int err = -1; 609 610 if (kfd_interrupt_init(node)) { 611 dev_err(kfd_device, "Error initializing interrupts\n"); 612 goto kfd_interrupt_error; 613 } 614 615 node->dqm = device_queue_manager_init(node); 616 if (!node->dqm) { 617 dev_err(kfd_device, "Error initializing queue manager\n"); 618 goto device_queue_manager_error; 619 } 620 621 if (kfd_gws_init(node)) { 622 dev_err(kfd_device, "Could not allocate %d gws\n", 623 node->adev->gds.gws_size); 624 goto gws_error; 625 } 626 627 if (kfd_resume(node)) 628 goto kfd_resume_error; 629 630 if (kfd_topology_add_device(node)) { 631 dev_err(kfd_device, "Error adding device to topology\n"); 632 goto kfd_topology_add_device_error; 633 } 634 635 kfd_smi_init(node); 636 637 return 0; 638 639 kfd_topology_add_device_error: 640 kfd_resume_error: 641 gws_error: 642 device_queue_manager_uninit(node->dqm); 643 device_queue_manager_error: 644 kfd_interrupt_exit(node); 645 kfd_interrupt_error: 646 if (node->gws) 647 amdgpu_amdkfd_free_gws(node->adev, node->gws); 648 649 /* Cleanup the node memory here */ 650 kfree(node); 651 return err; 652 } 653 654 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 655 { 656 struct kfd_node *knode; 657 unsigned int i; 658 659 /* 660 * flush_work ensures that there are no outstanding 661 * work-queue items that will access interrupt_ring. New work items 662 * can't be created because we stopped interrupt handling above. 663 */ 664 flush_workqueue(kfd->ih_wq); 665 destroy_workqueue(kfd->ih_wq); 666 667 for (i = 0; i < num_nodes; i++) { 668 knode = kfd->nodes[i]; 669 device_queue_manager_uninit(knode->dqm); 670 kfd_interrupt_exit(knode); 671 kfd_topology_remove_device(knode); 672 if (knode->gws) 673 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 674 kfree(knode); 675 kfd->nodes[i] = NULL; 676 } 677 } 678 679 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 680 unsigned int kfd_node_idx) 681 { 682 struct amdgpu_device *adev = node->adev; 683 uint32_t xcc_mask = node->xcc_mask; 684 uint32_t xcc, mapped_xcc; 685 /* 686 * Interrupt bitmap is setup for processing interrupts from 687 * different XCDs and AIDs. 688 * Interrupt bitmap is defined as follows: 689 * 1. Bits 0-15 - correspond to the NodeId field. 690 * Each bit corresponds to NodeId number. For example, if 691 * a KFD node has interrupt bitmap set to 0x7, then this 692 * KFD node will process interrupts with NodeId = 0, 1 and 2 693 * in the IH cookie. 694 * 2. Bits 16-31 - unused. 695 * 696 * Please note that the kfd_node_idx argument passed to this 697 * function is not related to NodeId field received in the 698 * IH cookie. 699 * 700 * In CPX mode, a KFD node will process an interrupt if: 701 * - the Node Id matches the corresponding bit set in 702 * Bits 0-15. 703 * - AND VMID reported in the interrupt lies within the 704 * VMID range of the node. 705 */ 706 for_each_inst(xcc, xcc_mask) { 707 mapped_xcc = GET_INST(GC, xcc); 708 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 709 } 710 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 711 node->interrupt_bitmap); 712 } 713 714 bool kgd2kfd_device_init(struct kfd_dev *kfd, 715 const struct kgd2kfd_shared_resources *gpu_resources) 716 { 717 unsigned int size, map_process_packet_size, i; 718 struct kfd_node *node; 719 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 720 unsigned int max_proc_per_quantum; 721 int partition_mode; 722 int xcp_idx; 723 724 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 725 KGD_ENGINE_MEC1); 726 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 727 KGD_ENGINE_MEC2); 728 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 729 KGD_ENGINE_SDMA1); 730 kfd->shared_resources = *gpu_resources; 731 732 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 733 734 if (kfd->num_nodes == 0) { 735 dev_err(kfd_device, 736 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 737 kfd->adev->gfx.num_xcc_per_xcp); 738 goto out; 739 } 740 741 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 742 * 32 and 64-bit requests are possible and must be 743 * supported. 744 */ 745 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 746 if (!kfd->pci_atomic_requested && 747 kfd->device_info.needs_pci_atomics && 748 (!kfd->device_info.no_atomic_fw_version || 749 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 750 dev_info(kfd_device, 751 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 752 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 753 kfd->mec_fw_version, 754 kfd->device_info.no_atomic_fw_version); 755 return false; 756 } 757 758 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 759 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 760 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 761 762 /* For multi-partition capable GPUs, we need special handling for VMIDs 763 * depending on partition mode. 764 * In CPX mode, the VMID range needs to be shared between XCDs. 765 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 766 * divide them equally, we change starting VMID to 4 and not use 767 * VMID 3. 768 * If the VMID range changes for multi-partition capable GPUs, then 769 * this code MUST be revisited. 770 */ 771 if (kfd->adev->xcp_mgr) { 772 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 773 AMDGPU_XCP_FL_LOCKED); 774 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 775 kfd->num_nodes != 1) { 776 vmid_num_kfd /= 2; 777 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 778 } 779 } 780 781 /* Verify module parameters regarding mapped process number*/ 782 if (hws_max_conc_proc >= 0) 783 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 784 else 785 max_proc_per_quantum = vmid_num_kfd; 786 787 /* calculate max size of mqds needed for queues */ 788 size = max_num_of_queues_per_device * 789 kfd->device_info.mqd_size_aligned; 790 791 /* 792 * calculate max size of runlist packet. 793 * There can be only 2 packets at once 794 */ 795 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 796 sizeof(struct pm4_mes_map_process_aldebaran) : 797 sizeof(struct pm4_mes_map_process); 798 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 799 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 800 + sizeof(struct pm4_mes_runlist)) * 2; 801 802 /* Add size of HIQ & DIQ */ 803 size += KFD_KERNEL_QUEUE_SIZE * 2; 804 805 /* add another 512KB for all other allocations on gart (HPD, fences) */ 806 size += 512 * 1024; 807 808 if (amdgpu_amdkfd_alloc_gtt_mem( 809 kfd->adev, size, &kfd->gtt_mem, 810 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 811 false)) { 812 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 813 goto alloc_gtt_mem_failure; 814 } 815 816 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 817 818 /* Initialize GTT sa with 512 byte chunk size */ 819 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 820 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 821 goto kfd_gtt_sa_init_error; 822 } 823 824 if (kfd_doorbell_init(kfd)) { 825 dev_err(kfd_device, 826 "Error initializing doorbell aperture\n"); 827 goto kfd_doorbell_error; 828 } 829 830 if (amdgpu_use_xgmi_p2p) 831 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 832 833 /* 834 * For multi-partition capable GPUs, the KFD abstracts all partitions 835 * within a socket as xGMI connected in the topology so assign a unique 836 * hive id per device based on the pci device location if device is in 837 * PCIe mode. 838 */ 839 if (!kfd->hive_id && kfd->num_nodes > 1) 840 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 841 842 kfd->noretry = kfd->adev->gmc.noretry; 843 844 kfd_cwsr_init(kfd); 845 846 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 847 kfd->num_nodes); 848 849 /* Allocate the KFD nodes */ 850 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 851 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 852 if (!node) 853 goto node_alloc_error; 854 855 node->node_id = i; 856 node->adev = kfd->adev; 857 node->kfd = kfd; 858 node->kfd2kgd = kfd->kfd2kgd; 859 node->vm_info.vmid_num_kfd = vmid_num_kfd; 860 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 861 /* TODO : Check if error handling is needed */ 862 if (node->xcp) { 863 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 864 &node->xcc_mask); 865 ++xcp_idx; 866 } else { 867 node->xcc_mask = 868 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 869 } 870 871 if (node->xcp) { 872 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 873 node->node_id, node->xcp->mem_id, 874 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 875 } 876 877 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 878 kfd->num_nodes != 1) { 879 /* For multi-partition capable GPUs and CPX mode, first 880 * XCD gets VMID range 4-9 and second XCD gets VMID 881 * range 10-15. 882 */ 883 884 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 885 first_vmid_kfd : 886 first_vmid_kfd+vmid_num_kfd; 887 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 888 last_vmid_kfd-vmid_num_kfd : 889 last_vmid_kfd; 890 node->compute_vmid_bitmap = 891 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 892 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 893 } else { 894 node->vm_info.first_vmid_kfd = first_vmid_kfd; 895 node->vm_info.last_vmid_kfd = last_vmid_kfd; 896 node->compute_vmid_bitmap = 897 gpu_resources->compute_vmid_bitmap; 898 } 899 node->max_proc_per_quantum = max_proc_per_quantum; 900 atomic_set(&node->sram_ecc_flag, 0); 901 902 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 903 &node->local_mem_info, node->xcp); 904 905 if (kfd->adev->xcp_mgr) 906 kfd_setup_interrupt_bitmap(node, i); 907 908 /* Initialize the KFD node */ 909 if (kfd_init_node(node)) { 910 dev_err(kfd_device, "Error initializing KFD node\n"); 911 goto node_init_error; 912 } 913 914 spin_lock_init(&node->watch_points_lock); 915 916 kfd->nodes[i] = node; 917 } 918 919 svm_range_set_max_pages(kfd->adev); 920 921 kfd->init_complete = true; 922 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 923 kfd->adev->pdev->device); 924 925 pr_debug("Starting kfd with the following scheduling policy %d\n", 926 node->dqm->sched_policy); 927 928 goto out; 929 930 node_init_error: 931 node_alloc_error: 932 kfd_cleanup_nodes(kfd, i); 933 kfd_doorbell_fini(kfd); 934 kfd_doorbell_error: 935 kfd_gtt_sa_fini(kfd); 936 kfd_gtt_sa_init_error: 937 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 938 alloc_gtt_mem_failure: 939 dev_err(kfd_device, 940 "device %x:%x NOT added due to errors\n", 941 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 942 out: 943 return kfd->init_complete; 944 } 945 946 void kgd2kfd_device_exit(struct kfd_dev *kfd) 947 { 948 if (kfd->init_complete) { 949 /* Cleanup KFD nodes */ 950 kfd_cleanup_nodes(kfd, kfd->num_nodes); 951 /* Cleanup common/shared resources */ 952 kfd_doorbell_fini(kfd); 953 ida_destroy(&kfd->doorbell_ida); 954 kfd_gtt_sa_fini(kfd); 955 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 956 } 957 958 kfree(kfd); 959 } 960 961 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 962 struct amdgpu_reset_context *reset_context) 963 { 964 struct kfd_node *node; 965 int i; 966 967 if (!kfd->init_complete) 968 return 0; 969 970 for (i = 0; i < kfd->num_nodes; i++) { 971 node = kfd->nodes[i]; 972 kfd_smi_event_update_gpu_reset(node, false, reset_context); 973 } 974 975 kgd2kfd_suspend(kfd, false); 976 977 for (i = 0; i < kfd->num_nodes; i++) 978 kfd_signal_reset_event(kfd->nodes[i]); 979 980 return 0; 981 } 982 983 /* 984 * Fix me. KFD won't be able to resume existing process for now. 985 * We will keep all existing process in a evicted state and 986 * wait the process to be terminated. 987 */ 988 989 int kgd2kfd_post_reset(struct kfd_dev *kfd) 990 { 991 int ret; 992 struct kfd_node *node; 993 int i; 994 995 if (!kfd->init_complete) 996 return 0; 997 998 for (i = 0; i < kfd->num_nodes; i++) { 999 ret = kfd_resume(kfd->nodes[i]); 1000 if (ret) 1001 return ret; 1002 } 1003 1004 mutex_lock(&kfd_processes_mutex); 1005 --kfd_locked; 1006 mutex_unlock(&kfd_processes_mutex); 1007 1008 for (i = 0; i < kfd->num_nodes; i++) { 1009 node = kfd->nodes[i]; 1010 atomic_set(&node->sram_ecc_flag, 0); 1011 kfd_smi_event_update_gpu_reset(node, true, NULL); 1012 } 1013 1014 return 0; 1015 } 1016 1017 bool kfd_is_locked(void) 1018 { 1019 lockdep_assert_held(&kfd_processes_mutex); 1020 return (kfd_locked > 0); 1021 } 1022 1023 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 1024 { 1025 struct kfd_node *node; 1026 int i; 1027 1028 if (!kfd->init_complete) 1029 return; 1030 1031 /* for runtime suspend, skip locking kfd */ 1032 if (!run_pm) { 1033 mutex_lock(&kfd_processes_mutex); 1034 /* For first KFD device suspend all the KFD processes */ 1035 if (++kfd_locked == 1) 1036 kfd_suspend_all_processes(); 1037 mutex_unlock(&kfd_processes_mutex); 1038 } 1039 1040 for (i = 0; i < kfd->num_nodes; i++) { 1041 node = kfd->nodes[i]; 1042 node->dqm->ops.stop(node->dqm); 1043 } 1044 } 1045 1046 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1047 { 1048 int ret, i; 1049 1050 if (!kfd->init_complete) 1051 return 0; 1052 1053 for (i = 0; i < kfd->num_nodes; i++) { 1054 ret = kfd_resume(kfd->nodes[i]); 1055 if (ret) 1056 return ret; 1057 } 1058 1059 /* for runtime resume, skip unlocking kfd */ 1060 if (!run_pm) { 1061 mutex_lock(&kfd_processes_mutex); 1062 if (--kfd_locked == 0) 1063 ret = kfd_resume_all_processes(); 1064 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1065 mutex_unlock(&kfd_processes_mutex); 1066 } 1067 1068 return ret; 1069 } 1070 1071 static int kfd_resume(struct kfd_node *node) 1072 { 1073 int err = 0; 1074 1075 err = node->dqm->ops.start(node->dqm); 1076 if (err) 1077 dev_err(kfd_device, 1078 "Error starting queue manager for device %x:%x\n", 1079 node->adev->pdev->vendor, node->adev->pdev->device); 1080 1081 return err; 1082 } 1083 1084 /* This is called directly from KGD at ISR. */ 1085 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1086 { 1087 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1088 bool is_patched = false; 1089 unsigned long flags; 1090 struct kfd_node *node; 1091 1092 if (!kfd->init_complete) 1093 return; 1094 1095 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1096 dev_err_once(kfd_device, "Ring entry too small\n"); 1097 return; 1098 } 1099 1100 for (i = 0; i < kfd->num_nodes; i++) { 1101 node = kfd->nodes[i]; 1102 spin_lock_irqsave(&node->interrupt_lock, flags); 1103 1104 if (node->interrupts_active 1105 && interrupt_is_wanted(node, ih_ring_entry, 1106 patched_ihre, &is_patched) 1107 && enqueue_ih_ring_entry(node, 1108 is_patched ? patched_ihre : ih_ring_entry)) { 1109 queue_work(node->kfd->ih_wq, &node->interrupt_work); 1110 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1111 return; 1112 } 1113 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1114 } 1115 1116 } 1117 1118 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1119 { 1120 struct kfd_process *p; 1121 int r; 1122 1123 /* Because we are called from arbitrary context (workqueue) as opposed 1124 * to process context, kfd_process could attempt to exit while we are 1125 * running so the lookup function increments the process ref count. 1126 */ 1127 p = kfd_lookup_process_by_mm(mm); 1128 if (!p) 1129 return -ESRCH; 1130 1131 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1132 r = kfd_process_evict_queues(p, trigger); 1133 1134 kfd_unref_process(p); 1135 return r; 1136 } 1137 1138 int kgd2kfd_resume_mm(struct mm_struct *mm) 1139 { 1140 struct kfd_process *p; 1141 int r; 1142 1143 /* Because we are called from arbitrary context (workqueue) as opposed 1144 * to process context, kfd_process could attempt to exit while we are 1145 * running so the lookup function increments the process ref count. 1146 */ 1147 p = kfd_lookup_process_by_mm(mm); 1148 if (!p) 1149 return -ESRCH; 1150 1151 r = kfd_process_restore_queues(p); 1152 1153 kfd_unref_process(p); 1154 return r; 1155 } 1156 1157 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1158 * prepare for safe eviction of KFD BOs that belong to the specified 1159 * process. 1160 * 1161 * @mm: mm_struct that identifies the specified KFD process 1162 * @fence: eviction fence attached to KFD process BOs 1163 * 1164 */ 1165 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1166 struct dma_fence *fence) 1167 { 1168 struct kfd_process *p; 1169 unsigned long active_time; 1170 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1171 1172 if (!fence) 1173 return -EINVAL; 1174 1175 if (dma_fence_is_signaled(fence)) 1176 return 0; 1177 1178 p = kfd_lookup_process_by_mm(mm); 1179 if (!p) 1180 return -ENODEV; 1181 1182 if (fence->seqno == p->last_eviction_seqno) 1183 goto out; 1184 1185 p->last_eviction_seqno = fence->seqno; 1186 1187 /* Avoid KFD process starvation. Wait for at least 1188 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1189 */ 1190 active_time = get_jiffies_64() - p->last_restore_timestamp; 1191 if (delay_jiffies > active_time) 1192 delay_jiffies -= active_time; 1193 else 1194 delay_jiffies = 0; 1195 1196 /* During process initialization eviction_work.dwork is initialized 1197 * to kfd_evict_bo_worker 1198 */ 1199 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1200 p->lead_thread->pid, delay_jiffies); 1201 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1202 out: 1203 kfd_unref_process(p); 1204 return 0; 1205 } 1206 1207 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1208 unsigned int chunk_size) 1209 { 1210 if (WARN_ON(buf_size < chunk_size)) 1211 return -EINVAL; 1212 if (WARN_ON(buf_size == 0)) 1213 return -EINVAL; 1214 if (WARN_ON(chunk_size == 0)) 1215 return -EINVAL; 1216 1217 kfd->gtt_sa_chunk_size = chunk_size; 1218 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1219 1220 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1221 GFP_KERNEL); 1222 if (!kfd->gtt_sa_bitmap) 1223 return -ENOMEM; 1224 1225 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1226 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1227 1228 mutex_init(&kfd->gtt_sa_lock); 1229 1230 return 0; 1231 } 1232 1233 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1234 { 1235 mutex_destroy(&kfd->gtt_sa_lock); 1236 bitmap_free(kfd->gtt_sa_bitmap); 1237 } 1238 1239 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1240 unsigned int bit_num, 1241 unsigned int chunk_size) 1242 { 1243 return start_addr + bit_num * chunk_size; 1244 } 1245 1246 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1247 unsigned int bit_num, 1248 unsigned int chunk_size) 1249 { 1250 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1251 } 1252 1253 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1254 struct kfd_mem_obj **mem_obj) 1255 { 1256 unsigned int found, start_search, cur_size; 1257 struct kfd_dev *kfd = node->kfd; 1258 1259 if (size == 0) 1260 return -EINVAL; 1261 1262 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1263 return -ENOMEM; 1264 1265 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1266 if (!(*mem_obj)) 1267 return -ENOMEM; 1268 1269 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1270 1271 start_search = 0; 1272 1273 mutex_lock(&kfd->gtt_sa_lock); 1274 1275 kfd_gtt_restart_search: 1276 /* Find the first chunk that is free */ 1277 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1278 kfd->gtt_sa_num_of_chunks, 1279 start_search); 1280 1281 pr_debug("Found = %d\n", found); 1282 1283 /* If there wasn't any free chunk, bail out */ 1284 if (found == kfd->gtt_sa_num_of_chunks) 1285 goto kfd_gtt_no_free_chunk; 1286 1287 /* Update fields of mem_obj */ 1288 (*mem_obj)->range_start = found; 1289 (*mem_obj)->range_end = found; 1290 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1291 kfd->gtt_start_gpu_addr, 1292 found, 1293 kfd->gtt_sa_chunk_size); 1294 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1295 kfd->gtt_start_cpu_ptr, 1296 found, 1297 kfd->gtt_sa_chunk_size); 1298 1299 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1300 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1301 1302 /* If we need only one chunk, mark it as allocated and get out */ 1303 if (size <= kfd->gtt_sa_chunk_size) { 1304 pr_debug("Single bit\n"); 1305 __set_bit(found, kfd->gtt_sa_bitmap); 1306 goto kfd_gtt_out; 1307 } 1308 1309 /* Otherwise, try to see if we have enough contiguous chunks */ 1310 cur_size = size - kfd->gtt_sa_chunk_size; 1311 do { 1312 (*mem_obj)->range_end = 1313 find_next_zero_bit(kfd->gtt_sa_bitmap, 1314 kfd->gtt_sa_num_of_chunks, ++found); 1315 /* 1316 * If next free chunk is not contiguous than we need to 1317 * restart our search from the last free chunk we found (which 1318 * wasn't contiguous to the previous ones 1319 */ 1320 if ((*mem_obj)->range_end != found) { 1321 start_search = found; 1322 goto kfd_gtt_restart_search; 1323 } 1324 1325 /* 1326 * If we reached end of buffer, bail out with error 1327 */ 1328 if (found == kfd->gtt_sa_num_of_chunks) 1329 goto kfd_gtt_no_free_chunk; 1330 1331 /* Check if we don't need another chunk */ 1332 if (cur_size <= kfd->gtt_sa_chunk_size) 1333 cur_size = 0; 1334 else 1335 cur_size -= kfd->gtt_sa_chunk_size; 1336 1337 } while (cur_size > 0); 1338 1339 pr_debug("range_start = %d, range_end = %d\n", 1340 (*mem_obj)->range_start, (*mem_obj)->range_end); 1341 1342 /* Mark the chunks as allocated */ 1343 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1344 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1345 1346 kfd_gtt_out: 1347 mutex_unlock(&kfd->gtt_sa_lock); 1348 return 0; 1349 1350 kfd_gtt_no_free_chunk: 1351 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1352 mutex_unlock(&kfd->gtt_sa_lock); 1353 kfree(*mem_obj); 1354 return -ENOMEM; 1355 } 1356 1357 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1358 { 1359 struct kfd_dev *kfd = node->kfd; 1360 1361 /* Act like kfree when trying to free a NULL object */ 1362 if (!mem_obj) 1363 return 0; 1364 1365 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1366 mem_obj, mem_obj->range_start, mem_obj->range_end); 1367 1368 mutex_lock(&kfd->gtt_sa_lock); 1369 1370 /* Mark the chunks as free */ 1371 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1372 mem_obj->range_end - mem_obj->range_start + 1); 1373 1374 mutex_unlock(&kfd->gtt_sa_lock); 1375 1376 kfree(mem_obj); 1377 return 0; 1378 } 1379 1380 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1381 { 1382 /* 1383 * TODO: Currently update SRAM ECC flag for first node. 1384 * This needs to be updated later when we can 1385 * identify SRAM ECC error on other nodes also. 1386 */ 1387 if (kfd) 1388 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1389 } 1390 1391 void kfd_inc_compute_active(struct kfd_node *node) 1392 { 1393 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1394 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1395 } 1396 1397 void kfd_dec_compute_active(struct kfd_node *node) 1398 { 1399 int count = atomic_dec_return(&node->kfd->compute_profile); 1400 1401 if (count == 0) 1402 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1403 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1404 } 1405 1406 static bool kfd_compute_active(struct kfd_node *node) 1407 { 1408 if (atomic_read(&node->kfd->compute_profile)) 1409 return true; 1410 return false; 1411 } 1412 1413 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1414 { 1415 /* 1416 * TODO: For now, raise the throttling event only on first node. 1417 * This will need to change after we are able to determine 1418 * which node raised the throttling event. 1419 */ 1420 if (kfd && kfd->init_complete) 1421 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1422 throttle_bitmask); 1423 } 1424 1425 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1426 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1427 * When the device has more than two engines, we reserve two for PCIe to enable 1428 * full-duplex and the rest are used as XGMI. 1429 */ 1430 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1431 { 1432 /* If XGMI is not supported, all SDMA engines are PCIe */ 1433 if (!node->adev->gmc.xgmi.supported) 1434 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1435 1436 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1437 } 1438 1439 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1440 { 1441 /* After reserved for PCIe, the rest of engines are XGMI */ 1442 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1443 kfd_get_num_sdma_engines(node); 1444 } 1445 1446 int kgd2kfd_check_and_lock_kfd(void) 1447 { 1448 mutex_lock(&kfd_processes_mutex); 1449 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1450 mutex_unlock(&kfd_processes_mutex); 1451 return -EBUSY; 1452 } 1453 1454 ++kfd_locked; 1455 mutex_unlock(&kfd_processes_mutex); 1456 1457 return 0; 1458 } 1459 1460 void kgd2kfd_unlock_kfd(void) 1461 { 1462 mutex_lock(&kfd_processes_mutex); 1463 --kfd_locked; 1464 mutex_unlock(&kfd_processes_mutex); 1465 } 1466 1467 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1468 { 1469 struct kfd_node *node; 1470 int ret; 1471 1472 if (!kfd->init_complete) 1473 return 0; 1474 1475 if (node_id >= kfd->num_nodes) { 1476 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1477 node_id, kfd->num_nodes - 1); 1478 return -EINVAL; 1479 } 1480 node = kfd->nodes[node_id]; 1481 1482 ret = node->dqm->ops.unhalt(node->dqm); 1483 if (ret) 1484 dev_err(kfd_device, "Error in starting scheduler\n"); 1485 1486 return ret; 1487 } 1488 1489 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1490 { 1491 struct kfd_node *node; 1492 1493 if (!kfd->init_complete) 1494 return 0; 1495 1496 if (node_id >= kfd->num_nodes) { 1497 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1498 node_id, kfd->num_nodes - 1); 1499 return -EINVAL; 1500 } 1501 1502 node = kfd->nodes[node_id]; 1503 return node->dqm->ops.halt(node->dqm); 1504 } 1505 1506 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1507 { 1508 struct kfd_node *node; 1509 1510 if (!kfd->init_complete) 1511 return false; 1512 1513 if (node_id >= kfd->num_nodes) { 1514 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1515 node_id, kfd->num_nodes - 1); 1516 return false; 1517 } 1518 1519 node = kfd->nodes[node_id]; 1520 1521 return kfd_compute_active(node); 1522 } 1523 1524 /** 1525 * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9 1526 * @adev: amdgpu device 1527 * @entry: vm fault interrupt vector 1528 * @retry_fault: if this is retry fault 1529 * 1530 * retry fault - 1531 * with CAM enabled, adev primary ring 1532 * | gmc_v9_0_process_interrupt() 1533 * adev soft_ring 1534 * | gmc_v9_0_process_interrupt() worker failed to recover page fault 1535 * KFD node ih_fifo 1536 * | KFD interrupt_wq worker 1537 * kfd_signal_vm_fault_event 1538 * 1539 * without CAM, adev primary ring1 1540 * | gmc_v9_0_process_interrupt worker failed to recvoer page fault 1541 * KFD node ih_fifo 1542 * | KFD interrupt_wq worker 1543 * kfd_signal_vm_fault_event 1544 * 1545 * no-retry fault - 1546 * adev primary ring 1547 * | gmc_v9_0_process_interrupt() 1548 * KFD node ih_fifo 1549 * | KFD interrupt_wq worker 1550 * kfd_signal_vm_fault_event 1551 * 1552 * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault 1553 * of same process, don't copy interrupt to KFD node ih_fifo. 1554 * With gdb debugger enabled, need convert the retry fault to no-retry fault for 1555 * debugger, cannot use the fast path. 1556 * 1557 * Return: 1558 * true - use the fast path to handle this fault 1559 * false - use normal path to handle it 1560 */ 1561 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 1562 bool retry_fault) 1563 { 1564 struct kfd_process *p; 1565 u32 cam_index; 1566 1567 if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) { 1568 p = kfd_lookup_process_by_pasid(entry->pasid, NULL); 1569 if (!p) 1570 return true; 1571 1572 if (p->gpu_page_fault && !p->debug_trap_enabled) { 1573 if (retry_fault && adev->irq.retry_cam_enabled) { 1574 cam_index = entry->src_data[2] & 0x3ff; 1575 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 1576 } 1577 1578 kfd_unref_process(p); 1579 return true; 1580 } 1581 1582 /* 1583 * This is the first page fault, set flag and then signal user space 1584 */ 1585 p->gpu_page_fault = true; 1586 kfd_unref_process(p); 1587 } 1588 return false; 1589 } 1590 1591 #if defined(CONFIG_DEBUG_FS) 1592 1593 /* This function will send a package to HIQ to hang the HWS 1594 * which will trigger a GPU reset and bring the HWS back to normal state 1595 */ 1596 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1597 { 1598 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1599 pr_err("HWS is not enabled"); 1600 return -EINVAL; 1601 } 1602 1603 return dqm_debugfs_hang_hws(dev->dqm); 1604 } 1605 1606 #endif 1607