1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 60 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 61 unsigned int chunk_size); 62 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 63 64 static int kfd_resume(struct kfd_node *kfd); 65 66 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 67 { 68 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 69 70 switch (sdma_version) { 71 case IP_VERSION(4, 0, 0):/* VEGA10 */ 72 case IP_VERSION(4, 0, 1):/* VEGA12 */ 73 case IP_VERSION(4, 1, 0):/* RAVEN */ 74 case IP_VERSION(4, 1, 1):/* RAVEN */ 75 case IP_VERSION(4, 1, 2):/* RENOIR */ 76 case IP_VERSION(5, 2, 1):/* VANGOGH */ 77 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 78 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 79 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 80 kfd->device_info.num_sdma_queues_per_engine = 2; 81 break; 82 case IP_VERSION(4, 2, 0):/* VEGA20 */ 83 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 84 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 85 case IP_VERSION(4, 4, 2): 86 case IP_VERSION(5, 0, 0):/* NAVI10 */ 87 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 88 case IP_VERSION(5, 0, 2):/* NAVI14 */ 89 case IP_VERSION(5, 0, 5):/* NAVI12 */ 90 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 91 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 92 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 93 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 94 case IP_VERSION(6, 0, 0): 95 case IP_VERSION(6, 0, 1): 96 case IP_VERSION(6, 0, 2): 97 case IP_VERSION(6, 0, 3): 98 case IP_VERSION(6, 1, 0): 99 kfd->device_info.num_sdma_queues_per_engine = 8; 100 break; 101 default: 102 dev_warn(kfd_device, 103 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 104 sdma_version); 105 kfd->device_info.num_sdma_queues_per_engine = 8; 106 } 107 108 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 109 110 switch (sdma_version) { 111 case IP_VERSION(6, 0, 0): 112 case IP_VERSION(6, 0, 1): 113 case IP_VERSION(6, 0, 2): 114 case IP_VERSION(6, 0, 3): 115 case IP_VERSION(6, 1, 0): 116 /* Reserve 1 for paging and 1 for gfx */ 117 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 118 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 119 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 120 kfd->adev->sdma.num_instances * 121 kfd->device_info.num_reserved_sdma_queues_per_engine); 122 break; 123 default: 124 break; 125 } 126 } 127 128 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 129 { 130 uint32_t gc_version = KFD_GC_VERSION(kfd); 131 132 switch (gc_version) { 133 case IP_VERSION(9, 0, 1): /* VEGA10 */ 134 case IP_VERSION(9, 1, 0): /* RAVEN */ 135 case IP_VERSION(9, 2, 1): /* VEGA12 */ 136 case IP_VERSION(9, 2, 2): /* RAVEN */ 137 case IP_VERSION(9, 3, 0): /* RENOIR */ 138 case IP_VERSION(9, 4, 0): /* VEGA20 */ 139 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 140 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 141 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 142 break; 143 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 144 kfd->device_info.event_interrupt_class = 145 &event_interrupt_class_v9_4_3; 146 break; 147 case IP_VERSION(10, 3, 1): /* VANGOGH */ 148 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 149 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 150 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 151 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 152 case IP_VERSION(10, 1, 4): 153 case IP_VERSION(10, 1, 10): /* NAVI10 */ 154 case IP_VERSION(10, 1, 2): /* NAVI12 */ 155 case IP_VERSION(10, 1, 1): /* NAVI14 */ 156 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 157 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 158 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 159 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 160 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 161 break; 162 case IP_VERSION(11, 0, 0): 163 case IP_VERSION(11, 0, 1): 164 case IP_VERSION(11, 0, 2): 165 case IP_VERSION(11, 0, 3): 166 case IP_VERSION(11, 0, 4): 167 case IP_VERSION(11, 5, 0): 168 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 169 break; 170 default: 171 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 172 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 173 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 174 } 175 } 176 177 static void kfd_device_info_init(struct kfd_dev *kfd, 178 bool vf, uint32_t gfx_target_version) 179 { 180 uint32_t gc_version = KFD_GC_VERSION(kfd); 181 uint32_t asic_type = kfd->adev->asic_type; 182 183 kfd->device_info.max_pasid_bits = 16; 184 kfd->device_info.max_no_of_hqd = 24; 185 kfd->device_info.num_of_watch_points = 4; 186 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 187 kfd->device_info.gfx_target_version = gfx_target_version; 188 189 if (KFD_IS_SOC15(kfd)) { 190 kfd->device_info.doorbell_size = 8; 191 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 192 kfd->device_info.supports_cwsr = true; 193 194 kfd_device_info_set_sdma_info(kfd); 195 196 kfd_device_info_set_event_interrupt_class(kfd); 197 198 if (gc_version < IP_VERSION(11, 0, 0)) { 199 /* Navi2x+, Navi1x+ */ 200 if (gc_version == IP_VERSION(10, 3, 6)) 201 kfd->device_info.no_atomic_fw_version = 14; 202 else if (gc_version == IP_VERSION(10, 3, 7)) 203 kfd->device_info.no_atomic_fw_version = 3; 204 else if (gc_version >= IP_VERSION(10, 3, 0)) 205 kfd->device_info.no_atomic_fw_version = 92; 206 else if (gc_version >= IP_VERSION(10, 1, 1)) 207 kfd->device_info.no_atomic_fw_version = 145; 208 209 /* Navi1x+ */ 210 if (gc_version >= IP_VERSION(10, 1, 1)) 211 kfd->device_info.needs_pci_atomics = true; 212 } else if (gc_version < IP_VERSION(12, 0, 0)) { 213 /* 214 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 215 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 216 * PCIe atomics support. 217 */ 218 kfd->device_info.needs_pci_atomics = true; 219 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 220 } 221 } else { 222 kfd->device_info.doorbell_size = 4; 223 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 224 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 225 kfd->device_info.num_sdma_queues_per_engine = 2; 226 227 if (asic_type != CHIP_KAVERI && 228 asic_type != CHIP_HAWAII && 229 asic_type != CHIP_TONGA) 230 kfd->device_info.supports_cwsr = true; 231 232 if (asic_type != CHIP_HAWAII && !vf) 233 kfd->device_info.needs_pci_atomics = true; 234 } 235 } 236 237 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 238 { 239 struct kfd_dev *kfd = NULL; 240 const struct kfd2kgd_calls *f2g = NULL; 241 uint32_t gfx_target_version = 0; 242 243 switch (adev->asic_type) { 244 #ifdef CONFIG_DRM_AMDGPU_CIK 245 case CHIP_KAVERI: 246 gfx_target_version = 70000; 247 if (!vf) 248 f2g = &gfx_v7_kfd2kgd; 249 break; 250 #endif 251 case CHIP_CARRIZO: 252 gfx_target_version = 80001; 253 if (!vf) 254 f2g = &gfx_v8_kfd2kgd; 255 break; 256 #ifdef CONFIG_DRM_AMDGPU_CIK 257 case CHIP_HAWAII: 258 gfx_target_version = 70001; 259 if (!amdgpu_exp_hw_support) 260 pr_info( 261 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 262 ); 263 else if (!vf) 264 f2g = &gfx_v7_kfd2kgd; 265 break; 266 #endif 267 case CHIP_TONGA: 268 gfx_target_version = 80002; 269 if (!vf) 270 f2g = &gfx_v8_kfd2kgd; 271 break; 272 case CHIP_FIJI: 273 case CHIP_POLARIS10: 274 gfx_target_version = 80003; 275 f2g = &gfx_v8_kfd2kgd; 276 break; 277 case CHIP_POLARIS11: 278 case CHIP_POLARIS12: 279 case CHIP_VEGAM: 280 gfx_target_version = 80003; 281 if (!vf) 282 f2g = &gfx_v8_kfd2kgd; 283 break; 284 default: 285 switch (adev->ip_versions[GC_HWIP][0]) { 286 /* Vega 10 */ 287 case IP_VERSION(9, 0, 1): 288 gfx_target_version = 90000; 289 f2g = &gfx_v9_kfd2kgd; 290 break; 291 /* Raven */ 292 case IP_VERSION(9, 1, 0): 293 case IP_VERSION(9, 2, 2): 294 gfx_target_version = 90002; 295 if (!vf) 296 f2g = &gfx_v9_kfd2kgd; 297 break; 298 /* Vega12 */ 299 case IP_VERSION(9, 2, 1): 300 gfx_target_version = 90004; 301 if (!vf) 302 f2g = &gfx_v9_kfd2kgd; 303 break; 304 /* Renoir */ 305 case IP_VERSION(9, 3, 0): 306 gfx_target_version = 90012; 307 if (!vf) 308 f2g = &gfx_v9_kfd2kgd; 309 break; 310 /* Vega20 */ 311 case IP_VERSION(9, 4, 0): 312 gfx_target_version = 90006; 313 if (!vf) 314 f2g = &gfx_v9_kfd2kgd; 315 break; 316 /* Arcturus */ 317 case IP_VERSION(9, 4, 1): 318 gfx_target_version = 90008; 319 f2g = &arcturus_kfd2kgd; 320 break; 321 /* Aldebaran */ 322 case IP_VERSION(9, 4, 2): 323 gfx_target_version = 90010; 324 f2g = &aldebaran_kfd2kgd; 325 break; 326 case IP_VERSION(9, 4, 3): 327 gfx_target_version = adev->rev_id >= 1 ? 90402 328 : adev->flags & AMD_IS_APU ? 90400 329 : 90401; 330 f2g = &gc_9_4_3_kfd2kgd; 331 break; 332 /* Navi10 */ 333 case IP_VERSION(10, 1, 10): 334 gfx_target_version = 100100; 335 if (!vf) 336 f2g = &gfx_v10_kfd2kgd; 337 break; 338 /* Navi12 */ 339 case IP_VERSION(10, 1, 2): 340 gfx_target_version = 100101; 341 f2g = &gfx_v10_kfd2kgd; 342 break; 343 /* Navi14 */ 344 case IP_VERSION(10, 1, 1): 345 gfx_target_version = 100102; 346 if (!vf) 347 f2g = &gfx_v10_kfd2kgd; 348 break; 349 /* Cyan Skillfish */ 350 case IP_VERSION(10, 1, 3): 351 case IP_VERSION(10, 1, 4): 352 gfx_target_version = 100103; 353 if (!vf) 354 f2g = &gfx_v10_kfd2kgd; 355 break; 356 /* Sienna Cichlid */ 357 case IP_VERSION(10, 3, 0): 358 gfx_target_version = 100300; 359 f2g = &gfx_v10_3_kfd2kgd; 360 break; 361 /* Navy Flounder */ 362 case IP_VERSION(10, 3, 2): 363 gfx_target_version = 100301; 364 f2g = &gfx_v10_3_kfd2kgd; 365 break; 366 /* Van Gogh */ 367 case IP_VERSION(10, 3, 1): 368 gfx_target_version = 100303; 369 if (!vf) 370 f2g = &gfx_v10_3_kfd2kgd; 371 break; 372 /* Dimgrey Cavefish */ 373 case IP_VERSION(10, 3, 4): 374 gfx_target_version = 100302; 375 f2g = &gfx_v10_3_kfd2kgd; 376 break; 377 /* Beige Goby */ 378 case IP_VERSION(10, 3, 5): 379 gfx_target_version = 100304; 380 f2g = &gfx_v10_3_kfd2kgd; 381 break; 382 /* Yellow Carp */ 383 case IP_VERSION(10, 3, 3): 384 gfx_target_version = 100305; 385 if (!vf) 386 f2g = &gfx_v10_3_kfd2kgd; 387 break; 388 case IP_VERSION(10, 3, 6): 389 case IP_VERSION(10, 3, 7): 390 gfx_target_version = 100306; 391 if (!vf) 392 f2g = &gfx_v10_3_kfd2kgd; 393 break; 394 case IP_VERSION(11, 0, 0): 395 gfx_target_version = 110000; 396 f2g = &gfx_v11_kfd2kgd; 397 break; 398 case IP_VERSION(11, 0, 1): 399 case IP_VERSION(11, 0, 4): 400 gfx_target_version = 110003; 401 f2g = &gfx_v11_kfd2kgd; 402 break; 403 case IP_VERSION(11, 0, 2): 404 gfx_target_version = 110002; 405 f2g = &gfx_v11_kfd2kgd; 406 break; 407 case IP_VERSION(11, 0, 3): 408 if ((adev->pdev->device == 0x7460 && 409 adev->pdev->revision == 0x00) || 410 (adev->pdev->device == 0x7461 && 411 adev->pdev->revision == 0x00)) 412 /* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */ 413 gfx_target_version = 110005; 414 else 415 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 416 gfx_target_version = 110001; 417 f2g = &gfx_v11_kfd2kgd; 418 break; 419 case IP_VERSION(11, 5, 0): 420 gfx_target_version = 110500; 421 f2g = &gfx_v11_kfd2kgd; 422 break; 423 default: 424 break; 425 } 426 break; 427 } 428 429 if (!f2g) { 430 if (adev->ip_versions[GC_HWIP][0]) 431 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 432 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 433 else 434 dev_err(kfd_device, "%s %s not supported in kfd\n", 435 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 436 return NULL; 437 } 438 439 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 440 if (!kfd) 441 return NULL; 442 443 kfd->adev = adev; 444 kfd_device_info_init(kfd, vf, gfx_target_version); 445 kfd->init_complete = false; 446 kfd->kfd2kgd = f2g; 447 atomic_set(&kfd->compute_profile, 0); 448 449 mutex_init(&kfd->doorbell_mutex); 450 451 ida_init(&kfd->doorbell_ida); 452 453 return kfd; 454 } 455 456 static void kfd_cwsr_init(struct kfd_dev *kfd) 457 { 458 if (cwsr_enable && kfd->device_info.supports_cwsr) { 459 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 460 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 461 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 462 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 463 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 464 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 465 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 466 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 467 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 468 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 469 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 470 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 471 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) { 472 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE); 473 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 474 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 475 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 476 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 477 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 478 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 479 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 480 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 481 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 482 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 483 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 484 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 485 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 486 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 487 } else { 488 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 489 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 490 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 491 } 492 493 kfd->cwsr_enabled = true; 494 } 495 } 496 497 static int kfd_gws_init(struct kfd_node *node) 498 { 499 int ret = 0; 500 struct kfd_dev *kfd = node->kfd; 501 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 502 503 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 504 return 0; 505 506 if (hws_gws_support || (KFD_IS_SOC15(node) && 507 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 508 && kfd->mec2_fw_version >= 0x81b3) || 509 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 510 && kfd->mec2_fw_version >= 0x1b3) || 511 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 512 && kfd->mec2_fw_version >= 0x30) || 513 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 514 && kfd->mec2_fw_version >= 0x28) || 515 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3)) || 516 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 517 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 518 && kfd->mec2_fw_version >= 0x6b) || 519 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 520 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 521 && mes_rev >= 68)))) 522 ret = amdgpu_amdkfd_alloc_gws(node->adev, 523 node->adev->gds.gws_size, &node->gws); 524 525 return ret; 526 } 527 528 static void kfd_smi_init(struct kfd_node *dev) 529 { 530 INIT_LIST_HEAD(&dev->smi_clients); 531 spin_lock_init(&dev->smi_lock); 532 } 533 534 static int kfd_init_node(struct kfd_node *node) 535 { 536 int err = -1; 537 538 if (kfd_interrupt_init(node)) { 539 dev_err(kfd_device, "Error initializing interrupts\n"); 540 goto kfd_interrupt_error; 541 } 542 543 node->dqm = device_queue_manager_init(node); 544 if (!node->dqm) { 545 dev_err(kfd_device, "Error initializing queue manager\n"); 546 goto device_queue_manager_error; 547 } 548 549 if (kfd_gws_init(node)) { 550 dev_err(kfd_device, "Could not allocate %d gws\n", 551 node->adev->gds.gws_size); 552 goto gws_error; 553 } 554 555 if (kfd_resume(node)) 556 goto kfd_resume_error; 557 558 if (kfd_topology_add_device(node)) { 559 dev_err(kfd_device, "Error adding device to topology\n"); 560 goto kfd_topology_add_device_error; 561 } 562 563 kfd_smi_init(node); 564 565 return 0; 566 567 kfd_topology_add_device_error: 568 kfd_resume_error: 569 gws_error: 570 device_queue_manager_uninit(node->dqm); 571 device_queue_manager_error: 572 kfd_interrupt_exit(node); 573 kfd_interrupt_error: 574 if (node->gws) 575 amdgpu_amdkfd_free_gws(node->adev, node->gws); 576 577 /* Cleanup the node memory here */ 578 kfree(node); 579 return err; 580 } 581 582 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 583 { 584 struct kfd_node *knode; 585 unsigned int i; 586 587 for (i = 0; i < num_nodes; i++) { 588 knode = kfd->nodes[i]; 589 device_queue_manager_uninit(knode->dqm); 590 kfd_interrupt_exit(knode); 591 kfd_topology_remove_device(knode); 592 if (knode->gws) 593 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 594 kfree(knode); 595 kfd->nodes[i] = NULL; 596 } 597 } 598 599 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 600 unsigned int kfd_node_idx) 601 { 602 struct amdgpu_device *adev = node->adev; 603 uint32_t xcc_mask = node->xcc_mask; 604 uint32_t xcc, mapped_xcc; 605 /* 606 * Interrupt bitmap is setup for processing interrupts from 607 * different XCDs and AIDs. 608 * Interrupt bitmap is defined as follows: 609 * 1. Bits 0-15 - correspond to the NodeId field. 610 * Each bit corresponds to NodeId number. For example, if 611 * a KFD node has interrupt bitmap set to 0x7, then this 612 * KFD node will process interrupts with NodeId = 0, 1 and 2 613 * in the IH cookie. 614 * 2. Bits 16-31 - unused. 615 * 616 * Please note that the kfd_node_idx argument passed to this 617 * function is not related to NodeId field received in the 618 * IH cookie. 619 * 620 * In CPX mode, a KFD node will process an interrupt if: 621 * - the Node Id matches the corresponding bit set in 622 * Bits 0-15. 623 * - AND VMID reported in the interrupt lies within the 624 * VMID range of the node. 625 */ 626 for_each_inst(xcc, xcc_mask) { 627 mapped_xcc = GET_INST(GC, xcc); 628 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 629 } 630 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 631 node->interrupt_bitmap); 632 } 633 634 bool kgd2kfd_device_init(struct kfd_dev *kfd, 635 const struct kgd2kfd_shared_resources *gpu_resources) 636 { 637 unsigned int size, map_process_packet_size, i; 638 struct kfd_node *node; 639 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 640 unsigned int max_proc_per_quantum; 641 int partition_mode; 642 int xcp_idx; 643 644 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 645 KGD_ENGINE_MEC1); 646 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 647 KGD_ENGINE_MEC2); 648 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 649 KGD_ENGINE_SDMA1); 650 kfd->shared_resources = *gpu_resources; 651 652 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 653 654 if (kfd->num_nodes == 0) { 655 dev_err(kfd_device, 656 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 657 kfd->adev->gfx.num_xcc_per_xcp); 658 goto out; 659 } 660 661 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 662 * 32 and 64-bit requests are possible and must be 663 * supported. 664 */ 665 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 666 if (!kfd->pci_atomic_requested && 667 kfd->device_info.needs_pci_atomics && 668 (!kfd->device_info.no_atomic_fw_version || 669 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 670 dev_info(kfd_device, 671 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 672 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 673 kfd->mec_fw_version, 674 kfd->device_info.no_atomic_fw_version); 675 return false; 676 } 677 678 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 679 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 680 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 681 682 /* For GFX9.4.3, we need special handling for VMIDs depending on 683 * partition mode. 684 * In CPX mode, the VMID range needs to be shared between XCDs. 685 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 686 * divide them equally, we change starting VMID to 4 and not use 687 * VMID 3. 688 * If the VMID range changes for GFX9.4.3, then this code MUST be 689 * revisited. 690 */ 691 if (kfd->adev->xcp_mgr) { 692 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 693 AMDGPU_XCP_FL_LOCKED); 694 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 695 kfd->num_nodes != 1) { 696 vmid_num_kfd /= 2; 697 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 698 } 699 } 700 701 /* Verify module parameters regarding mapped process number*/ 702 if (hws_max_conc_proc >= 0) 703 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 704 else 705 max_proc_per_quantum = vmid_num_kfd; 706 707 /* calculate max size of mqds needed for queues */ 708 size = max_num_of_queues_per_device * 709 kfd->device_info.mqd_size_aligned; 710 711 /* 712 * calculate max size of runlist packet. 713 * There can be only 2 packets at once 714 */ 715 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 716 sizeof(struct pm4_mes_map_process_aldebaran) : 717 sizeof(struct pm4_mes_map_process); 718 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 719 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 720 + sizeof(struct pm4_mes_runlist)) * 2; 721 722 /* Add size of HIQ & DIQ */ 723 size += KFD_KERNEL_QUEUE_SIZE * 2; 724 725 /* add another 512KB for all other allocations on gart (HPD, fences) */ 726 size += 512 * 1024; 727 728 if (amdgpu_amdkfd_alloc_gtt_mem( 729 kfd->adev, size, &kfd->gtt_mem, 730 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 731 false)) { 732 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 733 goto alloc_gtt_mem_failure; 734 } 735 736 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 737 738 /* Initialize GTT sa with 512 byte chunk size */ 739 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 740 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 741 goto kfd_gtt_sa_init_error; 742 } 743 744 if (kfd_doorbell_init(kfd)) { 745 dev_err(kfd_device, 746 "Error initializing doorbell aperture\n"); 747 goto kfd_doorbell_error; 748 } 749 750 if (amdgpu_use_xgmi_p2p) 751 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 752 753 /* 754 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 755 * xGMI connected in the topology so assign a unique hive id per 756 * device based on the pci device location if device is in PCIe mode. 757 */ 758 if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1) 759 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 760 761 kfd->noretry = kfd->adev->gmc.noretry; 762 763 kfd_cwsr_init(kfd); 764 765 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 766 kfd->num_nodes); 767 768 /* Allocate the KFD nodes */ 769 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 770 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 771 if (!node) 772 goto node_alloc_error; 773 774 node->node_id = i; 775 node->adev = kfd->adev; 776 node->kfd = kfd; 777 node->kfd2kgd = kfd->kfd2kgd; 778 node->vm_info.vmid_num_kfd = vmid_num_kfd; 779 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 780 /* TODO : Check if error handling is needed */ 781 if (node->xcp) { 782 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 783 &node->xcc_mask); 784 ++xcp_idx; 785 } else { 786 node->xcc_mask = 787 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 788 } 789 790 if (node->xcp) { 791 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 792 node->node_id, node->xcp->mem_id, 793 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 794 } 795 796 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 797 partition_mode == AMDGPU_CPX_PARTITION_MODE && 798 kfd->num_nodes != 1) { 799 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 800 * 4-9 and second XCD gets VMID range 10-15. 801 */ 802 803 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 804 first_vmid_kfd : 805 first_vmid_kfd+vmid_num_kfd; 806 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 807 last_vmid_kfd-vmid_num_kfd : 808 last_vmid_kfd; 809 node->compute_vmid_bitmap = 810 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 811 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 812 } else { 813 node->vm_info.first_vmid_kfd = first_vmid_kfd; 814 node->vm_info.last_vmid_kfd = last_vmid_kfd; 815 node->compute_vmid_bitmap = 816 gpu_resources->compute_vmid_bitmap; 817 } 818 node->max_proc_per_quantum = max_proc_per_quantum; 819 atomic_set(&node->sram_ecc_flag, 0); 820 821 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 822 &node->local_mem_info, node->xcp); 823 824 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) 825 kfd_setup_interrupt_bitmap(node, i); 826 827 /* Initialize the KFD node */ 828 if (kfd_init_node(node)) { 829 dev_err(kfd_device, "Error initializing KFD node\n"); 830 goto node_init_error; 831 } 832 kfd->nodes[i] = node; 833 } 834 835 svm_range_set_max_pages(kfd->adev); 836 837 spin_lock_init(&kfd->watch_points_lock); 838 839 kfd->init_complete = true; 840 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 841 kfd->adev->pdev->device); 842 843 pr_debug("Starting kfd with the following scheduling policy %d\n", 844 node->dqm->sched_policy); 845 846 goto out; 847 848 node_init_error: 849 node_alloc_error: 850 kfd_cleanup_nodes(kfd, i); 851 kfd_doorbell_fini(kfd); 852 kfd_doorbell_error: 853 kfd_gtt_sa_fini(kfd); 854 kfd_gtt_sa_init_error: 855 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 856 alloc_gtt_mem_failure: 857 dev_err(kfd_device, 858 "device %x:%x NOT added due to errors\n", 859 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 860 out: 861 return kfd->init_complete; 862 } 863 864 void kgd2kfd_device_exit(struct kfd_dev *kfd) 865 { 866 if (kfd->init_complete) { 867 /* Cleanup KFD nodes */ 868 kfd_cleanup_nodes(kfd, kfd->num_nodes); 869 /* Cleanup common/shared resources */ 870 kfd_doorbell_fini(kfd); 871 ida_destroy(&kfd->doorbell_ida); 872 kfd_gtt_sa_fini(kfd); 873 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 874 } 875 876 kfree(kfd); 877 } 878 879 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 880 { 881 struct kfd_node *node; 882 int i; 883 884 if (!kfd->init_complete) 885 return 0; 886 887 for (i = 0; i < kfd->num_nodes; i++) { 888 node = kfd->nodes[i]; 889 kfd_smi_event_update_gpu_reset(node, false); 890 node->dqm->ops.pre_reset(node->dqm); 891 } 892 893 kgd2kfd_suspend(kfd, false); 894 895 for (i = 0; i < kfd->num_nodes; i++) 896 kfd_signal_reset_event(kfd->nodes[i]); 897 898 return 0; 899 } 900 901 /* 902 * Fix me. KFD won't be able to resume existing process for now. 903 * We will keep all existing process in a evicted state and 904 * wait the process to be terminated. 905 */ 906 907 int kgd2kfd_post_reset(struct kfd_dev *kfd) 908 { 909 int ret; 910 struct kfd_node *node; 911 int i; 912 913 if (!kfd->init_complete) 914 return 0; 915 916 for (i = 0; i < kfd->num_nodes; i++) { 917 ret = kfd_resume(kfd->nodes[i]); 918 if (ret) 919 return ret; 920 } 921 922 mutex_lock(&kfd_processes_mutex); 923 --kfd_locked; 924 mutex_unlock(&kfd_processes_mutex); 925 926 for (i = 0; i < kfd->num_nodes; i++) { 927 node = kfd->nodes[i]; 928 atomic_set(&node->sram_ecc_flag, 0); 929 kfd_smi_event_update_gpu_reset(node, true); 930 } 931 932 return 0; 933 } 934 935 bool kfd_is_locked(void) 936 { 937 lockdep_assert_held(&kfd_processes_mutex); 938 return (kfd_locked > 0); 939 } 940 941 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 942 { 943 struct kfd_node *node; 944 int i; 945 int count; 946 947 if (!kfd->init_complete) 948 return; 949 950 /* for runtime suspend, skip locking kfd */ 951 if (!run_pm) { 952 mutex_lock(&kfd_processes_mutex); 953 count = ++kfd_locked; 954 mutex_unlock(&kfd_processes_mutex); 955 956 /* For first KFD device suspend all the KFD processes */ 957 if (count == 1) 958 kfd_suspend_all_processes(); 959 } 960 961 for (i = 0; i < kfd->num_nodes; i++) { 962 node = kfd->nodes[i]; 963 node->dqm->ops.stop(node->dqm); 964 } 965 } 966 967 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 968 { 969 int ret, count, i; 970 971 if (!kfd->init_complete) 972 return 0; 973 974 for (i = 0; i < kfd->num_nodes; i++) { 975 ret = kfd_resume(kfd->nodes[i]); 976 if (ret) 977 return ret; 978 } 979 980 /* for runtime resume, skip unlocking kfd */ 981 if (!run_pm) { 982 mutex_lock(&kfd_processes_mutex); 983 count = --kfd_locked; 984 mutex_unlock(&kfd_processes_mutex); 985 986 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 987 if (count == 0) 988 ret = kfd_resume_all_processes(); 989 } 990 991 return ret; 992 } 993 994 static int kfd_resume(struct kfd_node *node) 995 { 996 int err = 0; 997 998 err = node->dqm->ops.start(node->dqm); 999 if (err) 1000 dev_err(kfd_device, 1001 "Error starting queue manager for device %x:%x\n", 1002 node->adev->pdev->vendor, node->adev->pdev->device); 1003 1004 return err; 1005 } 1006 1007 static inline void kfd_queue_work(struct workqueue_struct *wq, 1008 struct work_struct *work) 1009 { 1010 int cpu, new_cpu; 1011 1012 cpu = new_cpu = smp_processor_id(); 1013 do { 1014 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1015 if (cpu_to_node(new_cpu) == numa_node_id()) 1016 break; 1017 } while (cpu != new_cpu); 1018 1019 queue_work_on(new_cpu, wq, work); 1020 } 1021 1022 /* This is called directly from KGD at ISR. */ 1023 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1024 { 1025 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1026 bool is_patched = false; 1027 unsigned long flags; 1028 struct kfd_node *node; 1029 1030 if (!kfd->init_complete) 1031 return; 1032 1033 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1034 dev_err_once(kfd_device, "Ring entry too small\n"); 1035 return; 1036 } 1037 1038 for (i = 0; i < kfd->num_nodes; i++) { 1039 node = kfd->nodes[i]; 1040 spin_lock_irqsave(&node->interrupt_lock, flags); 1041 1042 if (node->interrupts_active 1043 && interrupt_is_wanted(node, ih_ring_entry, 1044 patched_ihre, &is_patched) 1045 && enqueue_ih_ring_entry(node, 1046 is_patched ? patched_ihre : ih_ring_entry)) { 1047 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1048 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1049 return; 1050 } 1051 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1052 } 1053 1054 } 1055 1056 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1057 { 1058 struct kfd_process *p; 1059 int r; 1060 1061 /* Because we are called from arbitrary context (workqueue) as opposed 1062 * to process context, kfd_process could attempt to exit while we are 1063 * running so the lookup function increments the process ref count. 1064 */ 1065 p = kfd_lookup_process_by_mm(mm); 1066 if (!p) 1067 return -ESRCH; 1068 1069 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1070 r = kfd_process_evict_queues(p, trigger); 1071 1072 kfd_unref_process(p); 1073 return r; 1074 } 1075 1076 int kgd2kfd_resume_mm(struct mm_struct *mm) 1077 { 1078 struct kfd_process *p; 1079 int r; 1080 1081 /* Because we are called from arbitrary context (workqueue) as opposed 1082 * to process context, kfd_process could attempt to exit while we are 1083 * running so the lookup function increments the process ref count. 1084 */ 1085 p = kfd_lookup_process_by_mm(mm); 1086 if (!p) 1087 return -ESRCH; 1088 1089 r = kfd_process_restore_queues(p); 1090 1091 kfd_unref_process(p); 1092 return r; 1093 } 1094 1095 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1096 * prepare for safe eviction of KFD BOs that belong to the specified 1097 * process. 1098 * 1099 * @mm: mm_struct that identifies the specified KFD process 1100 * @fence: eviction fence attached to KFD process BOs 1101 * 1102 */ 1103 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1104 struct dma_fence *fence) 1105 { 1106 struct kfd_process *p; 1107 unsigned long active_time; 1108 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1109 1110 if (!fence) 1111 return -EINVAL; 1112 1113 if (dma_fence_is_signaled(fence)) 1114 return 0; 1115 1116 p = kfd_lookup_process_by_mm(mm); 1117 if (!p) 1118 return -ENODEV; 1119 1120 if (fence->seqno == p->last_eviction_seqno) 1121 goto out; 1122 1123 p->last_eviction_seqno = fence->seqno; 1124 1125 /* Avoid KFD process starvation. Wait for at least 1126 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1127 */ 1128 active_time = get_jiffies_64() - p->last_restore_timestamp; 1129 if (delay_jiffies > active_time) 1130 delay_jiffies -= active_time; 1131 else 1132 delay_jiffies = 0; 1133 1134 /* During process initialization eviction_work.dwork is initialized 1135 * to kfd_evict_bo_worker 1136 */ 1137 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1138 p->lead_thread->pid, delay_jiffies); 1139 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1140 out: 1141 kfd_unref_process(p); 1142 return 0; 1143 } 1144 1145 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1146 unsigned int chunk_size) 1147 { 1148 if (WARN_ON(buf_size < chunk_size)) 1149 return -EINVAL; 1150 if (WARN_ON(buf_size == 0)) 1151 return -EINVAL; 1152 if (WARN_ON(chunk_size == 0)) 1153 return -EINVAL; 1154 1155 kfd->gtt_sa_chunk_size = chunk_size; 1156 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1157 1158 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1159 GFP_KERNEL); 1160 if (!kfd->gtt_sa_bitmap) 1161 return -ENOMEM; 1162 1163 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1164 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1165 1166 mutex_init(&kfd->gtt_sa_lock); 1167 1168 return 0; 1169 } 1170 1171 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1172 { 1173 mutex_destroy(&kfd->gtt_sa_lock); 1174 bitmap_free(kfd->gtt_sa_bitmap); 1175 } 1176 1177 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1178 unsigned int bit_num, 1179 unsigned int chunk_size) 1180 { 1181 return start_addr + bit_num * chunk_size; 1182 } 1183 1184 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1185 unsigned int bit_num, 1186 unsigned int chunk_size) 1187 { 1188 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1189 } 1190 1191 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1192 struct kfd_mem_obj **mem_obj) 1193 { 1194 unsigned int found, start_search, cur_size; 1195 struct kfd_dev *kfd = node->kfd; 1196 1197 if (size == 0) 1198 return -EINVAL; 1199 1200 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1201 return -ENOMEM; 1202 1203 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1204 if (!(*mem_obj)) 1205 return -ENOMEM; 1206 1207 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1208 1209 start_search = 0; 1210 1211 mutex_lock(&kfd->gtt_sa_lock); 1212 1213 kfd_gtt_restart_search: 1214 /* Find the first chunk that is free */ 1215 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1216 kfd->gtt_sa_num_of_chunks, 1217 start_search); 1218 1219 pr_debug("Found = %d\n", found); 1220 1221 /* If there wasn't any free chunk, bail out */ 1222 if (found == kfd->gtt_sa_num_of_chunks) 1223 goto kfd_gtt_no_free_chunk; 1224 1225 /* Update fields of mem_obj */ 1226 (*mem_obj)->range_start = found; 1227 (*mem_obj)->range_end = found; 1228 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1229 kfd->gtt_start_gpu_addr, 1230 found, 1231 kfd->gtt_sa_chunk_size); 1232 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1233 kfd->gtt_start_cpu_ptr, 1234 found, 1235 kfd->gtt_sa_chunk_size); 1236 1237 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1238 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1239 1240 /* If we need only one chunk, mark it as allocated and get out */ 1241 if (size <= kfd->gtt_sa_chunk_size) { 1242 pr_debug("Single bit\n"); 1243 __set_bit(found, kfd->gtt_sa_bitmap); 1244 goto kfd_gtt_out; 1245 } 1246 1247 /* Otherwise, try to see if we have enough contiguous chunks */ 1248 cur_size = size - kfd->gtt_sa_chunk_size; 1249 do { 1250 (*mem_obj)->range_end = 1251 find_next_zero_bit(kfd->gtt_sa_bitmap, 1252 kfd->gtt_sa_num_of_chunks, ++found); 1253 /* 1254 * If next free chunk is not contiguous than we need to 1255 * restart our search from the last free chunk we found (which 1256 * wasn't contiguous to the previous ones 1257 */ 1258 if ((*mem_obj)->range_end != found) { 1259 start_search = found; 1260 goto kfd_gtt_restart_search; 1261 } 1262 1263 /* 1264 * If we reached end of buffer, bail out with error 1265 */ 1266 if (found == kfd->gtt_sa_num_of_chunks) 1267 goto kfd_gtt_no_free_chunk; 1268 1269 /* Check if we don't need another chunk */ 1270 if (cur_size <= kfd->gtt_sa_chunk_size) 1271 cur_size = 0; 1272 else 1273 cur_size -= kfd->gtt_sa_chunk_size; 1274 1275 } while (cur_size > 0); 1276 1277 pr_debug("range_start = %d, range_end = %d\n", 1278 (*mem_obj)->range_start, (*mem_obj)->range_end); 1279 1280 /* Mark the chunks as allocated */ 1281 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1282 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1283 1284 kfd_gtt_out: 1285 mutex_unlock(&kfd->gtt_sa_lock); 1286 return 0; 1287 1288 kfd_gtt_no_free_chunk: 1289 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1290 mutex_unlock(&kfd->gtt_sa_lock); 1291 kfree(*mem_obj); 1292 return -ENOMEM; 1293 } 1294 1295 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1296 { 1297 struct kfd_dev *kfd = node->kfd; 1298 1299 /* Act like kfree when trying to free a NULL object */ 1300 if (!mem_obj) 1301 return 0; 1302 1303 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1304 mem_obj, mem_obj->range_start, mem_obj->range_end); 1305 1306 mutex_lock(&kfd->gtt_sa_lock); 1307 1308 /* Mark the chunks as free */ 1309 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1310 mem_obj->range_end - mem_obj->range_start + 1); 1311 1312 mutex_unlock(&kfd->gtt_sa_lock); 1313 1314 kfree(mem_obj); 1315 return 0; 1316 } 1317 1318 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1319 { 1320 /* 1321 * TODO: Currently update SRAM ECC flag for first node. 1322 * This needs to be updated later when we can 1323 * identify SRAM ECC error on other nodes also. 1324 */ 1325 if (kfd) 1326 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1327 } 1328 1329 void kfd_inc_compute_active(struct kfd_node *node) 1330 { 1331 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1332 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1333 } 1334 1335 void kfd_dec_compute_active(struct kfd_node *node) 1336 { 1337 int count = atomic_dec_return(&node->kfd->compute_profile); 1338 1339 if (count == 0) 1340 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1341 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1342 } 1343 1344 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1345 { 1346 /* 1347 * TODO: For now, raise the throttling event only on first node. 1348 * This will need to change after we are able to determine 1349 * which node raised the throttling event. 1350 */ 1351 if (kfd && kfd->init_complete) 1352 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1353 throttle_bitmask); 1354 } 1355 1356 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1357 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1358 * When the device has more than two engines, we reserve two for PCIe to enable 1359 * full-duplex and the rest are used as XGMI. 1360 */ 1361 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1362 { 1363 /* If XGMI is not supported, all SDMA engines are PCIe */ 1364 if (!node->adev->gmc.xgmi.supported) 1365 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1366 1367 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1368 } 1369 1370 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1371 { 1372 /* After reserved for PCIe, the rest of engines are XGMI */ 1373 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1374 kfd_get_num_sdma_engines(node); 1375 } 1376 1377 int kgd2kfd_check_and_lock_kfd(void) 1378 { 1379 mutex_lock(&kfd_processes_mutex); 1380 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1381 mutex_unlock(&kfd_processes_mutex); 1382 return -EBUSY; 1383 } 1384 1385 ++kfd_locked; 1386 mutex_unlock(&kfd_processes_mutex); 1387 1388 return 0; 1389 } 1390 1391 void kgd2kfd_unlock_kfd(void) 1392 { 1393 mutex_lock(&kfd_processes_mutex); 1394 --kfd_locked; 1395 mutex_unlock(&kfd_processes_mutex); 1396 } 1397 1398 #if defined(CONFIG_DEBUG_FS) 1399 1400 /* This function will send a package to HIQ to hang the HWS 1401 * which will trigger a GPU reset and bring the HWS back to normal state 1402 */ 1403 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1404 { 1405 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1406 pr_err("HWS is not enabled"); 1407 return -EINVAL; 1408 } 1409 1410 return dqm_debugfs_hang_hws(dev->dqm); 1411 } 1412 1413 #endif 1414