1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 extern const struct kfd2kgd_calls gfx_v12_1_kfd2kgd; 61 62 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 63 unsigned int chunk_size); 64 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 65 66 static int kfd_resume(struct kfd_node *kfd); 67 68 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 69 { 70 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 71 72 switch (sdma_version) { 73 case IP_VERSION(4, 0, 0):/* VEGA10 */ 74 case IP_VERSION(4, 0, 1):/* VEGA12 */ 75 case IP_VERSION(4, 1, 0):/* RAVEN */ 76 case IP_VERSION(4, 1, 1):/* RAVEN */ 77 case IP_VERSION(4, 1, 2):/* RENOIR */ 78 case IP_VERSION(5, 2, 1):/* VANGOGH */ 79 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 80 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 81 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 82 kfd->device_info.num_sdma_queues_per_engine = 2; 83 break; 84 case IP_VERSION(4, 2, 0):/* VEGA20 */ 85 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 86 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 87 case IP_VERSION(4, 4, 2): 88 case IP_VERSION(4, 4, 5): 89 case IP_VERSION(4, 4, 4): 90 case IP_VERSION(5, 0, 0):/* NAVI10 */ 91 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 92 case IP_VERSION(5, 0, 2):/* NAVI14 */ 93 case IP_VERSION(5, 0, 5):/* NAVI12 */ 94 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 95 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 96 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 97 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 98 kfd->device_info.num_sdma_queues_per_engine = 8; 99 break; 100 case IP_VERSION(6, 0, 0): 101 case IP_VERSION(6, 0, 1): 102 case IP_VERSION(6, 0, 2): 103 case IP_VERSION(6, 0, 3): 104 case IP_VERSION(6, 1, 0): 105 case IP_VERSION(6, 1, 1): 106 case IP_VERSION(6, 1, 2): 107 case IP_VERSION(6, 1, 3): 108 case IP_VERSION(6, 1, 4): 109 case IP_VERSION(6, 4, 0): 110 case IP_VERSION(7, 0, 0): 111 case IP_VERSION(7, 0, 1): 112 case IP_VERSION(7, 1, 0): 113 kfd->device_info.num_sdma_queues_per_engine = 8; 114 /* Reserve 1 for paging and 1 for gfx */ 115 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 116 break; 117 default: 118 dev_warn(kfd_device, 119 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 120 sdma_version); 121 kfd->device_info.num_sdma_queues_per_engine = 8; 122 } 123 } 124 125 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 126 { 127 uint32_t gc_version = KFD_GC_VERSION(kfd); 128 129 switch (gc_version) { 130 case IP_VERSION(9, 0, 1): /* VEGA10 */ 131 case IP_VERSION(9, 1, 0): /* RAVEN */ 132 case IP_VERSION(9, 2, 1): /* VEGA12 */ 133 case IP_VERSION(9, 2, 2): /* RAVEN */ 134 case IP_VERSION(9, 3, 0): /* RENOIR */ 135 case IP_VERSION(9, 4, 0): /* VEGA20 */ 136 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 137 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 138 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 139 break; 140 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 141 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 142 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */ 143 kfd->device_info.event_interrupt_class = 144 &event_interrupt_class_v9_4_3; 145 break; 146 case IP_VERSION(10, 3, 1): /* VANGOGH */ 147 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 148 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 149 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 150 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 151 case IP_VERSION(10, 1, 4): 152 case IP_VERSION(10, 1, 10): /* NAVI10 */ 153 case IP_VERSION(10, 1, 2): /* NAVI12 */ 154 case IP_VERSION(10, 1, 1): /* NAVI14 */ 155 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 156 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 157 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 158 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 159 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 160 break; 161 case IP_VERSION(11, 0, 0): 162 case IP_VERSION(11, 0, 1): 163 case IP_VERSION(11, 0, 2): 164 case IP_VERSION(11, 0, 3): 165 case IP_VERSION(11, 0, 4): 166 case IP_VERSION(11, 5, 0): 167 case IP_VERSION(11, 5, 1): 168 case IP_VERSION(11, 5, 2): 169 case IP_VERSION(11, 5, 3): 170 case IP_VERSION(11, 5, 4): 171 case IP_VERSION(11, 5, 6): 172 case IP_VERSION(11, 7, 0): 173 case IP_VERSION(11, 7, 1): 174 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 175 break; 176 case IP_VERSION(12, 0, 0): 177 case IP_VERSION(12, 0, 1): 178 /* GFX12_TODO: Change to v12 version. */ 179 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 180 break; 181 case IP_VERSION(12, 1, 0): 182 kfd->device_info.event_interrupt_class = 183 &event_interrupt_class_v12_1; 184 break; 185 default: 186 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 187 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 188 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 189 } 190 } 191 192 static void kfd_device_info_init(struct kfd_dev *kfd, 193 bool vf, uint32_t gfx_target_version) 194 { 195 uint32_t gc_version = KFD_GC_VERSION(kfd); 196 uint32_t asic_type = kfd->adev->asic_type; 197 198 kfd->device_info.max_pasid_bits = 16; 199 kfd->device_info.max_no_of_hqd = 24; 200 kfd->device_info.num_of_watch_points = 4; 201 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 202 kfd->device_info.gfx_target_version = gfx_target_version; 203 204 if (KFD_IS_SOC15(kfd)) { 205 kfd->device_info.doorbell_size = 8; 206 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 207 kfd->device_info.supports_cwsr = true; 208 209 kfd_device_info_set_sdma_info(kfd); 210 211 kfd_device_info_set_event_interrupt_class(kfd); 212 213 if (gc_version < IP_VERSION(11, 0, 0)) { 214 /* Navi2x+, Navi1x+ */ 215 if (gc_version == IP_VERSION(10, 3, 6)) 216 kfd->device_info.no_atomic_fw_version = 14; 217 else if (gc_version == IP_VERSION(10, 3, 7)) 218 kfd->device_info.no_atomic_fw_version = 3; 219 else if (gc_version >= IP_VERSION(10, 3, 0)) 220 kfd->device_info.no_atomic_fw_version = 92; 221 else if (gc_version >= IP_VERSION(10, 1, 1)) 222 kfd->device_info.no_atomic_fw_version = 145; 223 224 /* Navi1x+ */ 225 if (gc_version >= IP_VERSION(10, 1, 1)) 226 kfd->device_info.needs_pci_atomics = true; 227 } else if (gc_version < IP_VERSION(12, 0, 0)) { 228 /* 229 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 230 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 231 * PCIe atomics support. 232 */ 233 kfd->device_info.needs_pci_atomics = true; 234 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 235 } else if (gc_version < IP_VERSION(13, 0, 0)) { 236 kfd->device_info.needs_pci_atomics = true; 237 kfd->device_info.no_atomic_fw_version = 2090; 238 } else { 239 kfd->device_info.needs_pci_atomics = true; 240 } 241 } else { 242 kfd->device_info.doorbell_size = 4; 243 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 244 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 245 kfd->device_info.num_sdma_queues_per_engine = 2; 246 247 if (asic_type != CHIP_KAVERI && 248 asic_type != CHIP_HAWAII && 249 asic_type != CHIP_TONGA) 250 kfd->device_info.supports_cwsr = true; 251 252 if (asic_type != CHIP_HAWAII && !vf) 253 kfd->device_info.needs_pci_atomics = true; 254 } 255 } 256 257 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 258 { 259 struct kfd_dev *kfd = NULL; 260 const struct kfd2kgd_calls *f2g = NULL; 261 uint32_t gfx_target_version = 0; 262 263 switch (adev->asic_type) { 264 #ifdef CONFIG_DRM_AMDGPU_CIK 265 case CHIP_KAVERI: 266 gfx_target_version = 70000; 267 if (!vf) 268 f2g = &gfx_v7_kfd2kgd; 269 break; 270 #endif 271 case CHIP_CARRIZO: 272 gfx_target_version = 80001; 273 if (!vf) 274 f2g = &gfx_v8_kfd2kgd; 275 break; 276 #ifdef CONFIG_DRM_AMDGPU_CIK 277 case CHIP_HAWAII: 278 gfx_target_version = 70001; 279 if (!amdgpu_exp_hw_support) 280 pr_info( 281 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 282 ); 283 else if (!vf) 284 f2g = &gfx_v7_kfd2kgd; 285 break; 286 #endif 287 case CHIP_TONGA: 288 gfx_target_version = 80002; 289 if (!vf) 290 f2g = &gfx_v8_kfd2kgd; 291 break; 292 case CHIP_FIJI: 293 case CHIP_POLARIS10: 294 gfx_target_version = 80003; 295 f2g = &gfx_v8_kfd2kgd; 296 break; 297 case CHIP_POLARIS11: 298 case CHIP_POLARIS12: 299 case CHIP_VEGAM: 300 gfx_target_version = 80003; 301 if (!vf) 302 f2g = &gfx_v8_kfd2kgd; 303 break; 304 default: 305 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 306 /* Vega 10 */ 307 case IP_VERSION(9, 0, 1): 308 gfx_target_version = 90000; 309 f2g = &gfx_v9_kfd2kgd; 310 break; 311 /* Raven */ 312 case IP_VERSION(9, 1, 0): 313 case IP_VERSION(9, 2, 2): 314 gfx_target_version = 90002; 315 if (!vf) 316 f2g = &gfx_v9_kfd2kgd; 317 break; 318 /* Vega12 */ 319 case IP_VERSION(9, 2, 1): 320 gfx_target_version = 90004; 321 if (!vf) 322 f2g = &gfx_v9_kfd2kgd; 323 break; 324 /* Renoir */ 325 case IP_VERSION(9, 3, 0): 326 gfx_target_version = 90012; 327 if (!vf) 328 f2g = &gfx_v9_kfd2kgd; 329 break; 330 /* Vega20 */ 331 case IP_VERSION(9, 4, 0): 332 gfx_target_version = 90006; 333 if (!vf) 334 f2g = &gfx_v9_kfd2kgd; 335 break; 336 /* Arcturus */ 337 case IP_VERSION(9, 4, 1): 338 gfx_target_version = 90008; 339 f2g = &arcturus_kfd2kgd; 340 break; 341 /* Aldebaran */ 342 case IP_VERSION(9, 4, 2): 343 gfx_target_version = 90010; 344 f2g = &aldebaran_kfd2kgd; 345 break; 346 case IP_VERSION(9, 4, 3): 347 case IP_VERSION(9, 4, 4): 348 gfx_target_version = 90402; 349 f2g = &gc_9_4_3_kfd2kgd; 350 break; 351 case IP_VERSION(9, 5, 0): 352 gfx_target_version = 90500; 353 f2g = &gc_9_4_3_kfd2kgd; 354 break; 355 /* Navi10 */ 356 case IP_VERSION(10, 1, 10): 357 gfx_target_version = 100100; 358 if (!vf) 359 f2g = &gfx_v10_kfd2kgd; 360 break; 361 /* Navi12 */ 362 case IP_VERSION(10, 1, 2): 363 gfx_target_version = 100101; 364 f2g = &gfx_v10_kfd2kgd; 365 break; 366 /* Navi14 */ 367 case IP_VERSION(10, 1, 1): 368 gfx_target_version = 100102; 369 if (!vf) 370 f2g = &gfx_v10_kfd2kgd; 371 break; 372 /* Cyan Skillfish */ 373 case IP_VERSION(10, 1, 3): 374 case IP_VERSION(10, 1, 4): 375 gfx_target_version = 100103; 376 if (!vf) 377 f2g = &gfx_v10_kfd2kgd; 378 break; 379 /* Sienna Cichlid */ 380 case IP_VERSION(10, 3, 0): 381 gfx_target_version = 100300; 382 f2g = &gfx_v10_3_kfd2kgd; 383 break; 384 /* Navy Flounder */ 385 case IP_VERSION(10, 3, 2): 386 gfx_target_version = 100301; 387 f2g = &gfx_v10_3_kfd2kgd; 388 break; 389 /* Van Gogh */ 390 case IP_VERSION(10, 3, 1): 391 gfx_target_version = 100303; 392 if (!vf) 393 f2g = &gfx_v10_3_kfd2kgd; 394 break; 395 /* Dimgrey Cavefish */ 396 case IP_VERSION(10, 3, 4): 397 gfx_target_version = 100302; 398 f2g = &gfx_v10_3_kfd2kgd; 399 break; 400 /* Beige Goby */ 401 case IP_VERSION(10, 3, 5): 402 gfx_target_version = 100304; 403 f2g = &gfx_v10_3_kfd2kgd; 404 break; 405 /* Yellow Carp */ 406 case IP_VERSION(10, 3, 3): 407 gfx_target_version = 100305; 408 if (!vf) 409 f2g = &gfx_v10_3_kfd2kgd; 410 break; 411 case IP_VERSION(10, 3, 6): 412 case IP_VERSION(10, 3, 7): 413 gfx_target_version = 100306; 414 if (!vf) 415 f2g = &gfx_v10_3_kfd2kgd; 416 break; 417 case IP_VERSION(11, 0, 0): 418 gfx_target_version = 110000; 419 f2g = &gfx_v11_kfd2kgd; 420 break; 421 case IP_VERSION(11, 0, 1): 422 case IP_VERSION(11, 0, 4): 423 gfx_target_version = 110003; 424 f2g = &gfx_v11_kfd2kgd; 425 break; 426 case IP_VERSION(11, 0, 2): 427 gfx_target_version = 110002; 428 f2g = &gfx_v11_kfd2kgd; 429 break; 430 case IP_VERSION(11, 0, 3): 431 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 432 gfx_target_version = 110001; 433 f2g = &gfx_v11_kfd2kgd; 434 break; 435 case IP_VERSION(11, 5, 0): 436 gfx_target_version = 110500; 437 f2g = &gfx_v11_kfd2kgd; 438 break; 439 case IP_VERSION(11, 5, 1): 440 gfx_target_version = 110501; 441 f2g = &gfx_v11_kfd2kgd; 442 break; 443 case IP_VERSION(11, 5, 2): 444 gfx_target_version = 110502; 445 f2g = &gfx_v11_kfd2kgd; 446 break; 447 case IP_VERSION(11, 5, 3): 448 gfx_target_version = 110503; 449 f2g = &gfx_v11_kfd2kgd; 450 break; 451 case IP_VERSION(11, 5, 4): 452 case IP_VERSION(11, 5, 6): 453 gfx_target_version = 110504; 454 f2g = &gfx_v11_kfd2kgd; 455 break; 456 case IP_VERSION(11, 7, 0): 457 gfx_target_version = 110700; 458 f2g = &gfx_v11_kfd2kgd; 459 break; 460 case IP_VERSION(11, 7, 1): 461 gfx_target_version = 110701; 462 f2g = &gfx_v11_kfd2kgd; 463 break; 464 case IP_VERSION(12, 0, 0): 465 gfx_target_version = 120000; 466 f2g = &gfx_v12_kfd2kgd; 467 break; 468 case IP_VERSION(12, 0, 1): 469 gfx_target_version = 120001; 470 f2g = &gfx_v12_kfd2kgd; 471 break; 472 case IP_VERSION(12, 1, 0): 473 gfx_target_version = 120500; 474 f2g = &gfx_v12_1_kfd2kgd; 475 break; 476 default: 477 break; 478 } 479 break; 480 } 481 482 if (!f2g) { 483 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 484 dev_info(kfd_device, 485 "GC IP %06x %s not supported in kfd\n", 486 amdgpu_ip_version(adev, GC_HWIP, 0), 487 vf ? "VF" : ""); 488 else 489 dev_info(kfd_device, "%s %s not supported in kfd\n", 490 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 491 return NULL; 492 } 493 494 kfd = kzalloc_obj(*kfd); 495 if (!kfd) 496 return NULL; 497 498 kfd->adev = adev; 499 kfd_device_info_init(kfd, vf, gfx_target_version); 500 kfd->init_complete = false; 501 kfd->kfd2kgd = f2g; 502 atomic_set(&kfd->compute_profile, 0); 503 504 mutex_init(&kfd->doorbell_mutex); 505 506 ida_init(&kfd->doorbell_ida); 507 atomic_set(&kfd->kfd_processes_count, 0); 508 509 return kfd; 510 } 511 512 static void kfd_cwsr_init(struct kfd_dev *kfd) 513 { 514 if (cwsr_enable && kfd->device_info.supports_cwsr) { 515 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 516 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 517 > KFD_CWSR_TMA_OFFSET); 518 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 519 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 520 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 521 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 522 > KFD_CWSR_TMA_OFFSET); 523 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 524 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 525 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 526 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 527 > KFD_CWSR_TMA_OFFSET); 528 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 529 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 530 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 531 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 532 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 533 > KFD_CWSR_TMA_OFFSET); 534 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 535 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 536 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) { 537 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE); 538 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex; 539 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex); 540 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 541 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 542 > KFD_CWSR_TMA_OFFSET); 543 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 544 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 545 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 546 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 547 > KFD_CWSR_TMA_OFFSET); 548 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 549 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 550 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 551 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 552 > KFD_CWSR_TMA_OFFSET); 553 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 554 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 555 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 556 /* The gfx11 cwsr trap handler must fit inside a single 557 page. */ 558 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 559 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 560 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 561 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 1, 0)) { 562 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 563 > KFD_CWSR_TMA_OFFSET); 564 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 565 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 566 } else { 567 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_1_0_hex) 568 > KFD_CWSR_TMA_OFFSET); 569 kfd->cwsr_isa = cwsr_trap_gfx12_1_0_hex; 570 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_1_0_hex); 571 } 572 573 kfd->cwsr_enabled = true; 574 } 575 } 576 577 static int kfd_gws_init(struct kfd_node *node) 578 { 579 int ret = 0; 580 struct kfd_dev *kfd = node->kfd; 581 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 582 583 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 584 return 0; 585 586 if (hws_gws_support || (KFD_IS_SOC15(node) && 587 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 588 && kfd->mec2_fw_version >= 0x81b3) || 589 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 590 && kfd->mec2_fw_version >= 0x1b3) || 591 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 592 && kfd->mec2_fw_version >= 0x30) || 593 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 594 && kfd->mec2_fw_version >= 0x28) || 595 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 596 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 597 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) || 598 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 599 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 600 && kfd->mec2_fw_version >= 0x6b) || 601 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 602 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 603 && mes_rev >= 68) || 604 (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))))) { 605 if (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0)) 606 node->adev->gds.gws_size = 64; 607 ret = amdgpu_amdkfd_alloc_gws(node->adev, 608 node->adev->gds.gws_size, &node->gws); 609 } 610 611 return ret; 612 } 613 614 static void kfd_smi_init(struct kfd_node *dev) 615 { 616 INIT_LIST_HEAD(&dev->smi_clients); 617 spin_lock_init(&dev->smi_lock); 618 } 619 620 static int kfd_init_node(struct kfd_node *node) 621 { 622 int err = -1; 623 624 if (kfd_interrupt_init(node)) { 625 dev_err(kfd_device, "Error initializing interrupts\n"); 626 goto kfd_interrupt_error; 627 } 628 629 node->dqm = device_queue_manager_init(node); 630 if (!node->dqm) { 631 dev_err(kfd_device, "Error initializing queue manager\n"); 632 goto device_queue_manager_error; 633 } 634 635 if (kfd_gws_init(node)) { 636 dev_err(kfd_device, "Could not allocate %d gws\n", 637 node->adev->gds.gws_size); 638 goto gws_error; 639 } 640 641 if (kfd_resume(node)) 642 goto kfd_resume_error; 643 644 if (kfd_topology_add_device(node)) { 645 dev_err(kfd_device, "Error adding device to topology\n"); 646 goto kfd_topology_add_device_error; 647 } 648 649 kfd_smi_init(node); 650 651 return 0; 652 653 kfd_topology_add_device_error: 654 kfd_resume_error: 655 gws_error: 656 device_queue_manager_uninit(node->dqm); 657 device_queue_manager_error: 658 kfd_interrupt_exit(node); 659 kfd_interrupt_error: 660 if (node->gws) 661 amdgpu_amdkfd_free_gws(node->adev, node->gws); 662 663 /* Cleanup the node memory here */ 664 kfree(node); 665 return err; 666 } 667 668 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 669 { 670 struct kfd_node *knode; 671 unsigned int i; 672 673 /* 674 * flush_work ensures that there are no outstanding 675 * work-queue items that will access interrupt_ring. New work items 676 * can't be created because we stopped interrupt handling above. 677 */ 678 flush_workqueue(kfd->ih_wq); 679 destroy_workqueue(kfd->ih_wq); 680 681 for (i = 0; i < num_nodes; i++) { 682 knode = kfd->nodes[i]; 683 device_queue_manager_uninit(knode->dqm); 684 kfd_interrupt_exit(knode); 685 kfd_topology_remove_device(knode); 686 if (knode->gws) 687 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 688 kfree(knode); 689 kfd->nodes[i] = NULL; 690 } 691 } 692 693 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 694 unsigned int kfd_node_idx) 695 { 696 struct amdgpu_device *adev = node->adev; 697 uint32_t xcc_mask = node->xcc_mask; 698 uint32_t xcc, mapped_xcc; 699 uint32_t bitmap; 700 /* 701 * Interrupt bitmap is setup for processing interrupts from 702 * different XCDs and AIDs. 703 * Interrupt bitmap is defined as follows: 704 * 1. Bits 0-15 - correspond to the NodeId field. 705 * Each bit corresponds to NodeId number. For example, if 706 * a KFD node has interrupt bitmap set to 0x7, then this 707 * KFD node will process interrupts with NodeId = 0, 1 and 2 708 * in the IH cookie. 709 * 2. Bits 16-31 - unused. 710 * 711 * Please note that the kfd_node_idx argument passed to this 712 * function is not related to NodeId field received in the 713 * IH cookie. 714 * 715 * In CPX mode, a KFD node will process an interrupt if: 716 * - the Node Id matches the corresponding bit set in 717 * Bits 0-15. 718 * - AND VMID reported in the interrupt lies within the 719 * VMID range of the node. 720 */ 721 switch (KFD_GC_VERSION(node)) { 722 case IP_VERSION(12, 1, 0): 723 for_each_inst(xcc, xcc_mask) { 724 mapped_xcc = GET_INST(GC, xcc); 725 bitmap = 0x2 | (0x4 << (mapped_xcc % 4)); 726 if (mapped_xcc/4) 727 bitmap = bitmap << 8; 728 node->interrupt_bitmap |= bitmap; 729 } 730 break; 731 default: 732 for_each_inst(xcc, xcc_mask) { 733 mapped_xcc = GET_INST(GC, xcc); 734 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 735 } 736 break; 737 } 738 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 739 node->interrupt_bitmap); 740 } 741 742 bool kgd2kfd_device_init(struct kfd_dev *kfd, 743 const struct kgd2kfd_shared_resources *gpu_resources) 744 { 745 unsigned int size, map_process_packet_size, i; 746 struct kfd_node *node; 747 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 748 unsigned int max_proc_per_quantum; 749 int partition_mode; 750 int xcp_idx; 751 752 kfd->profiler_process = NULL; 753 mutex_init(&kfd->profiler_lock); 754 755 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 756 KGD_ENGINE_MEC1); 757 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 758 KGD_ENGINE_MEC2); 759 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 760 KGD_ENGINE_SDMA1); 761 kfd->shared_resources = *gpu_resources; 762 763 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 764 765 if (kfd->num_nodes == 0) { 766 dev_err(kfd_device, 767 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 768 kfd->adev->gfx.num_xcc_per_xcp); 769 goto out; 770 } 771 772 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 773 * 32 and 64-bit requests are possible and must be 774 * supported. 775 */ 776 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 777 if (!kfd->pci_atomic_requested && 778 kfd->device_info.needs_pci_atomics && 779 (!kfd->device_info.no_atomic_fw_version || 780 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 781 dev_info(kfd_device, 782 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 783 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 784 kfd->mec_fw_version, 785 kfd->device_info.no_atomic_fw_version); 786 return false; 787 } 788 789 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 790 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 791 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 792 793 /* For multi-partition capable GPUs, we need special handling for VMIDs 794 * depending on partition mode. 795 * In CPX mode, the VMID range needs to be shared between XCDs. 796 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 797 * divide them equally, we change starting VMID to 4 and not use 798 * VMID 3. 799 * If the VMID range changes for multi-partition capable GPUs, then 800 * this code MUST be revisited. 801 */ 802 if (kfd->adev->xcp_mgr && (KFD_GC_VERSION(kfd) != IP_VERSION(12, 1, 0))) { 803 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 804 AMDGPU_XCP_FL_LOCKED); 805 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 806 kfd->num_nodes != 1) { 807 vmid_num_kfd /= 2; 808 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 809 } 810 } 811 812 /* Verify module parameters regarding mapped process number*/ 813 if (hws_max_conc_proc >= 0) 814 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 815 else 816 max_proc_per_quantum = vmid_num_kfd; 817 818 /* calculate max size of mqds needed for queues */ 819 size = max_num_of_queues_per_device * 820 kfd->device_info.mqd_size_aligned; 821 822 /* 823 * calculate max size of runlist packet. 824 * There can be only 2 packets at once 825 */ 826 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 827 sizeof(struct pm4_mes_map_process_aldebaran) : 828 sizeof(struct pm4_mes_map_process); 829 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 830 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 831 + sizeof(struct pm4_mes_runlist)) * 2; 832 833 /* Add size of HIQ & DIQ */ 834 size += KFD_KERNEL_QUEUE_SIZE * 2; 835 836 /* add another 512KB for all other allocations on gart (HPD, fences) */ 837 size += 512 * 1024; 838 839 if (amdgpu_amdkfd_alloc_kernel_mem( 840 kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT, 841 &kfd->gtt_mem, 842 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 843 false)) { 844 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 845 goto alloc_kernel_mem_failure; 846 } 847 848 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 849 850 /* Initialize GTT sa with 512 byte chunk size */ 851 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 852 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 853 goto kfd_gtt_sa_init_error; 854 } 855 856 if (kfd_doorbell_init(kfd)) { 857 dev_err(kfd_device, 858 "Error initializing doorbell aperture\n"); 859 goto kfd_doorbell_error; 860 } 861 862 if (amdgpu_use_xgmi_p2p) 863 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 864 865 /* 866 * For multi-partition capable GPUs, the KFD abstracts all partitions 867 * within a socket as xGMI connected in the topology so assign a unique 868 * hive id per device based on the pci device location if device is in 869 * PCIe mode. 870 */ 871 if (!kfd->hive_id && kfd->num_nodes > 1) 872 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 873 874 kfd->noretry = kfd->adev->gmc.noretry; 875 876 kfd_cwsr_init(kfd); 877 878 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 879 kfd->num_nodes); 880 881 /* Allocate the KFD nodes */ 882 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 883 node = kzalloc_obj(struct kfd_node); 884 if (!node) 885 goto node_alloc_error; 886 887 node->node_id = i; 888 node->adev = kfd->adev; 889 node->kfd = kfd; 890 node->kfd2kgd = kfd->kfd2kgd; 891 node->vm_info.vmid_num_kfd = vmid_num_kfd; 892 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 893 /* TODO : Check if error handling is needed */ 894 if (node->xcp) { 895 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 896 &node->xcc_mask); 897 ++xcp_idx; 898 } else { 899 node->xcc_mask = 900 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 901 } 902 903 if (node->xcp) { 904 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 905 node->node_id, node->xcp->mem_id, 906 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 907 } 908 909 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 910 kfd->num_nodes != 1 && 911 (KFD_GC_VERSION(kfd) != IP_VERSION(12, 1, 0))) { 912 /* For multi-partition capable GPUs and CPX mode, first 913 * XCD gets VMID range 4-9 and second XCD gets VMID 914 * range 10-15. 915 */ 916 917 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 918 first_vmid_kfd : 919 first_vmid_kfd+vmid_num_kfd; 920 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 921 last_vmid_kfd-vmid_num_kfd : 922 last_vmid_kfd; 923 node->compute_vmid_bitmap = 924 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 925 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 926 } else { 927 node->vm_info.first_vmid_kfd = first_vmid_kfd; 928 node->vm_info.last_vmid_kfd = last_vmid_kfd; 929 node->compute_vmid_bitmap = 930 gpu_resources->compute_vmid_bitmap; 931 } 932 933 node->max_proc_per_quantum = max_proc_per_quantum; 934 atomic_set(&node->sram_ecc_flag, 0); 935 936 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 937 &node->local_mem_info, node->xcp); 938 939 if (kfd->adev->xcp_mgr) 940 kfd_setup_interrupt_bitmap(node, i); 941 942 /* Initialize the KFD node */ 943 if (kfd_init_node(node)) { 944 dev_err(kfd_device, "Error initializing KFD node\n"); 945 goto node_init_error; 946 } 947 948 spin_lock_init(&node->watch_points_lock); 949 950 kfd->nodes[i] = node; 951 } 952 953 svm_range_set_max_pages(kfd->adev); 954 955 kfd->init_complete = true; 956 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 957 kfd->adev->pdev->device); 958 959 pr_debug("Starting kfd with the following scheduling policy %d\n", 960 node->dqm->sched_policy); 961 962 goto out; 963 964 node_init_error: 965 node_alloc_error: 966 kfd_cleanup_nodes(kfd, i); 967 kfd_doorbell_fini(kfd); 968 kfd_doorbell_error: 969 kfd_gtt_sa_fini(kfd); 970 kfd_gtt_sa_init_error: 971 amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); 972 alloc_kernel_mem_failure: 973 dev_err(kfd_device, 974 "device %x:%x NOT added due to errors\n", 975 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 976 out: 977 return kfd->init_complete; 978 } 979 980 void kgd2kfd_device_exit(struct kfd_dev *kfd) 981 { 982 if (kfd->init_complete) { 983 /* Cleanup KFD nodes */ 984 kfd_cleanup_nodes(kfd, kfd->num_nodes); 985 /* Cleanup common/shared resources */ 986 kfd_doorbell_fini(kfd); 987 ida_destroy(&kfd->doorbell_ida); 988 kfd_gtt_sa_fini(kfd); 989 amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); 990 mutex_destroy(&kfd->profiler_lock); 991 } 992 993 kfree(kfd); 994 995 /* after remove a kfd device unlock kfd driver */ 996 kgd2kfd_unlock_kfd(NULL); 997 } 998 999 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 1000 struct amdgpu_reset_context *reset_context) 1001 { 1002 struct kfd_node *node; 1003 int i; 1004 1005 if (!kfd->init_complete) 1006 return 0; 1007 1008 for (i = 0; i < kfd->num_nodes; i++) { 1009 node = kfd->nodes[i]; 1010 kfd_smi_event_update_gpu_reset(node, false, reset_context); 1011 } 1012 1013 kgd2kfd_suspend(kfd, true); 1014 1015 for (i = 0; i < kfd->num_nodes; i++) 1016 kfd_signal_reset_event(kfd->nodes[i]); 1017 1018 return 0; 1019 } 1020 1021 /* 1022 * Fix me. KFD won't be able to resume existing process for now. 1023 * We will keep all existing process in a evicted state and 1024 * wait the process to be terminated. 1025 */ 1026 1027 int kgd2kfd_post_reset(struct kfd_dev *kfd) 1028 { 1029 int ret; 1030 struct kfd_node *node; 1031 int i; 1032 1033 if (!kfd->init_complete) 1034 return 0; 1035 1036 for (i = 0; i < kfd->num_nodes; i++) { 1037 ret = kfd_resume(kfd->nodes[i]); 1038 if (ret) 1039 return ret; 1040 } 1041 1042 mutex_lock(&kfd_processes_mutex); 1043 --kfd_locked; 1044 mutex_unlock(&kfd_processes_mutex); 1045 1046 for (i = 0; i < kfd->num_nodes; i++) { 1047 node = kfd->nodes[i]; 1048 atomic_set(&node->sram_ecc_flag, 0); 1049 kfd_smi_event_update_gpu_reset(node, true, NULL); 1050 } 1051 1052 return 0; 1053 } 1054 1055 bool kfd_is_locked(struct kfd_dev *kfd) 1056 { 1057 uint8_t id = 0; 1058 struct kfd_node *dev; 1059 1060 lockdep_assert_held(&kfd_processes_mutex); 1061 1062 /* check reset/suspend lock */ 1063 if (kfd_locked > 0) 1064 return true; 1065 1066 if (kfd) 1067 return kfd->kfd_dev_lock > 0; 1068 1069 /* check lock on all cgroup accessible devices */ 1070 while (kfd_topology_enum_kfd_devices(id++, &dev) == 0) { 1071 if (!dev || kfd_devcgroup_check_permission(dev)) 1072 continue; 1073 1074 if (dev->kfd->kfd_dev_lock > 0) 1075 return true; 1076 } 1077 1078 return false; 1079 } 1080 1081 void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) 1082 { 1083 struct kfd_node *node; 1084 int i; 1085 1086 if (!kfd->init_complete) 1087 return; 1088 1089 if (suspend_proc) 1090 kgd2kfd_suspend_process(kfd); 1091 1092 for (i = 0; i < kfd->num_nodes; i++) { 1093 node = kfd->nodes[i]; 1094 node->dqm->ops.stop(node->dqm); 1095 } 1096 } 1097 1098 int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) 1099 { 1100 int ret = 0, i; 1101 1102 if (!kfd->init_complete) 1103 return 0; 1104 1105 for (i = 0; i < kfd->num_nodes; i++) { 1106 ret = kfd_resume(kfd->nodes[i]); 1107 if (ret) 1108 return ret; 1109 } 1110 1111 if (resume_proc) 1112 ret = kgd2kfd_resume_process(kfd); 1113 1114 return ret; 1115 } 1116 1117 void kgd2kfd_suspend_process(struct kfd_dev *kfd) 1118 { 1119 if (!kfd->init_complete) 1120 return; 1121 1122 mutex_lock(&kfd_processes_mutex); 1123 /* For first KFD device suspend all the KFD processes */ 1124 if (++kfd_locked == 1) 1125 kfd_suspend_all_processes(); 1126 mutex_unlock(&kfd_processes_mutex); 1127 } 1128 1129 int kgd2kfd_resume_process(struct kfd_dev *kfd) 1130 { 1131 int ret = 0; 1132 1133 if (!kfd->init_complete) 1134 return 0; 1135 1136 mutex_lock(&kfd_processes_mutex); 1137 if (--kfd_locked == 0) 1138 ret = kfd_resume_all_processes(); 1139 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1140 mutex_unlock(&kfd_processes_mutex); 1141 1142 return ret; 1143 } 1144 1145 static int kfd_resume(struct kfd_node *node) 1146 { 1147 int err = 0; 1148 1149 err = node->dqm->ops.start(node->dqm); 1150 if (err) 1151 dev_err(kfd_device, 1152 "Error starting queue manager for device %x:%x\n", 1153 node->adev->pdev->vendor, node->adev->pdev->device); 1154 1155 return err; 1156 } 1157 1158 /* This is called directly from KGD at ISR. */ 1159 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1160 { 1161 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1162 bool is_patched = false; 1163 unsigned long flags; 1164 struct kfd_node *node; 1165 1166 if (!kfd->init_complete) 1167 return; 1168 1169 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1170 dev_err_once(kfd_device, "Ring entry too small\n"); 1171 return; 1172 } 1173 1174 for (i = 0; i < kfd->num_nodes; i++) { 1175 /* Race if another thread in b/w 1176 * kfd_cleanup_nodes and kfree(kfd), 1177 * when kfd->nodes[i] = NULL 1178 */ 1179 if (kfd->nodes[i]) 1180 node = kfd->nodes[i]; 1181 else 1182 return; 1183 1184 spin_lock_irqsave(&node->interrupt_lock, flags); 1185 1186 if (node->interrupts_active 1187 && interrupt_is_wanted(node, ih_ring_entry, 1188 patched_ihre, &is_patched) 1189 && enqueue_ih_ring_entry(node, 1190 is_patched ? patched_ihre : ih_ring_entry)) { 1191 queue_work(node->kfd->ih_wq, &node->interrupt_work); 1192 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1193 return; 1194 } 1195 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1196 } 1197 1198 } 1199 1200 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1201 { 1202 struct kfd_process *p; 1203 int r; 1204 1205 /* Because we are called from arbitrary context (workqueue) as opposed 1206 * to process context, kfd_process could attempt to exit while we are 1207 * running so the lookup function increments the process ref count. 1208 */ 1209 p = kfd_lookup_process_by_mm(mm); 1210 if (!p) 1211 return -ESRCH; 1212 1213 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1214 r = kfd_process_evict_queues(p, trigger); 1215 1216 kfd_unref_process(p); 1217 return r; 1218 } 1219 1220 int kgd2kfd_resume_mm(struct mm_struct *mm) 1221 { 1222 struct kfd_process *p; 1223 int r; 1224 1225 /* Because we are called from arbitrary context (workqueue) as opposed 1226 * to process context, kfd_process could attempt to exit while we are 1227 * running so the lookup function increments the process ref count. 1228 */ 1229 p = kfd_lookup_process_by_mm(mm); 1230 if (!p) 1231 return -ESRCH; 1232 1233 r = kfd_process_restore_queues(p); 1234 1235 kfd_unref_process(p); 1236 return r; 1237 } 1238 1239 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1240 * prepare for safe eviction of KFD BOs that belong to the specified 1241 * process. 1242 * 1243 * @mm: mm_struct that identifies a group of KFD processes 1244 * @context_id: an id that identifies a specific KFD context in the above kfd process group 1245 * @fence: eviction fence attached to KFD process BOs 1246 * 1247 */ 1248 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1249 u16 context_id, struct dma_fence *fence) 1250 { 1251 struct kfd_process *p; 1252 unsigned long active_time; 1253 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1254 1255 if (!fence) 1256 return -EINVAL; 1257 1258 if (dma_fence_is_signaled(fence)) 1259 return 0; 1260 1261 p = kfd_lookup_process_by_id(mm, context_id); 1262 if (!p) 1263 return -ENODEV; 1264 1265 if (fence->seqno == p->last_eviction_seqno) 1266 goto out; 1267 1268 p->last_eviction_seqno = fence->seqno; 1269 1270 /* Avoid KFD process starvation. Wait for at least 1271 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1272 */ 1273 active_time = get_jiffies_64() - p->last_restore_timestamp; 1274 if (delay_jiffies > active_time) 1275 delay_jiffies -= active_time; 1276 else 1277 delay_jiffies = 0; 1278 1279 /* During process initialization eviction_work.dwork is initialized 1280 * to kfd_evict_bo_worker 1281 */ 1282 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1283 p->lead_thread->pid, delay_jiffies); 1284 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1285 out: 1286 kfd_unref_process(p); 1287 return 0; 1288 } 1289 1290 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1291 unsigned int chunk_size) 1292 { 1293 if (WARN_ON(buf_size < chunk_size)) 1294 return -EINVAL; 1295 if (WARN_ON(buf_size == 0)) 1296 return -EINVAL; 1297 if (WARN_ON(chunk_size == 0)) 1298 return -EINVAL; 1299 1300 kfd->gtt_sa_chunk_size = chunk_size; 1301 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1302 1303 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1304 GFP_KERNEL); 1305 if (!kfd->gtt_sa_bitmap) 1306 return -ENOMEM; 1307 1308 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1309 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1310 1311 mutex_init(&kfd->gtt_sa_lock); 1312 1313 return 0; 1314 } 1315 1316 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1317 { 1318 mutex_destroy(&kfd->gtt_sa_lock); 1319 bitmap_free(kfd->gtt_sa_bitmap); 1320 } 1321 1322 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1323 unsigned int bit_num, 1324 unsigned int chunk_size) 1325 { 1326 return start_addr + bit_num * chunk_size; 1327 } 1328 1329 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1330 unsigned int bit_num, 1331 unsigned int chunk_size) 1332 { 1333 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1334 } 1335 1336 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1337 struct kfd_mem_obj **mem_obj) 1338 { 1339 unsigned int found, start_search, cur_size; 1340 struct kfd_dev *kfd = node->kfd; 1341 1342 if (size == 0) 1343 return -EINVAL; 1344 1345 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1346 return -ENOMEM; 1347 1348 *mem_obj = kzalloc_obj(struct kfd_mem_obj); 1349 if (!(*mem_obj)) 1350 return -ENOMEM; 1351 1352 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1353 1354 start_search = 0; 1355 1356 mutex_lock(&kfd->gtt_sa_lock); 1357 1358 kfd_gtt_restart_search: 1359 /* Find the first chunk that is free */ 1360 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1361 kfd->gtt_sa_num_of_chunks, 1362 start_search); 1363 1364 pr_debug("Found = %d\n", found); 1365 1366 /* If there wasn't any free chunk, bail out */ 1367 if (found == kfd->gtt_sa_num_of_chunks) 1368 goto kfd_gtt_no_free_chunk; 1369 1370 /* Update fields of mem_obj */ 1371 (*mem_obj)->range_start = found; 1372 (*mem_obj)->range_end = found; 1373 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1374 kfd->gtt_start_gpu_addr, 1375 found, 1376 kfd->gtt_sa_chunk_size); 1377 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1378 kfd->gtt_start_cpu_ptr, 1379 found, 1380 kfd->gtt_sa_chunk_size); 1381 1382 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1383 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1384 1385 /* If we need only one chunk, mark it as allocated and get out */ 1386 if (size <= kfd->gtt_sa_chunk_size) { 1387 pr_debug("Single bit\n"); 1388 __set_bit(found, kfd->gtt_sa_bitmap); 1389 goto kfd_gtt_out; 1390 } 1391 1392 /* Otherwise, try to see if we have enough contiguous chunks */ 1393 cur_size = size - kfd->gtt_sa_chunk_size; 1394 do { 1395 (*mem_obj)->range_end = 1396 find_next_zero_bit(kfd->gtt_sa_bitmap, 1397 kfd->gtt_sa_num_of_chunks, ++found); 1398 /* 1399 * If next free chunk is not contiguous than we need to 1400 * restart our search from the last free chunk we found (which 1401 * wasn't contiguous to the previous ones 1402 */ 1403 if ((*mem_obj)->range_end != found) { 1404 start_search = found; 1405 goto kfd_gtt_restart_search; 1406 } 1407 1408 /* 1409 * If we reached end of buffer, bail out with error 1410 */ 1411 if (found == kfd->gtt_sa_num_of_chunks) 1412 goto kfd_gtt_no_free_chunk; 1413 1414 /* Check if we don't need another chunk */ 1415 if (cur_size <= kfd->gtt_sa_chunk_size) 1416 cur_size = 0; 1417 else 1418 cur_size -= kfd->gtt_sa_chunk_size; 1419 1420 } while (cur_size > 0); 1421 1422 pr_debug("range_start = %d, range_end = %d\n", 1423 (*mem_obj)->range_start, (*mem_obj)->range_end); 1424 1425 /* Mark the chunks as allocated */ 1426 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1427 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1428 1429 kfd_gtt_out: 1430 mutex_unlock(&kfd->gtt_sa_lock); 1431 return 0; 1432 1433 kfd_gtt_no_free_chunk: 1434 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1435 mutex_unlock(&kfd->gtt_sa_lock); 1436 kfree(*mem_obj); 1437 return -ENOMEM; 1438 } 1439 1440 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1441 { 1442 struct kfd_dev *kfd = node->kfd; 1443 1444 /* Act like kfree when trying to free a NULL object */ 1445 if (!mem_obj) 1446 return 0; 1447 1448 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1449 mem_obj, mem_obj->range_start, mem_obj->range_end); 1450 1451 mutex_lock(&kfd->gtt_sa_lock); 1452 1453 /* Mark the chunks as free */ 1454 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1455 mem_obj->range_end - mem_obj->range_start + 1); 1456 1457 mutex_unlock(&kfd->gtt_sa_lock); 1458 1459 kfree(mem_obj); 1460 return 0; 1461 } 1462 1463 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1464 { 1465 /* 1466 * TODO: Currently update SRAM ECC flag for first node. 1467 * This needs to be updated later when we can 1468 * identify SRAM ECC error on other nodes also. 1469 */ 1470 if (kfd) 1471 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1472 } 1473 1474 void kfd_inc_compute_active(struct kfd_node *node) 1475 { 1476 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1477 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1478 } 1479 1480 void kfd_dec_compute_active(struct kfd_node *node) 1481 { 1482 int count = atomic_dec_return(&node->kfd->compute_profile); 1483 1484 if (count == 0) 1485 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1486 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1487 } 1488 1489 static bool kfd_compute_active(struct kfd_node *node) 1490 { 1491 if (atomic_read(&node->kfd->compute_profile)) 1492 return true; 1493 return false; 1494 } 1495 1496 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1497 { 1498 /* 1499 * TODO: For now, raise the throttling event only on first node. 1500 * This will need to change after we are able to determine 1501 * which node raised the throttling event. 1502 */ 1503 if (kfd && kfd->init_complete) 1504 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1505 throttle_bitmask); 1506 } 1507 1508 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1509 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1510 * When the device has more than two engines, we reserve two for PCIe to enable 1511 * full-duplex and the rest are used as XGMI. 1512 */ 1513 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1514 { 1515 /* If XGMI is not supported, all SDMA engines are PCIe */ 1516 if (!node->adev->gmc.xgmi.supported) 1517 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1518 1519 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1520 } 1521 1522 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1523 { 1524 /* After reserved for PCIe, the rest of engines are XGMI */ 1525 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1526 kfd_get_num_sdma_engines(node); 1527 } 1528 1529 int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) 1530 { 1531 struct kfd_process *p; 1532 int r = 0, temp, idx; 1533 1534 mutex_lock(&kfd_processes_mutex); 1535 1536 /* kfd_processes_count is per kfd_dev, return -EBUSY without 1537 * further check 1538 */ 1539 if (!!atomic_read(&kfd->kfd_processes_count)) { 1540 pr_debug("process_wq_release not finished\n"); 1541 r = -EBUSY; 1542 goto out; 1543 } 1544 1545 if (hash_empty(kfd_processes_table) && !kfd_is_locked(kfd)) 1546 goto out; 1547 1548 /* fail under system reset/resume or kfd device is partition switching. */ 1549 if (kfd_is_locked(kfd)) { 1550 r = -EBUSY; 1551 goto out; 1552 } 1553 1554 /* 1555 * ensure all running processes are cgroup excluded from device before mode switch. 1556 * i.e. no pdd was created on the process socket. 1557 */ 1558 idx = srcu_read_lock(&kfd_processes_srcu); 1559 hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { 1560 int i; 1561 1562 for (i = 0; i < p->n_pdds; i++) { 1563 if (p->pdds[i]->dev->kfd != kfd) 1564 continue; 1565 1566 r = -EBUSY; 1567 goto proc_check_unlock; 1568 } 1569 } 1570 1571 proc_check_unlock: 1572 srcu_read_unlock(&kfd_processes_srcu, idx); 1573 out: 1574 if (!r) 1575 ++kfd->kfd_dev_lock; 1576 mutex_unlock(&kfd_processes_mutex); 1577 1578 return r; 1579 } 1580 1581 /* unlock a kfd dev or kfd driver */ 1582 void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) 1583 { 1584 mutex_lock(&kfd_processes_mutex); 1585 if (kfd) 1586 --kfd->kfd_dev_lock; 1587 else 1588 --kfd_locked; 1589 mutex_unlock(&kfd_processes_mutex); 1590 } 1591 1592 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1593 { 1594 struct kfd_node *node; 1595 int ret; 1596 1597 if (!kfd->init_complete) 1598 return 0; 1599 1600 if (node_id >= kfd->num_nodes) { 1601 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1602 node_id, kfd->num_nodes - 1); 1603 return -EINVAL; 1604 } 1605 node = kfd->nodes[node_id]; 1606 1607 ret = node->dqm->ops.unhalt(node->dqm); 1608 if (ret) 1609 dev_err(kfd_device, "Error in starting scheduler\n"); 1610 1611 return ret; 1612 } 1613 1614 int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) 1615 { 1616 struct kfd_node *node; 1617 int i, r; 1618 1619 if (!kfd->init_complete) 1620 return 0; 1621 1622 for (i = 0; i < kfd->num_nodes; i++) { 1623 node = kfd->nodes[i]; 1624 r = node->dqm->ops.unhalt(node->dqm); 1625 if (r) { 1626 dev_err(kfd_device, "Error in starting scheduler\n"); 1627 return r; 1628 } 1629 } 1630 return 0; 1631 } 1632 1633 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1634 { 1635 struct kfd_node *node; 1636 1637 if (!kfd->init_complete) 1638 return 0; 1639 1640 if (node_id >= kfd->num_nodes) { 1641 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1642 node_id, kfd->num_nodes - 1); 1643 return -EINVAL; 1644 } 1645 1646 node = kfd->nodes[node_id]; 1647 return node->dqm->ops.halt(node->dqm); 1648 } 1649 1650 int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) 1651 { 1652 struct kfd_node *node; 1653 int i, r; 1654 1655 if (!kfd->init_complete) 1656 return 0; 1657 1658 for (i = 0; i < kfd->num_nodes; i++) { 1659 node = kfd->nodes[i]; 1660 r = node->dqm->ops.halt(node->dqm); 1661 if (r) 1662 return r; 1663 } 1664 return 0; 1665 } 1666 1667 int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev) 1668 { 1669 if (!adev->kfd.init_complete) 1670 return 0; 1671 1672 return kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); 1673 } 1674 1675 int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev) 1676 { 1677 if (!adev->kfd.init_complete) 1678 return 0; 1679 1680 return kgd2kfd_start_sched_all_nodes(adev->kfd.dev); 1681 } 1682 1683 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1684 { 1685 struct kfd_node *node; 1686 1687 if (!kfd->init_complete) 1688 return false; 1689 1690 if (node_id >= kfd->num_nodes) { 1691 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1692 node_id, kfd->num_nodes - 1); 1693 return false; 1694 } 1695 1696 node = kfd->nodes[node_id]; 1697 1698 return kfd_compute_active(node); 1699 } 1700 1701 /** 1702 * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9 1703 * @adev: amdgpu device 1704 * @entry: vm fault interrupt vector 1705 * @retry_fault: if this is retry fault 1706 * 1707 * retry fault - 1708 * with CAM enabled, adev primary ring 1709 * | gmc_v9_0_process_interrupt() 1710 * adev soft_ring 1711 * | gmc_v9_0_process_interrupt() worker failed to recover page fault 1712 * KFD node ih_fifo 1713 * | KFD interrupt_wq worker 1714 * kfd_signal_vm_fault_event 1715 * 1716 * without CAM, adev primary ring1 1717 * | gmc_v9_0_process_interrupt worker failed to recvoer page fault 1718 * KFD node ih_fifo 1719 * | KFD interrupt_wq worker 1720 * kfd_signal_vm_fault_event 1721 * 1722 * no-retry fault - 1723 * adev primary ring 1724 * | gmc_v9_0_process_interrupt() 1725 * KFD node ih_fifo 1726 * | KFD interrupt_wq worker 1727 * kfd_signal_vm_fault_event 1728 * 1729 * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault 1730 * of same process, don't copy interrupt to KFD node ih_fifo. 1731 * With gdb debugger enabled, need convert the retry fault to no-retry fault for 1732 * debugger, cannot use the fast path. 1733 * 1734 * Return: 1735 * true - use the fast path to handle this fault 1736 * false - use normal path to handle it 1737 */ 1738 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 1739 bool retry_fault) 1740 { 1741 struct kfd_process *p; 1742 u32 cam_index; 1743 u32 src_data_idx; 1744 1745 src_data_idx = (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) ? 1746 3 : 2; 1747 1748 if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) { 1749 p = kfd_lookup_process_by_pasid(entry->pasid, NULL); 1750 if (!p) 1751 return true; 1752 1753 if (p->gpu_page_fault && !p->debug_trap_enabled) { 1754 if (retry_fault && adev->irq.retry_cam_enabled) { 1755 cam_index = entry->src_data[src_data_idx] & 0x3ff; 1756 1757 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 1758 } 1759 1760 kfd_unref_process(p); 1761 return true; 1762 } 1763 1764 /* 1765 * This is the first page fault, set flag and then signal user space 1766 */ 1767 p->gpu_page_fault = true; 1768 kfd_unref_process(p); 1769 } 1770 return false; 1771 } 1772 1773 /** kgd2kfd_teardown_processes - gracefully tear down existing 1774 * kfd processes that use adev 1775 * 1776 * @adev: amdgpu_device where kfd processes run on and will be 1777 * teardown 1778 * 1779 */ 1780 void kgd2kfd_teardown_processes(struct amdgpu_device *adev) 1781 { 1782 struct hlist_node *p_temp; 1783 struct kfd_process *p; 1784 struct kfd_node *dev; 1785 unsigned int temp; 1786 1787 mutex_lock(&kfd_processes_mutex); 1788 1789 if (hash_empty(kfd_processes_table)) { 1790 mutex_unlock(&kfd_processes_mutex); 1791 return; 1792 } 1793 1794 hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { 1795 for (int i = 0; i < p->n_pdds; i++) { 1796 dev = p->pdds[i]->dev; 1797 if (dev->adev == adev) 1798 kfd_signal_process_terminate_event(p); 1799 } 1800 } 1801 1802 mutex_unlock(&kfd_processes_mutex); 1803 1804 /* wait all kfd processes use adev terminate */ 1805 while (!!atomic_read(&adev->kfd.dev->kfd_processes_count)) 1806 cond_resched(); 1807 } 1808 1809 #if defined(CONFIG_DEBUG_FS) 1810 1811 /* This function will send a package to HIQ to hang the HWS 1812 * which will trigger a GPU reset and bring the HWS back to normal state 1813 */ 1814 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1815 { 1816 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1817 pr_err("HWS is not enabled"); 1818 return -EINVAL; 1819 } 1820 1821 if (dev->kfd->shared_resources.enable_mes) { 1822 dev_err(dev->adev->dev, "Inducing MES hang is not supported\n"); 1823 return -EINVAL; 1824 } 1825 1826 return dqm_debugfs_hang_hws(dev->dqm); 1827 } 1828 1829 #endif 1830