1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(4, 4, 5): 88 case IP_VERSION(4, 4, 4): 89 case IP_VERSION(5, 0, 0):/* NAVI10 */ 90 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 91 case IP_VERSION(5, 0, 2):/* NAVI14 */ 92 case IP_VERSION(5, 0, 5):/* NAVI12 */ 93 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 94 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 95 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 96 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 97 kfd->device_info.num_sdma_queues_per_engine = 8; 98 break; 99 case IP_VERSION(6, 0, 0): 100 case IP_VERSION(6, 0, 1): 101 case IP_VERSION(6, 0, 2): 102 case IP_VERSION(6, 0, 3): 103 case IP_VERSION(6, 1, 0): 104 case IP_VERSION(6, 1, 1): 105 case IP_VERSION(6, 1, 2): 106 case IP_VERSION(6, 1, 3): 107 case IP_VERSION(7, 0, 0): 108 case IP_VERSION(7, 0, 1): 109 case IP_VERSION(7, 1, 0): 110 kfd->device_info.num_sdma_queues_per_engine = 8; 111 /* Reserve 1 for paging and 1 for gfx */ 112 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 113 break; 114 default: 115 dev_warn(kfd_device, 116 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 117 sdma_version); 118 kfd->device_info.num_sdma_queues_per_engine = 8; 119 } 120 } 121 122 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 123 { 124 uint32_t gc_version = KFD_GC_VERSION(kfd); 125 126 switch (gc_version) { 127 case IP_VERSION(9, 0, 1): /* VEGA10 */ 128 case IP_VERSION(9, 1, 0): /* RAVEN */ 129 case IP_VERSION(9, 2, 1): /* VEGA12 */ 130 case IP_VERSION(9, 2, 2): /* RAVEN */ 131 case IP_VERSION(9, 3, 0): /* RENOIR */ 132 case IP_VERSION(9, 4, 0): /* VEGA20 */ 133 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 134 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 135 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 136 break; 137 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 138 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 139 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */ 140 kfd->device_info.event_interrupt_class = 141 &event_interrupt_class_v9_4_3; 142 break; 143 case IP_VERSION(10, 3, 1): /* VANGOGH */ 144 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 145 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 146 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 147 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 148 case IP_VERSION(10, 1, 4): 149 case IP_VERSION(10, 1, 10): /* NAVI10 */ 150 case IP_VERSION(10, 1, 2): /* NAVI12 */ 151 case IP_VERSION(10, 1, 1): /* NAVI14 */ 152 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 153 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 154 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 155 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 156 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 157 break; 158 case IP_VERSION(11, 0, 0): 159 case IP_VERSION(11, 0, 1): 160 case IP_VERSION(11, 0, 2): 161 case IP_VERSION(11, 0, 3): 162 case IP_VERSION(11, 0, 4): 163 case IP_VERSION(11, 5, 0): 164 case IP_VERSION(11, 5, 1): 165 case IP_VERSION(11, 5, 2): 166 case IP_VERSION(11, 5, 3): 167 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 168 break; 169 case IP_VERSION(12, 0, 0): 170 case IP_VERSION(12, 0, 1): 171 /* GFX12_TODO: Change to v12 version. */ 172 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 173 break; 174 default: 175 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 176 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 177 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 178 } 179 } 180 181 static void kfd_device_info_init(struct kfd_dev *kfd, 182 bool vf, uint32_t gfx_target_version) 183 { 184 uint32_t gc_version = KFD_GC_VERSION(kfd); 185 uint32_t asic_type = kfd->adev->asic_type; 186 187 kfd->device_info.max_pasid_bits = 16; 188 kfd->device_info.max_no_of_hqd = 24; 189 kfd->device_info.num_of_watch_points = 4; 190 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 191 kfd->device_info.gfx_target_version = gfx_target_version; 192 193 if (KFD_IS_SOC15(kfd)) { 194 kfd->device_info.doorbell_size = 8; 195 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 196 kfd->device_info.supports_cwsr = true; 197 198 kfd_device_info_set_sdma_info(kfd); 199 200 kfd_device_info_set_event_interrupt_class(kfd); 201 202 if (gc_version < IP_VERSION(11, 0, 0)) { 203 /* Navi2x+, Navi1x+ */ 204 if (gc_version == IP_VERSION(10, 3, 6)) 205 kfd->device_info.no_atomic_fw_version = 14; 206 else if (gc_version == IP_VERSION(10, 3, 7)) 207 kfd->device_info.no_atomic_fw_version = 3; 208 else if (gc_version >= IP_VERSION(10, 3, 0)) 209 kfd->device_info.no_atomic_fw_version = 92; 210 else if (gc_version >= IP_VERSION(10, 1, 1)) 211 kfd->device_info.no_atomic_fw_version = 145; 212 213 /* Navi1x+ */ 214 if (gc_version >= IP_VERSION(10, 1, 1)) 215 kfd->device_info.needs_pci_atomics = true; 216 } else if (gc_version < IP_VERSION(12, 0, 0)) { 217 /* 218 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 219 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 220 * PCIe atomics support. 221 */ 222 kfd->device_info.needs_pci_atomics = true; 223 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 224 } else if (gc_version < IP_VERSION(13, 0, 0)) { 225 kfd->device_info.needs_pci_atomics = true; 226 kfd->device_info.no_atomic_fw_version = 2090; 227 } else { 228 kfd->device_info.needs_pci_atomics = true; 229 } 230 } else { 231 kfd->device_info.doorbell_size = 4; 232 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 233 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 234 kfd->device_info.num_sdma_queues_per_engine = 2; 235 236 if (asic_type != CHIP_KAVERI && 237 asic_type != CHIP_HAWAII && 238 asic_type != CHIP_TONGA) 239 kfd->device_info.supports_cwsr = true; 240 241 if (asic_type != CHIP_HAWAII && !vf) 242 kfd->device_info.needs_pci_atomics = true; 243 } 244 } 245 246 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 247 { 248 struct kfd_dev *kfd = NULL; 249 const struct kfd2kgd_calls *f2g = NULL; 250 uint32_t gfx_target_version = 0; 251 252 switch (adev->asic_type) { 253 #ifdef CONFIG_DRM_AMDGPU_CIK 254 case CHIP_KAVERI: 255 gfx_target_version = 70000; 256 if (!vf) 257 f2g = &gfx_v7_kfd2kgd; 258 break; 259 #endif 260 case CHIP_CARRIZO: 261 gfx_target_version = 80001; 262 if (!vf) 263 f2g = &gfx_v8_kfd2kgd; 264 break; 265 #ifdef CONFIG_DRM_AMDGPU_CIK 266 case CHIP_HAWAII: 267 gfx_target_version = 70001; 268 if (!amdgpu_exp_hw_support) 269 pr_info( 270 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 271 ); 272 else if (!vf) 273 f2g = &gfx_v7_kfd2kgd; 274 break; 275 #endif 276 case CHIP_TONGA: 277 gfx_target_version = 80002; 278 if (!vf) 279 f2g = &gfx_v8_kfd2kgd; 280 break; 281 case CHIP_FIJI: 282 case CHIP_POLARIS10: 283 gfx_target_version = 80003; 284 f2g = &gfx_v8_kfd2kgd; 285 break; 286 case CHIP_POLARIS11: 287 case CHIP_POLARIS12: 288 case CHIP_VEGAM: 289 gfx_target_version = 80003; 290 if (!vf) 291 f2g = &gfx_v8_kfd2kgd; 292 break; 293 default: 294 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 295 /* Vega 10 */ 296 case IP_VERSION(9, 0, 1): 297 gfx_target_version = 90000; 298 f2g = &gfx_v9_kfd2kgd; 299 break; 300 /* Raven */ 301 case IP_VERSION(9, 1, 0): 302 case IP_VERSION(9, 2, 2): 303 gfx_target_version = 90002; 304 if (!vf) 305 f2g = &gfx_v9_kfd2kgd; 306 break; 307 /* Vega12 */ 308 case IP_VERSION(9, 2, 1): 309 gfx_target_version = 90004; 310 if (!vf) 311 f2g = &gfx_v9_kfd2kgd; 312 break; 313 /* Renoir */ 314 case IP_VERSION(9, 3, 0): 315 gfx_target_version = 90012; 316 if (!vf) 317 f2g = &gfx_v9_kfd2kgd; 318 break; 319 /* Vega20 */ 320 case IP_VERSION(9, 4, 0): 321 gfx_target_version = 90006; 322 if (!vf) 323 f2g = &gfx_v9_kfd2kgd; 324 break; 325 /* Arcturus */ 326 case IP_VERSION(9, 4, 1): 327 gfx_target_version = 90008; 328 f2g = &arcturus_kfd2kgd; 329 break; 330 /* Aldebaran */ 331 case IP_VERSION(9, 4, 2): 332 gfx_target_version = 90010; 333 f2g = &aldebaran_kfd2kgd; 334 break; 335 case IP_VERSION(9, 4, 3): 336 case IP_VERSION(9, 4, 4): 337 gfx_target_version = 90402; 338 f2g = &gc_9_4_3_kfd2kgd; 339 break; 340 case IP_VERSION(9, 5, 0): 341 gfx_target_version = 90500; 342 f2g = &gc_9_4_3_kfd2kgd; 343 break; 344 /* Navi10 */ 345 case IP_VERSION(10, 1, 10): 346 gfx_target_version = 100100; 347 if (!vf) 348 f2g = &gfx_v10_kfd2kgd; 349 break; 350 /* Navi12 */ 351 case IP_VERSION(10, 1, 2): 352 gfx_target_version = 100101; 353 f2g = &gfx_v10_kfd2kgd; 354 break; 355 /* Navi14 */ 356 case IP_VERSION(10, 1, 1): 357 gfx_target_version = 100102; 358 if (!vf) 359 f2g = &gfx_v10_kfd2kgd; 360 break; 361 /* Cyan Skillfish */ 362 case IP_VERSION(10, 1, 3): 363 case IP_VERSION(10, 1, 4): 364 gfx_target_version = 100103; 365 if (!vf) 366 f2g = &gfx_v10_kfd2kgd; 367 break; 368 /* Sienna Cichlid */ 369 case IP_VERSION(10, 3, 0): 370 gfx_target_version = 100300; 371 f2g = &gfx_v10_3_kfd2kgd; 372 break; 373 /* Navy Flounder */ 374 case IP_VERSION(10, 3, 2): 375 gfx_target_version = 100301; 376 f2g = &gfx_v10_3_kfd2kgd; 377 break; 378 /* Van Gogh */ 379 case IP_VERSION(10, 3, 1): 380 gfx_target_version = 100303; 381 if (!vf) 382 f2g = &gfx_v10_3_kfd2kgd; 383 break; 384 /* Dimgrey Cavefish */ 385 case IP_VERSION(10, 3, 4): 386 gfx_target_version = 100302; 387 f2g = &gfx_v10_3_kfd2kgd; 388 break; 389 /* Beige Goby */ 390 case IP_VERSION(10, 3, 5): 391 gfx_target_version = 100304; 392 f2g = &gfx_v10_3_kfd2kgd; 393 break; 394 /* Yellow Carp */ 395 case IP_VERSION(10, 3, 3): 396 gfx_target_version = 100305; 397 if (!vf) 398 f2g = &gfx_v10_3_kfd2kgd; 399 break; 400 case IP_VERSION(10, 3, 6): 401 case IP_VERSION(10, 3, 7): 402 gfx_target_version = 100306; 403 if (!vf) 404 f2g = &gfx_v10_3_kfd2kgd; 405 break; 406 case IP_VERSION(11, 0, 0): 407 gfx_target_version = 110000; 408 f2g = &gfx_v11_kfd2kgd; 409 break; 410 case IP_VERSION(11, 0, 1): 411 case IP_VERSION(11, 0, 4): 412 gfx_target_version = 110003; 413 f2g = &gfx_v11_kfd2kgd; 414 break; 415 case IP_VERSION(11, 0, 2): 416 gfx_target_version = 110002; 417 f2g = &gfx_v11_kfd2kgd; 418 break; 419 case IP_VERSION(11, 0, 3): 420 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 421 gfx_target_version = 110001; 422 f2g = &gfx_v11_kfd2kgd; 423 break; 424 case IP_VERSION(11, 5, 0): 425 gfx_target_version = 110500; 426 f2g = &gfx_v11_kfd2kgd; 427 break; 428 case IP_VERSION(11, 5, 1): 429 gfx_target_version = 110501; 430 f2g = &gfx_v11_kfd2kgd; 431 break; 432 case IP_VERSION(11, 5, 2): 433 gfx_target_version = 110502; 434 f2g = &gfx_v11_kfd2kgd; 435 break; 436 case IP_VERSION(11, 5, 3): 437 gfx_target_version = 110503; 438 f2g = &gfx_v11_kfd2kgd; 439 break; 440 case IP_VERSION(12, 0, 0): 441 gfx_target_version = 120000; 442 f2g = &gfx_v12_kfd2kgd; 443 break; 444 case IP_VERSION(12, 0, 1): 445 gfx_target_version = 120001; 446 f2g = &gfx_v12_kfd2kgd; 447 break; 448 default: 449 break; 450 } 451 break; 452 } 453 454 if (!f2g) { 455 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 456 dev_info(kfd_device, 457 "GC IP %06x %s not supported in kfd\n", 458 amdgpu_ip_version(adev, GC_HWIP, 0), 459 vf ? "VF" : ""); 460 else 461 dev_info(kfd_device, "%s %s not supported in kfd\n", 462 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 463 return NULL; 464 } 465 466 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 467 if (!kfd) 468 return NULL; 469 470 kfd->adev = adev; 471 kfd_device_info_init(kfd, vf, gfx_target_version); 472 kfd->init_complete = false; 473 kfd->kfd2kgd = f2g; 474 atomic_set(&kfd->compute_profile, 0); 475 476 mutex_init(&kfd->doorbell_mutex); 477 478 ida_init(&kfd->doorbell_ida); 479 atomic_set(&kfd->kfd_processes_count, 0); 480 481 return kfd; 482 } 483 484 static void kfd_cwsr_init(struct kfd_dev *kfd) 485 { 486 if (cwsr_enable && kfd->device_info.supports_cwsr) { 487 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 488 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 489 > KFD_CWSR_TMA_OFFSET); 490 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 491 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 492 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 493 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 494 > KFD_CWSR_TMA_OFFSET); 495 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 496 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 497 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 498 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 499 > KFD_CWSR_TMA_OFFSET); 500 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 501 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 502 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 503 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 504 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 505 > KFD_CWSR_TMA_OFFSET); 506 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 507 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 508 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) { 509 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE); 510 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex; 511 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex); 512 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 513 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 514 > KFD_CWSR_TMA_OFFSET); 515 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 516 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 517 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 518 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 519 > KFD_CWSR_TMA_OFFSET); 520 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 521 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 522 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 523 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 524 > KFD_CWSR_TMA_OFFSET); 525 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 526 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 527 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 528 /* The gfx11 cwsr trap handler must fit inside a single 529 page. */ 530 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 531 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 532 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 533 } else { 534 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 535 > KFD_CWSR_TMA_OFFSET); 536 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 537 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 538 } 539 540 kfd->cwsr_enabled = true; 541 } 542 } 543 544 static int kfd_gws_init(struct kfd_node *node) 545 { 546 int ret = 0; 547 struct kfd_dev *kfd = node->kfd; 548 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 549 550 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 551 return 0; 552 553 if (hws_gws_support || (KFD_IS_SOC15(node) && 554 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 555 && kfd->mec2_fw_version >= 0x81b3) || 556 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 557 && kfd->mec2_fw_version >= 0x1b3) || 558 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 559 && kfd->mec2_fw_version >= 0x30) || 560 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 561 && kfd->mec2_fw_version >= 0x28) || 562 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 563 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 564 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) || 565 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 566 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 567 && kfd->mec2_fw_version >= 0x6b) || 568 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 569 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 570 && mes_rev >= 68) || 571 (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))))) { 572 if (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0)) 573 node->adev->gds.gws_size = 64; 574 ret = amdgpu_amdkfd_alloc_gws(node->adev, 575 node->adev->gds.gws_size, &node->gws); 576 } 577 578 return ret; 579 } 580 581 static void kfd_smi_init(struct kfd_node *dev) 582 { 583 INIT_LIST_HEAD(&dev->smi_clients); 584 spin_lock_init(&dev->smi_lock); 585 } 586 587 static int kfd_init_node(struct kfd_node *node) 588 { 589 int err = -1; 590 591 if (kfd_interrupt_init(node)) { 592 dev_err(kfd_device, "Error initializing interrupts\n"); 593 goto kfd_interrupt_error; 594 } 595 596 node->dqm = device_queue_manager_init(node); 597 if (!node->dqm) { 598 dev_err(kfd_device, "Error initializing queue manager\n"); 599 goto device_queue_manager_error; 600 } 601 602 if (kfd_gws_init(node)) { 603 dev_err(kfd_device, "Could not allocate %d gws\n", 604 node->adev->gds.gws_size); 605 goto gws_error; 606 } 607 608 if (kfd_resume(node)) 609 goto kfd_resume_error; 610 611 if (kfd_topology_add_device(node)) { 612 dev_err(kfd_device, "Error adding device to topology\n"); 613 goto kfd_topology_add_device_error; 614 } 615 616 kfd_smi_init(node); 617 618 return 0; 619 620 kfd_topology_add_device_error: 621 kfd_resume_error: 622 gws_error: 623 device_queue_manager_uninit(node->dqm); 624 device_queue_manager_error: 625 kfd_interrupt_exit(node); 626 kfd_interrupt_error: 627 if (node->gws) 628 amdgpu_amdkfd_free_gws(node->adev, node->gws); 629 630 /* Cleanup the node memory here */ 631 kfree(node); 632 return err; 633 } 634 635 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 636 { 637 struct kfd_node *knode; 638 unsigned int i; 639 640 /* 641 * flush_work ensures that there are no outstanding 642 * work-queue items that will access interrupt_ring. New work items 643 * can't be created because we stopped interrupt handling above. 644 */ 645 flush_workqueue(kfd->ih_wq); 646 destroy_workqueue(kfd->ih_wq); 647 648 for (i = 0; i < num_nodes; i++) { 649 knode = kfd->nodes[i]; 650 device_queue_manager_uninit(knode->dqm); 651 kfd_interrupt_exit(knode); 652 kfd_topology_remove_device(knode); 653 if (knode->gws) 654 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 655 kfree(knode); 656 kfd->nodes[i] = NULL; 657 } 658 } 659 660 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 661 unsigned int kfd_node_idx) 662 { 663 struct amdgpu_device *adev = node->adev; 664 uint32_t xcc_mask = node->xcc_mask; 665 uint32_t xcc, mapped_xcc; 666 /* 667 * Interrupt bitmap is setup for processing interrupts from 668 * different XCDs and AIDs. 669 * Interrupt bitmap is defined as follows: 670 * 1. Bits 0-15 - correspond to the NodeId field. 671 * Each bit corresponds to NodeId number. For example, if 672 * a KFD node has interrupt bitmap set to 0x7, then this 673 * KFD node will process interrupts with NodeId = 0, 1 and 2 674 * in the IH cookie. 675 * 2. Bits 16-31 - unused. 676 * 677 * Please note that the kfd_node_idx argument passed to this 678 * function is not related to NodeId field received in the 679 * IH cookie. 680 * 681 * In CPX mode, a KFD node will process an interrupt if: 682 * - the Node Id matches the corresponding bit set in 683 * Bits 0-15. 684 * - AND VMID reported in the interrupt lies within the 685 * VMID range of the node. 686 */ 687 for_each_inst(xcc, xcc_mask) { 688 mapped_xcc = GET_INST(GC, xcc); 689 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 690 } 691 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 692 node->interrupt_bitmap); 693 } 694 695 bool kgd2kfd_device_init(struct kfd_dev *kfd, 696 const struct kgd2kfd_shared_resources *gpu_resources) 697 { 698 unsigned int size, map_process_packet_size, i; 699 struct kfd_node *node; 700 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 701 unsigned int max_proc_per_quantum; 702 int partition_mode; 703 int xcp_idx; 704 705 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 706 KGD_ENGINE_MEC1); 707 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 708 KGD_ENGINE_MEC2); 709 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 710 KGD_ENGINE_SDMA1); 711 kfd->shared_resources = *gpu_resources; 712 713 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 714 715 if (kfd->num_nodes == 0) { 716 dev_err(kfd_device, 717 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 718 kfd->adev->gfx.num_xcc_per_xcp); 719 goto out; 720 } 721 722 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 723 * 32 and 64-bit requests are possible and must be 724 * supported. 725 */ 726 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 727 if (!kfd->pci_atomic_requested && 728 kfd->device_info.needs_pci_atomics && 729 (!kfd->device_info.no_atomic_fw_version || 730 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 731 dev_info(kfd_device, 732 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 733 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 734 kfd->mec_fw_version, 735 kfd->device_info.no_atomic_fw_version); 736 return false; 737 } 738 739 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 740 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 741 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 742 743 /* For multi-partition capable GPUs, we need special handling for VMIDs 744 * depending on partition mode. 745 * In CPX mode, the VMID range needs to be shared between XCDs. 746 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 747 * divide them equally, we change starting VMID to 4 and not use 748 * VMID 3. 749 * If the VMID range changes for multi-partition capable GPUs, then 750 * this code MUST be revisited. 751 */ 752 if (kfd->adev->xcp_mgr) { 753 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 754 AMDGPU_XCP_FL_LOCKED); 755 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 756 kfd->num_nodes != 1) { 757 vmid_num_kfd /= 2; 758 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 759 } 760 } 761 762 /* Verify module parameters regarding mapped process number*/ 763 if (hws_max_conc_proc >= 0) 764 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 765 else 766 max_proc_per_quantum = vmid_num_kfd; 767 768 /* calculate max size of mqds needed for queues */ 769 size = max_num_of_queues_per_device * 770 kfd->device_info.mqd_size_aligned; 771 772 /* 773 * calculate max size of runlist packet. 774 * There can be only 2 packets at once 775 */ 776 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 777 sizeof(struct pm4_mes_map_process_aldebaran) : 778 sizeof(struct pm4_mes_map_process); 779 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 780 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 781 + sizeof(struct pm4_mes_runlist)) * 2; 782 783 /* Add size of HIQ & DIQ */ 784 size += KFD_KERNEL_QUEUE_SIZE * 2; 785 786 /* add another 512KB for all other allocations on gart (HPD, fences) */ 787 size += 512 * 1024; 788 789 if (amdgpu_amdkfd_alloc_gtt_mem( 790 kfd->adev, size, &kfd->gtt_mem, 791 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 792 false)) { 793 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 794 goto alloc_gtt_mem_failure; 795 } 796 797 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 798 799 /* Initialize GTT sa with 512 byte chunk size */ 800 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 801 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 802 goto kfd_gtt_sa_init_error; 803 } 804 805 if (kfd_doorbell_init(kfd)) { 806 dev_err(kfd_device, 807 "Error initializing doorbell aperture\n"); 808 goto kfd_doorbell_error; 809 } 810 811 if (amdgpu_use_xgmi_p2p) 812 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 813 814 /* 815 * For multi-partition capable GPUs, the KFD abstracts all partitions 816 * within a socket as xGMI connected in the topology so assign a unique 817 * hive id per device based on the pci device location if device is in 818 * PCIe mode. 819 */ 820 if (!kfd->hive_id && kfd->num_nodes > 1) 821 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 822 823 kfd->noretry = kfd->adev->gmc.noretry; 824 825 kfd_cwsr_init(kfd); 826 827 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 828 kfd->num_nodes); 829 830 /* Allocate the KFD nodes */ 831 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 832 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 833 if (!node) 834 goto node_alloc_error; 835 836 node->node_id = i; 837 node->adev = kfd->adev; 838 node->kfd = kfd; 839 node->kfd2kgd = kfd->kfd2kgd; 840 node->vm_info.vmid_num_kfd = vmid_num_kfd; 841 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 842 /* TODO : Check if error handling is needed */ 843 if (node->xcp) { 844 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 845 &node->xcc_mask); 846 ++xcp_idx; 847 } else { 848 node->xcc_mask = 849 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 850 } 851 852 if (node->xcp) { 853 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 854 node->node_id, node->xcp->mem_id, 855 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 856 } 857 858 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 859 kfd->num_nodes != 1) { 860 /* For multi-partition capable GPUs and CPX mode, first 861 * XCD gets VMID range 4-9 and second XCD gets VMID 862 * range 10-15. 863 */ 864 865 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 866 first_vmid_kfd : 867 first_vmid_kfd+vmid_num_kfd; 868 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 869 last_vmid_kfd-vmid_num_kfd : 870 last_vmid_kfd; 871 node->compute_vmid_bitmap = 872 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 873 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 874 } else { 875 node->vm_info.first_vmid_kfd = first_vmid_kfd; 876 node->vm_info.last_vmid_kfd = last_vmid_kfd; 877 node->compute_vmid_bitmap = 878 gpu_resources->compute_vmid_bitmap; 879 } 880 node->max_proc_per_quantum = max_proc_per_quantum; 881 atomic_set(&node->sram_ecc_flag, 0); 882 883 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 884 &node->local_mem_info, node->xcp); 885 886 if (kfd->adev->xcp_mgr) 887 kfd_setup_interrupt_bitmap(node, i); 888 889 /* Initialize the KFD node */ 890 if (kfd_init_node(node)) { 891 dev_err(kfd_device, "Error initializing KFD node\n"); 892 goto node_init_error; 893 } 894 895 spin_lock_init(&node->watch_points_lock); 896 897 kfd->nodes[i] = node; 898 } 899 900 svm_range_set_max_pages(kfd->adev); 901 902 kfd->init_complete = true; 903 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 904 kfd->adev->pdev->device); 905 906 pr_debug("Starting kfd with the following scheduling policy %d\n", 907 node->dqm->sched_policy); 908 909 goto out; 910 911 node_init_error: 912 node_alloc_error: 913 kfd_cleanup_nodes(kfd, i); 914 kfd_doorbell_fini(kfd); 915 kfd_doorbell_error: 916 kfd_gtt_sa_fini(kfd); 917 kfd_gtt_sa_init_error: 918 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 919 alloc_gtt_mem_failure: 920 dev_err(kfd_device, 921 "device %x:%x NOT added due to errors\n", 922 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 923 out: 924 return kfd->init_complete; 925 } 926 927 void kgd2kfd_device_exit(struct kfd_dev *kfd) 928 { 929 if (kfd->init_complete) { 930 /* Cleanup KFD nodes */ 931 kfd_cleanup_nodes(kfd, kfd->num_nodes); 932 /* Cleanup common/shared resources */ 933 kfd_doorbell_fini(kfd); 934 ida_destroy(&kfd->doorbell_ida); 935 kfd_gtt_sa_fini(kfd); 936 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 937 } 938 939 kfree(kfd); 940 } 941 942 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 943 struct amdgpu_reset_context *reset_context) 944 { 945 struct kfd_node *node; 946 int i; 947 948 if (!kfd->init_complete) 949 return 0; 950 951 for (i = 0; i < kfd->num_nodes; i++) { 952 node = kfd->nodes[i]; 953 kfd_smi_event_update_gpu_reset(node, false, reset_context); 954 } 955 956 kgd2kfd_suspend(kfd, true); 957 958 for (i = 0; i < kfd->num_nodes; i++) 959 kfd_signal_reset_event(kfd->nodes[i]); 960 961 return 0; 962 } 963 964 /* 965 * Fix me. KFD won't be able to resume existing process for now. 966 * We will keep all existing process in a evicted state and 967 * wait the process to be terminated. 968 */ 969 970 int kgd2kfd_post_reset(struct kfd_dev *kfd) 971 { 972 int ret; 973 struct kfd_node *node; 974 int i; 975 976 if (!kfd->init_complete) 977 return 0; 978 979 for (i = 0; i < kfd->num_nodes; i++) { 980 ret = kfd_resume(kfd->nodes[i]); 981 if (ret) 982 return ret; 983 } 984 985 mutex_lock(&kfd_processes_mutex); 986 --kfd_locked; 987 mutex_unlock(&kfd_processes_mutex); 988 989 for (i = 0; i < kfd->num_nodes; i++) { 990 node = kfd->nodes[i]; 991 atomic_set(&node->sram_ecc_flag, 0); 992 kfd_smi_event_update_gpu_reset(node, true, NULL); 993 } 994 995 return 0; 996 } 997 998 bool kfd_is_locked(struct kfd_dev *kfd) 999 { 1000 uint8_t id = 0; 1001 struct kfd_node *dev; 1002 1003 lockdep_assert_held(&kfd_processes_mutex); 1004 1005 /* check reset/suspend lock */ 1006 if (kfd_locked > 0) 1007 return true; 1008 1009 if (kfd) 1010 return kfd->kfd_dev_lock > 0; 1011 1012 /* check lock on all cgroup accessible devices */ 1013 while (kfd_topology_enum_kfd_devices(id++, &dev) == 0) { 1014 if (!dev || kfd_devcgroup_check_permission(dev)) 1015 continue; 1016 1017 if (dev->kfd->kfd_dev_lock > 0) 1018 return true; 1019 } 1020 1021 return false; 1022 } 1023 1024 void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) 1025 { 1026 struct kfd_node *node; 1027 int i; 1028 1029 if (!kfd->init_complete) 1030 return; 1031 1032 if (suspend_proc) 1033 kgd2kfd_suspend_process(kfd); 1034 1035 for (i = 0; i < kfd->num_nodes; i++) { 1036 node = kfd->nodes[i]; 1037 node->dqm->ops.stop(node->dqm); 1038 } 1039 } 1040 1041 int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) 1042 { 1043 int ret = 0, i; 1044 1045 if (!kfd->init_complete) 1046 return 0; 1047 1048 for (i = 0; i < kfd->num_nodes; i++) { 1049 ret = kfd_resume(kfd->nodes[i]); 1050 if (ret) 1051 return ret; 1052 } 1053 1054 if (resume_proc) 1055 ret = kgd2kfd_resume_process(kfd); 1056 1057 return ret; 1058 } 1059 1060 void kgd2kfd_suspend_process(struct kfd_dev *kfd) 1061 { 1062 if (!kfd->init_complete) 1063 return; 1064 1065 mutex_lock(&kfd_processes_mutex); 1066 /* For first KFD device suspend all the KFD processes */ 1067 if (++kfd_locked == 1) 1068 kfd_suspend_all_processes(); 1069 mutex_unlock(&kfd_processes_mutex); 1070 } 1071 1072 int kgd2kfd_resume_process(struct kfd_dev *kfd) 1073 { 1074 int ret = 0; 1075 1076 if (!kfd->init_complete) 1077 return 0; 1078 1079 mutex_lock(&kfd_processes_mutex); 1080 if (--kfd_locked == 0) 1081 ret = kfd_resume_all_processes(); 1082 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1083 mutex_unlock(&kfd_processes_mutex); 1084 1085 return ret; 1086 } 1087 1088 static int kfd_resume(struct kfd_node *node) 1089 { 1090 int err = 0; 1091 1092 err = node->dqm->ops.start(node->dqm); 1093 if (err) 1094 dev_err(kfd_device, 1095 "Error starting queue manager for device %x:%x\n", 1096 node->adev->pdev->vendor, node->adev->pdev->device); 1097 1098 return err; 1099 } 1100 1101 /* This is called directly from KGD at ISR. */ 1102 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1103 { 1104 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1105 bool is_patched = false; 1106 unsigned long flags; 1107 struct kfd_node *node; 1108 1109 if (!kfd->init_complete) 1110 return; 1111 1112 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1113 dev_err_once(kfd_device, "Ring entry too small\n"); 1114 return; 1115 } 1116 1117 for (i = 0; i < kfd->num_nodes; i++) { 1118 /* Race if another thread in b/w 1119 * kfd_cleanup_nodes and kfree(kfd), 1120 * when kfd->nodes[i] = NULL 1121 */ 1122 if (kfd->nodes[i]) 1123 node = kfd->nodes[i]; 1124 else 1125 return; 1126 1127 spin_lock_irqsave(&node->interrupt_lock, flags); 1128 1129 if (node->interrupts_active 1130 && interrupt_is_wanted(node, ih_ring_entry, 1131 patched_ihre, &is_patched) 1132 && enqueue_ih_ring_entry(node, 1133 is_patched ? patched_ihre : ih_ring_entry)) { 1134 queue_work(node->kfd->ih_wq, &node->interrupt_work); 1135 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1136 return; 1137 } 1138 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1139 } 1140 1141 } 1142 1143 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1144 { 1145 struct kfd_process *p; 1146 int r; 1147 1148 /* Because we are called from arbitrary context (workqueue) as opposed 1149 * to process context, kfd_process could attempt to exit while we are 1150 * running so the lookup function increments the process ref count. 1151 */ 1152 p = kfd_lookup_process_by_mm(mm); 1153 if (!p) 1154 return -ESRCH; 1155 1156 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1157 r = kfd_process_evict_queues(p, trigger); 1158 1159 kfd_unref_process(p); 1160 return r; 1161 } 1162 1163 int kgd2kfd_resume_mm(struct mm_struct *mm) 1164 { 1165 struct kfd_process *p; 1166 int r; 1167 1168 /* Because we are called from arbitrary context (workqueue) as opposed 1169 * to process context, kfd_process could attempt to exit while we are 1170 * running so the lookup function increments the process ref count. 1171 */ 1172 p = kfd_lookup_process_by_mm(mm); 1173 if (!p) 1174 return -ESRCH; 1175 1176 r = kfd_process_restore_queues(p); 1177 1178 kfd_unref_process(p); 1179 return r; 1180 } 1181 1182 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1183 * prepare for safe eviction of KFD BOs that belong to the specified 1184 * process. 1185 * 1186 * @mm: mm_struct that identifies the specified KFD process 1187 * @fence: eviction fence attached to KFD process BOs 1188 * 1189 */ 1190 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1191 struct dma_fence *fence) 1192 { 1193 struct kfd_process *p; 1194 unsigned long active_time; 1195 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1196 1197 if (!fence) 1198 return -EINVAL; 1199 1200 if (dma_fence_is_signaled(fence)) 1201 return 0; 1202 1203 p = kfd_lookup_process_by_mm(mm); 1204 if (!p) 1205 return -ENODEV; 1206 1207 if (fence->seqno == p->last_eviction_seqno) 1208 goto out; 1209 1210 p->last_eviction_seqno = fence->seqno; 1211 1212 /* Avoid KFD process starvation. Wait for at least 1213 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1214 */ 1215 active_time = get_jiffies_64() - p->last_restore_timestamp; 1216 if (delay_jiffies > active_time) 1217 delay_jiffies -= active_time; 1218 else 1219 delay_jiffies = 0; 1220 1221 /* During process initialization eviction_work.dwork is initialized 1222 * to kfd_evict_bo_worker 1223 */ 1224 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1225 p->lead_thread->pid, delay_jiffies); 1226 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1227 out: 1228 kfd_unref_process(p); 1229 return 0; 1230 } 1231 1232 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1233 unsigned int chunk_size) 1234 { 1235 if (WARN_ON(buf_size < chunk_size)) 1236 return -EINVAL; 1237 if (WARN_ON(buf_size == 0)) 1238 return -EINVAL; 1239 if (WARN_ON(chunk_size == 0)) 1240 return -EINVAL; 1241 1242 kfd->gtt_sa_chunk_size = chunk_size; 1243 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1244 1245 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1246 GFP_KERNEL); 1247 if (!kfd->gtt_sa_bitmap) 1248 return -ENOMEM; 1249 1250 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1251 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1252 1253 mutex_init(&kfd->gtt_sa_lock); 1254 1255 return 0; 1256 } 1257 1258 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1259 { 1260 mutex_destroy(&kfd->gtt_sa_lock); 1261 bitmap_free(kfd->gtt_sa_bitmap); 1262 } 1263 1264 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1265 unsigned int bit_num, 1266 unsigned int chunk_size) 1267 { 1268 return start_addr + bit_num * chunk_size; 1269 } 1270 1271 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1272 unsigned int bit_num, 1273 unsigned int chunk_size) 1274 { 1275 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1276 } 1277 1278 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1279 struct kfd_mem_obj **mem_obj) 1280 { 1281 unsigned int found, start_search, cur_size; 1282 struct kfd_dev *kfd = node->kfd; 1283 1284 if (size == 0) 1285 return -EINVAL; 1286 1287 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1288 return -ENOMEM; 1289 1290 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1291 if (!(*mem_obj)) 1292 return -ENOMEM; 1293 1294 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1295 1296 start_search = 0; 1297 1298 mutex_lock(&kfd->gtt_sa_lock); 1299 1300 kfd_gtt_restart_search: 1301 /* Find the first chunk that is free */ 1302 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1303 kfd->gtt_sa_num_of_chunks, 1304 start_search); 1305 1306 pr_debug("Found = %d\n", found); 1307 1308 /* If there wasn't any free chunk, bail out */ 1309 if (found == kfd->gtt_sa_num_of_chunks) 1310 goto kfd_gtt_no_free_chunk; 1311 1312 /* Update fields of mem_obj */ 1313 (*mem_obj)->range_start = found; 1314 (*mem_obj)->range_end = found; 1315 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1316 kfd->gtt_start_gpu_addr, 1317 found, 1318 kfd->gtt_sa_chunk_size); 1319 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1320 kfd->gtt_start_cpu_ptr, 1321 found, 1322 kfd->gtt_sa_chunk_size); 1323 1324 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1325 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1326 1327 /* If we need only one chunk, mark it as allocated and get out */ 1328 if (size <= kfd->gtt_sa_chunk_size) { 1329 pr_debug("Single bit\n"); 1330 __set_bit(found, kfd->gtt_sa_bitmap); 1331 goto kfd_gtt_out; 1332 } 1333 1334 /* Otherwise, try to see if we have enough contiguous chunks */ 1335 cur_size = size - kfd->gtt_sa_chunk_size; 1336 do { 1337 (*mem_obj)->range_end = 1338 find_next_zero_bit(kfd->gtt_sa_bitmap, 1339 kfd->gtt_sa_num_of_chunks, ++found); 1340 /* 1341 * If next free chunk is not contiguous than we need to 1342 * restart our search from the last free chunk we found (which 1343 * wasn't contiguous to the previous ones 1344 */ 1345 if ((*mem_obj)->range_end != found) { 1346 start_search = found; 1347 goto kfd_gtt_restart_search; 1348 } 1349 1350 /* 1351 * If we reached end of buffer, bail out with error 1352 */ 1353 if (found == kfd->gtt_sa_num_of_chunks) 1354 goto kfd_gtt_no_free_chunk; 1355 1356 /* Check if we don't need another chunk */ 1357 if (cur_size <= kfd->gtt_sa_chunk_size) 1358 cur_size = 0; 1359 else 1360 cur_size -= kfd->gtt_sa_chunk_size; 1361 1362 } while (cur_size > 0); 1363 1364 pr_debug("range_start = %d, range_end = %d\n", 1365 (*mem_obj)->range_start, (*mem_obj)->range_end); 1366 1367 /* Mark the chunks as allocated */ 1368 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1369 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1370 1371 kfd_gtt_out: 1372 mutex_unlock(&kfd->gtt_sa_lock); 1373 return 0; 1374 1375 kfd_gtt_no_free_chunk: 1376 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1377 mutex_unlock(&kfd->gtt_sa_lock); 1378 kfree(*mem_obj); 1379 return -ENOMEM; 1380 } 1381 1382 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1383 { 1384 struct kfd_dev *kfd = node->kfd; 1385 1386 /* Act like kfree when trying to free a NULL object */ 1387 if (!mem_obj) 1388 return 0; 1389 1390 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1391 mem_obj, mem_obj->range_start, mem_obj->range_end); 1392 1393 mutex_lock(&kfd->gtt_sa_lock); 1394 1395 /* Mark the chunks as free */ 1396 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1397 mem_obj->range_end - mem_obj->range_start + 1); 1398 1399 mutex_unlock(&kfd->gtt_sa_lock); 1400 1401 kfree(mem_obj); 1402 return 0; 1403 } 1404 1405 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1406 { 1407 /* 1408 * TODO: Currently update SRAM ECC flag for first node. 1409 * This needs to be updated later when we can 1410 * identify SRAM ECC error on other nodes also. 1411 */ 1412 if (kfd) 1413 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1414 } 1415 1416 void kfd_inc_compute_active(struct kfd_node *node) 1417 { 1418 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1419 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1420 } 1421 1422 void kfd_dec_compute_active(struct kfd_node *node) 1423 { 1424 int count = atomic_dec_return(&node->kfd->compute_profile); 1425 1426 if (count == 0) 1427 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1428 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1429 } 1430 1431 static bool kfd_compute_active(struct kfd_node *node) 1432 { 1433 if (atomic_read(&node->kfd->compute_profile)) 1434 return true; 1435 return false; 1436 } 1437 1438 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1439 { 1440 /* 1441 * TODO: For now, raise the throttling event only on first node. 1442 * This will need to change after we are able to determine 1443 * which node raised the throttling event. 1444 */ 1445 if (kfd && kfd->init_complete) 1446 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1447 throttle_bitmask); 1448 } 1449 1450 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1451 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1452 * When the device has more than two engines, we reserve two for PCIe to enable 1453 * full-duplex and the rest are used as XGMI. 1454 */ 1455 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1456 { 1457 /* If XGMI is not supported, all SDMA engines are PCIe */ 1458 if (!node->adev->gmc.xgmi.supported) 1459 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1460 1461 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1462 } 1463 1464 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1465 { 1466 /* After reserved for PCIe, the rest of engines are XGMI */ 1467 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1468 kfd_get_num_sdma_engines(node); 1469 } 1470 1471 int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) 1472 { 1473 struct kfd_process *p; 1474 int r = 0, temp, idx; 1475 1476 mutex_lock(&kfd_processes_mutex); 1477 1478 /* kfd_processes_count is per kfd_dev, return -EBUSY without 1479 * further check 1480 */ 1481 if (!!atomic_read(&kfd->kfd_processes_count)) { 1482 pr_debug("process_wq_release not finished\n"); 1483 r = -EBUSY; 1484 goto out; 1485 } 1486 1487 if (hash_empty(kfd_processes_table) && !kfd_is_locked(kfd)) 1488 goto out; 1489 1490 /* fail under system reset/resume or kfd device is partition switching. */ 1491 if (kfd_is_locked(kfd)) { 1492 r = -EBUSY; 1493 goto out; 1494 } 1495 1496 /* 1497 * ensure all running processes are cgroup excluded from device before mode switch. 1498 * i.e. no pdd was created on the process socket. 1499 */ 1500 idx = srcu_read_lock(&kfd_processes_srcu); 1501 hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { 1502 int i; 1503 1504 for (i = 0; i < p->n_pdds; i++) { 1505 if (p->pdds[i]->dev->kfd != kfd) 1506 continue; 1507 1508 r = -EBUSY; 1509 goto proc_check_unlock; 1510 } 1511 } 1512 1513 proc_check_unlock: 1514 srcu_read_unlock(&kfd_processes_srcu, idx); 1515 out: 1516 if (!r) 1517 ++kfd->kfd_dev_lock; 1518 mutex_unlock(&kfd_processes_mutex); 1519 1520 return r; 1521 } 1522 1523 void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) 1524 { 1525 mutex_lock(&kfd_processes_mutex); 1526 --kfd->kfd_dev_lock; 1527 mutex_unlock(&kfd_processes_mutex); 1528 } 1529 1530 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1531 { 1532 struct kfd_node *node; 1533 int ret; 1534 1535 if (!kfd->init_complete) 1536 return 0; 1537 1538 if (node_id >= kfd->num_nodes) { 1539 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1540 node_id, kfd->num_nodes - 1); 1541 return -EINVAL; 1542 } 1543 node = kfd->nodes[node_id]; 1544 1545 ret = node->dqm->ops.unhalt(node->dqm); 1546 if (ret) 1547 dev_err(kfd_device, "Error in starting scheduler\n"); 1548 1549 return ret; 1550 } 1551 1552 int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) 1553 { 1554 struct kfd_node *node; 1555 int i, r; 1556 1557 if (!kfd->init_complete) 1558 return 0; 1559 1560 for (i = 0; i < kfd->num_nodes; i++) { 1561 node = kfd->nodes[i]; 1562 r = node->dqm->ops.unhalt(node->dqm); 1563 if (r) { 1564 dev_err(kfd_device, "Error in starting scheduler\n"); 1565 return r; 1566 } 1567 } 1568 return 0; 1569 } 1570 1571 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1572 { 1573 struct kfd_node *node; 1574 1575 if (!kfd->init_complete) 1576 return 0; 1577 1578 if (node_id >= kfd->num_nodes) { 1579 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1580 node_id, kfd->num_nodes - 1); 1581 return -EINVAL; 1582 } 1583 1584 node = kfd->nodes[node_id]; 1585 return node->dqm->ops.halt(node->dqm); 1586 } 1587 1588 int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) 1589 { 1590 struct kfd_node *node; 1591 int i, r; 1592 1593 if (!kfd->init_complete) 1594 return 0; 1595 1596 for (i = 0; i < kfd->num_nodes; i++) { 1597 node = kfd->nodes[i]; 1598 r = node->dqm->ops.halt(node->dqm); 1599 if (r) 1600 return r; 1601 } 1602 return 0; 1603 } 1604 1605 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1606 { 1607 struct kfd_node *node; 1608 1609 if (!kfd->init_complete) 1610 return false; 1611 1612 if (node_id >= kfd->num_nodes) { 1613 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1614 node_id, kfd->num_nodes - 1); 1615 return false; 1616 } 1617 1618 node = kfd->nodes[node_id]; 1619 1620 return kfd_compute_active(node); 1621 } 1622 1623 /** 1624 * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9 1625 * @adev: amdgpu device 1626 * @entry: vm fault interrupt vector 1627 * @retry_fault: if this is retry fault 1628 * 1629 * retry fault - 1630 * with CAM enabled, adev primary ring 1631 * | gmc_v9_0_process_interrupt() 1632 * adev soft_ring 1633 * | gmc_v9_0_process_interrupt() worker failed to recover page fault 1634 * KFD node ih_fifo 1635 * | KFD interrupt_wq worker 1636 * kfd_signal_vm_fault_event 1637 * 1638 * without CAM, adev primary ring1 1639 * | gmc_v9_0_process_interrupt worker failed to recvoer page fault 1640 * KFD node ih_fifo 1641 * | KFD interrupt_wq worker 1642 * kfd_signal_vm_fault_event 1643 * 1644 * no-retry fault - 1645 * adev primary ring 1646 * | gmc_v9_0_process_interrupt() 1647 * KFD node ih_fifo 1648 * | KFD interrupt_wq worker 1649 * kfd_signal_vm_fault_event 1650 * 1651 * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault 1652 * of same process, don't copy interrupt to KFD node ih_fifo. 1653 * With gdb debugger enabled, need convert the retry fault to no-retry fault for 1654 * debugger, cannot use the fast path. 1655 * 1656 * Return: 1657 * true - use the fast path to handle this fault 1658 * false - use normal path to handle it 1659 */ 1660 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 1661 bool retry_fault) 1662 { 1663 struct kfd_process *p; 1664 u32 cam_index; 1665 1666 if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) { 1667 p = kfd_lookup_process_by_pasid(entry->pasid, NULL); 1668 if (!p) 1669 return true; 1670 1671 if (p->gpu_page_fault && !p->debug_trap_enabled) { 1672 if (retry_fault && adev->irq.retry_cam_enabled) { 1673 cam_index = entry->src_data[2] & 0x3ff; 1674 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 1675 } 1676 1677 kfd_unref_process(p); 1678 return true; 1679 } 1680 1681 /* 1682 * This is the first page fault, set flag and then signal user space 1683 */ 1684 p->gpu_page_fault = true; 1685 kfd_unref_process(p); 1686 } 1687 return false; 1688 } 1689 1690 #if defined(CONFIG_DEBUG_FS) 1691 1692 /* This function will send a package to HIQ to hang the HWS 1693 * which will trigger a GPU reset and bring the HWS back to normal state 1694 */ 1695 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1696 { 1697 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1698 pr_err("HWS is not enabled"); 1699 return -EINVAL; 1700 } 1701 1702 if (dev->kfd->shared_resources.enable_mes) { 1703 dev_err(dev->adev->dev, "Inducing MES hang is not supported\n"); 1704 return -EINVAL; 1705 } 1706 1707 return dqm_debugfs_hang_hws(dev->dqm); 1708 } 1709 1710 #endif 1711