1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_svm.h" 36 #include "kfd_migrate.h" 37 #include "amdgpu.h" 38 #include "amdgpu_xcp.h" 39 40 #define MQD_SIZE_ALIGNED 768 41 42 /* 43 * kfd_locked is used to lock the kfd driver during suspend or reset 44 * once locked, kfd driver will stop any further GPU execution. 45 * create process (open) will return -EAGAIN. 46 */ 47 static int kfd_locked; 48 49 #ifdef CONFIG_DRM_AMDGPU_CIK 50 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 51 #endif 52 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 54 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 55 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 56 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume_iommu(struct kfd_dev *kfd); 66 static int kfd_resume(struct kfd_node *kfd); 67 68 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 69 { 70 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 71 72 switch (sdma_version) { 73 case IP_VERSION(4, 0, 0):/* VEGA10 */ 74 case IP_VERSION(4, 0, 1):/* VEGA12 */ 75 case IP_VERSION(4, 1, 0):/* RAVEN */ 76 case IP_VERSION(4, 1, 1):/* RAVEN */ 77 case IP_VERSION(4, 1, 2):/* RENOIR */ 78 case IP_VERSION(5, 2, 1):/* VANGOGH */ 79 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 80 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 81 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 82 kfd->device_info.num_sdma_queues_per_engine = 2; 83 break; 84 case IP_VERSION(4, 2, 0):/* VEGA20 */ 85 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 86 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 87 case IP_VERSION(4, 4, 2): 88 case IP_VERSION(5, 0, 0):/* NAVI10 */ 89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 90 case IP_VERSION(5, 0, 2):/* NAVI14 */ 91 case IP_VERSION(5, 0, 5):/* NAVI12 */ 92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 96 case IP_VERSION(6, 0, 0): 97 case IP_VERSION(6, 0, 1): 98 case IP_VERSION(6, 0, 2): 99 case IP_VERSION(6, 0, 3): 100 kfd->device_info.num_sdma_queues_per_engine = 8; 101 break; 102 default: 103 dev_warn(kfd_device, 104 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 105 sdma_version); 106 kfd->device_info.num_sdma_queues_per_engine = 8; 107 } 108 109 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 110 111 switch (sdma_version) { 112 case IP_VERSION(6, 0, 0): 113 case IP_VERSION(6, 0, 1): 114 case IP_VERSION(6, 0, 2): 115 case IP_VERSION(6, 0, 3): 116 /* Reserve 1 for paging and 1 for gfx */ 117 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 118 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 119 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 120 kfd->adev->sdma.num_instances * 121 kfd->device_info.num_reserved_sdma_queues_per_engine); 122 break; 123 default: 124 break; 125 } 126 } 127 128 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 129 { 130 uint32_t gc_version = KFD_GC_VERSION(kfd); 131 132 switch (gc_version) { 133 case IP_VERSION(9, 0, 1): /* VEGA10 */ 134 case IP_VERSION(9, 1, 0): /* RAVEN */ 135 case IP_VERSION(9, 2, 1): /* VEGA12 */ 136 case IP_VERSION(9, 2, 2): /* RAVEN */ 137 case IP_VERSION(9, 3, 0): /* RENOIR */ 138 case IP_VERSION(9, 4, 0): /* VEGA20 */ 139 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 140 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 141 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 142 break; 143 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 144 kfd->device_info.event_interrupt_class = 145 &event_interrupt_class_v9_4_3; 146 break; 147 case IP_VERSION(10, 3, 1): /* VANGOGH */ 148 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 149 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 150 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 151 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 152 case IP_VERSION(10, 1, 4): 153 case IP_VERSION(10, 1, 10): /* NAVI10 */ 154 case IP_VERSION(10, 1, 2): /* NAVI12 */ 155 case IP_VERSION(10, 1, 1): /* NAVI14 */ 156 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 157 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 158 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 159 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 160 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 161 break; 162 case IP_VERSION(11, 0, 0): 163 case IP_VERSION(11, 0, 1): 164 case IP_VERSION(11, 0, 2): 165 case IP_VERSION(11, 0, 3): 166 case IP_VERSION(11, 0, 4): 167 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 168 break; 169 default: 170 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 171 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 172 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 173 } 174 } 175 176 static void kfd_device_info_init(struct kfd_dev *kfd, 177 bool vf, uint32_t gfx_target_version) 178 { 179 uint32_t gc_version = KFD_GC_VERSION(kfd); 180 uint32_t asic_type = kfd->adev->asic_type; 181 182 kfd->device_info.max_pasid_bits = 16; 183 kfd->device_info.max_no_of_hqd = 24; 184 kfd->device_info.num_of_watch_points = 4; 185 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 186 kfd->device_info.gfx_target_version = gfx_target_version; 187 188 if (KFD_IS_SOC15(kfd)) { 189 kfd->device_info.doorbell_size = 8; 190 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 191 kfd->device_info.supports_cwsr = true; 192 193 kfd_device_info_set_sdma_info(kfd); 194 195 kfd_device_info_set_event_interrupt_class(kfd); 196 197 if (gc_version < IP_VERSION(11, 0, 0)) { 198 /* Navi2x+, Navi1x+ */ 199 if (gc_version == IP_VERSION(10, 3, 6)) 200 kfd->device_info.no_atomic_fw_version = 14; 201 else if (gc_version == IP_VERSION(10, 3, 7)) 202 kfd->device_info.no_atomic_fw_version = 3; 203 else if (gc_version >= IP_VERSION(10, 3, 0)) 204 kfd->device_info.no_atomic_fw_version = 92; 205 else if (gc_version >= IP_VERSION(10, 1, 1)) 206 kfd->device_info.no_atomic_fw_version = 145; 207 208 /* Navi1x+ */ 209 if (gc_version >= IP_VERSION(10, 1, 1)) 210 kfd->device_info.needs_pci_atomics = true; 211 } else if (gc_version < IP_VERSION(12, 0, 0)) { 212 /* 213 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 214 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 215 * PCIe atomics support. 216 */ 217 kfd->device_info.needs_pci_atomics = true; 218 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 219 } 220 } else { 221 kfd->device_info.doorbell_size = 4; 222 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 223 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 224 kfd->device_info.num_sdma_queues_per_engine = 2; 225 226 if (asic_type != CHIP_KAVERI && 227 asic_type != CHIP_HAWAII && 228 asic_type != CHIP_TONGA) 229 kfd->device_info.supports_cwsr = true; 230 231 if (asic_type != CHIP_HAWAII && !vf) 232 kfd->device_info.needs_pci_atomics = true; 233 } 234 } 235 236 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 237 { 238 struct kfd_dev *kfd = NULL; 239 const struct kfd2kgd_calls *f2g = NULL; 240 uint32_t gfx_target_version = 0; 241 242 switch (adev->asic_type) { 243 #ifdef CONFIG_DRM_AMDGPU_CIK 244 case CHIP_KAVERI: 245 gfx_target_version = 70000; 246 if (!vf) 247 f2g = &gfx_v7_kfd2kgd; 248 break; 249 #endif 250 case CHIP_CARRIZO: 251 gfx_target_version = 80001; 252 if (!vf) 253 f2g = &gfx_v8_kfd2kgd; 254 break; 255 #ifdef CONFIG_DRM_AMDGPU_CIK 256 case CHIP_HAWAII: 257 gfx_target_version = 70001; 258 if (!amdgpu_exp_hw_support) 259 pr_info( 260 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 261 ); 262 else if (!vf) 263 f2g = &gfx_v7_kfd2kgd; 264 break; 265 #endif 266 case CHIP_TONGA: 267 gfx_target_version = 80002; 268 if (!vf) 269 f2g = &gfx_v8_kfd2kgd; 270 break; 271 case CHIP_FIJI: 272 case CHIP_POLARIS10: 273 gfx_target_version = 80003; 274 f2g = &gfx_v8_kfd2kgd; 275 break; 276 case CHIP_POLARIS11: 277 case CHIP_POLARIS12: 278 case CHIP_VEGAM: 279 gfx_target_version = 80003; 280 if (!vf) 281 f2g = &gfx_v8_kfd2kgd; 282 break; 283 default: 284 switch (adev->ip_versions[GC_HWIP][0]) { 285 /* Vega 10 */ 286 case IP_VERSION(9, 0, 1): 287 gfx_target_version = 90000; 288 f2g = &gfx_v9_kfd2kgd; 289 break; 290 /* Raven */ 291 case IP_VERSION(9, 1, 0): 292 case IP_VERSION(9, 2, 2): 293 gfx_target_version = 90002; 294 if (!vf) 295 f2g = &gfx_v9_kfd2kgd; 296 break; 297 /* Vega12 */ 298 case IP_VERSION(9, 2, 1): 299 gfx_target_version = 90004; 300 if (!vf) 301 f2g = &gfx_v9_kfd2kgd; 302 break; 303 /* Renoir */ 304 case IP_VERSION(9, 3, 0): 305 gfx_target_version = 90012; 306 if (!vf) 307 f2g = &gfx_v9_kfd2kgd; 308 break; 309 /* Vega20 */ 310 case IP_VERSION(9, 4, 0): 311 gfx_target_version = 90006; 312 if (!vf) 313 f2g = &gfx_v9_kfd2kgd; 314 break; 315 /* Arcturus */ 316 case IP_VERSION(9, 4, 1): 317 gfx_target_version = 90008; 318 f2g = &arcturus_kfd2kgd; 319 break; 320 /* Aldebaran */ 321 case IP_VERSION(9, 4, 2): 322 gfx_target_version = 90010; 323 f2g = &aldebaran_kfd2kgd; 324 break; 325 case IP_VERSION(9, 4, 3): 326 gfx_target_version = adev->rev_id >= 1 ? 90402 327 : adev->flags & AMD_IS_APU ? 90400 328 : 90401; 329 f2g = &gc_9_4_3_kfd2kgd; 330 break; 331 /* Navi10 */ 332 case IP_VERSION(10, 1, 10): 333 gfx_target_version = 100100; 334 if (!vf) 335 f2g = &gfx_v10_kfd2kgd; 336 break; 337 /* Navi12 */ 338 case IP_VERSION(10, 1, 2): 339 gfx_target_version = 100101; 340 f2g = &gfx_v10_kfd2kgd; 341 break; 342 /* Navi14 */ 343 case IP_VERSION(10, 1, 1): 344 gfx_target_version = 100102; 345 if (!vf) 346 f2g = &gfx_v10_kfd2kgd; 347 break; 348 /* Cyan Skillfish */ 349 case IP_VERSION(10, 1, 3): 350 case IP_VERSION(10, 1, 4): 351 gfx_target_version = 100103; 352 if (!vf) 353 f2g = &gfx_v10_kfd2kgd; 354 break; 355 /* Sienna Cichlid */ 356 case IP_VERSION(10, 3, 0): 357 gfx_target_version = 100300; 358 f2g = &gfx_v10_3_kfd2kgd; 359 break; 360 /* Navy Flounder */ 361 case IP_VERSION(10, 3, 2): 362 gfx_target_version = 100301; 363 f2g = &gfx_v10_3_kfd2kgd; 364 break; 365 /* Van Gogh */ 366 case IP_VERSION(10, 3, 1): 367 gfx_target_version = 100303; 368 if (!vf) 369 f2g = &gfx_v10_3_kfd2kgd; 370 break; 371 /* Dimgrey Cavefish */ 372 case IP_VERSION(10, 3, 4): 373 gfx_target_version = 100302; 374 f2g = &gfx_v10_3_kfd2kgd; 375 break; 376 /* Beige Goby */ 377 case IP_VERSION(10, 3, 5): 378 gfx_target_version = 100304; 379 f2g = &gfx_v10_3_kfd2kgd; 380 break; 381 /* Yellow Carp */ 382 case IP_VERSION(10, 3, 3): 383 gfx_target_version = 100305; 384 if (!vf) 385 f2g = &gfx_v10_3_kfd2kgd; 386 break; 387 case IP_VERSION(10, 3, 6): 388 case IP_VERSION(10, 3, 7): 389 gfx_target_version = 100306; 390 if (!vf) 391 f2g = &gfx_v10_3_kfd2kgd; 392 break; 393 case IP_VERSION(11, 0, 0): 394 gfx_target_version = 110000; 395 f2g = &gfx_v11_kfd2kgd; 396 break; 397 case IP_VERSION(11, 0, 1): 398 case IP_VERSION(11, 0, 4): 399 gfx_target_version = 110003; 400 f2g = &gfx_v11_kfd2kgd; 401 break; 402 case IP_VERSION(11, 0, 2): 403 gfx_target_version = 110002; 404 f2g = &gfx_v11_kfd2kgd; 405 break; 406 case IP_VERSION(11, 0, 3): 407 if ((adev->pdev->device == 0x7460 && 408 adev->pdev->revision == 0x00) || 409 (adev->pdev->device == 0x7461 && 410 adev->pdev->revision == 0x00)) 411 /* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */ 412 gfx_target_version = 110005; 413 else 414 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 415 gfx_target_version = 110001; 416 f2g = &gfx_v11_kfd2kgd; 417 break; 418 default: 419 break; 420 } 421 break; 422 } 423 424 if (!f2g) { 425 if (adev->ip_versions[GC_HWIP][0]) 426 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 427 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 428 else 429 dev_err(kfd_device, "%s %s not supported in kfd\n", 430 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 431 return NULL; 432 } 433 434 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 435 if (!kfd) 436 return NULL; 437 438 kfd->adev = adev; 439 kfd_device_info_init(kfd, vf, gfx_target_version); 440 kfd->init_complete = false; 441 kfd->kfd2kgd = f2g; 442 atomic_set(&kfd->compute_profile, 0); 443 444 mutex_init(&kfd->doorbell_mutex); 445 memset(&kfd->doorbell_available_index, 0, 446 sizeof(kfd->doorbell_available_index)); 447 448 ida_init(&kfd->doorbell_ida); 449 450 return kfd; 451 } 452 453 static void kfd_cwsr_init(struct kfd_dev *kfd) 454 { 455 if (cwsr_enable && kfd->device_info.supports_cwsr) { 456 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 457 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 458 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 459 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 460 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 461 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 462 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 463 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 464 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 465 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 466 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 467 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 468 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) { 469 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE); 470 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 471 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 472 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 473 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 474 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 475 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 476 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 477 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 478 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 479 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 480 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 481 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 482 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 483 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 484 } else { 485 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 486 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 487 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 488 } 489 490 kfd->cwsr_enabled = true; 491 } 492 } 493 494 static int kfd_gws_init(struct kfd_node *node) 495 { 496 int ret = 0; 497 struct kfd_dev *kfd = node->kfd; 498 499 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 500 return 0; 501 502 if (hws_gws_support || (KFD_IS_SOC15(node) && 503 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 504 && kfd->mec2_fw_version >= 0x81b3) || 505 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 506 && kfd->mec2_fw_version >= 0x1b3) || 507 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 508 && kfd->mec2_fw_version >= 0x30) || 509 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 510 && kfd->mec2_fw_version >= 0x28) || 511 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3)) || 512 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 513 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 514 && kfd->mec2_fw_version >= 0x6b)))) 515 ret = amdgpu_amdkfd_alloc_gws(node->adev, 516 node->adev->gds.gws_size, &node->gws); 517 518 return ret; 519 } 520 521 static void kfd_smi_init(struct kfd_node *dev) 522 { 523 INIT_LIST_HEAD(&dev->smi_clients); 524 spin_lock_init(&dev->smi_lock); 525 } 526 527 static int kfd_init_node(struct kfd_node *node) 528 { 529 int err = -1; 530 531 if (kfd_interrupt_init(node)) { 532 dev_err(kfd_device, "Error initializing interrupts\n"); 533 goto kfd_interrupt_error; 534 } 535 536 node->dqm = device_queue_manager_init(node); 537 if (!node->dqm) { 538 dev_err(kfd_device, "Error initializing queue manager\n"); 539 goto device_queue_manager_error; 540 } 541 542 if (kfd_gws_init(node)) { 543 dev_err(kfd_device, "Could not allocate %d gws\n", 544 node->adev->gds.gws_size); 545 goto gws_error; 546 } 547 548 if (kfd_resume(node)) 549 goto kfd_resume_error; 550 551 if (kfd_topology_add_device(node)) { 552 dev_err(kfd_device, "Error adding device to topology\n"); 553 goto kfd_topology_add_device_error; 554 } 555 556 kfd_smi_init(node); 557 558 return 0; 559 560 kfd_topology_add_device_error: 561 kfd_resume_error: 562 gws_error: 563 device_queue_manager_uninit(node->dqm); 564 device_queue_manager_error: 565 kfd_interrupt_exit(node); 566 kfd_interrupt_error: 567 if (node->gws) 568 amdgpu_amdkfd_free_gws(node->adev, node->gws); 569 570 /* Cleanup the node memory here */ 571 kfree(node); 572 return err; 573 } 574 575 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 576 { 577 struct kfd_node *knode; 578 unsigned int i; 579 580 for (i = 0; i < num_nodes; i++) { 581 knode = kfd->nodes[i]; 582 device_queue_manager_uninit(knode->dqm); 583 kfd_interrupt_exit(knode); 584 kfd_topology_remove_device(knode); 585 if (knode->gws) 586 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 587 kfree(knode); 588 kfd->nodes[i] = NULL; 589 } 590 } 591 592 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 593 unsigned int kfd_node_idx) 594 { 595 struct amdgpu_device *adev = node->adev; 596 uint32_t xcc_mask = node->xcc_mask; 597 uint32_t xcc, mapped_xcc; 598 /* 599 * Interrupt bitmap is setup for processing interrupts from 600 * different XCDs and AIDs. 601 * Interrupt bitmap is defined as follows: 602 * 1. Bits 0-15 - correspond to the NodeId field. 603 * Each bit corresponds to NodeId number. For example, if 604 * a KFD node has interrupt bitmap set to 0x7, then this 605 * KFD node will process interrupts with NodeId = 0, 1 and 2 606 * in the IH cookie. 607 * 2. Bits 16-31 - unused. 608 * 609 * Please note that the kfd_node_idx argument passed to this 610 * function is not related to NodeId field received in the 611 * IH cookie. 612 * 613 * In CPX mode, a KFD node will process an interrupt if: 614 * - the Node Id matches the corresponding bit set in 615 * Bits 0-15. 616 * - AND VMID reported in the interrupt lies within the 617 * VMID range of the node. 618 */ 619 for_each_inst(xcc, xcc_mask) { 620 mapped_xcc = GET_INST(GC, xcc); 621 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 622 } 623 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 624 node->interrupt_bitmap); 625 } 626 627 bool kgd2kfd_device_init(struct kfd_dev *kfd, 628 const struct kgd2kfd_shared_resources *gpu_resources) 629 { 630 unsigned int size, map_process_packet_size, i; 631 struct kfd_node *node; 632 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 633 unsigned int max_proc_per_quantum; 634 int partition_mode; 635 int xcp_idx; 636 637 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 638 KGD_ENGINE_MEC1); 639 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 640 KGD_ENGINE_MEC2); 641 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 642 KGD_ENGINE_SDMA1); 643 kfd->shared_resources = *gpu_resources; 644 645 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 646 647 if (kfd->num_nodes == 0) { 648 dev_err(kfd_device, 649 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 650 kfd->adev->gfx.num_xcc_per_xcp); 651 goto out; 652 } 653 654 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 655 * 32 and 64-bit requests are possible and must be 656 * supported. 657 */ 658 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 659 if (!kfd->pci_atomic_requested && 660 kfd->device_info.needs_pci_atomics && 661 (!kfd->device_info.no_atomic_fw_version || 662 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 663 dev_info(kfd_device, 664 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 665 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 666 kfd->mec_fw_version, 667 kfd->device_info.no_atomic_fw_version); 668 return false; 669 } 670 671 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 672 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 673 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 674 675 /* For GFX9.4.3, we need special handling for VMIDs depending on 676 * partition mode. 677 * In CPX mode, the VMID range needs to be shared between XCDs. 678 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 679 * divide them equally, we change starting VMID to 4 and not use 680 * VMID 3. 681 * If the VMID range changes for GFX9.4.3, then this code MUST be 682 * revisited. 683 */ 684 if (kfd->adev->xcp_mgr) { 685 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 686 AMDGPU_XCP_FL_LOCKED); 687 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 688 kfd->num_nodes != 1) { 689 vmid_num_kfd /= 2; 690 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 691 } 692 } 693 694 /* Verify module parameters regarding mapped process number*/ 695 if (hws_max_conc_proc >= 0) 696 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 697 else 698 max_proc_per_quantum = vmid_num_kfd; 699 700 /* calculate max size of mqds needed for queues */ 701 size = max_num_of_queues_per_device * 702 kfd->device_info.mqd_size_aligned; 703 704 /* 705 * calculate max size of runlist packet. 706 * There can be only 2 packets at once 707 */ 708 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 709 sizeof(struct pm4_mes_map_process_aldebaran) : 710 sizeof(struct pm4_mes_map_process); 711 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 712 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 713 + sizeof(struct pm4_mes_runlist)) * 2; 714 715 /* Add size of HIQ & DIQ */ 716 size += KFD_KERNEL_QUEUE_SIZE * 2; 717 718 /* add another 512KB for all other allocations on gart (HPD, fences) */ 719 size += 512 * 1024; 720 721 if (amdgpu_amdkfd_alloc_gtt_mem( 722 kfd->adev, size, &kfd->gtt_mem, 723 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 724 false)) { 725 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 726 goto alloc_gtt_mem_failure; 727 } 728 729 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 730 731 /* Initialize GTT sa with 512 byte chunk size */ 732 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 733 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 734 goto kfd_gtt_sa_init_error; 735 } 736 737 if (kfd_doorbell_init(kfd)) { 738 dev_err(kfd_device, 739 "Error initializing doorbell aperture\n"); 740 goto kfd_doorbell_error; 741 } 742 743 if (amdgpu_use_xgmi_p2p) 744 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 745 746 /* 747 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 748 * xGMI connected in the topology so assign a unique hive id per 749 * device based on the pci device location if device is in PCIe mode. 750 */ 751 if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1) 752 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 753 754 kfd->noretry = kfd->adev->gmc.noretry; 755 756 /* If CRAT is broken, won't set iommu enabled */ 757 kfd_double_confirm_iommu_support(kfd); 758 759 if (kfd_iommu_device_init(kfd)) { 760 kfd->use_iommu_v2 = false; 761 dev_err(kfd_device, "Error initializing iommuv2\n"); 762 goto device_iommu_error; 763 } 764 765 kfd_cwsr_init(kfd); 766 767 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 768 kfd->num_nodes); 769 770 /* Allocate the KFD nodes */ 771 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 772 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 773 if (!node) 774 goto node_alloc_error; 775 776 node->node_id = i; 777 node->adev = kfd->adev; 778 node->kfd = kfd; 779 node->kfd2kgd = kfd->kfd2kgd; 780 node->vm_info.vmid_num_kfd = vmid_num_kfd; 781 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 782 /* TODO : Check if error handling is needed */ 783 if (node->xcp) { 784 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 785 &node->xcc_mask); 786 ++xcp_idx; 787 } else { 788 node->xcc_mask = 789 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 790 } 791 792 if (node->xcp) { 793 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 794 node->node_id, node->xcp->mem_id, 795 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 796 } 797 798 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 799 partition_mode == AMDGPU_CPX_PARTITION_MODE && 800 kfd->num_nodes != 1) { 801 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 802 * 4-9 and second XCD gets VMID range 10-15. 803 */ 804 805 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 806 first_vmid_kfd : 807 first_vmid_kfd+vmid_num_kfd; 808 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 809 last_vmid_kfd-vmid_num_kfd : 810 last_vmid_kfd; 811 node->compute_vmid_bitmap = 812 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 813 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 814 } else { 815 node->vm_info.first_vmid_kfd = first_vmid_kfd; 816 node->vm_info.last_vmid_kfd = last_vmid_kfd; 817 node->compute_vmid_bitmap = 818 gpu_resources->compute_vmid_bitmap; 819 } 820 node->max_proc_per_quantum = max_proc_per_quantum; 821 atomic_set(&node->sram_ecc_flag, 0); 822 823 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 824 &node->local_mem_info, node->xcp); 825 826 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) 827 kfd_setup_interrupt_bitmap(node, i); 828 829 /* Initialize the KFD node */ 830 if (kfd_init_node(node)) { 831 dev_err(kfd_device, "Error initializing KFD node\n"); 832 goto node_init_error; 833 } 834 kfd->nodes[i] = node; 835 } 836 837 svm_range_set_max_pages(kfd->adev); 838 839 if (kfd_resume_iommu(kfd)) 840 goto kfd_resume_iommu_error; 841 842 spin_lock_init(&kfd->watch_points_lock); 843 844 kfd->init_complete = true; 845 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 846 kfd->adev->pdev->device); 847 848 pr_debug("Starting kfd with the following scheduling policy %d\n", 849 node->dqm->sched_policy); 850 851 goto out; 852 853 kfd_resume_iommu_error: 854 node_init_error: 855 node_alloc_error: 856 kfd_cleanup_nodes(kfd, i); 857 device_iommu_error: 858 kfd_doorbell_fini(kfd); 859 kfd_doorbell_error: 860 kfd_gtt_sa_fini(kfd); 861 kfd_gtt_sa_init_error: 862 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 863 alloc_gtt_mem_failure: 864 dev_err(kfd_device, 865 "device %x:%x NOT added due to errors\n", 866 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 867 out: 868 return kfd->init_complete; 869 } 870 871 void kgd2kfd_device_exit(struct kfd_dev *kfd) 872 { 873 if (kfd->init_complete) { 874 /* Cleanup KFD nodes */ 875 kfd_cleanup_nodes(kfd, kfd->num_nodes); 876 /* Cleanup common/shared resources */ 877 kfd_doorbell_fini(kfd); 878 ida_destroy(&kfd->doorbell_ida); 879 kfd_gtt_sa_fini(kfd); 880 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 881 } 882 883 kfree(kfd); 884 } 885 886 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 887 { 888 struct kfd_node *node; 889 int i; 890 891 if (!kfd->init_complete) 892 return 0; 893 894 for (i = 0; i < kfd->num_nodes; i++) { 895 node = kfd->nodes[i]; 896 kfd_smi_event_update_gpu_reset(node, false); 897 node->dqm->ops.pre_reset(node->dqm); 898 } 899 900 kgd2kfd_suspend(kfd, false); 901 902 for (i = 0; i < kfd->num_nodes; i++) 903 kfd_signal_reset_event(kfd->nodes[i]); 904 905 return 0; 906 } 907 908 /* 909 * Fix me. KFD won't be able to resume existing process for now. 910 * We will keep all existing process in a evicted state and 911 * wait the process to be terminated. 912 */ 913 914 int kgd2kfd_post_reset(struct kfd_dev *kfd) 915 { 916 int ret; 917 struct kfd_node *node; 918 int i; 919 920 if (!kfd->init_complete) 921 return 0; 922 923 for (i = 0; i < kfd->num_nodes; i++) { 924 ret = kfd_resume(kfd->nodes[i]); 925 if (ret) 926 return ret; 927 } 928 929 mutex_lock(&kfd_processes_mutex); 930 --kfd_locked; 931 mutex_unlock(&kfd_processes_mutex); 932 933 for (i = 0; i < kfd->num_nodes; i++) { 934 node = kfd->nodes[i]; 935 atomic_set(&node->sram_ecc_flag, 0); 936 kfd_smi_event_update_gpu_reset(node, true); 937 } 938 939 return 0; 940 } 941 942 bool kfd_is_locked(void) 943 { 944 lockdep_assert_held(&kfd_processes_mutex); 945 return (kfd_locked > 0); 946 } 947 948 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 949 { 950 struct kfd_node *node; 951 int i; 952 int count; 953 954 if (!kfd->init_complete) 955 return; 956 957 /* for runtime suspend, skip locking kfd */ 958 if (!run_pm) { 959 mutex_lock(&kfd_processes_mutex); 960 count = ++kfd_locked; 961 mutex_unlock(&kfd_processes_mutex); 962 963 /* For first KFD device suspend all the KFD processes */ 964 if (count == 1) 965 kfd_suspend_all_processes(); 966 } 967 968 for (i = 0; i < kfd->num_nodes; i++) { 969 node = kfd->nodes[i]; 970 node->dqm->ops.stop(node->dqm); 971 } 972 kfd_iommu_suspend(kfd); 973 } 974 975 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 976 { 977 int ret, count, i; 978 979 if (!kfd->init_complete) 980 return 0; 981 982 for (i = 0; i < kfd->num_nodes; i++) { 983 ret = kfd_resume(kfd->nodes[i]); 984 if (ret) 985 return ret; 986 } 987 988 /* for runtime resume, skip unlocking kfd */ 989 if (!run_pm) { 990 mutex_lock(&kfd_processes_mutex); 991 count = --kfd_locked; 992 mutex_unlock(&kfd_processes_mutex); 993 994 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 995 if (count == 0) 996 ret = kfd_resume_all_processes(); 997 } 998 999 return ret; 1000 } 1001 1002 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 1003 { 1004 if (!kfd->init_complete) 1005 return 0; 1006 1007 return kfd_resume_iommu(kfd); 1008 } 1009 1010 static int kfd_resume_iommu(struct kfd_dev *kfd) 1011 { 1012 int err = 0; 1013 1014 err = kfd_iommu_resume(kfd); 1015 if (err) 1016 dev_err(kfd_device, 1017 "Failed to resume IOMMU for device %x:%x\n", 1018 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 1019 return err; 1020 } 1021 1022 static int kfd_resume(struct kfd_node *node) 1023 { 1024 int err = 0; 1025 1026 err = node->dqm->ops.start(node->dqm); 1027 if (err) 1028 dev_err(kfd_device, 1029 "Error starting queue manager for device %x:%x\n", 1030 node->adev->pdev->vendor, node->adev->pdev->device); 1031 1032 return err; 1033 } 1034 1035 static inline void kfd_queue_work(struct workqueue_struct *wq, 1036 struct work_struct *work) 1037 { 1038 int cpu, new_cpu; 1039 1040 cpu = new_cpu = smp_processor_id(); 1041 do { 1042 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1043 if (cpu_to_node(new_cpu) == numa_node_id()) 1044 break; 1045 } while (cpu != new_cpu); 1046 1047 queue_work_on(new_cpu, wq, work); 1048 } 1049 1050 /* This is called directly from KGD at ISR. */ 1051 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1052 { 1053 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1054 bool is_patched = false; 1055 unsigned long flags; 1056 struct kfd_node *node; 1057 1058 if (!kfd->init_complete) 1059 return; 1060 1061 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1062 dev_err_once(kfd_device, "Ring entry too small\n"); 1063 return; 1064 } 1065 1066 for (i = 0; i < kfd->num_nodes; i++) { 1067 node = kfd->nodes[i]; 1068 spin_lock_irqsave(&node->interrupt_lock, flags); 1069 1070 if (node->interrupts_active 1071 && interrupt_is_wanted(node, ih_ring_entry, 1072 patched_ihre, &is_patched) 1073 && enqueue_ih_ring_entry(node, 1074 is_patched ? patched_ihre : ih_ring_entry)) { 1075 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1076 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1077 return; 1078 } 1079 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1080 } 1081 1082 } 1083 1084 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1085 { 1086 struct kfd_process *p; 1087 int r; 1088 1089 /* Because we are called from arbitrary context (workqueue) as opposed 1090 * to process context, kfd_process could attempt to exit while we are 1091 * running so the lookup function increments the process ref count. 1092 */ 1093 p = kfd_lookup_process_by_mm(mm); 1094 if (!p) 1095 return -ESRCH; 1096 1097 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1098 r = kfd_process_evict_queues(p, trigger); 1099 1100 kfd_unref_process(p); 1101 return r; 1102 } 1103 1104 int kgd2kfd_resume_mm(struct mm_struct *mm) 1105 { 1106 struct kfd_process *p; 1107 int r; 1108 1109 /* Because we are called from arbitrary context (workqueue) as opposed 1110 * to process context, kfd_process could attempt to exit while we are 1111 * running so the lookup function increments the process ref count. 1112 */ 1113 p = kfd_lookup_process_by_mm(mm); 1114 if (!p) 1115 return -ESRCH; 1116 1117 r = kfd_process_restore_queues(p); 1118 1119 kfd_unref_process(p); 1120 return r; 1121 } 1122 1123 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1124 * prepare for safe eviction of KFD BOs that belong to the specified 1125 * process. 1126 * 1127 * @mm: mm_struct that identifies the specified KFD process 1128 * @fence: eviction fence attached to KFD process BOs 1129 * 1130 */ 1131 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1132 struct dma_fence *fence) 1133 { 1134 struct kfd_process *p; 1135 unsigned long active_time; 1136 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1137 1138 if (!fence) 1139 return -EINVAL; 1140 1141 if (dma_fence_is_signaled(fence)) 1142 return 0; 1143 1144 p = kfd_lookup_process_by_mm(mm); 1145 if (!p) 1146 return -ENODEV; 1147 1148 if (fence->seqno == p->last_eviction_seqno) 1149 goto out; 1150 1151 p->last_eviction_seqno = fence->seqno; 1152 1153 /* Avoid KFD process starvation. Wait for at least 1154 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1155 */ 1156 active_time = get_jiffies_64() - p->last_restore_timestamp; 1157 if (delay_jiffies > active_time) 1158 delay_jiffies -= active_time; 1159 else 1160 delay_jiffies = 0; 1161 1162 /* During process initialization eviction_work.dwork is initialized 1163 * to kfd_evict_bo_worker 1164 */ 1165 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1166 p->lead_thread->pid, delay_jiffies); 1167 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1168 out: 1169 kfd_unref_process(p); 1170 return 0; 1171 } 1172 1173 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1174 unsigned int chunk_size) 1175 { 1176 if (WARN_ON(buf_size < chunk_size)) 1177 return -EINVAL; 1178 if (WARN_ON(buf_size == 0)) 1179 return -EINVAL; 1180 if (WARN_ON(chunk_size == 0)) 1181 return -EINVAL; 1182 1183 kfd->gtt_sa_chunk_size = chunk_size; 1184 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1185 1186 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1187 GFP_KERNEL); 1188 if (!kfd->gtt_sa_bitmap) 1189 return -ENOMEM; 1190 1191 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1192 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1193 1194 mutex_init(&kfd->gtt_sa_lock); 1195 1196 return 0; 1197 } 1198 1199 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1200 { 1201 mutex_destroy(&kfd->gtt_sa_lock); 1202 bitmap_free(kfd->gtt_sa_bitmap); 1203 } 1204 1205 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1206 unsigned int bit_num, 1207 unsigned int chunk_size) 1208 { 1209 return start_addr + bit_num * chunk_size; 1210 } 1211 1212 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1213 unsigned int bit_num, 1214 unsigned int chunk_size) 1215 { 1216 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1217 } 1218 1219 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1220 struct kfd_mem_obj **mem_obj) 1221 { 1222 unsigned int found, start_search, cur_size; 1223 struct kfd_dev *kfd = node->kfd; 1224 1225 if (size == 0) 1226 return -EINVAL; 1227 1228 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1229 return -ENOMEM; 1230 1231 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1232 if (!(*mem_obj)) 1233 return -ENOMEM; 1234 1235 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1236 1237 start_search = 0; 1238 1239 mutex_lock(&kfd->gtt_sa_lock); 1240 1241 kfd_gtt_restart_search: 1242 /* Find the first chunk that is free */ 1243 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1244 kfd->gtt_sa_num_of_chunks, 1245 start_search); 1246 1247 pr_debug("Found = %d\n", found); 1248 1249 /* If there wasn't any free chunk, bail out */ 1250 if (found == kfd->gtt_sa_num_of_chunks) 1251 goto kfd_gtt_no_free_chunk; 1252 1253 /* Update fields of mem_obj */ 1254 (*mem_obj)->range_start = found; 1255 (*mem_obj)->range_end = found; 1256 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1257 kfd->gtt_start_gpu_addr, 1258 found, 1259 kfd->gtt_sa_chunk_size); 1260 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1261 kfd->gtt_start_cpu_ptr, 1262 found, 1263 kfd->gtt_sa_chunk_size); 1264 1265 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1266 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1267 1268 /* If we need only one chunk, mark it as allocated and get out */ 1269 if (size <= kfd->gtt_sa_chunk_size) { 1270 pr_debug("Single bit\n"); 1271 __set_bit(found, kfd->gtt_sa_bitmap); 1272 goto kfd_gtt_out; 1273 } 1274 1275 /* Otherwise, try to see if we have enough contiguous chunks */ 1276 cur_size = size - kfd->gtt_sa_chunk_size; 1277 do { 1278 (*mem_obj)->range_end = 1279 find_next_zero_bit(kfd->gtt_sa_bitmap, 1280 kfd->gtt_sa_num_of_chunks, ++found); 1281 /* 1282 * If next free chunk is not contiguous than we need to 1283 * restart our search from the last free chunk we found (which 1284 * wasn't contiguous to the previous ones 1285 */ 1286 if ((*mem_obj)->range_end != found) { 1287 start_search = found; 1288 goto kfd_gtt_restart_search; 1289 } 1290 1291 /* 1292 * If we reached end of buffer, bail out with error 1293 */ 1294 if (found == kfd->gtt_sa_num_of_chunks) 1295 goto kfd_gtt_no_free_chunk; 1296 1297 /* Check if we don't need another chunk */ 1298 if (cur_size <= kfd->gtt_sa_chunk_size) 1299 cur_size = 0; 1300 else 1301 cur_size -= kfd->gtt_sa_chunk_size; 1302 1303 } while (cur_size > 0); 1304 1305 pr_debug("range_start = %d, range_end = %d\n", 1306 (*mem_obj)->range_start, (*mem_obj)->range_end); 1307 1308 /* Mark the chunks as allocated */ 1309 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1310 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1311 1312 kfd_gtt_out: 1313 mutex_unlock(&kfd->gtt_sa_lock); 1314 return 0; 1315 1316 kfd_gtt_no_free_chunk: 1317 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1318 mutex_unlock(&kfd->gtt_sa_lock); 1319 kfree(*mem_obj); 1320 return -ENOMEM; 1321 } 1322 1323 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1324 { 1325 struct kfd_dev *kfd = node->kfd; 1326 1327 /* Act like kfree when trying to free a NULL object */ 1328 if (!mem_obj) 1329 return 0; 1330 1331 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1332 mem_obj, mem_obj->range_start, mem_obj->range_end); 1333 1334 mutex_lock(&kfd->gtt_sa_lock); 1335 1336 /* Mark the chunks as free */ 1337 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1338 mem_obj->range_end - mem_obj->range_start + 1); 1339 1340 mutex_unlock(&kfd->gtt_sa_lock); 1341 1342 kfree(mem_obj); 1343 return 0; 1344 } 1345 1346 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1347 { 1348 /* 1349 * TODO: Currently update SRAM ECC flag for first node. 1350 * This needs to be updated later when we can 1351 * identify SRAM ECC error on other nodes also. 1352 */ 1353 if (kfd) 1354 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1355 } 1356 1357 void kfd_inc_compute_active(struct kfd_node *node) 1358 { 1359 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1360 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1361 } 1362 1363 void kfd_dec_compute_active(struct kfd_node *node) 1364 { 1365 int count = atomic_dec_return(&node->kfd->compute_profile); 1366 1367 if (count == 0) 1368 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1369 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1370 } 1371 1372 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1373 { 1374 /* 1375 * TODO: For now, raise the throttling event only on first node. 1376 * This will need to change after we are able to determine 1377 * which node raised the throttling event. 1378 */ 1379 if (kfd && kfd->init_complete) 1380 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1381 throttle_bitmask); 1382 } 1383 1384 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1385 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1386 * When the device has more than two engines, we reserve two for PCIe to enable 1387 * full-duplex and the rest are used as XGMI. 1388 */ 1389 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1390 { 1391 /* If XGMI is not supported, all SDMA engines are PCIe */ 1392 if (!node->adev->gmc.xgmi.supported) 1393 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1394 1395 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1396 } 1397 1398 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1399 { 1400 /* After reserved for PCIe, the rest of engines are XGMI */ 1401 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1402 kfd_get_num_sdma_engines(node); 1403 } 1404 1405 int kgd2kfd_check_and_lock_kfd(void) 1406 { 1407 mutex_lock(&kfd_processes_mutex); 1408 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1409 mutex_unlock(&kfd_processes_mutex); 1410 return -EBUSY; 1411 } 1412 1413 ++kfd_locked; 1414 mutex_unlock(&kfd_processes_mutex); 1415 1416 return 0; 1417 } 1418 1419 void kgd2kfd_unlock_kfd(void) 1420 { 1421 mutex_lock(&kfd_processes_mutex); 1422 --kfd_locked; 1423 mutex_unlock(&kfd_processes_mutex); 1424 } 1425 1426 #if defined(CONFIG_DEBUG_FS) 1427 1428 /* This function will send a package to HIQ to hang the HWS 1429 * which will trigger a GPU reset and bring the HWS back to normal state 1430 */ 1431 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1432 { 1433 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1434 pr_err("HWS is not enabled"); 1435 return -EINVAL; 1436 } 1437 1438 return dqm_debugfs_hang_hws(dev->dqm); 1439 } 1440 1441 #endif 1442