1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(4, 4, 5): 88 case IP_VERSION(4, 4, 4): 89 case IP_VERSION(5, 0, 0):/* NAVI10 */ 90 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 91 case IP_VERSION(5, 0, 2):/* NAVI14 */ 92 case IP_VERSION(5, 0, 5):/* NAVI12 */ 93 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 94 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 95 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 96 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 97 case IP_VERSION(6, 0, 0): 98 case IP_VERSION(6, 0, 1): 99 case IP_VERSION(6, 0, 2): 100 case IP_VERSION(6, 0, 3): 101 case IP_VERSION(6, 1, 0): 102 case IP_VERSION(6, 1, 1): 103 case IP_VERSION(6, 1, 2): 104 case IP_VERSION(6, 1, 3): 105 case IP_VERSION(7, 0, 0): 106 case IP_VERSION(7, 0, 1): 107 kfd->device_info.num_sdma_queues_per_engine = 8; 108 break; 109 default: 110 dev_warn(kfd_device, 111 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 112 sdma_version); 113 kfd->device_info.num_sdma_queues_per_engine = 8; 114 } 115 116 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 117 118 switch (sdma_version) { 119 case IP_VERSION(6, 0, 0): 120 case IP_VERSION(6, 0, 1): 121 case IP_VERSION(6, 0, 2): 122 case IP_VERSION(6, 0, 3): 123 case IP_VERSION(6, 1, 0): 124 case IP_VERSION(6, 1, 1): 125 case IP_VERSION(6, 1, 2): 126 case IP_VERSION(6, 1, 3): 127 case IP_VERSION(7, 0, 0): 128 case IP_VERSION(7, 0, 1): 129 /* Reserve 1 for paging and 1 for gfx */ 130 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 131 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 132 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 133 kfd->adev->sdma.num_instances * 134 kfd->device_info.num_reserved_sdma_queues_per_engine); 135 break; 136 default: 137 break; 138 } 139 } 140 141 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 142 { 143 uint32_t gc_version = KFD_GC_VERSION(kfd); 144 145 switch (gc_version) { 146 case IP_VERSION(9, 0, 1): /* VEGA10 */ 147 case IP_VERSION(9, 1, 0): /* RAVEN */ 148 case IP_VERSION(9, 2, 1): /* VEGA12 */ 149 case IP_VERSION(9, 2, 2): /* RAVEN */ 150 case IP_VERSION(9, 3, 0): /* RENOIR */ 151 case IP_VERSION(9, 4, 0): /* VEGA20 */ 152 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 153 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 154 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 155 break; 156 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 157 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 158 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */ 159 kfd->device_info.event_interrupt_class = 160 &event_interrupt_class_v9_4_3; 161 break; 162 case IP_VERSION(10, 3, 1): /* VANGOGH */ 163 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 164 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 165 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 166 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 167 case IP_VERSION(10, 1, 4): 168 case IP_VERSION(10, 1, 10): /* NAVI10 */ 169 case IP_VERSION(10, 1, 2): /* NAVI12 */ 170 case IP_VERSION(10, 1, 1): /* NAVI14 */ 171 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 172 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 173 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 174 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 175 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 176 break; 177 case IP_VERSION(11, 0, 0): 178 case IP_VERSION(11, 0, 1): 179 case IP_VERSION(11, 0, 2): 180 case IP_VERSION(11, 0, 3): 181 case IP_VERSION(11, 0, 4): 182 case IP_VERSION(11, 5, 0): 183 case IP_VERSION(11, 5, 1): 184 case IP_VERSION(11, 5, 2): 185 case IP_VERSION(11, 5, 3): 186 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 187 break; 188 case IP_VERSION(12, 0, 0): 189 case IP_VERSION(12, 0, 1): 190 /* GFX12_TODO: Change to v12 version. */ 191 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 192 break; 193 default: 194 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 195 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 196 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 197 } 198 } 199 200 static void kfd_device_info_init(struct kfd_dev *kfd, 201 bool vf, uint32_t gfx_target_version) 202 { 203 uint32_t gc_version = KFD_GC_VERSION(kfd); 204 uint32_t asic_type = kfd->adev->asic_type; 205 206 kfd->device_info.max_pasid_bits = 16; 207 kfd->device_info.max_no_of_hqd = 24; 208 kfd->device_info.num_of_watch_points = 4; 209 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 210 kfd->device_info.gfx_target_version = gfx_target_version; 211 212 if (KFD_IS_SOC15(kfd)) { 213 kfd->device_info.doorbell_size = 8; 214 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 215 kfd->device_info.supports_cwsr = true; 216 217 kfd_device_info_set_sdma_info(kfd); 218 219 kfd_device_info_set_event_interrupt_class(kfd); 220 221 if (gc_version < IP_VERSION(11, 0, 0)) { 222 /* Navi2x+, Navi1x+ */ 223 if (gc_version == IP_VERSION(10, 3, 6)) 224 kfd->device_info.no_atomic_fw_version = 14; 225 else if (gc_version == IP_VERSION(10, 3, 7)) 226 kfd->device_info.no_atomic_fw_version = 3; 227 else if (gc_version >= IP_VERSION(10, 3, 0)) 228 kfd->device_info.no_atomic_fw_version = 92; 229 else if (gc_version >= IP_VERSION(10, 1, 1)) 230 kfd->device_info.no_atomic_fw_version = 145; 231 232 /* Navi1x+ */ 233 if (gc_version >= IP_VERSION(10, 1, 1)) 234 kfd->device_info.needs_pci_atomics = true; 235 } else if (gc_version < IP_VERSION(12, 0, 0)) { 236 /* 237 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 238 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 239 * PCIe atomics support. 240 */ 241 kfd->device_info.needs_pci_atomics = true; 242 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 243 } else if (gc_version < IP_VERSION(13, 0, 0)) { 244 kfd->device_info.needs_pci_atomics = true; 245 kfd->device_info.no_atomic_fw_version = 2090; 246 } else { 247 kfd->device_info.needs_pci_atomics = true; 248 } 249 } else { 250 kfd->device_info.doorbell_size = 4; 251 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 252 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 253 kfd->device_info.num_sdma_queues_per_engine = 2; 254 255 if (asic_type != CHIP_KAVERI && 256 asic_type != CHIP_HAWAII && 257 asic_type != CHIP_TONGA) 258 kfd->device_info.supports_cwsr = true; 259 260 if (asic_type != CHIP_HAWAII && !vf) 261 kfd->device_info.needs_pci_atomics = true; 262 } 263 } 264 265 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 266 { 267 struct kfd_dev *kfd = NULL; 268 const struct kfd2kgd_calls *f2g = NULL; 269 uint32_t gfx_target_version = 0; 270 271 switch (adev->asic_type) { 272 #ifdef CONFIG_DRM_AMDGPU_CIK 273 case CHIP_KAVERI: 274 gfx_target_version = 70000; 275 if (!vf) 276 f2g = &gfx_v7_kfd2kgd; 277 break; 278 #endif 279 case CHIP_CARRIZO: 280 gfx_target_version = 80001; 281 if (!vf) 282 f2g = &gfx_v8_kfd2kgd; 283 break; 284 #ifdef CONFIG_DRM_AMDGPU_CIK 285 case CHIP_HAWAII: 286 gfx_target_version = 70001; 287 if (!amdgpu_exp_hw_support) 288 pr_info( 289 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 290 ); 291 else if (!vf) 292 f2g = &gfx_v7_kfd2kgd; 293 break; 294 #endif 295 case CHIP_TONGA: 296 gfx_target_version = 80002; 297 if (!vf) 298 f2g = &gfx_v8_kfd2kgd; 299 break; 300 case CHIP_FIJI: 301 case CHIP_POLARIS10: 302 gfx_target_version = 80003; 303 f2g = &gfx_v8_kfd2kgd; 304 break; 305 case CHIP_POLARIS11: 306 case CHIP_POLARIS12: 307 case CHIP_VEGAM: 308 gfx_target_version = 80003; 309 if (!vf) 310 f2g = &gfx_v8_kfd2kgd; 311 break; 312 default: 313 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 314 /* Vega 10 */ 315 case IP_VERSION(9, 0, 1): 316 gfx_target_version = 90000; 317 f2g = &gfx_v9_kfd2kgd; 318 break; 319 /* Raven */ 320 case IP_VERSION(9, 1, 0): 321 case IP_VERSION(9, 2, 2): 322 gfx_target_version = 90002; 323 if (!vf) 324 f2g = &gfx_v9_kfd2kgd; 325 break; 326 /* Vega12 */ 327 case IP_VERSION(9, 2, 1): 328 gfx_target_version = 90004; 329 if (!vf) 330 f2g = &gfx_v9_kfd2kgd; 331 break; 332 /* Renoir */ 333 case IP_VERSION(9, 3, 0): 334 gfx_target_version = 90012; 335 if (!vf) 336 f2g = &gfx_v9_kfd2kgd; 337 break; 338 /* Vega20 */ 339 case IP_VERSION(9, 4, 0): 340 gfx_target_version = 90006; 341 if (!vf) 342 f2g = &gfx_v9_kfd2kgd; 343 break; 344 /* Arcturus */ 345 case IP_VERSION(9, 4, 1): 346 gfx_target_version = 90008; 347 f2g = &arcturus_kfd2kgd; 348 break; 349 /* Aldebaran */ 350 case IP_VERSION(9, 4, 2): 351 gfx_target_version = 90010; 352 f2g = &aldebaran_kfd2kgd; 353 break; 354 case IP_VERSION(9, 4, 3): 355 gfx_target_version = adev->rev_id >= 1 ? 90402 356 : adev->flags & AMD_IS_APU ? 90400 357 : 90401; 358 f2g = &gc_9_4_3_kfd2kgd; 359 break; 360 case IP_VERSION(9, 4, 4): 361 gfx_target_version = 90402; 362 f2g = &gc_9_4_3_kfd2kgd; 363 break; 364 case IP_VERSION(9, 5, 0): 365 gfx_target_version = 90500; 366 f2g = &gc_9_4_3_kfd2kgd; 367 break; 368 /* Navi10 */ 369 case IP_VERSION(10, 1, 10): 370 gfx_target_version = 100100; 371 if (!vf) 372 f2g = &gfx_v10_kfd2kgd; 373 break; 374 /* Navi12 */ 375 case IP_VERSION(10, 1, 2): 376 gfx_target_version = 100101; 377 f2g = &gfx_v10_kfd2kgd; 378 break; 379 /* Navi14 */ 380 case IP_VERSION(10, 1, 1): 381 gfx_target_version = 100102; 382 if (!vf) 383 f2g = &gfx_v10_kfd2kgd; 384 break; 385 /* Cyan Skillfish */ 386 case IP_VERSION(10, 1, 3): 387 case IP_VERSION(10, 1, 4): 388 gfx_target_version = 100103; 389 if (!vf) 390 f2g = &gfx_v10_kfd2kgd; 391 break; 392 /* Sienna Cichlid */ 393 case IP_VERSION(10, 3, 0): 394 gfx_target_version = 100300; 395 f2g = &gfx_v10_3_kfd2kgd; 396 break; 397 /* Navy Flounder */ 398 case IP_VERSION(10, 3, 2): 399 gfx_target_version = 100301; 400 f2g = &gfx_v10_3_kfd2kgd; 401 break; 402 /* Van Gogh */ 403 case IP_VERSION(10, 3, 1): 404 gfx_target_version = 100303; 405 if (!vf) 406 f2g = &gfx_v10_3_kfd2kgd; 407 break; 408 /* Dimgrey Cavefish */ 409 case IP_VERSION(10, 3, 4): 410 gfx_target_version = 100302; 411 f2g = &gfx_v10_3_kfd2kgd; 412 break; 413 /* Beige Goby */ 414 case IP_VERSION(10, 3, 5): 415 gfx_target_version = 100304; 416 f2g = &gfx_v10_3_kfd2kgd; 417 break; 418 /* Yellow Carp */ 419 case IP_VERSION(10, 3, 3): 420 gfx_target_version = 100305; 421 if (!vf) 422 f2g = &gfx_v10_3_kfd2kgd; 423 break; 424 case IP_VERSION(10, 3, 6): 425 case IP_VERSION(10, 3, 7): 426 gfx_target_version = 100306; 427 if (!vf) 428 f2g = &gfx_v10_3_kfd2kgd; 429 break; 430 case IP_VERSION(11, 0, 0): 431 gfx_target_version = 110000; 432 f2g = &gfx_v11_kfd2kgd; 433 break; 434 case IP_VERSION(11, 0, 1): 435 case IP_VERSION(11, 0, 4): 436 gfx_target_version = 110003; 437 f2g = &gfx_v11_kfd2kgd; 438 break; 439 case IP_VERSION(11, 0, 2): 440 gfx_target_version = 110002; 441 f2g = &gfx_v11_kfd2kgd; 442 break; 443 case IP_VERSION(11, 0, 3): 444 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 445 gfx_target_version = 110001; 446 f2g = &gfx_v11_kfd2kgd; 447 break; 448 case IP_VERSION(11, 5, 0): 449 gfx_target_version = 110500; 450 f2g = &gfx_v11_kfd2kgd; 451 break; 452 case IP_VERSION(11, 5, 1): 453 gfx_target_version = 110501; 454 f2g = &gfx_v11_kfd2kgd; 455 break; 456 case IP_VERSION(11, 5, 2): 457 gfx_target_version = 110502; 458 f2g = &gfx_v11_kfd2kgd; 459 break; 460 case IP_VERSION(11, 5, 3): 461 gfx_target_version = 110503; 462 f2g = &gfx_v11_kfd2kgd; 463 break; 464 case IP_VERSION(12, 0, 0): 465 gfx_target_version = 120000; 466 f2g = &gfx_v12_kfd2kgd; 467 break; 468 case IP_VERSION(12, 0, 1): 469 gfx_target_version = 120001; 470 f2g = &gfx_v12_kfd2kgd; 471 break; 472 default: 473 break; 474 } 475 break; 476 } 477 478 if (!f2g) { 479 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 480 dev_info(kfd_device, 481 "GC IP %06x %s not supported in kfd\n", 482 amdgpu_ip_version(adev, GC_HWIP, 0), 483 vf ? "VF" : ""); 484 else 485 dev_info(kfd_device, "%s %s not supported in kfd\n", 486 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 487 return NULL; 488 } 489 490 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 491 if (!kfd) 492 return NULL; 493 494 kfd->adev = adev; 495 kfd_device_info_init(kfd, vf, gfx_target_version); 496 kfd->init_complete = false; 497 kfd->kfd2kgd = f2g; 498 atomic_set(&kfd->compute_profile, 0); 499 500 mutex_init(&kfd->doorbell_mutex); 501 502 ida_init(&kfd->doorbell_ida); 503 504 return kfd; 505 } 506 507 static void kfd_cwsr_init(struct kfd_dev *kfd) 508 { 509 if (cwsr_enable && kfd->device_info.supports_cwsr) { 510 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 511 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 512 > KFD_CWSR_TMA_OFFSET); 513 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 514 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 515 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 516 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 517 > KFD_CWSR_TMA_OFFSET); 518 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 519 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 520 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 521 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 522 > KFD_CWSR_TMA_OFFSET); 523 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 524 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 525 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 526 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 527 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 528 > KFD_CWSR_TMA_OFFSET); 529 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 530 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 531 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) { 532 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE); 533 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex; 534 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex); 535 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 536 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 537 > KFD_CWSR_TMA_OFFSET); 538 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 539 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 540 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 541 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 542 > KFD_CWSR_TMA_OFFSET); 543 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 544 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 545 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 546 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 547 > KFD_CWSR_TMA_OFFSET); 548 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 549 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 550 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 551 /* The gfx11 cwsr trap handler must fit inside a single 552 page. */ 553 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 554 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 555 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 556 } else { 557 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 558 > KFD_CWSR_TMA_OFFSET); 559 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 560 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 561 } 562 563 kfd->cwsr_enabled = true; 564 } 565 } 566 567 static int kfd_gws_init(struct kfd_node *node) 568 { 569 int ret = 0; 570 struct kfd_dev *kfd = node->kfd; 571 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 572 573 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 574 return 0; 575 576 if (hws_gws_support || (KFD_IS_SOC15(node) && 577 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 578 && kfd->mec2_fw_version >= 0x81b3) || 579 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 580 && kfd->mec2_fw_version >= 0x1b3) || 581 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 582 && kfd->mec2_fw_version >= 0x30) || 583 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 584 && kfd->mec2_fw_version >= 0x28) || 585 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 586 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 587 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) || 588 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 589 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 590 && kfd->mec2_fw_version >= 0x6b) || 591 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 592 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 593 && mes_rev >= 68) || 594 (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))))) { 595 if (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0)) 596 node->adev->gds.gws_size = 64; 597 ret = amdgpu_amdkfd_alloc_gws(node->adev, 598 node->adev->gds.gws_size, &node->gws); 599 } 600 601 return ret; 602 } 603 604 static void kfd_smi_init(struct kfd_node *dev) 605 { 606 INIT_LIST_HEAD(&dev->smi_clients); 607 spin_lock_init(&dev->smi_lock); 608 } 609 610 static int kfd_init_node(struct kfd_node *node) 611 { 612 int err = -1; 613 614 if (kfd_interrupt_init(node)) { 615 dev_err(kfd_device, "Error initializing interrupts\n"); 616 goto kfd_interrupt_error; 617 } 618 619 node->dqm = device_queue_manager_init(node); 620 if (!node->dqm) { 621 dev_err(kfd_device, "Error initializing queue manager\n"); 622 goto device_queue_manager_error; 623 } 624 625 if (kfd_gws_init(node)) { 626 dev_err(kfd_device, "Could not allocate %d gws\n", 627 node->adev->gds.gws_size); 628 goto gws_error; 629 } 630 631 if (kfd_resume(node)) 632 goto kfd_resume_error; 633 634 if (kfd_topology_add_device(node)) { 635 dev_err(kfd_device, "Error adding device to topology\n"); 636 goto kfd_topology_add_device_error; 637 } 638 639 kfd_smi_init(node); 640 641 return 0; 642 643 kfd_topology_add_device_error: 644 kfd_resume_error: 645 gws_error: 646 device_queue_manager_uninit(node->dqm); 647 device_queue_manager_error: 648 kfd_interrupt_exit(node); 649 kfd_interrupt_error: 650 if (node->gws) 651 amdgpu_amdkfd_free_gws(node->adev, node->gws); 652 653 /* Cleanup the node memory here */ 654 kfree(node); 655 return err; 656 } 657 658 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 659 { 660 struct kfd_node *knode; 661 unsigned int i; 662 663 /* 664 * flush_work ensures that there are no outstanding 665 * work-queue items that will access interrupt_ring. New work items 666 * can't be created because we stopped interrupt handling above. 667 */ 668 flush_workqueue(kfd->ih_wq); 669 destroy_workqueue(kfd->ih_wq); 670 671 for (i = 0; i < num_nodes; i++) { 672 knode = kfd->nodes[i]; 673 device_queue_manager_uninit(knode->dqm); 674 kfd_interrupt_exit(knode); 675 kfd_topology_remove_device(knode); 676 if (knode->gws) 677 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 678 kfree(knode); 679 kfd->nodes[i] = NULL; 680 } 681 } 682 683 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 684 unsigned int kfd_node_idx) 685 { 686 struct amdgpu_device *adev = node->adev; 687 uint32_t xcc_mask = node->xcc_mask; 688 uint32_t xcc, mapped_xcc; 689 /* 690 * Interrupt bitmap is setup for processing interrupts from 691 * different XCDs and AIDs. 692 * Interrupt bitmap is defined as follows: 693 * 1. Bits 0-15 - correspond to the NodeId field. 694 * Each bit corresponds to NodeId number. For example, if 695 * a KFD node has interrupt bitmap set to 0x7, then this 696 * KFD node will process interrupts with NodeId = 0, 1 and 2 697 * in the IH cookie. 698 * 2. Bits 16-31 - unused. 699 * 700 * Please note that the kfd_node_idx argument passed to this 701 * function is not related to NodeId field received in the 702 * IH cookie. 703 * 704 * In CPX mode, a KFD node will process an interrupt if: 705 * - the Node Id matches the corresponding bit set in 706 * Bits 0-15. 707 * - AND VMID reported in the interrupt lies within the 708 * VMID range of the node. 709 */ 710 for_each_inst(xcc, xcc_mask) { 711 mapped_xcc = GET_INST(GC, xcc); 712 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 713 } 714 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 715 node->interrupt_bitmap); 716 } 717 718 bool kgd2kfd_device_init(struct kfd_dev *kfd, 719 const struct kgd2kfd_shared_resources *gpu_resources) 720 { 721 unsigned int size, map_process_packet_size, i; 722 struct kfd_node *node; 723 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 724 unsigned int max_proc_per_quantum; 725 int partition_mode; 726 int xcp_idx; 727 728 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 729 KGD_ENGINE_MEC1); 730 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 731 KGD_ENGINE_MEC2); 732 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 733 KGD_ENGINE_SDMA1); 734 kfd->shared_resources = *gpu_resources; 735 736 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 737 738 if (kfd->num_nodes == 0) { 739 dev_err(kfd_device, 740 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 741 kfd->adev->gfx.num_xcc_per_xcp); 742 goto out; 743 } 744 745 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 746 * 32 and 64-bit requests are possible and must be 747 * supported. 748 */ 749 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 750 if (!kfd->pci_atomic_requested && 751 kfd->device_info.needs_pci_atomics && 752 (!kfd->device_info.no_atomic_fw_version || 753 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 754 dev_info(kfd_device, 755 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 756 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 757 kfd->mec_fw_version, 758 kfd->device_info.no_atomic_fw_version); 759 return false; 760 } 761 762 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 763 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 764 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 765 766 /* For multi-partition capable GPUs, we need special handling for VMIDs 767 * depending on partition mode. 768 * In CPX mode, the VMID range needs to be shared between XCDs. 769 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 770 * divide them equally, we change starting VMID to 4 and not use 771 * VMID 3. 772 * If the VMID range changes for multi-partition capable GPUs, then 773 * this code MUST be revisited. 774 */ 775 if (kfd->adev->xcp_mgr) { 776 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 777 AMDGPU_XCP_FL_LOCKED); 778 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 779 kfd->num_nodes != 1) { 780 vmid_num_kfd /= 2; 781 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 782 } 783 } 784 785 /* Verify module parameters regarding mapped process number*/ 786 if (hws_max_conc_proc >= 0) 787 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 788 else 789 max_proc_per_quantum = vmid_num_kfd; 790 791 /* calculate max size of mqds needed for queues */ 792 size = max_num_of_queues_per_device * 793 kfd->device_info.mqd_size_aligned; 794 795 /* 796 * calculate max size of runlist packet. 797 * There can be only 2 packets at once 798 */ 799 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 800 sizeof(struct pm4_mes_map_process_aldebaran) : 801 sizeof(struct pm4_mes_map_process); 802 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 803 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 804 + sizeof(struct pm4_mes_runlist)) * 2; 805 806 /* Add size of HIQ & DIQ */ 807 size += KFD_KERNEL_QUEUE_SIZE * 2; 808 809 /* add another 512KB for all other allocations on gart (HPD, fences) */ 810 size += 512 * 1024; 811 812 if (amdgpu_amdkfd_alloc_gtt_mem( 813 kfd->adev, size, &kfd->gtt_mem, 814 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 815 false)) { 816 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 817 goto alloc_gtt_mem_failure; 818 } 819 820 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 821 822 /* Initialize GTT sa with 512 byte chunk size */ 823 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 824 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 825 goto kfd_gtt_sa_init_error; 826 } 827 828 if (kfd_doorbell_init(kfd)) { 829 dev_err(kfd_device, 830 "Error initializing doorbell aperture\n"); 831 goto kfd_doorbell_error; 832 } 833 834 if (amdgpu_use_xgmi_p2p) 835 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 836 837 /* 838 * For multi-partition capable GPUs, the KFD abstracts all partitions 839 * within a socket as xGMI connected in the topology so assign a unique 840 * hive id per device based on the pci device location if device is in 841 * PCIe mode. 842 */ 843 if (!kfd->hive_id && kfd->num_nodes > 1) 844 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 845 846 kfd->noretry = kfd->adev->gmc.noretry; 847 848 kfd_cwsr_init(kfd); 849 850 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 851 kfd->num_nodes); 852 853 /* Allocate the KFD nodes */ 854 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 855 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 856 if (!node) 857 goto node_alloc_error; 858 859 node->node_id = i; 860 node->adev = kfd->adev; 861 node->kfd = kfd; 862 node->kfd2kgd = kfd->kfd2kgd; 863 node->vm_info.vmid_num_kfd = vmid_num_kfd; 864 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 865 /* TODO : Check if error handling is needed */ 866 if (node->xcp) { 867 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 868 &node->xcc_mask); 869 ++xcp_idx; 870 } else { 871 node->xcc_mask = 872 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 873 } 874 875 if (node->xcp) { 876 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 877 node->node_id, node->xcp->mem_id, 878 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 879 } 880 881 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 882 kfd->num_nodes != 1) { 883 /* For multi-partition capable GPUs and CPX mode, first 884 * XCD gets VMID range 4-9 and second XCD gets VMID 885 * range 10-15. 886 */ 887 888 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 889 first_vmid_kfd : 890 first_vmid_kfd+vmid_num_kfd; 891 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 892 last_vmid_kfd-vmid_num_kfd : 893 last_vmid_kfd; 894 node->compute_vmid_bitmap = 895 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 896 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 897 } else { 898 node->vm_info.first_vmid_kfd = first_vmid_kfd; 899 node->vm_info.last_vmid_kfd = last_vmid_kfd; 900 node->compute_vmid_bitmap = 901 gpu_resources->compute_vmid_bitmap; 902 } 903 node->max_proc_per_quantum = max_proc_per_quantum; 904 atomic_set(&node->sram_ecc_flag, 0); 905 906 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 907 &node->local_mem_info, node->xcp); 908 909 if (kfd->adev->xcp_mgr) 910 kfd_setup_interrupt_bitmap(node, i); 911 912 /* Initialize the KFD node */ 913 if (kfd_init_node(node)) { 914 dev_err(kfd_device, "Error initializing KFD node\n"); 915 goto node_init_error; 916 } 917 918 spin_lock_init(&node->watch_points_lock); 919 920 kfd->nodes[i] = node; 921 } 922 923 svm_range_set_max_pages(kfd->adev); 924 925 kfd->init_complete = true; 926 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 927 kfd->adev->pdev->device); 928 929 pr_debug("Starting kfd with the following scheduling policy %d\n", 930 node->dqm->sched_policy); 931 932 goto out; 933 934 node_init_error: 935 node_alloc_error: 936 kfd_cleanup_nodes(kfd, i); 937 kfd_doorbell_fini(kfd); 938 kfd_doorbell_error: 939 kfd_gtt_sa_fini(kfd); 940 kfd_gtt_sa_init_error: 941 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 942 alloc_gtt_mem_failure: 943 dev_err(kfd_device, 944 "device %x:%x NOT added due to errors\n", 945 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 946 out: 947 return kfd->init_complete; 948 } 949 950 void kgd2kfd_device_exit(struct kfd_dev *kfd) 951 { 952 if (kfd->init_complete) { 953 /* Cleanup KFD nodes */ 954 kfd_cleanup_nodes(kfd, kfd->num_nodes); 955 /* Cleanup common/shared resources */ 956 kfd_doorbell_fini(kfd); 957 ida_destroy(&kfd->doorbell_ida); 958 kfd_gtt_sa_fini(kfd); 959 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 960 } 961 962 kfree(kfd); 963 } 964 965 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 966 struct amdgpu_reset_context *reset_context) 967 { 968 struct kfd_node *node; 969 int i; 970 971 if (!kfd->init_complete) 972 return 0; 973 974 for (i = 0; i < kfd->num_nodes; i++) { 975 node = kfd->nodes[i]; 976 kfd_smi_event_update_gpu_reset(node, false, reset_context); 977 } 978 979 kgd2kfd_suspend(kfd, false); 980 981 for (i = 0; i < kfd->num_nodes; i++) 982 kfd_signal_reset_event(kfd->nodes[i]); 983 984 return 0; 985 } 986 987 /* 988 * Fix me. KFD won't be able to resume existing process for now. 989 * We will keep all existing process in a evicted state and 990 * wait the process to be terminated. 991 */ 992 993 int kgd2kfd_post_reset(struct kfd_dev *kfd) 994 { 995 int ret; 996 struct kfd_node *node; 997 int i; 998 999 if (!kfd->init_complete) 1000 return 0; 1001 1002 for (i = 0; i < kfd->num_nodes; i++) { 1003 ret = kfd_resume(kfd->nodes[i]); 1004 if (ret) 1005 return ret; 1006 } 1007 1008 mutex_lock(&kfd_processes_mutex); 1009 --kfd_locked; 1010 mutex_unlock(&kfd_processes_mutex); 1011 1012 for (i = 0; i < kfd->num_nodes; i++) { 1013 node = kfd->nodes[i]; 1014 atomic_set(&node->sram_ecc_flag, 0); 1015 kfd_smi_event_update_gpu_reset(node, true, NULL); 1016 } 1017 1018 return 0; 1019 } 1020 1021 bool kfd_is_locked(void) 1022 { 1023 lockdep_assert_held(&kfd_processes_mutex); 1024 return (kfd_locked > 0); 1025 } 1026 1027 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 1028 { 1029 struct kfd_node *node; 1030 int i; 1031 1032 if (!kfd->init_complete) 1033 return; 1034 1035 /* for runtime suspend, skip locking kfd */ 1036 if (!run_pm) { 1037 mutex_lock(&kfd_processes_mutex); 1038 /* For first KFD device suspend all the KFD processes */ 1039 if (++kfd_locked == 1) 1040 kfd_suspend_all_processes(); 1041 mutex_unlock(&kfd_processes_mutex); 1042 } 1043 1044 for (i = 0; i < kfd->num_nodes; i++) { 1045 node = kfd->nodes[i]; 1046 node->dqm->ops.stop(node->dqm); 1047 } 1048 } 1049 1050 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1051 { 1052 int ret, i; 1053 1054 if (!kfd->init_complete) 1055 return 0; 1056 1057 for (i = 0; i < kfd->num_nodes; i++) { 1058 ret = kfd_resume(kfd->nodes[i]); 1059 if (ret) 1060 return ret; 1061 } 1062 1063 /* for runtime resume, skip unlocking kfd */ 1064 if (!run_pm) { 1065 mutex_lock(&kfd_processes_mutex); 1066 if (--kfd_locked == 0) 1067 ret = kfd_resume_all_processes(); 1068 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1069 mutex_unlock(&kfd_processes_mutex); 1070 } 1071 1072 return ret; 1073 } 1074 1075 static int kfd_resume(struct kfd_node *node) 1076 { 1077 int err = 0; 1078 1079 err = node->dqm->ops.start(node->dqm); 1080 if (err) 1081 dev_err(kfd_device, 1082 "Error starting queue manager for device %x:%x\n", 1083 node->adev->pdev->vendor, node->adev->pdev->device); 1084 1085 return err; 1086 } 1087 1088 /* This is called directly from KGD at ISR. */ 1089 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1090 { 1091 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1092 bool is_patched = false; 1093 unsigned long flags; 1094 struct kfd_node *node; 1095 1096 if (!kfd->init_complete) 1097 return; 1098 1099 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1100 dev_err_once(kfd_device, "Ring entry too small\n"); 1101 return; 1102 } 1103 1104 for (i = 0; i < kfd->num_nodes; i++) { 1105 node = kfd->nodes[i]; 1106 spin_lock_irqsave(&node->interrupt_lock, flags); 1107 1108 if (node->interrupts_active 1109 && interrupt_is_wanted(node, ih_ring_entry, 1110 patched_ihre, &is_patched) 1111 && enqueue_ih_ring_entry(node, 1112 is_patched ? patched_ihre : ih_ring_entry)) { 1113 queue_work(node->kfd->ih_wq, &node->interrupt_work); 1114 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1115 return; 1116 } 1117 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1118 } 1119 1120 } 1121 1122 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1123 { 1124 struct kfd_process *p; 1125 int r; 1126 1127 /* Because we are called from arbitrary context (workqueue) as opposed 1128 * to process context, kfd_process could attempt to exit while we are 1129 * running so the lookup function increments the process ref count. 1130 */ 1131 p = kfd_lookup_process_by_mm(mm); 1132 if (!p) 1133 return -ESRCH; 1134 1135 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1136 r = kfd_process_evict_queues(p, trigger); 1137 1138 kfd_unref_process(p); 1139 return r; 1140 } 1141 1142 int kgd2kfd_resume_mm(struct mm_struct *mm) 1143 { 1144 struct kfd_process *p; 1145 int r; 1146 1147 /* Because we are called from arbitrary context (workqueue) as opposed 1148 * to process context, kfd_process could attempt to exit while we are 1149 * running so the lookup function increments the process ref count. 1150 */ 1151 p = kfd_lookup_process_by_mm(mm); 1152 if (!p) 1153 return -ESRCH; 1154 1155 r = kfd_process_restore_queues(p); 1156 1157 kfd_unref_process(p); 1158 return r; 1159 } 1160 1161 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1162 * prepare for safe eviction of KFD BOs that belong to the specified 1163 * process. 1164 * 1165 * @mm: mm_struct that identifies the specified KFD process 1166 * @fence: eviction fence attached to KFD process BOs 1167 * 1168 */ 1169 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1170 struct dma_fence *fence) 1171 { 1172 struct kfd_process *p; 1173 unsigned long active_time; 1174 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1175 1176 if (!fence) 1177 return -EINVAL; 1178 1179 if (dma_fence_is_signaled(fence)) 1180 return 0; 1181 1182 p = kfd_lookup_process_by_mm(mm); 1183 if (!p) 1184 return -ENODEV; 1185 1186 if (fence->seqno == p->last_eviction_seqno) 1187 goto out; 1188 1189 p->last_eviction_seqno = fence->seqno; 1190 1191 /* Avoid KFD process starvation. Wait for at least 1192 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1193 */ 1194 active_time = get_jiffies_64() - p->last_restore_timestamp; 1195 if (delay_jiffies > active_time) 1196 delay_jiffies -= active_time; 1197 else 1198 delay_jiffies = 0; 1199 1200 /* During process initialization eviction_work.dwork is initialized 1201 * to kfd_evict_bo_worker 1202 */ 1203 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1204 p->lead_thread->pid, delay_jiffies); 1205 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1206 out: 1207 kfd_unref_process(p); 1208 return 0; 1209 } 1210 1211 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1212 unsigned int chunk_size) 1213 { 1214 if (WARN_ON(buf_size < chunk_size)) 1215 return -EINVAL; 1216 if (WARN_ON(buf_size == 0)) 1217 return -EINVAL; 1218 if (WARN_ON(chunk_size == 0)) 1219 return -EINVAL; 1220 1221 kfd->gtt_sa_chunk_size = chunk_size; 1222 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1223 1224 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1225 GFP_KERNEL); 1226 if (!kfd->gtt_sa_bitmap) 1227 return -ENOMEM; 1228 1229 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1230 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1231 1232 mutex_init(&kfd->gtt_sa_lock); 1233 1234 return 0; 1235 } 1236 1237 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1238 { 1239 mutex_destroy(&kfd->gtt_sa_lock); 1240 bitmap_free(kfd->gtt_sa_bitmap); 1241 } 1242 1243 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1244 unsigned int bit_num, 1245 unsigned int chunk_size) 1246 { 1247 return start_addr + bit_num * chunk_size; 1248 } 1249 1250 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1251 unsigned int bit_num, 1252 unsigned int chunk_size) 1253 { 1254 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1255 } 1256 1257 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1258 struct kfd_mem_obj **mem_obj) 1259 { 1260 unsigned int found, start_search, cur_size; 1261 struct kfd_dev *kfd = node->kfd; 1262 1263 if (size == 0) 1264 return -EINVAL; 1265 1266 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1267 return -ENOMEM; 1268 1269 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1270 if (!(*mem_obj)) 1271 return -ENOMEM; 1272 1273 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1274 1275 start_search = 0; 1276 1277 mutex_lock(&kfd->gtt_sa_lock); 1278 1279 kfd_gtt_restart_search: 1280 /* Find the first chunk that is free */ 1281 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1282 kfd->gtt_sa_num_of_chunks, 1283 start_search); 1284 1285 pr_debug("Found = %d\n", found); 1286 1287 /* If there wasn't any free chunk, bail out */ 1288 if (found == kfd->gtt_sa_num_of_chunks) 1289 goto kfd_gtt_no_free_chunk; 1290 1291 /* Update fields of mem_obj */ 1292 (*mem_obj)->range_start = found; 1293 (*mem_obj)->range_end = found; 1294 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1295 kfd->gtt_start_gpu_addr, 1296 found, 1297 kfd->gtt_sa_chunk_size); 1298 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1299 kfd->gtt_start_cpu_ptr, 1300 found, 1301 kfd->gtt_sa_chunk_size); 1302 1303 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1304 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1305 1306 /* If we need only one chunk, mark it as allocated and get out */ 1307 if (size <= kfd->gtt_sa_chunk_size) { 1308 pr_debug("Single bit\n"); 1309 __set_bit(found, kfd->gtt_sa_bitmap); 1310 goto kfd_gtt_out; 1311 } 1312 1313 /* Otherwise, try to see if we have enough contiguous chunks */ 1314 cur_size = size - kfd->gtt_sa_chunk_size; 1315 do { 1316 (*mem_obj)->range_end = 1317 find_next_zero_bit(kfd->gtt_sa_bitmap, 1318 kfd->gtt_sa_num_of_chunks, ++found); 1319 /* 1320 * If next free chunk is not contiguous than we need to 1321 * restart our search from the last free chunk we found (which 1322 * wasn't contiguous to the previous ones 1323 */ 1324 if ((*mem_obj)->range_end != found) { 1325 start_search = found; 1326 goto kfd_gtt_restart_search; 1327 } 1328 1329 /* 1330 * If we reached end of buffer, bail out with error 1331 */ 1332 if (found == kfd->gtt_sa_num_of_chunks) 1333 goto kfd_gtt_no_free_chunk; 1334 1335 /* Check if we don't need another chunk */ 1336 if (cur_size <= kfd->gtt_sa_chunk_size) 1337 cur_size = 0; 1338 else 1339 cur_size -= kfd->gtt_sa_chunk_size; 1340 1341 } while (cur_size > 0); 1342 1343 pr_debug("range_start = %d, range_end = %d\n", 1344 (*mem_obj)->range_start, (*mem_obj)->range_end); 1345 1346 /* Mark the chunks as allocated */ 1347 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1348 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1349 1350 kfd_gtt_out: 1351 mutex_unlock(&kfd->gtt_sa_lock); 1352 return 0; 1353 1354 kfd_gtt_no_free_chunk: 1355 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1356 mutex_unlock(&kfd->gtt_sa_lock); 1357 kfree(*mem_obj); 1358 return -ENOMEM; 1359 } 1360 1361 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1362 { 1363 struct kfd_dev *kfd = node->kfd; 1364 1365 /* Act like kfree when trying to free a NULL object */ 1366 if (!mem_obj) 1367 return 0; 1368 1369 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1370 mem_obj, mem_obj->range_start, mem_obj->range_end); 1371 1372 mutex_lock(&kfd->gtt_sa_lock); 1373 1374 /* Mark the chunks as free */ 1375 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1376 mem_obj->range_end - mem_obj->range_start + 1); 1377 1378 mutex_unlock(&kfd->gtt_sa_lock); 1379 1380 kfree(mem_obj); 1381 return 0; 1382 } 1383 1384 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1385 { 1386 /* 1387 * TODO: Currently update SRAM ECC flag for first node. 1388 * This needs to be updated later when we can 1389 * identify SRAM ECC error on other nodes also. 1390 */ 1391 if (kfd) 1392 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1393 } 1394 1395 void kfd_inc_compute_active(struct kfd_node *node) 1396 { 1397 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1398 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1399 } 1400 1401 void kfd_dec_compute_active(struct kfd_node *node) 1402 { 1403 int count = atomic_dec_return(&node->kfd->compute_profile); 1404 1405 if (count == 0) 1406 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1407 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1408 } 1409 1410 static bool kfd_compute_active(struct kfd_node *node) 1411 { 1412 if (atomic_read(&node->kfd->compute_profile)) 1413 return true; 1414 return false; 1415 } 1416 1417 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1418 { 1419 /* 1420 * TODO: For now, raise the throttling event only on first node. 1421 * This will need to change after we are able to determine 1422 * which node raised the throttling event. 1423 */ 1424 if (kfd && kfd->init_complete) 1425 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1426 throttle_bitmask); 1427 } 1428 1429 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1430 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1431 * When the device has more than two engines, we reserve two for PCIe to enable 1432 * full-duplex and the rest are used as XGMI. 1433 */ 1434 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1435 { 1436 /* If XGMI is not supported, all SDMA engines are PCIe */ 1437 if (!node->adev->gmc.xgmi.supported) 1438 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1439 1440 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1441 } 1442 1443 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1444 { 1445 /* After reserved for PCIe, the rest of engines are XGMI */ 1446 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1447 kfd_get_num_sdma_engines(node); 1448 } 1449 1450 int kgd2kfd_check_and_lock_kfd(void) 1451 { 1452 mutex_lock(&kfd_processes_mutex); 1453 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1454 mutex_unlock(&kfd_processes_mutex); 1455 return -EBUSY; 1456 } 1457 1458 ++kfd_locked; 1459 mutex_unlock(&kfd_processes_mutex); 1460 1461 return 0; 1462 } 1463 1464 void kgd2kfd_unlock_kfd(void) 1465 { 1466 mutex_lock(&kfd_processes_mutex); 1467 --kfd_locked; 1468 mutex_unlock(&kfd_processes_mutex); 1469 } 1470 1471 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1472 { 1473 struct kfd_node *node; 1474 int ret; 1475 1476 if (!kfd->init_complete) 1477 return 0; 1478 1479 if (node_id >= kfd->num_nodes) { 1480 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1481 node_id, kfd->num_nodes - 1); 1482 return -EINVAL; 1483 } 1484 node = kfd->nodes[node_id]; 1485 1486 ret = node->dqm->ops.unhalt(node->dqm); 1487 if (ret) 1488 dev_err(kfd_device, "Error in starting scheduler\n"); 1489 1490 return ret; 1491 } 1492 1493 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1494 { 1495 struct kfd_node *node; 1496 1497 if (!kfd->init_complete) 1498 return 0; 1499 1500 if (node_id >= kfd->num_nodes) { 1501 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1502 node_id, kfd->num_nodes - 1); 1503 return -EINVAL; 1504 } 1505 1506 node = kfd->nodes[node_id]; 1507 return node->dqm->ops.halt(node->dqm); 1508 } 1509 1510 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1511 { 1512 struct kfd_node *node; 1513 1514 if (!kfd->init_complete) 1515 return false; 1516 1517 if (node_id >= kfd->num_nodes) { 1518 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1519 node_id, kfd->num_nodes - 1); 1520 return false; 1521 } 1522 1523 node = kfd->nodes[node_id]; 1524 1525 return kfd_compute_active(node); 1526 } 1527 1528 /** 1529 * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9 1530 * @adev: amdgpu device 1531 * @entry: vm fault interrupt vector 1532 * @retry_fault: if this is retry fault 1533 * 1534 * retry fault - 1535 * with CAM enabled, adev primary ring 1536 * | gmc_v9_0_process_interrupt() 1537 * adev soft_ring 1538 * | gmc_v9_0_process_interrupt() worker failed to recover page fault 1539 * KFD node ih_fifo 1540 * | KFD interrupt_wq worker 1541 * kfd_signal_vm_fault_event 1542 * 1543 * without CAM, adev primary ring1 1544 * | gmc_v9_0_process_interrupt worker failed to recvoer page fault 1545 * KFD node ih_fifo 1546 * | KFD interrupt_wq worker 1547 * kfd_signal_vm_fault_event 1548 * 1549 * no-retry fault - 1550 * adev primary ring 1551 * | gmc_v9_0_process_interrupt() 1552 * KFD node ih_fifo 1553 * | KFD interrupt_wq worker 1554 * kfd_signal_vm_fault_event 1555 * 1556 * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault 1557 * of same process, don't copy interrupt to KFD node ih_fifo. 1558 * With gdb debugger enabled, need convert the retry fault to no-retry fault for 1559 * debugger, cannot use the fast path. 1560 * 1561 * Return: 1562 * true - use the fast path to handle this fault 1563 * false - use normal path to handle it 1564 */ 1565 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 1566 bool retry_fault) 1567 { 1568 struct kfd_process *p; 1569 u32 cam_index; 1570 1571 if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) { 1572 p = kfd_lookup_process_by_pasid(entry->pasid, NULL); 1573 if (!p) 1574 return true; 1575 1576 if (p->gpu_page_fault && !p->debug_trap_enabled) { 1577 if (retry_fault && adev->irq.retry_cam_enabled) { 1578 cam_index = entry->src_data[2] & 0x3ff; 1579 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 1580 } 1581 1582 kfd_unref_process(p); 1583 return true; 1584 } 1585 1586 /* 1587 * This is the first page fault, set flag and then signal user space 1588 */ 1589 p->gpu_page_fault = true; 1590 kfd_unref_process(p); 1591 } 1592 return false; 1593 } 1594 1595 #if defined(CONFIG_DEBUG_FS) 1596 1597 /* This function will send a package to HIQ to hang the HWS 1598 * which will trigger a GPU reset and bring the HWS back to normal state 1599 */ 1600 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1601 { 1602 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1603 pr_err("HWS is not enabled"); 1604 return -EINVAL; 1605 } 1606 1607 if (dev->kfd->shared_resources.enable_mes) { 1608 dev_err(dev->adev->dev, "Inducing MES hang is not supported\n"); 1609 return -EINVAL; 1610 } 1611 1612 return dqm_debugfs_hang_hws(dev->dqm); 1613 } 1614 1615 #endif 1616