1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(4, 4, 5): 88 case IP_VERSION(4, 4, 4): 89 case IP_VERSION(5, 0, 0):/* NAVI10 */ 90 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 91 case IP_VERSION(5, 0, 2):/* NAVI14 */ 92 case IP_VERSION(5, 0, 5):/* NAVI12 */ 93 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 94 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 95 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 96 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 97 case IP_VERSION(6, 0, 0): 98 case IP_VERSION(6, 0, 1): 99 case IP_VERSION(6, 0, 2): 100 case IP_VERSION(6, 0, 3): 101 case IP_VERSION(6, 1, 0): 102 case IP_VERSION(6, 1, 1): 103 case IP_VERSION(6, 1, 2): 104 case IP_VERSION(7, 0, 0): 105 case IP_VERSION(7, 0, 1): 106 kfd->device_info.num_sdma_queues_per_engine = 8; 107 break; 108 default: 109 dev_warn(kfd_device, 110 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 111 sdma_version); 112 kfd->device_info.num_sdma_queues_per_engine = 8; 113 } 114 115 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 116 117 switch (sdma_version) { 118 case IP_VERSION(6, 0, 0): 119 case IP_VERSION(6, 0, 1): 120 case IP_VERSION(6, 0, 2): 121 case IP_VERSION(6, 0, 3): 122 case IP_VERSION(6, 1, 0): 123 case IP_VERSION(6, 1, 1): 124 case IP_VERSION(6, 1, 2): 125 case IP_VERSION(7, 0, 0): 126 case IP_VERSION(7, 0, 1): 127 /* Reserve 1 for paging and 1 for gfx */ 128 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 129 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 130 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 131 kfd->adev->sdma.num_instances * 132 kfd->device_info.num_reserved_sdma_queues_per_engine); 133 break; 134 default: 135 break; 136 } 137 } 138 139 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 140 { 141 uint32_t gc_version = KFD_GC_VERSION(kfd); 142 143 switch (gc_version) { 144 case IP_VERSION(9, 0, 1): /* VEGA10 */ 145 case IP_VERSION(9, 1, 0): /* RAVEN */ 146 case IP_VERSION(9, 2, 1): /* VEGA12 */ 147 case IP_VERSION(9, 2, 2): /* RAVEN */ 148 case IP_VERSION(9, 3, 0): /* RENOIR */ 149 case IP_VERSION(9, 4, 0): /* VEGA20 */ 150 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 151 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 152 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 153 break; 154 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 155 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 156 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */ 157 kfd->device_info.event_interrupt_class = 158 &event_interrupt_class_v9_4_3; 159 break; 160 case IP_VERSION(10, 3, 1): /* VANGOGH */ 161 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 162 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 163 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 164 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 165 case IP_VERSION(10, 1, 4): 166 case IP_VERSION(10, 1, 10): /* NAVI10 */ 167 case IP_VERSION(10, 1, 2): /* NAVI12 */ 168 case IP_VERSION(10, 1, 1): /* NAVI14 */ 169 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 170 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 171 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 172 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 173 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 174 break; 175 case IP_VERSION(11, 0, 0): 176 case IP_VERSION(11, 0, 1): 177 case IP_VERSION(11, 0, 2): 178 case IP_VERSION(11, 0, 3): 179 case IP_VERSION(11, 0, 4): 180 case IP_VERSION(11, 5, 0): 181 case IP_VERSION(11, 5, 1): 182 case IP_VERSION(11, 5, 2): 183 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 184 break; 185 case IP_VERSION(12, 0, 0): 186 case IP_VERSION(12, 0, 1): 187 /* GFX12_TODO: Change to v12 version. */ 188 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 189 break; 190 default: 191 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 192 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 193 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 194 } 195 } 196 197 static void kfd_device_info_init(struct kfd_dev *kfd, 198 bool vf, uint32_t gfx_target_version) 199 { 200 uint32_t gc_version = KFD_GC_VERSION(kfd); 201 uint32_t asic_type = kfd->adev->asic_type; 202 203 kfd->device_info.max_pasid_bits = 16; 204 kfd->device_info.max_no_of_hqd = 24; 205 kfd->device_info.num_of_watch_points = 4; 206 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 207 kfd->device_info.gfx_target_version = gfx_target_version; 208 209 if (KFD_IS_SOC15(kfd)) { 210 kfd->device_info.doorbell_size = 8; 211 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 212 kfd->device_info.supports_cwsr = true; 213 214 kfd_device_info_set_sdma_info(kfd); 215 216 kfd_device_info_set_event_interrupt_class(kfd); 217 218 if (gc_version < IP_VERSION(11, 0, 0)) { 219 /* Navi2x+, Navi1x+ */ 220 if (gc_version == IP_VERSION(10, 3, 6)) 221 kfd->device_info.no_atomic_fw_version = 14; 222 else if (gc_version == IP_VERSION(10, 3, 7)) 223 kfd->device_info.no_atomic_fw_version = 3; 224 else if (gc_version >= IP_VERSION(10, 3, 0)) 225 kfd->device_info.no_atomic_fw_version = 92; 226 else if (gc_version >= IP_VERSION(10, 1, 1)) 227 kfd->device_info.no_atomic_fw_version = 145; 228 229 /* Navi1x+ */ 230 if (gc_version >= IP_VERSION(10, 1, 1)) 231 kfd->device_info.needs_pci_atomics = true; 232 } else if (gc_version < IP_VERSION(12, 0, 0)) { 233 /* 234 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 235 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 236 * PCIe atomics support. 237 */ 238 kfd->device_info.needs_pci_atomics = true; 239 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 240 } else if (gc_version < IP_VERSION(13, 0, 0)) { 241 kfd->device_info.needs_pci_atomics = true; 242 kfd->device_info.no_atomic_fw_version = 2090; 243 } else { 244 kfd->device_info.needs_pci_atomics = true; 245 } 246 } else { 247 kfd->device_info.doorbell_size = 4; 248 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 249 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 250 kfd->device_info.num_sdma_queues_per_engine = 2; 251 252 if (asic_type != CHIP_KAVERI && 253 asic_type != CHIP_HAWAII && 254 asic_type != CHIP_TONGA) 255 kfd->device_info.supports_cwsr = true; 256 257 if (asic_type != CHIP_HAWAII && !vf) 258 kfd->device_info.needs_pci_atomics = true; 259 } 260 } 261 262 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 263 { 264 struct kfd_dev *kfd = NULL; 265 const struct kfd2kgd_calls *f2g = NULL; 266 uint32_t gfx_target_version = 0; 267 268 switch (adev->asic_type) { 269 #ifdef CONFIG_DRM_AMDGPU_CIK 270 case CHIP_KAVERI: 271 gfx_target_version = 70000; 272 if (!vf) 273 f2g = &gfx_v7_kfd2kgd; 274 break; 275 #endif 276 case CHIP_CARRIZO: 277 gfx_target_version = 80001; 278 if (!vf) 279 f2g = &gfx_v8_kfd2kgd; 280 break; 281 #ifdef CONFIG_DRM_AMDGPU_CIK 282 case CHIP_HAWAII: 283 gfx_target_version = 70001; 284 if (!amdgpu_exp_hw_support) 285 pr_info( 286 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 287 ); 288 else if (!vf) 289 f2g = &gfx_v7_kfd2kgd; 290 break; 291 #endif 292 case CHIP_TONGA: 293 gfx_target_version = 80002; 294 if (!vf) 295 f2g = &gfx_v8_kfd2kgd; 296 break; 297 case CHIP_FIJI: 298 case CHIP_POLARIS10: 299 gfx_target_version = 80003; 300 f2g = &gfx_v8_kfd2kgd; 301 break; 302 case CHIP_POLARIS11: 303 case CHIP_POLARIS12: 304 case CHIP_VEGAM: 305 gfx_target_version = 80003; 306 if (!vf) 307 f2g = &gfx_v8_kfd2kgd; 308 break; 309 default: 310 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 311 /* Vega 10 */ 312 case IP_VERSION(9, 0, 1): 313 gfx_target_version = 90000; 314 f2g = &gfx_v9_kfd2kgd; 315 break; 316 /* Raven */ 317 case IP_VERSION(9, 1, 0): 318 case IP_VERSION(9, 2, 2): 319 gfx_target_version = 90002; 320 if (!vf) 321 f2g = &gfx_v9_kfd2kgd; 322 break; 323 /* Vega12 */ 324 case IP_VERSION(9, 2, 1): 325 gfx_target_version = 90004; 326 if (!vf) 327 f2g = &gfx_v9_kfd2kgd; 328 break; 329 /* Renoir */ 330 case IP_VERSION(9, 3, 0): 331 gfx_target_version = 90012; 332 if (!vf) 333 f2g = &gfx_v9_kfd2kgd; 334 break; 335 /* Vega20 */ 336 case IP_VERSION(9, 4, 0): 337 gfx_target_version = 90006; 338 if (!vf) 339 f2g = &gfx_v9_kfd2kgd; 340 break; 341 /* Arcturus */ 342 case IP_VERSION(9, 4, 1): 343 gfx_target_version = 90008; 344 f2g = &arcturus_kfd2kgd; 345 break; 346 /* Aldebaran */ 347 case IP_VERSION(9, 4, 2): 348 gfx_target_version = 90010; 349 f2g = &aldebaran_kfd2kgd; 350 break; 351 case IP_VERSION(9, 4, 3): 352 gfx_target_version = adev->rev_id >= 1 ? 90402 353 : adev->flags & AMD_IS_APU ? 90400 354 : 90401; 355 f2g = &gc_9_4_3_kfd2kgd; 356 break; 357 case IP_VERSION(9, 4, 4): 358 gfx_target_version = 90402; 359 f2g = &gc_9_4_3_kfd2kgd; 360 break; 361 case IP_VERSION(9, 5, 0): 362 gfx_target_version = 90500; 363 f2g = &gc_9_4_3_kfd2kgd; 364 break; 365 /* Navi10 */ 366 case IP_VERSION(10, 1, 10): 367 gfx_target_version = 100100; 368 if (!vf) 369 f2g = &gfx_v10_kfd2kgd; 370 break; 371 /* Navi12 */ 372 case IP_VERSION(10, 1, 2): 373 gfx_target_version = 100101; 374 f2g = &gfx_v10_kfd2kgd; 375 break; 376 /* Navi14 */ 377 case IP_VERSION(10, 1, 1): 378 gfx_target_version = 100102; 379 if (!vf) 380 f2g = &gfx_v10_kfd2kgd; 381 break; 382 /* Cyan Skillfish */ 383 case IP_VERSION(10, 1, 3): 384 case IP_VERSION(10, 1, 4): 385 gfx_target_version = 100103; 386 if (!vf) 387 f2g = &gfx_v10_kfd2kgd; 388 break; 389 /* Sienna Cichlid */ 390 case IP_VERSION(10, 3, 0): 391 gfx_target_version = 100300; 392 f2g = &gfx_v10_3_kfd2kgd; 393 break; 394 /* Navy Flounder */ 395 case IP_VERSION(10, 3, 2): 396 gfx_target_version = 100301; 397 f2g = &gfx_v10_3_kfd2kgd; 398 break; 399 /* Van Gogh */ 400 case IP_VERSION(10, 3, 1): 401 gfx_target_version = 100303; 402 if (!vf) 403 f2g = &gfx_v10_3_kfd2kgd; 404 break; 405 /* Dimgrey Cavefish */ 406 case IP_VERSION(10, 3, 4): 407 gfx_target_version = 100302; 408 f2g = &gfx_v10_3_kfd2kgd; 409 break; 410 /* Beige Goby */ 411 case IP_VERSION(10, 3, 5): 412 gfx_target_version = 100304; 413 f2g = &gfx_v10_3_kfd2kgd; 414 break; 415 /* Yellow Carp */ 416 case IP_VERSION(10, 3, 3): 417 gfx_target_version = 100305; 418 if (!vf) 419 f2g = &gfx_v10_3_kfd2kgd; 420 break; 421 case IP_VERSION(10, 3, 6): 422 case IP_VERSION(10, 3, 7): 423 gfx_target_version = 100306; 424 if (!vf) 425 f2g = &gfx_v10_3_kfd2kgd; 426 break; 427 case IP_VERSION(11, 0, 0): 428 gfx_target_version = 110000; 429 f2g = &gfx_v11_kfd2kgd; 430 break; 431 case IP_VERSION(11, 0, 1): 432 case IP_VERSION(11, 0, 4): 433 gfx_target_version = 110003; 434 f2g = &gfx_v11_kfd2kgd; 435 break; 436 case IP_VERSION(11, 0, 2): 437 gfx_target_version = 110002; 438 f2g = &gfx_v11_kfd2kgd; 439 break; 440 case IP_VERSION(11, 0, 3): 441 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 442 gfx_target_version = 110001; 443 f2g = &gfx_v11_kfd2kgd; 444 break; 445 case IP_VERSION(11, 5, 0): 446 gfx_target_version = 110500; 447 f2g = &gfx_v11_kfd2kgd; 448 break; 449 case IP_VERSION(11, 5, 1): 450 gfx_target_version = 110501; 451 f2g = &gfx_v11_kfd2kgd; 452 break; 453 case IP_VERSION(11, 5, 2): 454 gfx_target_version = 110502; 455 f2g = &gfx_v11_kfd2kgd; 456 break; 457 case IP_VERSION(12, 0, 0): 458 gfx_target_version = 120000; 459 f2g = &gfx_v12_kfd2kgd; 460 break; 461 case IP_VERSION(12, 0, 1): 462 gfx_target_version = 120001; 463 f2g = &gfx_v12_kfd2kgd; 464 break; 465 default: 466 break; 467 } 468 break; 469 } 470 471 if (!f2g) { 472 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 473 dev_info(kfd_device, 474 "GC IP %06x %s not supported in kfd\n", 475 amdgpu_ip_version(adev, GC_HWIP, 0), 476 vf ? "VF" : ""); 477 else 478 dev_info(kfd_device, "%s %s not supported in kfd\n", 479 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 480 return NULL; 481 } 482 483 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 484 if (!kfd) 485 return NULL; 486 487 kfd->adev = adev; 488 kfd_device_info_init(kfd, vf, gfx_target_version); 489 kfd->init_complete = false; 490 kfd->kfd2kgd = f2g; 491 atomic_set(&kfd->compute_profile, 0); 492 493 mutex_init(&kfd->doorbell_mutex); 494 495 ida_init(&kfd->doorbell_ida); 496 497 return kfd; 498 } 499 500 static void kfd_cwsr_init(struct kfd_dev *kfd) 501 { 502 if (cwsr_enable && kfd->device_info.supports_cwsr) { 503 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 504 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 505 > KFD_CWSR_TMA_OFFSET); 506 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 507 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 508 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 509 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 510 > KFD_CWSR_TMA_OFFSET); 511 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 512 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 513 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 514 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 515 > KFD_CWSR_TMA_OFFSET); 516 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 517 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 518 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 519 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 520 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 521 > KFD_CWSR_TMA_OFFSET); 522 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 523 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 524 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) { 525 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE); 526 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex; 527 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex); 528 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 529 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 530 > KFD_CWSR_TMA_OFFSET); 531 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 532 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 533 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 534 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 535 > KFD_CWSR_TMA_OFFSET); 536 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 537 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 538 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 539 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 540 > KFD_CWSR_TMA_OFFSET); 541 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 542 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 543 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 544 /* The gfx11 cwsr trap handler must fit inside a single 545 page. */ 546 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 547 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 548 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 549 } else { 550 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 551 > KFD_CWSR_TMA_OFFSET); 552 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 553 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 554 } 555 556 kfd->cwsr_enabled = true; 557 } 558 } 559 560 static int kfd_gws_init(struct kfd_node *node) 561 { 562 int ret = 0; 563 struct kfd_dev *kfd = node->kfd; 564 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 565 566 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 567 return 0; 568 569 if (hws_gws_support || (KFD_IS_SOC15(node) && 570 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 571 && kfd->mec2_fw_version >= 0x81b3) || 572 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 573 && kfd->mec2_fw_version >= 0x1b3) || 574 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 575 && kfd->mec2_fw_version >= 0x30) || 576 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 577 && kfd->mec2_fw_version >= 0x28) || 578 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 579 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 580 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) || 581 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 582 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 583 && kfd->mec2_fw_version >= 0x6b) || 584 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 585 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 586 && mes_rev >= 68)))) 587 ret = amdgpu_amdkfd_alloc_gws(node->adev, 588 node->adev->gds.gws_size, &node->gws); 589 590 return ret; 591 } 592 593 static void kfd_smi_init(struct kfd_node *dev) 594 { 595 INIT_LIST_HEAD(&dev->smi_clients); 596 spin_lock_init(&dev->smi_lock); 597 } 598 599 static int kfd_init_node(struct kfd_node *node) 600 { 601 int err = -1; 602 603 if (kfd_interrupt_init(node)) { 604 dev_err(kfd_device, "Error initializing interrupts\n"); 605 goto kfd_interrupt_error; 606 } 607 608 node->dqm = device_queue_manager_init(node); 609 if (!node->dqm) { 610 dev_err(kfd_device, "Error initializing queue manager\n"); 611 goto device_queue_manager_error; 612 } 613 614 if (kfd_gws_init(node)) { 615 dev_err(kfd_device, "Could not allocate %d gws\n", 616 node->adev->gds.gws_size); 617 goto gws_error; 618 } 619 620 if (kfd_resume(node)) 621 goto kfd_resume_error; 622 623 if (kfd_topology_add_device(node)) { 624 dev_err(kfd_device, "Error adding device to topology\n"); 625 goto kfd_topology_add_device_error; 626 } 627 628 kfd_smi_init(node); 629 630 return 0; 631 632 kfd_topology_add_device_error: 633 kfd_resume_error: 634 gws_error: 635 device_queue_manager_uninit(node->dqm); 636 device_queue_manager_error: 637 kfd_interrupt_exit(node); 638 kfd_interrupt_error: 639 if (node->gws) 640 amdgpu_amdkfd_free_gws(node->adev, node->gws); 641 642 /* Cleanup the node memory here */ 643 kfree(node); 644 return err; 645 } 646 647 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 648 { 649 struct kfd_node *knode; 650 unsigned int i; 651 652 for (i = 0; i < num_nodes; i++) { 653 knode = kfd->nodes[i]; 654 device_queue_manager_uninit(knode->dqm); 655 kfd_interrupt_exit(knode); 656 kfd_topology_remove_device(knode); 657 if (knode->gws) 658 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 659 kfree(knode); 660 kfd->nodes[i] = NULL; 661 } 662 } 663 664 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 665 unsigned int kfd_node_idx) 666 { 667 struct amdgpu_device *adev = node->adev; 668 uint32_t xcc_mask = node->xcc_mask; 669 uint32_t xcc, mapped_xcc; 670 /* 671 * Interrupt bitmap is setup for processing interrupts from 672 * different XCDs and AIDs. 673 * Interrupt bitmap is defined as follows: 674 * 1. Bits 0-15 - correspond to the NodeId field. 675 * Each bit corresponds to NodeId number. For example, if 676 * a KFD node has interrupt bitmap set to 0x7, then this 677 * KFD node will process interrupts with NodeId = 0, 1 and 2 678 * in the IH cookie. 679 * 2. Bits 16-31 - unused. 680 * 681 * Please note that the kfd_node_idx argument passed to this 682 * function is not related to NodeId field received in the 683 * IH cookie. 684 * 685 * In CPX mode, a KFD node will process an interrupt if: 686 * - the Node Id matches the corresponding bit set in 687 * Bits 0-15. 688 * - AND VMID reported in the interrupt lies within the 689 * VMID range of the node. 690 */ 691 for_each_inst(xcc, xcc_mask) { 692 mapped_xcc = GET_INST(GC, xcc); 693 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 694 } 695 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 696 node->interrupt_bitmap); 697 } 698 699 bool kgd2kfd_device_init(struct kfd_dev *kfd, 700 const struct kgd2kfd_shared_resources *gpu_resources) 701 { 702 unsigned int size, map_process_packet_size, i; 703 struct kfd_node *node; 704 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 705 unsigned int max_proc_per_quantum; 706 int partition_mode; 707 int xcp_idx; 708 709 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 710 KGD_ENGINE_MEC1); 711 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 712 KGD_ENGINE_MEC2); 713 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 714 KGD_ENGINE_SDMA1); 715 kfd->shared_resources = *gpu_resources; 716 717 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 718 719 if (kfd->num_nodes == 0) { 720 dev_err(kfd_device, 721 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 722 kfd->adev->gfx.num_xcc_per_xcp); 723 goto out; 724 } 725 726 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 727 * 32 and 64-bit requests are possible and must be 728 * supported. 729 */ 730 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 731 if (!kfd->pci_atomic_requested && 732 kfd->device_info.needs_pci_atomics && 733 (!kfd->device_info.no_atomic_fw_version || 734 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 735 dev_info(kfd_device, 736 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 737 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 738 kfd->mec_fw_version, 739 kfd->device_info.no_atomic_fw_version); 740 return false; 741 } 742 743 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 744 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 745 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 746 747 /* For multi-partition capable GPUs, we need special handling for VMIDs 748 * depending on partition mode. 749 * In CPX mode, the VMID range needs to be shared between XCDs. 750 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 751 * divide them equally, we change starting VMID to 4 and not use 752 * VMID 3. 753 * If the VMID range changes for multi-partition capable GPUs, then 754 * this code MUST be revisited. 755 */ 756 if (kfd->adev->xcp_mgr) { 757 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 758 AMDGPU_XCP_FL_LOCKED); 759 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 760 kfd->num_nodes != 1) { 761 vmid_num_kfd /= 2; 762 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 763 } 764 } 765 766 /* Verify module parameters regarding mapped process number*/ 767 if (hws_max_conc_proc >= 0) 768 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 769 else 770 max_proc_per_quantum = vmid_num_kfd; 771 772 /* calculate max size of mqds needed for queues */ 773 size = max_num_of_queues_per_device * 774 kfd->device_info.mqd_size_aligned; 775 776 /* 777 * calculate max size of runlist packet. 778 * There can be only 2 packets at once 779 */ 780 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 781 sizeof(struct pm4_mes_map_process_aldebaran) : 782 sizeof(struct pm4_mes_map_process); 783 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 784 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 785 + sizeof(struct pm4_mes_runlist)) * 2; 786 787 /* Add size of HIQ & DIQ */ 788 size += KFD_KERNEL_QUEUE_SIZE * 2; 789 790 /* add another 512KB for all other allocations on gart (HPD, fences) */ 791 size += 512 * 1024; 792 793 if (amdgpu_amdkfd_alloc_gtt_mem( 794 kfd->adev, size, &kfd->gtt_mem, 795 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 796 false)) { 797 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 798 goto alloc_gtt_mem_failure; 799 } 800 801 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 802 803 /* Initialize GTT sa with 512 byte chunk size */ 804 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 805 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 806 goto kfd_gtt_sa_init_error; 807 } 808 809 if (kfd_doorbell_init(kfd)) { 810 dev_err(kfd_device, 811 "Error initializing doorbell aperture\n"); 812 goto kfd_doorbell_error; 813 } 814 815 if (amdgpu_use_xgmi_p2p) 816 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 817 818 /* 819 * For multi-partition capable GPUs, the KFD abstracts all partitions 820 * within a socket as xGMI connected in the topology so assign a unique 821 * hive id per device based on the pci device location if device is in 822 * PCIe mode. 823 */ 824 if (!kfd->hive_id && kfd->num_nodes > 1) 825 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 826 827 kfd->noretry = kfd->adev->gmc.noretry; 828 829 kfd_cwsr_init(kfd); 830 831 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 832 kfd->num_nodes); 833 834 /* Allocate the KFD nodes */ 835 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 836 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 837 if (!node) 838 goto node_alloc_error; 839 840 node->node_id = i; 841 node->adev = kfd->adev; 842 node->kfd = kfd; 843 node->kfd2kgd = kfd->kfd2kgd; 844 node->vm_info.vmid_num_kfd = vmid_num_kfd; 845 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 846 /* TODO : Check if error handling is needed */ 847 if (node->xcp) { 848 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 849 &node->xcc_mask); 850 ++xcp_idx; 851 } else { 852 node->xcc_mask = 853 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 854 } 855 856 if (node->xcp) { 857 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 858 node->node_id, node->xcp->mem_id, 859 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 860 } 861 862 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 863 kfd->num_nodes != 1) { 864 /* For multi-partition capable GPUs and CPX mode, first 865 * XCD gets VMID range 4-9 and second XCD gets VMID 866 * range 10-15. 867 */ 868 869 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 870 first_vmid_kfd : 871 first_vmid_kfd+vmid_num_kfd; 872 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 873 last_vmid_kfd-vmid_num_kfd : 874 last_vmid_kfd; 875 node->compute_vmid_bitmap = 876 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 877 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 878 } else { 879 node->vm_info.first_vmid_kfd = first_vmid_kfd; 880 node->vm_info.last_vmid_kfd = last_vmid_kfd; 881 node->compute_vmid_bitmap = 882 gpu_resources->compute_vmid_bitmap; 883 } 884 node->max_proc_per_quantum = max_proc_per_quantum; 885 atomic_set(&node->sram_ecc_flag, 0); 886 887 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 888 &node->local_mem_info, node->xcp); 889 890 if (kfd->adev->xcp_mgr) 891 kfd_setup_interrupt_bitmap(node, i); 892 893 /* Initialize the KFD node */ 894 if (kfd_init_node(node)) { 895 dev_err(kfd_device, "Error initializing KFD node\n"); 896 goto node_init_error; 897 } 898 899 spin_lock_init(&node->watch_points_lock); 900 901 kfd->nodes[i] = node; 902 } 903 904 svm_range_set_max_pages(kfd->adev); 905 906 kfd->init_complete = true; 907 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 908 kfd->adev->pdev->device); 909 910 pr_debug("Starting kfd with the following scheduling policy %d\n", 911 node->dqm->sched_policy); 912 913 goto out; 914 915 node_init_error: 916 node_alloc_error: 917 kfd_cleanup_nodes(kfd, i); 918 kfd_doorbell_fini(kfd); 919 kfd_doorbell_error: 920 kfd_gtt_sa_fini(kfd); 921 kfd_gtt_sa_init_error: 922 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 923 alloc_gtt_mem_failure: 924 dev_err(kfd_device, 925 "device %x:%x NOT added due to errors\n", 926 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 927 out: 928 return kfd->init_complete; 929 } 930 931 void kgd2kfd_device_exit(struct kfd_dev *kfd) 932 { 933 if (kfd->init_complete) { 934 /* Cleanup KFD nodes */ 935 kfd_cleanup_nodes(kfd, kfd->num_nodes); 936 /* Cleanup common/shared resources */ 937 kfd_doorbell_fini(kfd); 938 ida_destroy(&kfd->doorbell_ida); 939 kfd_gtt_sa_fini(kfd); 940 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 941 } 942 943 kfree(kfd); 944 } 945 946 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 947 struct amdgpu_reset_context *reset_context) 948 { 949 struct kfd_node *node; 950 int i; 951 952 if (!kfd->init_complete) 953 return 0; 954 955 for (i = 0; i < kfd->num_nodes; i++) { 956 node = kfd->nodes[i]; 957 kfd_smi_event_update_gpu_reset(node, false, reset_context); 958 } 959 960 kgd2kfd_suspend(kfd, false); 961 962 for (i = 0; i < kfd->num_nodes; i++) 963 kfd_signal_reset_event(kfd->nodes[i]); 964 965 return 0; 966 } 967 968 /* 969 * Fix me. KFD won't be able to resume existing process for now. 970 * We will keep all existing process in a evicted state and 971 * wait the process to be terminated. 972 */ 973 974 int kgd2kfd_post_reset(struct kfd_dev *kfd) 975 { 976 int ret; 977 struct kfd_node *node; 978 int i; 979 980 if (!kfd->init_complete) 981 return 0; 982 983 for (i = 0; i < kfd->num_nodes; i++) { 984 ret = kfd_resume(kfd->nodes[i]); 985 if (ret) 986 return ret; 987 } 988 989 mutex_lock(&kfd_processes_mutex); 990 --kfd_locked; 991 mutex_unlock(&kfd_processes_mutex); 992 993 for (i = 0; i < kfd->num_nodes; i++) { 994 node = kfd->nodes[i]; 995 atomic_set(&node->sram_ecc_flag, 0); 996 kfd_smi_event_update_gpu_reset(node, true, NULL); 997 } 998 999 return 0; 1000 } 1001 1002 bool kfd_is_locked(void) 1003 { 1004 lockdep_assert_held(&kfd_processes_mutex); 1005 return (kfd_locked > 0); 1006 } 1007 1008 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 1009 { 1010 struct kfd_node *node; 1011 int i; 1012 1013 if (!kfd->init_complete) 1014 return; 1015 1016 /* for runtime suspend, skip locking kfd */ 1017 if (!run_pm) { 1018 mutex_lock(&kfd_processes_mutex); 1019 /* For first KFD device suspend all the KFD processes */ 1020 if (++kfd_locked == 1) 1021 kfd_suspend_all_processes(); 1022 mutex_unlock(&kfd_processes_mutex); 1023 } 1024 1025 for (i = 0; i < kfd->num_nodes; i++) { 1026 node = kfd->nodes[i]; 1027 node->dqm->ops.stop(node->dqm); 1028 } 1029 } 1030 1031 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1032 { 1033 int ret, i; 1034 1035 if (!kfd->init_complete) 1036 return 0; 1037 1038 for (i = 0; i < kfd->num_nodes; i++) { 1039 ret = kfd_resume(kfd->nodes[i]); 1040 if (ret) 1041 return ret; 1042 } 1043 1044 /* for runtime resume, skip unlocking kfd */ 1045 if (!run_pm) { 1046 mutex_lock(&kfd_processes_mutex); 1047 if (--kfd_locked == 0) 1048 ret = kfd_resume_all_processes(); 1049 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1050 mutex_unlock(&kfd_processes_mutex); 1051 } 1052 1053 return ret; 1054 } 1055 1056 static int kfd_resume(struct kfd_node *node) 1057 { 1058 int err = 0; 1059 1060 err = node->dqm->ops.start(node->dqm); 1061 if (err) 1062 dev_err(kfd_device, 1063 "Error starting queue manager for device %x:%x\n", 1064 node->adev->pdev->vendor, node->adev->pdev->device); 1065 1066 return err; 1067 } 1068 1069 static inline void kfd_queue_work(struct workqueue_struct *wq, 1070 struct work_struct *work) 1071 { 1072 int cpu, new_cpu; 1073 1074 cpu = new_cpu = smp_processor_id(); 1075 do { 1076 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1077 if (cpu_to_node(new_cpu) == numa_node_id()) 1078 break; 1079 } while (cpu != new_cpu); 1080 1081 queue_work_on(new_cpu, wq, work); 1082 } 1083 1084 /* This is called directly from KGD at ISR. */ 1085 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1086 { 1087 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1088 bool is_patched = false; 1089 unsigned long flags; 1090 struct kfd_node *node; 1091 1092 if (!kfd->init_complete) 1093 return; 1094 1095 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1096 dev_err_once(kfd_device, "Ring entry too small\n"); 1097 return; 1098 } 1099 1100 for (i = 0; i < kfd->num_nodes; i++) { 1101 node = kfd->nodes[i]; 1102 spin_lock_irqsave(&node->interrupt_lock, flags); 1103 1104 if (node->interrupts_active 1105 && interrupt_is_wanted(node, ih_ring_entry, 1106 patched_ihre, &is_patched) 1107 && enqueue_ih_ring_entry(node, 1108 is_patched ? patched_ihre : ih_ring_entry)) { 1109 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1110 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1111 return; 1112 } 1113 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1114 } 1115 1116 } 1117 1118 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1119 { 1120 struct kfd_process *p; 1121 int r; 1122 1123 /* Because we are called from arbitrary context (workqueue) as opposed 1124 * to process context, kfd_process could attempt to exit while we are 1125 * running so the lookup function increments the process ref count. 1126 */ 1127 p = kfd_lookup_process_by_mm(mm); 1128 if (!p) 1129 return -ESRCH; 1130 1131 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1132 r = kfd_process_evict_queues(p, trigger); 1133 1134 kfd_unref_process(p); 1135 return r; 1136 } 1137 1138 int kgd2kfd_resume_mm(struct mm_struct *mm) 1139 { 1140 struct kfd_process *p; 1141 int r; 1142 1143 /* Because we are called from arbitrary context (workqueue) as opposed 1144 * to process context, kfd_process could attempt to exit while we are 1145 * running so the lookup function increments the process ref count. 1146 */ 1147 p = kfd_lookup_process_by_mm(mm); 1148 if (!p) 1149 return -ESRCH; 1150 1151 r = kfd_process_restore_queues(p); 1152 1153 kfd_unref_process(p); 1154 return r; 1155 } 1156 1157 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1158 * prepare for safe eviction of KFD BOs that belong to the specified 1159 * process. 1160 * 1161 * @mm: mm_struct that identifies the specified KFD process 1162 * @fence: eviction fence attached to KFD process BOs 1163 * 1164 */ 1165 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1166 struct dma_fence *fence) 1167 { 1168 struct kfd_process *p; 1169 unsigned long active_time; 1170 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1171 1172 if (!fence) 1173 return -EINVAL; 1174 1175 if (dma_fence_is_signaled(fence)) 1176 return 0; 1177 1178 p = kfd_lookup_process_by_mm(mm); 1179 if (!p) 1180 return -ENODEV; 1181 1182 if (fence->seqno == p->last_eviction_seqno) 1183 goto out; 1184 1185 p->last_eviction_seqno = fence->seqno; 1186 1187 /* Avoid KFD process starvation. Wait for at least 1188 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1189 */ 1190 active_time = get_jiffies_64() - p->last_restore_timestamp; 1191 if (delay_jiffies > active_time) 1192 delay_jiffies -= active_time; 1193 else 1194 delay_jiffies = 0; 1195 1196 /* During process initialization eviction_work.dwork is initialized 1197 * to kfd_evict_bo_worker 1198 */ 1199 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1200 p->lead_thread->pid, delay_jiffies); 1201 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1202 out: 1203 kfd_unref_process(p); 1204 return 0; 1205 } 1206 1207 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1208 unsigned int chunk_size) 1209 { 1210 if (WARN_ON(buf_size < chunk_size)) 1211 return -EINVAL; 1212 if (WARN_ON(buf_size == 0)) 1213 return -EINVAL; 1214 if (WARN_ON(chunk_size == 0)) 1215 return -EINVAL; 1216 1217 kfd->gtt_sa_chunk_size = chunk_size; 1218 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1219 1220 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1221 GFP_KERNEL); 1222 if (!kfd->gtt_sa_bitmap) 1223 return -ENOMEM; 1224 1225 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1226 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1227 1228 mutex_init(&kfd->gtt_sa_lock); 1229 1230 return 0; 1231 } 1232 1233 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1234 { 1235 mutex_destroy(&kfd->gtt_sa_lock); 1236 bitmap_free(kfd->gtt_sa_bitmap); 1237 } 1238 1239 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1240 unsigned int bit_num, 1241 unsigned int chunk_size) 1242 { 1243 return start_addr + bit_num * chunk_size; 1244 } 1245 1246 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1247 unsigned int bit_num, 1248 unsigned int chunk_size) 1249 { 1250 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1251 } 1252 1253 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1254 struct kfd_mem_obj **mem_obj) 1255 { 1256 unsigned int found, start_search, cur_size; 1257 struct kfd_dev *kfd = node->kfd; 1258 1259 if (size == 0) 1260 return -EINVAL; 1261 1262 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1263 return -ENOMEM; 1264 1265 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1266 if (!(*mem_obj)) 1267 return -ENOMEM; 1268 1269 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1270 1271 start_search = 0; 1272 1273 mutex_lock(&kfd->gtt_sa_lock); 1274 1275 kfd_gtt_restart_search: 1276 /* Find the first chunk that is free */ 1277 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1278 kfd->gtt_sa_num_of_chunks, 1279 start_search); 1280 1281 pr_debug("Found = %d\n", found); 1282 1283 /* If there wasn't any free chunk, bail out */ 1284 if (found == kfd->gtt_sa_num_of_chunks) 1285 goto kfd_gtt_no_free_chunk; 1286 1287 /* Update fields of mem_obj */ 1288 (*mem_obj)->range_start = found; 1289 (*mem_obj)->range_end = found; 1290 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1291 kfd->gtt_start_gpu_addr, 1292 found, 1293 kfd->gtt_sa_chunk_size); 1294 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1295 kfd->gtt_start_cpu_ptr, 1296 found, 1297 kfd->gtt_sa_chunk_size); 1298 1299 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1300 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1301 1302 /* If we need only one chunk, mark it as allocated and get out */ 1303 if (size <= kfd->gtt_sa_chunk_size) { 1304 pr_debug("Single bit\n"); 1305 __set_bit(found, kfd->gtt_sa_bitmap); 1306 goto kfd_gtt_out; 1307 } 1308 1309 /* Otherwise, try to see if we have enough contiguous chunks */ 1310 cur_size = size - kfd->gtt_sa_chunk_size; 1311 do { 1312 (*mem_obj)->range_end = 1313 find_next_zero_bit(kfd->gtt_sa_bitmap, 1314 kfd->gtt_sa_num_of_chunks, ++found); 1315 /* 1316 * If next free chunk is not contiguous than we need to 1317 * restart our search from the last free chunk we found (which 1318 * wasn't contiguous to the previous ones 1319 */ 1320 if ((*mem_obj)->range_end != found) { 1321 start_search = found; 1322 goto kfd_gtt_restart_search; 1323 } 1324 1325 /* 1326 * If we reached end of buffer, bail out with error 1327 */ 1328 if (found == kfd->gtt_sa_num_of_chunks) 1329 goto kfd_gtt_no_free_chunk; 1330 1331 /* Check if we don't need another chunk */ 1332 if (cur_size <= kfd->gtt_sa_chunk_size) 1333 cur_size = 0; 1334 else 1335 cur_size -= kfd->gtt_sa_chunk_size; 1336 1337 } while (cur_size > 0); 1338 1339 pr_debug("range_start = %d, range_end = %d\n", 1340 (*mem_obj)->range_start, (*mem_obj)->range_end); 1341 1342 /* Mark the chunks as allocated */ 1343 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1344 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1345 1346 kfd_gtt_out: 1347 mutex_unlock(&kfd->gtt_sa_lock); 1348 return 0; 1349 1350 kfd_gtt_no_free_chunk: 1351 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1352 mutex_unlock(&kfd->gtt_sa_lock); 1353 kfree(*mem_obj); 1354 return -ENOMEM; 1355 } 1356 1357 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1358 { 1359 struct kfd_dev *kfd = node->kfd; 1360 1361 /* Act like kfree when trying to free a NULL object */ 1362 if (!mem_obj) 1363 return 0; 1364 1365 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1366 mem_obj, mem_obj->range_start, mem_obj->range_end); 1367 1368 mutex_lock(&kfd->gtt_sa_lock); 1369 1370 /* Mark the chunks as free */ 1371 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1372 mem_obj->range_end - mem_obj->range_start + 1); 1373 1374 mutex_unlock(&kfd->gtt_sa_lock); 1375 1376 kfree(mem_obj); 1377 return 0; 1378 } 1379 1380 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1381 { 1382 /* 1383 * TODO: Currently update SRAM ECC flag for first node. 1384 * This needs to be updated later when we can 1385 * identify SRAM ECC error on other nodes also. 1386 */ 1387 if (kfd) 1388 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1389 } 1390 1391 void kfd_inc_compute_active(struct kfd_node *node) 1392 { 1393 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1394 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1395 } 1396 1397 void kfd_dec_compute_active(struct kfd_node *node) 1398 { 1399 int count = atomic_dec_return(&node->kfd->compute_profile); 1400 1401 if (count == 0) 1402 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1403 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1404 } 1405 1406 static bool kfd_compute_active(struct kfd_node *node) 1407 { 1408 if (atomic_read(&node->kfd->compute_profile)) 1409 return true; 1410 return false; 1411 } 1412 1413 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1414 { 1415 /* 1416 * TODO: For now, raise the throttling event only on first node. 1417 * This will need to change after we are able to determine 1418 * which node raised the throttling event. 1419 */ 1420 if (kfd && kfd->init_complete) 1421 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1422 throttle_bitmask); 1423 } 1424 1425 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1426 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1427 * When the device has more than two engines, we reserve two for PCIe to enable 1428 * full-duplex and the rest are used as XGMI. 1429 */ 1430 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1431 { 1432 /* If XGMI is not supported, all SDMA engines are PCIe */ 1433 if (!node->adev->gmc.xgmi.supported) 1434 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1435 1436 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1437 } 1438 1439 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1440 { 1441 /* After reserved for PCIe, the rest of engines are XGMI */ 1442 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1443 kfd_get_num_sdma_engines(node); 1444 } 1445 1446 int kgd2kfd_check_and_lock_kfd(void) 1447 { 1448 mutex_lock(&kfd_processes_mutex); 1449 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1450 mutex_unlock(&kfd_processes_mutex); 1451 return -EBUSY; 1452 } 1453 1454 ++kfd_locked; 1455 mutex_unlock(&kfd_processes_mutex); 1456 1457 return 0; 1458 } 1459 1460 void kgd2kfd_unlock_kfd(void) 1461 { 1462 mutex_lock(&kfd_processes_mutex); 1463 --kfd_locked; 1464 mutex_unlock(&kfd_processes_mutex); 1465 } 1466 1467 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1468 { 1469 struct kfd_node *node; 1470 int ret; 1471 1472 if (!kfd->init_complete) 1473 return 0; 1474 1475 if (node_id >= kfd->num_nodes) { 1476 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1477 node_id, kfd->num_nodes - 1); 1478 return -EINVAL; 1479 } 1480 node = kfd->nodes[node_id]; 1481 1482 ret = node->dqm->ops.unhalt(node->dqm); 1483 if (ret) 1484 dev_err(kfd_device, "Error in starting scheduler\n"); 1485 1486 return ret; 1487 } 1488 1489 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1490 { 1491 struct kfd_node *node; 1492 1493 if (!kfd->init_complete) 1494 return 0; 1495 1496 if (node_id >= kfd->num_nodes) { 1497 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1498 node_id, kfd->num_nodes - 1); 1499 return -EINVAL; 1500 } 1501 1502 node = kfd->nodes[node_id]; 1503 return node->dqm->ops.halt(node->dqm); 1504 } 1505 1506 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1507 { 1508 struct kfd_node *node; 1509 1510 if (!kfd->init_complete) 1511 return false; 1512 1513 if (node_id >= kfd->num_nodes) { 1514 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1515 node_id, kfd->num_nodes - 1); 1516 return false; 1517 } 1518 1519 node = kfd->nodes[node_id]; 1520 1521 return kfd_compute_active(node); 1522 } 1523 1524 #if defined(CONFIG_DEBUG_FS) 1525 1526 /* This function will send a package to HIQ to hang the HWS 1527 * which will trigger a GPU reset and bring the HWS back to normal state 1528 */ 1529 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1530 { 1531 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1532 pr_err("HWS is not enabled"); 1533 return -EINVAL; 1534 } 1535 1536 return dqm_debugfs_hang_hws(dev->dqm); 1537 } 1538 1539 #endif 1540