1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(4, 4, 5): 88 case IP_VERSION(4, 4, 4): 89 case IP_VERSION(5, 0, 0):/* NAVI10 */ 90 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 91 case IP_VERSION(5, 0, 2):/* NAVI14 */ 92 case IP_VERSION(5, 0, 5):/* NAVI12 */ 93 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 94 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 95 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 96 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 97 case IP_VERSION(6, 0, 0): 98 case IP_VERSION(6, 0, 1): 99 case IP_VERSION(6, 0, 2): 100 case IP_VERSION(6, 0, 3): 101 case IP_VERSION(6, 1, 0): 102 case IP_VERSION(6, 1, 1): 103 case IP_VERSION(6, 1, 2): 104 case IP_VERSION(6, 1, 3): 105 case IP_VERSION(7, 0, 0): 106 case IP_VERSION(7, 0, 1): 107 kfd->device_info.num_sdma_queues_per_engine = 8; 108 break; 109 default: 110 dev_warn(kfd_device, 111 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 112 sdma_version); 113 kfd->device_info.num_sdma_queues_per_engine = 8; 114 } 115 116 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 117 118 switch (sdma_version) { 119 case IP_VERSION(6, 0, 0): 120 case IP_VERSION(6, 0, 1): 121 case IP_VERSION(6, 0, 2): 122 case IP_VERSION(6, 0, 3): 123 case IP_VERSION(6, 1, 0): 124 case IP_VERSION(6, 1, 1): 125 case IP_VERSION(6, 1, 2): 126 case IP_VERSION(6, 1, 3): 127 case IP_VERSION(7, 0, 0): 128 case IP_VERSION(7, 0, 1): 129 /* Reserve 1 for paging and 1 for gfx */ 130 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 131 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 132 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 133 kfd->adev->sdma.num_instances * 134 kfd->device_info.num_reserved_sdma_queues_per_engine); 135 break; 136 default: 137 break; 138 } 139 } 140 141 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 142 { 143 uint32_t gc_version = KFD_GC_VERSION(kfd); 144 145 switch (gc_version) { 146 case IP_VERSION(9, 0, 1): /* VEGA10 */ 147 case IP_VERSION(9, 1, 0): /* RAVEN */ 148 case IP_VERSION(9, 2, 1): /* VEGA12 */ 149 case IP_VERSION(9, 2, 2): /* RAVEN */ 150 case IP_VERSION(9, 3, 0): /* RENOIR */ 151 case IP_VERSION(9, 4, 0): /* VEGA20 */ 152 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 153 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 154 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 155 break; 156 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 157 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 158 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */ 159 kfd->device_info.event_interrupt_class = 160 &event_interrupt_class_v9_4_3; 161 break; 162 case IP_VERSION(10, 3, 1): /* VANGOGH */ 163 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 164 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 165 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 166 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 167 case IP_VERSION(10, 1, 4): 168 case IP_VERSION(10, 1, 10): /* NAVI10 */ 169 case IP_VERSION(10, 1, 2): /* NAVI12 */ 170 case IP_VERSION(10, 1, 1): /* NAVI14 */ 171 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 172 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 173 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 174 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 175 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 176 break; 177 case IP_VERSION(11, 0, 0): 178 case IP_VERSION(11, 0, 1): 179 case IP_VERSION(11, 0, 2): 180 case IP_VERSION(11, 0, 3): 181 case IP_VERSION(11, 0, 4): 182 case IP_VERSION(11, 5, 0): 183 case IP_VERSION(11, 5, 1): 184 case IP_VERSION(11, 5, 2): 185 case IP_VERSION(11, 5, 3): 186 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 187 break; 188 case IP_VERSION(12, 0, 0): 189 case IP_VERSION(12, 0, 1): 190 /* GFX12_TODO: Change to v12 version. */ 191 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 192 break; 193 default: 194 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 195 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 196 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 197 } 198 } 199 200 static void kfd_device_info_init(struct kfd_dev *kfd, 201 bool vf, uint32_t gfx_target_version) 202 { 203 uint32_t gc_version = KFD_GC_VERSION(kfd); 204 uint32_t asic_type = kfd->adev->asic_type; 205 206 kfd->device_info.max_pasid_bits = 16; 207 kfd->device_info.max_no_of_hqd = 24; 208 kfd->device_info.num_of_watch_points = 4; 209 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 210 kfd->device_info.gfx_target_version = gfx_target_version; 211 212 if (KFD_IS_SOC15(kfd)) { 213 kfd->device_info.doorbell_size = 8; 214 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 215 kfd->device_info.supports_cwsr = true; 216 217 kfd_device_info_set_sdma_info(kfd); 218 219 kfd_device_info_set_event_interrupt_class(kfd); 220 221 if (gc_version < IP_VERSION(11, 0, 0)) { 222 /* Navi2x+, Navi1x+ */ 223 if (gc_version == IP_VERSION(10, 3, 6)) 224 kfd->device_info.no_atomic_fw_version = 14; 225 else if (gc_version == IP_VERSION(10, 3, 7)) 226 kfd->device_info.no_atomic_fw_version = 3; 227 else if (gc_version >= IP_VERSION(10, 3, 0)) 228 kfd->device_info.no_atomic_fw_version = 92; 229 else if (gc_version >= IP_VERSION(10, 1, 1)) 230 kfd->device_info.no_atomic_fw_version = 145; 231 232 /* Navi1x+ */ 233 if (gc_version >= IP_VERSION(10, 1, 1)) 234 kfd->device_info.needs_pci_atomics = true; 235 } else if (gc_version < IP_VERSION(12, 0, 0)) { 236 /* 237 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 238 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 239 * PCIe atomics support. 240 */ 241 kfd->device_info.needs_pci_atomics = true; 242 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 243 } else if (gc_version < IP_VERSION(13, 0, 0)) { 244 kfd->device_info.needs_pci_atomics = true; 245 kfd->device_info.no_atomic_fw_version = 2090; 246 } else { 247 kfd->device_info.needs_pci_atomics = true; 248 } 249 } else { 250 kfd->device_info.doorbell_size = 4; 251 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 252 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 253 kfd->device_info.num_sdma_queues_per_engine = 2; 254 255 if (asic_type != CHIP_KAVERI && 256 asic_type != CHIP_HAWAII && 257 asic_type != CHIP_TONGA) 258 kfd->device_info.supports_cwsr = true; 259 260 if (asic_type != CHIP_HAWAII && !vf) 261 kfd->device_info.needs_pci_atomics = true; 262 } 263 } 264 265 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 266 { 267 struct kfd_dev *kfd = NULL; 268 const struct kfd2kgd_calls *f2g = NULL; 269 uint32_t gfx_target_version = 0; 270 271 switch (adev->asic_type) { 272 #ifdef CONFIG_DRM_AMDGPU_CIK 273 case CHIP_KAVERI: 274 gfx_target_version = 70000; 275 if (!vf) 276 f2g = &gfx_v7_kfd2kgd; 277 break; 278 #endif 279 case CHIP_CARRIZO: 280 gfx_target_version = 80001; 281 if (!vf) 282 f2g = &gfx_v8_kfd2kgd; 283 break; 284 #ifdef CONFIG_DRM_AMDGPU_CIK 285 case CHIP_HAWAII: 286 gfx_target_version = 70001; 287 if (!amdgpu_exp_hw_support) 288 pr_info( 289 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 290 ); 291 else if (!vf) 292 f2g = &gfx_v7_kfd2kgd; 293 break; 294 #endif 295 case CHIP_TONGA: 296 gfx_target_version = 80002; 297 if (!vf) 298 f2g = &gfx_v8_kfd2kgd; 299 break; 300 case CHIP_FIJI: 301 case CHIP_POLARIS10: 302 gfx_target_version = 80003; 303 f2g = &gfx_v8_kfd2kgd; 304 break; 305 case CHIP_POLARIS11: 306 case CHIP_POLARIS12: 307 case CHIP_VEGAM: 308 gfx_target_version = 80003; 309 if (!vf) 310 f2g = &gfx_v8_kfd2kgd; 311 break; 312 default: 313 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 314 /* Vega 10 */ 315 case IP_VERSION(9, 0, 1): 316 gfx_target_version = 90000; 317 f2g = &gfx_v9_kfd2kgd; 318 break; 319 /* Raven */ 320 case IP_VERSION(9, 1, 0): 321 case IP_VERSION(9, 2, 2): 322 gfx_target_version = 90002; 323 if (!vf) 324 f2g = &gfx_v9_kfd2kgd; 325 break; 326 /* Vega12 */ 327 case IP_VERSION(9, 2, 1): 328 gfx_target_version = 90004; 329 if (!vf) 330 f2g = &gfx_v9_kfd2kgd; 331 break; 332 /* Renoir */ 333 case IP_VERSION(9, 3, 0): 334 gfx_target_version = 90012; 335 if (!vf) 336 f2g = &gfx_v9_kfd2kgd; 337 break; 338 /* Vega20 */ 339 case IP_VERSION(9, 4, 0): 340 gfx_target_version = 90006; 341 if (!vf) 342 f2g = &gfx_v9_kfd2kgd; 343 break; 344 /* Arcturus */ 345 case IP_VERSION(9, 4, 1): 346 gfx_target_version = 90008; 347 f2g = &arcturus_kfd2kgd; 348 break; 349 /* Aldebaran */ 350 case IP_VERSION(9, 4, 2): 351 gfx_target_version = 90010; 352 f2g = &aldebaran_kfd2kgd; 353 break; 354 case IP_VERSION(9, 4, 3): 355 case IP_VERSION(9, 4, 4): 356 gfx_target_version = 90402; 357 f2g = &gc_9_4_3_kfd2kgd; 358 break; 359 case IP_VERSION(9, 5, 0): 360 gfx_target_version = 90500; 361 f2g = &gc_9_4_3_kfd2kgd; 362 break; 363 /* Navi10 */ 364 case IP_VERSION(10, 1, 10): 365 gfx_target_version = 100100; 366 if (!vf) 367 f2g = &gfx_v10_kfd2kgd; 368 break; 369 /* Navi12 */ 370 case IP_VERSION(10, 1, 2): 371 gfx_target_version = 100101; 372 f2g = &gfx_v10_kfd2kgd; 373 break; 374 /* Navi14 */ 375 case IP_VERSION(10, 1, 1): 376 gfx_target_version = 100102; 377 if (!vf) 378 f2g = &gfx_v10_kfd2kgd; 379 break; 380 /* Cyan Skillfish */ 381 case IP_VERSION(10, 1, 3): 382 case IP_VERSION(10, 1, 4): 383 gfx_target_version = 100103; 384 if (!vf) 385 f2g = &gfx_v10_kfd2kgd; 386 break; 387 /* Sienna Cichlid */ 388 case IP_VERSION(10, 3, 0): 389 gfx_target_version = 100300; 390 f2g = &gfx_v10_3_kfd2kgd; 391 break; 392 /* Navy Flounder */ 393 case IP_VERSION(10, 3, 2): 394 gfx_target_version = 100301; 395 f2g = &gfx_v10_3_kfd2kgd; 396 break; 397 /* Van Gogh */ 398 case IP_VERSION(10, 3, 1): 399 gfx_target_version = 100303; 400 if (!vf) 401 f2g = &gfx_v10_3_kfd2kgd; 402 break; 403 /* Dimgrey Cavefish */ 404 case IP_VERSION(10, 3, 4): 405 gfx_target_version = 100302; 406 f2g = &gfx_v10_3_kfd2kgd; 407 break; 408 /* Beige Goby */ 409 case IP_VERSION(10, 3, 5): 410 gfx_target_version = 100304; 411 f2g = &gfx_v10_3_kfd2kgd; 412 break; 413 /* Yellow Carp */ 414 case IP_VERSION(10, 3, 3): 415 gfx_target_version = 100305; 416 if (!vf) 417 f2g = &gfx_v10_3_kfd2kgd; 418 break; 419 case IP_VERSION(10, 3, 6): 420 case IP_VERSION(10, 3, 7): 421 gfx_target_version = 100306; 422 if (!vf) 423 f2g = &gfx_v10_3_kfd2kgd; 424 break; 425 case IP_VERSION(11, 0, 0): 426 gfx_target_version = 110000; 427 f2g = &gfx_v11_kfd2kgd; 428 break; 429 case IP_VERSION(11, 0, 1): 430 case IP_VERSION(11, 0, 4): 431 gfx_target_version = 110003; 432 f2g = &gfx_v11_kfd2kgd; 433 break; 434 case IP_VERSION(11, 0, 2): 435 gfx_target_version = 110002; 436 f2g = &gfx_v11_kfd2kgd; 437 break; 438 case IP_VERSION(11, 0, 3): 439 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 440 gfx_target_version = 110001; 441 f2g = &gfx_v11_kfd2kgd; 442 break; 443 case IP_VERSION(11, 5, 0): 444 gfx_target_version = 110500; 445 f2g = &gfx_v11_kfd2kgd; 446 break; 447 case IP_VERSION(11, 5, 1): 448 gfx_target_version = 110501; 449 f2g = &gfx_v11_kfd2kgd; 450 break; 451 case IP_VERSION(11, 5, 2): 452 gfx_target_version = 110502; 453 f2g = &gfx_v11_kfd2kgd; 454 break; 455 case IP_VERSION(11, 5, 3): 456 gfx_target_version = 110503; 457 f2g = &gfx_v11_kfd2kgd; 458 break; 459 case IP_VERSION(12, 0, 0): 460 gfx_target_version = 120000; 461 f2g = &gfx_v12_kfd2kgd; 462 break; 463 case IP_VERSION(12, 0, 1): 464 gfx_target_version = 120001; 465 f2g = &gfx_v12_kfd2kgd; 466 break; 467 default: 468 break; 469 } 470 break; 471 } 472 473 if (!f2g) { 474 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 475 dev_info(kfd_device, 476 "GC IP %06x %s not supported in kfd\n", 477 amdgpu_ip_version(adev, GC_HWIP, 0), 478 vf ? "VF" : ""); 479 else 480 dev_info(kfd_device, "%s %s not supported in kfd\n", 481 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 482 return NULL; 483 } 484 485 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 486 if (!kfd) 487 return NULL; 488 489 kfd->adev = adev; 490 kfd_device_info_init(kfd, vf, gfx_target_version); 491 kfd->init_complete = false; 492 kfd->kfd2kgd = f2g; 493 atomic_set(&kfd->compute_profile, 0); 494 495 mutex_init(&kfd->doorbell_mutex); 496 497 ida_init(&kfd->doorbell_ida); 498 499 return kfd; 500 } 501 502 static void kfd_cwsr_init(struct kfd_dev *kfd) 503 { 504 if (cwsr_enable && kfd->device_info.supports_cwsr) { 505 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 506 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 507 > KFD_CWSR_TMA_OFFSET); 508 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 509 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 510 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 511 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 512 > KFD_CWSR_TMA_OFFSET); 513 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 514 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 515 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 516 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 517 > KFD_CWSR_TMA_OFFSET); 518 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 519 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 520 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 521 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 522 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 523 > KFD_CWSR_TMA_OFFSET); 524 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 525 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 526 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) { 527 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE); 528 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex; 529 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex); 530 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 531 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 532 > KFD_CWSR_TMA_OFFSET); 533 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 534 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 535 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 536 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 537 > KFD_CWSR_TMA_OFFSET); 538 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 539 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 540 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 541 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 542 > KFD_CWSR_TMA_OFFSET); 543 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 544 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 545 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 546 /* The gfx11 cwsr trap handler must fit inside a single 547 page. */ 548 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 549 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 550 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 551 } else { 552 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 553 > KFD_CWSR_TMA_OFFSET); 554 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 555 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 556 } 557 558 kfd->cwsr_enabled = true; 559 } 560 } 561 562 static int kfd_gws_init(struct kfd_node *node) 563 { 564 int ret = 0; 565 struct kfd_dev *kfd = node->kfd; 566 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 567 568 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 569 return 0; 570 571 if (hws_gws_support || (KFD_IS_SOC15(node) && 572 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 573 && kfd->mec2_fw_version >= 0x81b3) || 574 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 575 && kfd->mec2_fw_version >= 0x1b3) || 576 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 577 && kfd->mec2_fw_version >= 0x30) || 578 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 579 && kfd->mec2_fw_version >= 0x28) || 580 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 581 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 582 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) || 583 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 584 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 585 && kfd->mec2_fw_version >= 0x6b) || 586 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 587 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 588 && mes_rev >= 68) || 589 (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))))) { 590 if (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0)) 591 node->adev->gds.gws_size = 64; 592 ret = amdgpu_amdkfd_alloc_gws(node->adev, 593 node->adev->gds.gws_size, &node->gws); 594 } 595 596 return ret; 597 } 598 599 static void kfd_smi_init(struct kfd_node *dev) 600 { 601 INIT_LIST_HEAD(&dev->smi_clients); 602 spin_lock_init(&dev->smi_lock); 603 } 604 605 static int kfd_init_node(struct kfd_node *node) 606 { 607 int err = -1; 608 609 if (kfd_interrupt_init(node)) { 610 dev_err(kfd_device, "Error initializing interrupts\n"); 611 goto kfd_interrupt_error; 612 } 613 614 node->dqm = device_queue_manager_init(node); 615 if (!node->dqm) { 616 dev_err(kfd_device, "Error initializing queue manager\n"); 617 goto device_queue_manager_error; 618 } 619 620 if (kfd_gws_init(node)) { 621 dev_err(kfd_device, "Could not allocate %d gws\n", 622 node->adev->gds.gws_size); 623 goto gws_error; 624 } 625 626 if (kfd_resume(node)) 627 goto kfd_resume_error; 628 629 if (kfd_topology_add_device(node)) { 630 dev_err(kfd_device, "Error adding device to topology\n"); 631 goto kfd_topology_add_device_error; 632 } 633 634 kfd_smi_init(node); 635 636 return 0; 637 638 kfd_topology_add_device_error: 639 kfd_resume_error: 640 gws_error: 641 device_queue_manager_uninit(node->dqm); 642 device_queue_manager_error: 643 kfd_interrupt_exit(node); 644 kfd_interrupt_error: 645 if (node->gws) 646 amdgpu_amdkfd_free_gws(node->adev, node->gws); 647 648 /* Cleanup the node memory here */ 649 kfree(node); 650 return err; 651 } 652 653 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 654 { 655 struct kfd_node *knode; 656 unsigned int i; 657 658 /* 659 * flush_work ensures that there are no outstanding 660 * work-queue items that will access interrupt_ring. New work items 661 * can't be created because we stopped interrupt handling above. 662 */ 663 flush_workqueue(kfd->ih_wq); 664 destroy_workqueue(kfd->ih_wq); 665 666 for (i = 0; i < num_nodes; i++) { 667 knode = kfd->nodes[i]; 668 device_queue_manager_uninit(knode->dqm); 669 kfd_interrupt_exit(knode); 670 kfd_topology_remove_device(knode); 671 if (knode->gws) 672 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 673 kfree(knode); 674 kfd->nodes[i] = NULL; 675 } 676 } 677 678 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 679 unsigned int kfd_node_idx) 680 { 681 struct amdgpu_device *adev = node->adev; 682 uint32_t xcc_mask = node->xcc_mask; 683 uint32_t xcc, mapped_xcc; 684 /* 685 * Interrupt bitmap is setup for processing interrupts from 686 * different XCDs and AIDs. 687 * Interrupt bitmap is defined as follows: 688 * 1. Bits 0-15 - correspond to the NodeId field. 689 * Each bit corresponds to NodeId number. For example, if 690 * a KFD node has interrupt bitmap set to 0x7, then this 691 * KFD node will process interrupts with NodeId = 0, 1 and 2 692 * in the IH cookie. 693 * 2. Bits 16-31 - unused. 694 * 695 * Please note that the kfd_node_idx argument passed to this 696 * function is not related to NodeId field received in the 697 * IH cookie. 698 * 699 * In CPX mode, a KFD node will process an interrupt if: 700 * - the Node Id matches the corresponding bit set in 701 * Bits 0-15. 702 * - AND VMID reported in the interrupt lies within the 703 * VMID range of the node. 704 */ 705 for_each_inst(xcc, xcc_mask) { 706 mapped_xcc = GET_INST(GC, xcc); 707 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 708 } 709 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 710 node->interrupt_bitmap); 711 } 712 713 bool kgd2kfd_device_init(struct kfd_dev *kfd, 714 const struct kgd2kfd_shared_resources *gpu_resources) 715 { 716 unsigned int size, map_process_packet_size, i; 717 struct kfd_node *node; 718 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 719 unsigned int max_proc_per_quantum; 720 int partition_mode; 721 int xcp_idx; 722 723 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 724 KGD_ENGINE_MEC1); 725 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 726 KGD_ENGINE_MEC2); 727 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 728 KGD_ENGINE_SDMA1); 729 kfd->shared_resources = *gpu_resources; 730 731 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 732 733 if (kfd->num_nodes == 0) { 734 dev_err(kfd_device, 735 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 736 kfd->adev->gfx.num_xcc_per_xcp); 737 goto out; 738 } 739 740 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 741 * 32 and 64-bit requests are possible and must be 742 * supported. 743 */ 744 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 745 if (!kfd->pci_atomic_requested && 746 kfd->device_info.needs_pci_atomics && 747 (!kfd->device_info.no_atomic_fw_version || 748 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 749 dev_info(kfd_device, 750 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 751 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 752 kfd->mec_fw_version, 753 kfd->device_info.no_atomic_fw_version); 754 return false; 755 } 756 757 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 758 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 759 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 760 761 /* For multi-partition capable GPUs, we need special handling for VMIDs 762 * depending on partition mode. 763 * In CPX mode, the VMID range needs to be shared between XCDs. 764 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 765 * divide them equally, we change starting VMID to 4 and not use 766 * VMID 3. 767 * If the VMID range changes for multi-partition capable GPUs, then 768 * this code MUST be revisited. 769 */ 770 if (kfd->adev->xcp_mgr) { 771 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 772 AMDGPU_XCP_FL_LOCKED); 773 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 774 kfd->num_nodes != 1) { 775 vmid_num_kfd /= 2; 776 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 777 } 778 } 779 780 /* Verify module parameters regarding mapped process number*/ 781 if (hws_max_conc_proc >= 0) 782 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 783 else 784 max_proc_per_quantum = vmid_num_kfd; 785 786 /* calculate max size of mqds needed for queues */ 787 size = max_num_of_queues_per_device * 788 kfd->device_info.mqd_size_aligned; 789 790 /* 791 * calculate max size of runlist packet. 792 * There can be only 2 packets at once 793 */ 794 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 795 sizeof(struct pm4_mes_map_process_aldebaran) : 796 sizeof(struct pm4_mes_map_process); 797 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 798 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 799 + sizeof(struct pm4_mes_runlist)) * 2; 800 801 /* Add size of HIQ & DIQ */ 802 size += KFD_KERNEL_QUEUE_SIZE * 2; 803 804 /* add another 512KB for all other allocations on gart (HPD, fences) */ 805 size += 512 * 1024; 806 807 if (amdgpu_amdkfd_alloc_gtt_mem( 808 kfd->adev, size, &kfd->gtt_mem, 809 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 810 false)) { 811 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 812 goto alloc_gtt_mem_failure; 813 } 814 815 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 816 817 /* Initialize GTT sa with 512 byte chunk size */ 818 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 819 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 820 goto kfd_gtt_sa_init_error; 821 } 822 823 if (kfd_doorbell_init(kfd)) { 824 dev_err(kfd_device, 825 "Error initializing doorbell aperture\n"); 826 goto kfd_doorbell_error; 827 } 828 829 if (amdgpu_use_xgmi_p2p) 830 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 831 832 /* 833 * For multi-partition capable GPUs, the KFD abstracts all partitions 834 * within a socket as xGMI connected in the topology so assign a unique 835 * hive id per device based on the pci device location if device is in 836 * PCIe mode. 837 */ 838 if (!kfd->hive_id && kfd->num_nodes > 1) 839 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 840 841 kfd->noretry = kfd->adev->gmc.noretry; 842 843 kfd_cwsr_init(kfd); 844 845 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 846 kfd->num_nodes); 847 848 /* Allocate the KFD nodes */ 849 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 850 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 851 if (!node) 852 goto node_alloc_error; 853 854 node->node_id = i; 855 node->adev = kfd->adev; 856 node->kfd = kfd; 857 node->kfd2kgd = kfd->kfd2kgd; 858 node->vm_info.vmid_num_kfd = vmid_num_kfd; 859 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 860 /* TODO : Check if error handling is needed */ 861 if (node->xcp) { 862 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 863 &node->xcc_mask); 864 ++xcp_idx; 865 } else { 866 node->xcc_mask = 867 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 868 } 869 870 if (node->xcp) { 871 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 872 node->node_id, node->xcp->mem_id, 873 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 874 } 875 876 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 877 kfd->num_nodes != 1) { 878 /* For multi-partition capable GPUs and CPX mode, first 879 * XCD gets VMID range 4-9 and second XCD gets VMID 880 * range 10-15. 881 */ 882 883 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 884 first_vmid_kfd : 885 first_vmid_kfd+vmid_num_kfd; 886 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 887 last_vmid_kfd-vmid_num_kfd : 888 last_vmid_kfd; 889 node->compute_vmid_bitmap = 890 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 891 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 892 } else { 893 node->vm_info.first_vmid_kfd = first_vmid_kfd; 894 node->vm_info.last_vmid_kfd = last_vmid_kfd; 895 node->compute_vmid_bitmap = 896 gpu_resources->compute_vmid_bitmap; 897 } 898 node->max_proc_per_quantum = max_proc_per_quantum; 899 atomic_set(&node->sram_ecc_flag, 0); 900 901 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 902 &node->local_mem_info, node->xcp); 903 904 if (kfd->adev->xcp_mgr) 905 kfd_setup_interrupt_bitmap(node, i); 906 907 /* Initialize the KFD node */ 908 if (kfd_init_node(node)) { 909 dev_err(kfd_device, "Error initializing KFD node\n"); 910 goto node_init_error; 911 } 912 913 spin_lock_init(&node->watch_points_lock); 914 915 kfd->nodes[i] = node; 916 } 917 918 svm_range_set_max_pages(kfd->adev); 919 920 kfd->init_complete = true; 921 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 922 kfd->adev->pdev->device); 923 924 pr_debug("Starting kfd with the following scheduling policy %d\n", 925 node->dqm->sched_policy); 926 927 goto out; 928 929 node_init_error: 930 node_alloc_error: 931 kfd_cleanup_nodes(kfd, i); 932 kfd_doorbell_fini(kfd); 933 kfd_doorbell_error: 934 kfd_gtt_sa_fini(kfd); 935 kfd_gtt_sa_init_error: 936 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 937 alloc_gtt_mem_failure: 938 dev_err(kfd_device, 939 "device %x:%x NOT added due to errors\n", 940 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 941 out: 942 return kfd->init_complete; 943 } 944 945 void kgd2kfd_device_exit(struct kfd_dev *kfd) 946 { 947 if (kfd->init_complete) { 948 /* Cleanup KFD nodes */ 949 kfd_cleanup_nodes(kfd, kfd->num_nodes); 950 /* Cleanup common/shared resources */ 951 kfd_doorbell_fini(kfd); 952 ida_destroy(&kfd->doorbell_ida); 953 kfd_gtt_sa_fini(kfd); 954 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 955 } 956 957 kfree(kfd); 958 } 959 960 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 961 struct amdgpu_reset_context *reset_context) 962 { 963 struct kfd_node *node; 964 int i; 965 966 if (!kfd->init_complete) 967 return 0; 968 969 for (i = 0; i < kfd->num_nodes; i++) { 970 node = kfd->nodes[i]; 971 kfd_smi_event_update_gpu_reset(node, false, reset_context); 972 } 973 974 kgd2kfd_suspend(kfd, false); 975 976 for (i = 0; i < kfd->num_nodes; i++) 977 kfd_signal_reset_event(kfd->nodes[i]); 978 979 return 0; 980 } 981 982 /* 983 * Fix me. KFD won't be able to resume existing process for now. 984 * We will keep all existing process in a evicted state and 985 * wait the process to be terminated. 986 */ 987 988 int kgd2kfd_post_reset(struct kfd_dev *kfd) 989 { 990 int ret; 991 struct kfd_node *node; 992 int i; 993 994 if (!kfd->init_complete) 995 return 0; 996 997 for (i = 0; i < kfd->num_nodes; i++) { 998 ret = kfd_resume(kfd->nodes[i]); 999 if (ret) 1000 return ret; 1001 } 1002 1003 mutex_lock(&kfd_processes_mutex); 1004 --kfd_locked; 1005 mutex_unlock(&kfd_processes_mutex); 1006 1007 for (i = 0; i < kfd->num_nodes; i++) { 1008 node = kfd->nodes[i]; 1009 atomic_set(&node->sram_ecc_flag, 0); 1010 kfd_smi_event_update_gpu_reset(node, true, NULL); 1011 } 1012 1013 return 0; 1014 } 1015 1016 bool kfd_is_locked(void) 1017 { 1018 lockdep_assert_held(&kfd_processes_mutex); 1019 return (kfd_locked > 0); 1020 } 1021 1022 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 1023 { 1024 struct kfd_node *node; 1025 int i; 1026 1027 if (!kfd->init_complete) 1028 return; 1029 1030 /* for runtime suspend, skip locking kfd */ 1031 if (!run_pm) { 1032 mutex_lock(&kfd_processes_mutex); 1033 /* For first KFD device suspend all the KFD processes */ 1034 if (++kfd_locked == 1) 1035 kfd_suspend_all_processes(); 1036 mutex_unlock(&kfd_processes_mutex); 1037 } 1038 1039 for (i = 0; i < kfd->num_nodes; i++) { 1040 node = kfd->nodes[i]; 1041 node->dqm->ops.stop(node->dqm); 1042 } 1043 } 1044 1045 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1046 { 1047 int ret, i; 1048 1049 if (!kfd->init_complete) 1050 return 0; 1051 1052 for (i = 0; i < kfd->num_nodes; i++) { 1053 ret = kfd_resume(kfd->nodes[i]); 1054 if (ret) 1055 return ret; 1056 } 1057 1058 /* for runtime resume, skip unlocking kfd */ 1059 if (!run_pm) { 1060 mutex_lock(&kfd_processes_mutex); 1061 if (--kfd_locked == 0) 1062 ret = kfd_resume_all_processes(); 1063 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1064 mutex_unlock(&kfd_processes_mutex); 1065 } 1066 1067 return ret; 1068 } 1069 1070 static int kfd_resume(struct kfd_node *node) 1071 { 1072 int err = 0; 1073 1074 err = node->dqm->ops.start(node->dqm); 1075 if (err) 1076 dev_err(kfd_device, 1077 "Error starting queue manager for device %x:%x\n", 1078 node->adev->pdev->vendor, node->adev->pdev->device); 1079 1080 return err; 1081 } 1082 1083 /* This is called directly from KGD at ISR. */ 1084 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1085 { 1086 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1087 bool is_patched = false; 1088 unsigned long flags; 1089 struct kfd_node *node; 1090 1091 if (!kfd->init_complete) 1092 return; 1093 1094 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1095 dev_err_once(kfd_device, "Ring entry too small\n"); 1096 return; 1097 } 1098 1099 for (i = 0; i < kfd->num_nodes; i++) { 1100 node = kfd->nodes[i]; 1101 spin_lock_irqsave(&node->interrupt_lock, flags); 1102 1103 if (node->interrupts_active 1104 && interrupt_is_wanted(node, ih_ring_entry, 1105 patched_ihre, &is_patched) 1106 && enqueue_ih_ring_entry(node, 1107 is_patched ? patched_ihre : ih_ring_entry)) { 1108 queue_work(node->kfd->ih_wq, &node->interrupt_work); 1109 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1110 return; 1111 } 1112 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1113 } 1114 1115 } 1116 1117 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1118 { 1119 struct kfd_process *p; 1120 int r; 1121 1122 /* Because we are called from arbitrary context (workqueue) as opposed 1123 * to process context, kfd_process could attempt to exit while we are 1124 * running so the lookup function increments the process ref count. 1125 */ 1126 p = kfd_lookup_process_by_mm(mm); 1127 if (!p) 1128 return -ESRCH; 1129 1130 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1131 r = kfd_process_evict_queues(p, trigger); 1132 1133 kfd_unref_process(p); 1134 return r; 1135 } 1136 1137 int kgd2kfd_resume_mm(struct mm_struct *mm) 1138 { 1139 struct kfd_process *p; 1140 int r; 1141 1142 /* Because we are called from arbitrary context (workqueue) as opposed 1143 * to process context, kfd_process could attempt to exit while we are 1144 * running so the lookup function increments the process ref count. 1145 */ 1146 p = kfd_lookup_process_by_mm(mm); 1147 if (!p) 1148 return -ESRCH; 1149 1150 r = kfd_process_restore_queues(p); 1151 1152 kfd_unref_process(p); 1153 return r; 1154 } 1155 1156 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1157 * prepare for safe eviction of KFD BOs that belong to the specified 1158 * process. 1159 * 1160 * @mm: mm_struct that identifies the specified KFD process 1161 * @fence: eviction fence attached to KFD process BOs 1162 * 1163 */ 1164 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1165 struct dma_fence *fence) 1166 { 1167 struct kfd_process *p; 1168 unsigned long active_time; 1169 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1170 1171 if (!fence) 1172 return -EINVAL; 1173 1174 if (dma_fence_is_signaled(fence)) 1175 return 0; 1176 1177 p = kfd_lookup_process_by_mm(mm); 1178 if (!p) 1179 return -ENODEV; 1180 1181 if (fence->seqno == p->last_eviction_seqno) 1182 goto out; 1183 1184 p->last_eviction_seqno = fence->seqno; 1185 1186 /* Avoid KFD process starvation. Wait for at least 1187 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1188 */ 1189 active_time = get_jiffies_64() - p->last_restore_timestamp; 1190 if (delay_jiffies > active_time) 1191 delay_jiffies -= active_time; 1192 else 1193 delay_jiffies = 0; 1194 1195 /* During process initialization eviction_work.dwork is initialized 1196 * to kfd_evict_bo_worker 1197 */ 1198 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1199 p->lead_thread->pid, delay_jiffies); 1200 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1201 out: 1202 kfd_unref_process(p); 1203 return 0; 1204 } 1205 1206 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1207 unsigned int chunk_size) 1208 { 1209 if (WARN_ON(buf_size < chunk_size)) 1210 return -EINVAL; 1211 if (WARN_ON(buf_size == 0)) 1212 return -EINVAL; 1213 if (WARN_ON(chunk_size == 0)) 1214 return -EINVAL; 1215 1216 kfd->gtt_sa_chunk_size = chunk_size; 1217 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1218 1219 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1220 GFP_KERNEL); 1221 if (!kfd->gtt_sa_bitmap) 1222 return -ENOMEM; 1223 1224 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1225 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1226 1227 mutex_init(&kfd->gtt_sa_lock); 1228 1229 return 0; 1230 } 1231 1232 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1233 { 1234 mutex_destroy(&kfd->gtt_sa_lock); 1235 bitmap_free(kfd->gtt_sa_bitmap); 1236 } 1237 1238 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1239 unsigned int bit_num, 1240 unsigned int chunk_size) 1241 { 1242 return start_addr + bit_num * chunk_size; 1243 } 1244 1245 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1246 unsigned int bit_num, 1247 unsigned int chunk_size) 1248 { 1249 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1250 } 1251 1252 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1253 struct kfd_mem_obj **mem_obj) 1254 { 1255 unsigned int found, start_search, cur_size; 1256 struct kfd_dev *kfd = node->kfd; 1257 1258 if (size == 0) 1259 return -EINVAL; 1260 1261 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1262 return -ENOMEM; 1263 1264 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1265 if (!(*mem_obj)) 1266 return -ENOMEM; 1267 1268 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1269 1270 start_search = 0; 1271 1272 mutex_lock(&kfd->gtt_sa_lock); 1273 1274 kfd_gtt_restart_search: 1275 /* Find the first chunk that is free */ 1276 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1277 kfd->gtt_sa_num_of_chunks, 1278 start_search); 1279 1280 pr_debug("Found = %d\n", found); 1281 1282 /* If there wasn't any free chunk, bail out */ 1283 if (found == kfd->gtt_sa_num_of_chunks) 1284 goto kfd_gtt_no_free_chunk; 1285 1286 /* Update fields of mem_obj */ 1287 (*mem_obj)->range_start = found; 1288 (*mem_obj)->range_end = found; 1289 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1290 kfd->gtt_start_gpu_addr, 1291 found, 1292 kfd->gtt_sa_chunk_size); 1293 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1294 kfd->gtt_start_cpu_ptr, 1295 found, 1296 kfd->gtt_sa_chunk_size); 1297 1298 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1299 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1300 1301 /* If we need only one chunk, mark it as allocated and get out */ 1302 if (size <= kfd->gtt_sa_chunk_size) { 1303 pr_debug("Single bit\n"); 1304 __set_bit(found, kfd->gtt_sa_bitmap); 1305 goto kfd_gtt_out; 1306 } 1307 1308 /* Otherwise, try to see if we have enough contiguous chunks */ 1309 cur_size = size - kfd->gtt_sa_chunk_size; 1310 do { 1311 (*mem_obj)->range_end = 1312 find_next_zero_bit(kfd->gtt_sa_bitmap, 1313 kfd->gtt_sa_num_of_chunks, ++found); 1314 /* 1315 * If next free chunk is not contiguous than we need to 1316 * restart our search from the last free chunk we found (which 1317 * wasn't contiguous to the previous ones 1318 */ 1319 if ((*mem_obj)->range_end != found) { 1320 start_search = found; 1321 goto kfd_gtt_restart_search; 1322 } 1323 1324 /* 1325 * If we reached end of buffer, bail out with error 1326 */ 1327 if (found == kfd->gtt_sa_num_of_chunks) 1328 goto kfd_gtt_no_free_chunk; 1329 1330 /* Check if we don't need another chunk */ 1331 if (cur_size <= kfd->gtt_sa_chunk_size) 1332 cur_size = 0; 1333 else 1334 cur_size -= kfd->gtt_sa_chunk_size; 1335 1336 } while (cur_size > 0); 1337 1338 pr_debug("range_start = %d, range_end = %d\n", 1339 (*mem_obj)->range_start, (*mem_obj)->range_end); 1340 1341 /* Mark the chunks as allocated */ 1342 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1343 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1344 1345 kfd_gtt_out: 1346 mutex_unlock(&kfd->gtt_sa_lock); 1347 return 0; 1348 1349 kfd_gtt_no_free_chunk: 1350 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1351 mutex_unlock(&kfd->gtt_sa_lock); 1352 kfree(*mem_obj); 1353 return -ENOMEM; 1354 } 1355 1356 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1357 { 1358 struct kfd_dev *kfd = node->kfd; 1359 1360 /* Act like kfree when trying to free a NULL object */ 1361 if (!mem_obj) 1362 return 0; 1363 1364 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1365 mem_obj, mem_obj->range_start, mem_obj->range_end); 1366 1367 mutex_lock(&kfd->gtt_sa_lock); 1368 1369 /* Mark the chunks as free */ 1370 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1371 mem_obj->range_end - mem_obj->range_start + 1); 1372 1373 mutex_unlock(&kfd->gtt_sa_lock); 1374 1375 kfree(mem_obj); 1376 return 0; 1377 } 1378 1379 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1380 { 1381 /* 1382 * TODO: Currently update SRAM ECC flag for first node. 1383 * This needs to be updated later when we can 1384 * identify SRAM ECC error on other nodes also. 1385 */ 1386 if (kfd) 1387 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1388 } 1389 1390 void kfd_inc_compute_active(struct kfd_node *node) 1391 { 1392 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1393 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1394 } 1395 1396 void kfd_dec_compute_active(struct kfd_node *node) 1397 { 1398 int count = atomic_dec_return(&node->kfd->compute_profile); 1399 1400 if (count == 0) 1401 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1402 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1403 } 1404 1405 static bool kfd_compute_active(struct kfd_node *node) 1406 { 1407 if (atomic_read(&node->kfd->compute_profile)) 1408 return true; 1409 return false; 1410 } 1411 1412 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1413 { 1414 /* 1415 * TODO: For now, raise the throttling event only on first node. 1416 * This will need to change after we are able to determine 1417 * which node raised the throttling event. 1418 */ 1419 if (kfd && kfd->init_complete) 1420 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1421 throttle_bitmask); 1422 } 1423 1424 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1425 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1426 * When the device has more than two engines, we reserve two for PCIe to enable 1427 * full-duplex and the rest are used as XGMI. 1428 */ 1429 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1430 { 1431 /* If XGMI is not supported, all SDMA engines are PCIe */ 1432 if (!node->adev->gmc.xgmi.supported) 1433 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1434 1435 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1436 } 1437 1438 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1439 { 1440 /* After reserved for PCIe, the rest of engines are XGMI */ 1441 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1442 kfd_get_num_sdma_engines(node); 1443 } 1444 1445 int kgd2kfd_check_and_lock_kfd(void) 1446 { 1447 mutex_lock(&kfd_processes_mutex); 1448 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1449 mutex_unlock(&kfd_processes_mutex); 1450 return -EBUSY; 1451 } 1452 1453 ++kfd_locked; 1454 mutex_unlock(&kfd_processes_mutex); 1455 1456 return 0; 1457 } 1458 1459 void kgd2kfd_unlock_kfd(void) 1460 { 1461 mutex_lock(&kfd_processes_mutex); 1462 --kfd_locked; 1463 mutex_unlock(&kfd_processes_mutex); 1464 } 1465 1466 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1467 { 1468 struct kfd_node *node; 1469 int ret; 1470 1471 if (!kfd->init_complete) 1472 return 0; 1473 1474 if (node_id >= kfd->num_nodes) { 1475 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1476 node_id, kfd->num_nodes - 1); 1477 return -EINVAL; 1478 } 1479 node = kfd->nodes[node_id]; 1480 1481 ret = node->dqm->ops.unhalt(node->dqm); 1482 if (ret) 1483 dev_err(kfd_device, "Error in starting scheduler\n"); 1484 1485 return ret; 1486 } 1487 1488 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1489 { 1490 struct kfd_node *node; 1491 1492 if (!kfd->init_complete) 1493 return 0; 1494 1495 if (node_id >= kfd->num_nodes) { 1496 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1497 node_id, kfd->num_nodes - 1); 1498 return -EINVAL; 1499 } 1500 1501 node = kfd->nodes[node_id]; 1502 return node->dqm->ops.halt(node->dqm); 1503 } 1504 1505 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1506 { 1507 struct kfd_node *node; 1508 1509 if (!kfd->init_complete) 1510 return false; 1511 1512 if (node_id >= kfd->num_nodes) { 1513 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1514 node_id, kfd->num_nodes - 1); 1515 return false; 1516 } 1517 1518 node = kfd->nodes[node_id]; 1519 1520 return kfd_compute_active(node); 1521 } 1522 1523 /** 1524 * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9 1525 * @adev: amdgpu device 1526 * @entry: vm fault interrupt vector 1527 * @retry_fault: if this is retry fault 1528 * 1529 * retry fault - 1530 * with CAM enabled, adev primary ring 1531 * | gmc_v9_0_process_interrupt() 1532 * adev soft_ring 1533 * | gmc_v9_0_process_interrupt() worker failed to recover page fault 1534 * KFD node ih_fifo 1535 * | KFD interrupt_wq worker 1536 * kfd_signal_vm_fault_event 1537 * 1538 * without CAM, adev primary ring1 1539 * | gmc_v9_0_process_interrupt worker failed to recvoer page fault 1540 * KFD node ih_fifo 1541 * | KFD interrupt_wq worker 1542 * kfd_signal_vm_fault_event 1543 * 1544 * no-retry fault - 1545 * adev primary ring 1546 * | gmc_v9_0_process_interrupt() 1547 * KFD node ih_fifo 1548 * | KFD interrupt_wq worker 1549 * kfd_signal_vm_fault_event 1550 * 1551 * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault 1552 * of same process, don't copy interrupt to KFD node ih_fifo. 1553 * With gdb debugger enabled, need convert the retry fault to no-retry fault for 1554 * debugger, cannot use the fast path. 1555 * 1556 * Return: 1557 * true - use the fast path to handle this fault 1558 * false - use normal path to handle it 1559 */ 1560 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 1561 bool retry_fault) 1562 { 1563 struct kfd_process *p; 1564 u32 cam_index; 1565 1566 if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) { 1567 p = kfd_lookup_process_by_pasid(entry->pasid, NULL); 1568 if (!p) 1569 return true; 1570 1571 if (p->gpu_page_fault && !p->debug_trap_enabled) { 1572 if (retry_fault && adev->irq.retry_cam_enabled) { 1573 cam_index = entry->src_data[2] & 0x3ff; 1574 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 1575 } 1576 1577 kfd_unref_process(p); 1578 return true; 1579 } 1580 1581 /* 1582 * This is the first page fault, set flag and then signal user space 1583 */ 1584 p->gpu_page_fault = true; 1585 kfd_unref_process(p); 1586 } 1587 return false; 1588 } 1589 1590 #if defined(CONFIG_DEBUG_FS) 1591 1592 /* This function will send a package to HIQ to hang the HWS 1593 * which will trigger a GPU reset and bring the HWS back to normal state 1594 */ 1595 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1596 { 1597 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1598 pr_err("HWS is not enabled"); 1599 return -EINVAL; 1600 } 1601 1602 if (dev->kfd->shared_resources.enable_mes) { 1603 dev_err(dev->adev->dev, "Inducing MES hang is not supported\n"); 1604 return -EINVAL; 1605 } 1606 1607 return dqm_debugfs_hang_hws(dev->dqm); 1608 } 1609 1610 #endif 1611