1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "kfd_pm4_headers_aldebaran.h" 30 #include "cwsr_trap_handler.h" 31 #include "kfd_iommu.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_migrate.h" 35 36 #define MQD_SIZE_ALIGNED 768 37 38 /* 39 * kfd_locked is used to lock the kfd driver during suspend or reset 40 * once locked, kfd driver will stop any further GPU execution. 41 * create process (open) will return -EAGAIN. 42 */ 43 static atomic_t kfd_locked = ATOMIC_INIT(0); 44 45 #ifdef CONFIG_DRM_AMDGPU_CIK 46 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 47 #endif 48 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 49 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 50 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 51 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 54 55 static const struct kfd2kgd_calls *kfd2kgd_funcs[] = { 56 #ifdef KFD_SUPPORT_IOMMU_V2 57 #ifdef CONFIG_DRM_AMDGPU_CIK 58 [CHIP_KAVERI] = &gfx_v7_kfd2kgd, 59 #endif 60 [CHIP_CARRIZO] = &gfx_v8_kfd2kgd, 61 [CHIP_RAVEN] = &gfx_v9_kfd2kgd, 62 #endif 63 #ifdef CONFIG_DRM_AMDGPU_CIK 64 [CHIP_HAWAII] = &gfx_v7_kfd2kgd, 65 #endif 66 [CHIP_TONGA] = &gfx_v8_kfd2kgd, 67 [CHIP_FIJI] = &gfx_v8_kfd2kgd, 68 [CHIP_POLARIS10] = &gfx_v8_kfd2kgd, 69 [CHIP_POLARIS11] = &gfx_v8_kfd2kgd, 70 [CHIP_POLARIS12] = &gfx_v8_kfd2kgd, 71 [CHIP_VEGAM] = &gfx_v8_kfd2kgd, 72 [CHIP_VEGA10] = &gfx_v9_kfd2kgd, 73 [CHIP_VEGA12] = &gfx_v9_kfd2kgd, 74 [CHIP_VEGA20] = &gfx_v9_kfd2kgd, 75 [CHIP_RENOIR] = &gfx_v9_kfd2kgd, 76 [CHIP_ARCTURUS] = &arcturus_kfd2kgd, 77 [CHIP_ALDEBARAN] = &aldebaran_kfd2kgd, 78 [CHIP_NAVI10] = &gfx_v10_kfd2kgd, 79 [CHIP_NAVI12] = &gfx_v10_kfd2kgd, 80 [CHIP_NAVI14] = &gfx_v10_kfd2kgd, 81 [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd, 82 [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd, 83 [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd, 84 [CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd, 85 [CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd, 86 }; 87 88 #ifdef KFD_SUPPORT_IOMMU_V2 89 static const struct kfd_device_info kaveri_device_info = { 90 .asic_family = CHIP_KAVERI, 91 .asic_name = "kaveri", 92 .max_pasid_bits = 16, 93 /* max num of queues for KV.TODO should be a dynamic value */ 94 .max_no_of_hqd = 24, 95 .doorbell_size = 4, 96 .ih_ring_entry_size = 4 * sizeof(uint32_t), 97 .event_interrupt_class = &event_interrupt_class_cik, 98 .num_of_watch_points = 4, 99 .mqd_size_aligned = MQD_SIZE_ALIGNED, 100 .supports_cwsr = false, 101 .needs_iommu_device = true, 102 .needs_pci_atomics = false, 103 .num_sdma_engines = 2, 104 .num_xgmi_sdma_engines = 0, 105 .num_sdma_queues_per_engine = 2, 106 }; 107 108 static const struct kfd_device_info carrizo_device_info = { 109 .asic_family = CHIP_CARRIZO, 110 .asic_name = "carrizo", 111 .max_pasid_bits = 16, 112 /* max num of queues for CZ.TODO should be a dynamic value */ 113 .max_no_of_hqd = 24, 114 .doorbell_size = 4, 115 .ih_ring_entry_size = 4 * sizeof(uint32_t), 116 .event_interrupt_class = &event_interrupt_class_cik, 117 .num_of_watch_points = 4, 118 .mqd_size_aligned = MQD_SIZE_ALIGNED, 119 .supports_cwsr = true, 120 .needs_iommu_device = true, 121 .needs_pci_atomics = false, 122 .num_sdma_engines = 2, 123 .num_xgmi_sdma_engines = 0, 124 .num_sdma_queues_per_engine = 2, 125 }; 126 #endif 127 128 static const struct kfd_device_info raven_device_info = { 129 .asic_family = CHIP_RAVEN, 130 .asic_name = "raven", 131 .max_pasid_bits = 16, 132 .max_no_of_hqd = 24, 133 .doorbell_size = 8, 134 .ih_ring_entry_size = 8 * sizeof(uint32_t), 135 .event_interrupt_class = &event_interrupt_class_v9, 136 .num_of_watch_points = 4, 137 .mqd_size_aligned = MQD_SIZE_ALIGNED, 138 .supports_cwsr = true, 139 .needs_iommu_device = true, 140 .needs_pci_atomics = true, 141 .num_sdma_engines = 1, 142 .num_xgmi_sdma_engines = 0, 143 .num_sdma_queues_per_engine = 2, 144 }; 145 146 static const struct kfd_device_info hawaii_device_info = { 147 .asic_family = CHIP_HAWAII, 148 .asic_name = "hawaii", 149 .max_pasid_bits = 16, 150 /* max num of queues for KV.TODO should be a dynamic value */ 151 .max_no_of_hqd = 24, 152 .doorbell_size = 4, 153 .ih_ring_entry_size = 4 * sizeof(uint32_t), 154 .event_interrupt_class = &event_interrupt_class_cik, 155 .num_of_watch_points = 4, 156 .mqd_size_aligned = MQD_SIZE_ALIGNED, 157 .supports_cwsr = false, 158 .needs_iommu_device = false, 159 .needs_pci_atomics = false, 160 .num_sdma_engines = 2, 161 .num_xgmi_sdma_engines = 0, 162 .num_sdma_queues_per_engine = 2, 163 }; 164 165 static const struct kfd_device_info tonga_device_info = { 166 .asic_family = CHIP_TONGA, 167 .asic_name = "tonga", 168 .max_pasid_bits = 16, 169 .max_no_of_hqd = 24, 170 .doorbell_size = 4, 171 .ih_ring_entry_size = 4 * sizeof(uint32_t), 172 .event_interrupt_class = &event_interrupt_class_cik, 173 .num_of_watch_points = 4, 174 .mqd_size_aligned = MQD_SIZE_ALIGNED, 175 .supports_cwsr = false, 176 .needs_iommu_device = false, 177 .needs_pci_atomics = true, 178 .num_sdma_engines = 2, 179 .num_xgmi_sdma_engines = 0, 180 .num_sdma_queues_per_engine = 2, 181 }; 182 183 static const struct kfd_device_info fiji_device_info = { 184 .asic_family = CHIP_FIJI, 185 .asic_name = "fiji", 186 .max_pasid_bits = 16, 187 .max_no_of_hqd = 24, 188 .doorbell_size = 4, 189 .ih_ring_entry_size = 4 * sizeof(uint32_t), 190 .event_interrupt_class = &event_interrupt_class_cik, 191 .num_of_watch_points = 4, 192 .mqd_size_aligned = MQD_SIZE_ALIGNED, 193 .supports_cwsr = true, 194 .needs_iommu_device = false, 195 .needs_pci_atomics = true, 196 .num_sdma_engines = 2, 197 .num_xgmi_sdma_engines = 0, 198 .num_sdma_queues_per_engine = 2, 199 }; 200 201 static const struct kfd_device_info fiji_vf_device_info = { 202 .asic_family = CHIP_FIJI, 203 .asic_name = "fiji", 204 .max_pasid_bits = 16, 205 .max_no_of_hqd = 24, 206 .doorbell_size = 4, 207 .ih_ring_entry_size = 4 * sizeof(uint32_t), 208 .event_interrupt_class = &event_interrupt_class_cik, 209 .num_of_watch_points = 4, 210 .mqd_size_aligned = MQD_SIZE_ALIGNED, 211 .supports_cwsr = true, 212 .needs_iommu_device = false, 213 .needs_pci_atomics = false, 214 .num_sdma_engines = 2, 215 .num_xgmi_sdma_engines = 0, 216 .num_sdma_queues_per_engine = 2, 217 }; 218 219 220 static const struct kfd_device_info polaris10_device_info = { 221 .asic_family = CHIP_POLARIS10, 222 .asic_name = "polaris10", 223 .max_pasid_bits = 16, 224 .max_no_of_hqd = 24, 225 .doorbell_size = 4, 226 .ih_ring_entry_size = 4 * sizeof(uint32_t), 227 .event_interrupt_class = &event_interrupt_class_cik, 228 .num_of_watch_points = 4, 229 .mqd_size_aligned = MQD_SIZE_ALIGNED, 230 .supports_cwsr = true, 231 .needs_iommu_device = false, 232 .needs_pci_atomics = true, 233 .num_sdma_engines = 2, 234 .num_xgmi_sdma_engines = 0, 235 .num_sdma_queues_per_engine = 2, 236 }; 237 238 static const struct kfd_device_info polaris10_vf_device_info = { 239 .asic_family = CHIP_POLARIS10, 240 .asic_name = "polaris10", 241 .max_pasid_bits = 16, 242 .max_no_of_hqd = 24, 243 .doorbell_size = 4, 244 .ih_ring_entry_size = 4 * sizeof(uint32_t), 245 .event_interrupt_class = &event_interrupt_class_cik, 246 .num_of_watch_points = 4, 247 .mqd_size_aligned = MQD_SIZE_ALIGNED, 248 .supports_cwsr = true, 249 .needs_iommu_device = false, 250 .needs_pci_atomics = false, 251 .num_sdma_engines = 2, 252 .num_xgmi_sdma_engines = 0, 253 .num_sdma_queues_per_engine = 2, 254 }; 255 256 static const struct kfd_device_info polaris11_device_info = { 257 .asic_family = CHIP_POLARIS11, 258 .asic_name = "polaris11", 259 .max_pasid_bits = 16, 260 .max_no_of_hqd = 24, 261 .doorbell_size = 4, 262 .ih_ring_entry_size = 4 * sizeof(uint32_t), 263 .event_interrupt_class = &event_interrupt_class_cik, 264 .num_of_watch_points = 4, 265 .mqd_size_aligned = MQD_SIZE_ALIGNED, 266 .supports_cwsr = true, 267 .needs_iommu_device = false, 268 .needs_pci_atomics = true, 269 .num_sdma_engines = 2, 270 .num_xgmi_sdma_engines = 0, 271 .num_sdma_queues_per_engine = 2, 272 }; 273 274 static const struct kfd_device_info polaris12_device_info = { 275 .asic_family = CHIP_POLARIS12, 276 .asic_name = "polaris12", 277 .max_pasid_bits = 16, 278 .max_no_of_hqd = 24, 279 .doorbell_size = 4, 280 .ih_ring_entry_size = 4 * sizeof(uint32_t), 281 .event_interrupt_class = &event_interrupt_class_cik, 282 .num_of_watch_points = 4, 283 .mqd_size_aligned = MQD_SIZE_ALIGNED, 284 .supports_cwsr = true, 285 .needs_iommu_device = false, 286 .needs_pci_atomics = true, 287 .num_sdma_engines = 2, 288 .num_xgmi_sdma_engines = 0, 289 .num_sdma_queues_per_engine = 2, 290 }; 291 292 static const struct kfd_device_info vegam_device_info = { 293 .asic_family = CHIP_VEGAM, 294 .asic_name = "vegam", 295 .max_pasid_bits = 16, 296 .max_no_of_hqd = 24, 297 .doorbell_size = 4, 298 .ih_ring_entry_size = 4 * sizeof(uint32_t), 299 .event_interrupt_class = &event_interrupt_class_cik, 300 .num_of_watch_points = 4, 301 .mqd_size_aligned = MQD_SIZE_ALIGNED, 302 .supports_cwsr = true, 303 .needs_iommu_device = false, 304 .needs_pci_atomics = true, 305 .num_sdma_engines = 2, 306 .num_xgmi_sdma_engines = 0, 307 .num_sdma_queues_per_engine = 2, 308 }; 309 310 static const struct kfd_device_info vega10_device_info = { 311 .asic_family = CHIP_VEGA10, 312 .asic_name = "vega10", 313 .max_pasid_bits = 16, 314 .max_no_of_hqd = 24, 315 .doorbell_size = 8, 316 .ih_ring_entry_size = 8 * sizeof(uint32_t), 317 .event_interrupt_class = &event_interrupt_class_v9, 318 .num_of_watch_points = 4, 319 .mqd_size_aligned = MQD_SIZE_ALIGNED, 320 .supports_cwsr = true, 321 .needs_iommu_device = false, 322 .needs_pci_atomics = false, 323 .num_sdma_engines = 2, 324 .num_xgmi_sdma_engines = 0, 325 .num_sdma_queues_per_engine = 2, 326 }; 327 328 static const struct kfd_device_info vega10_vf_device_info = { 329 .asic_family = CHIP_VEGA10, 330 .asic_name = "vega10", 331 .max_pasid_bits = 16, 332 .max_no_of_hqd = 24, 333 .doorbell_size = 8, 334 .ih_ring_entry_size = 8 * sizeof(uint32_t), 335 .event_interrupt_class = &event_interrupt_class_v9, 336 .num_of_watch_points = 4, 337 .mqd_size_aligned = MQD_SIZE_ALIGNED, 338 .supports_cwsr = true, 339 .needs_iommu_device = false, 340 .needs_pci_atomics = false, 341 .num_sdma_engines = 2, 342 .num_xgmi_sdma_engines = 0, 343 .num_sdma_queues_per_engine = 2, 344 }; 345 346 static const struct kfd_device_info vega12_device_info = { 347 .asic_family = CHIP_VEGA12, 348 .asic_name = "vega12", 349 .max_pasid_bits = 16, 350 .max_no_of_hqd = 24, 351 .doorbell_size = 8, 352 .ih_ring_entry_size = 8 * sizeof(uint32_t), 353 .event_interrupt_class = &event_interrupt_class_v9, 354 .num_of_watch_points = 4, 355 .mqd_size_aligned = MQD_SIZE_ALIGNED, 356 .supports_cwsr = true, 357 .needs_iommu_device = false, 358 .needs_pci_atomics = false, 359 .num_sdma_engines = 2, 360 .num_xgmi_sdma_engines = 0, 361 .num_sdma_queues_per_engine = 2, 362 }; 363 364 static const struct kfd_device_info vega20_device_info = { 365 .asic_family = CHIP_VEGA20, 366 .asic_name = "vega20", 367 .max_pasid_bits = 16, 368 .max_no_of_hqd = 24, 369 .doorbell_size = 8, 370 .ih_ring_entry_size = 8 * sizeof(uint32_t), 371 .event_interrupt_class = &event_interrupt_class_v9, 372 .num_of_watch_points = 4, 373 .mqd_size_aligned = MQD_SIZE_ALIGNED, 374 .supports_cwsr = true, 375 .needs_iommu_device = false, 376 .needs_pci_atomics = false, 377 .num_sdma_engines = 2, 378 .num_xgmi_sdma_engines = 0, 379 .num_sdma_queues_per_engine = 8, 380 }; 381 382 static const struct kfd_device_info arcturus_device_info = { 383 .asic_family = CHIP_ARCTURUS, 384 .asic_name = "arcturus", 385 .max_pasid_bits = 16, 386 .max_no_of_hqd = 24, 387 .doorbell_size = 8, 388 .ih_ring_entry_size = 8 * sizeof(uint32_t), 389 .event_interrupt_class = &event_interrupt_class_v9, 390 .num_of_watch_points = 4, 391 .mqd_size_aligned = MQD_SIZE_ALIGNED, 392 .supports_cwsr = true, 393 .needs_iommu_device = false, 394 .needs_pci_atomics = false, 395 .num_sdma_engines = 2, 396 .num_xgmi_sdma_engines = 6, 397 .num_sdma_queues_per_engine = 8, 398 }; 399 400 static const struct kfd_device_info aldebaran_device_info = { 401 .asic_family = CHIP_ALDEBARAN, 402 .asic_name = "aldebaran", 403 .max_pasid_bits = 16, 404 .max_no_of_hqd = 24, 405 .doorbell_size = 8, 406 .ih_ring_entry_size = 8 * sizeof(uint32_t), 407 .event_interrupt_class = &event_interrupt_class_v9, 408 .num_of_watch_points = 4, 409 .mqd_size_aligned = MQD_SIZE_ALIGNED, 410 .supports_cwsr = true, 411 .needs_iommu_device = false, 412 .needs_pci_atomics = false, 413 .num_sdma_engines = 2, 414 .num_xgmi_sdma_engines = 3, 415 .num_sdma_queues_per_engine = 8, 416 }; 417 418 static const struct kfd_device_info renoir_device_info = { 419 .asic_family = CHIP_RENOIR, 420 .asic_name = "renoir", 421 .max_pasid_bits = 16, 422 .max_no_of_hqd = 24, 423 .doorbell_size = 8, 424 .ih_ring_entry_size = 8 * sizeof(uint32_t), 425 .event_interrupt_class = &event_interrupt_class_v9, 426 .num_of_watch_points = 4, 427 .mqd_size_aligned = MQD_SIZE_ALIGNED, 428 .supports_cwsr = true, 429 .needs_iommu_device = false, 430 .needs_pci_atomics = false, 431 .num_sdma_engines = 1, 432 .num_xgmi_sdma_engines = 0, 433 .num_sdma_queues_per_engine = 2, 434 }; 435 436 static const struct kfd_device_info navi10_device_info = { 437 .asic_family = CHIP_NAVI10, 438 .asic_name = "navi10", 439 .max_pasid_bits = 16, 440 .max_no_of_hqd = 24, 441 .doorbell_size = 8, 442 .ih_ring_entry_size = 8 * sizeof(uint32_t), 443 .event_interrupt_class = &event_interrupt_class_v9, 444 .num_of_watch_points = 4, 445 .mqd_size_aligned = MQD_SIZE_ALIGNED, 446 .needs_iommu_device = false, 447 .supports_cwsr = true, 448 .needs_pci_atomics = true, 449 .num_sdma_engines = 2, 450 .num_xgmi_sdma_engines = 0, 451 .num_sdma_queues_per_engine = 8, 452 }; 453 454 static const struct kfd_device_info navi12_device_info = { 455 .asic_family = CHIP_NAVI12, 456 .asic_name = "navi12", 457 .max_pasid_bits = 16, 458 .max_no_of_hqd = 24, 459 .doorbell_size = 8, 460 .ih_ring_entry_size = 8 * sizeof(uint32_t), 461 .event_interrupt_class = &event_interrupt_class_v9, 462 .num_of_watch_points = 4, 463 .mqd_size_aligned = MQD_SIZE_ALIGNED, 464 .needs_iommu_device = false, 465 .supports_cwsr = true, 466 .needs_pci_atomics = true, 467 .num_sdma_engines = 2, 468 .num_xgmi_sdma_engines = 0, 469 .num_sdma_queues_per_engine = 8, 470 }; 471 472 static const struct kfd_device_info navi14_device_info = { 473 .asic_family = CHIP_NAVI14, 474 .asic_name = "navi14", 475 .max_pasid_bits = 16, 476 .max_no_of_hqd = 24, 477 .doorbell_size = 8, 478 .ih_ring_entry_size = 8 * sizeof(uint32_t), 479 .event_interrupt_class = &event_interrupt_class_v9, 480 .num_of_watch_points = 4, 481 .mqd_size_aligned = MQD_SIZE_ALIGNED, 482 .needs_iommu_device = false, 483 .supports_cwsr = true, 484 .needs_pci_atomics = true, 485 .num_sdma_engines = 2, 486 .num_xgmi_sdma_engines = 0, 487 .num_sdma_queues_per_engine = 8, 488 }; 489 490 static const struct kfd_device_info sienna_cichlid_device_info = { 491 .asic_family = CHIP_SIENNA_CICHLID, 492 .asic_name = "sienna_cichlid", 493 .max_pasid_bits = 16, 494 .max_no_of_hqd = 24, 495 .doorbell_size = 8, 496 .ih_ring_entry_size = 8 * sizeof(uint32_t), 497 .event_interrupt_class = &event_interrupt_class_v9, 498 .num_of_watch_points = 4, 499 .mqd_size_aligned = MQD_SIZE_ALIGNED, 500 .needs_iommu_device = false, 501 .supports_cwsr = true, 502 .needs_pci_atomics = true, 503 .num_sdma_engines = 4, 504 .num_xgmi_sdma_engines = 0, 505 .num_sdma_queues_per_engine = 8, 506 }; 507 508 static const struct kfd_device_info navy_flounder_device_info = { 509 .asic_family = CHIP_NAVY_FLOUNDER, 510 .asic_name = "navy_flounder", 511 .max_pasid_bits = 16, 512 .max_no_of_hqd = 24, 513 .doorbell_size = 8, 514 .ih_ring_entry_size = 8 * sizeof(uint32_t), 515 .event_interrupt_class = &event_interrupt_class_v9, 516 .num_of_watch_points = 4, 517 .mqd_size_aligned = MQD_SIZE_ALIGNED, 518 .needs_iommu_device = false, 519 .supports_cwsr = true, 520 .needs_pci_atomics = true, 521 .num_sdma_engines = 2, 522 .num_xgmi_sdma_engines = 0, 523 .num_sdma_queues_per_engine = 8, 524 }; 525 526 static const struct kfd_device_info vangogh_device_info = { 527 .asic_family = CHIP_VANGOGH, 528 .asic_name = "vangogh", 529 .max_pasid_bits = 16, 530 .max_no_of_hqd = 24, 531 .doorbell_size = 8, 532 .ih_ring_entry_size = 8 * sizeof(uint32_t), 533 .event_interrupt_class = &event_interrupt_class_v9, 534 .num_of_watch_points = 4, 535 .mqd_size_aligned = MQD_SIZE_ALIGNED, 536 .needs_iommu_device = false, 537 .supports_cwsr = true, 538 .needs_pci_atomics = false, 539 .num_sdma_engines = 1, 540 .num_xgmi_sdma_engines = 0, 541 .num_sdma_queues_per_engine = 2, 542 }; 543 544 static const struct kfd_device_info dimgrey_cavefish_device_info = { 545 .asic_family = CHIP_DIMGREY_CAVEFISH, 546 .asic_name = "dimgrey_cavefish", 547 .max_pasid_bits = 16, 548 .max_no_of_hqd = 24, 549 .doorbell_size = 8, 550 .ih_ring_entry_size = 8 * sizeof(uint32_t), 551 .event_interrupt_class = &event_interrupt_class_v9, 552 .num_of_watch_points = 4, 553 .mqd_size_aligned = MQD_SIZE_ALIGNED, 554 .needs_iommu_device = false, 555 .supports_cwsr = true, 556 .needs_pci_atomics = true, 557 .num_sdma_engines = 2, 558 .num_xgmi_sdma_engines = 0, 559 .num_sdma_queues_per_engine = 8, 560 }; 561 562 static const struct kfd_device_info beige_goby_device_info = { 563 .asic_family = CHIP_BEIGE_GOBY, 564 .asic_name = "beige_goby", 565 .max_pasid_bits = 16, 566 .max_no_of_hqd = 24, 567 .doorbell_size = 8, 568 .ih_ring_entry_size = 8 * sizeof(uint32_t), 569 .event_interrupt_class = &event_interrupt_class_v9, 570 .num_of_watch_points = 4, 571 .mqd_size_aligned = MQD_SIZE_ALIGNED, 572 .needs_iommu_device = false, 573 .supports_cwsr = true, 574 .needs_pci_atomics = true, 575 .num_sdma_engines = 1, 576 .num_xgmi_sdma_engines = 0, 577 .num_sdma_queues_per_engine = 8, 578 }; 579 580 581 /* For each entry, [0] is regular and [1] is virtualisation device. */ 582 static const struct kfd_device_info *kfd_supported_devices[][2] = { 583 #ifdef KFD_SUPPORT_IOMMU_V2 584 [CHIP_KAVERI] = {&kaveri_device_info, NULL}, 585 [CHIP_CARRIZO] = {&carrizo_device_info, NULL}, 586 #endif 587 [CHIP_RAVEN] = {&raven_device_info, NULL}, 588 [CHIP_HAWAII] = {&hawaii_device_info, NULL}, 589 [CHIP_TONGA] = {&tonga_device_info, NULL}, 590 [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info}, 591 [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info}, 592 [CHIP_POLARIS11] = {&polaris11_device_info, NULL}, 593 [CHIP_POLARIS12] = {&polaris12_device_info, NULL}, 594 [CHIP_VEGAM] = {&vegam_device_info, NULL}, 595 [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info}, 596 [CHIP_VEGA12] = {&vega12_device_info, NULL}, 597 [CHIP_VEGA20] = {&vega20_device_info, NULL}, 598 [CHIP_RENOIR] = {&renoir_device_info, NULL}, 599 [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info}, 600 [CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info}, 601 [CHIP_NAVI10] = {&navi10_device_info, NULL}, 602 [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info}, 603 [CHIP_NAVI14] = {&navi14_device_info, NULL}, 604 [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info}, 605 [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info}, 606 [CHIP_VANGOGH] = {&vangogh_device_info, NULL}, 607 [CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info}, 608 [CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info}, 609 }; 610 611 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 612 unsigned int chunk_size); 613 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 614 615 static int kfd_resume(struct kfd_dev *kfd); 616 617 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 618 struct pci_dev *pdev, unsigned int asic_type, bool vf) 619 { 620 struct kfd_dev *kfd; 621 const struct kfd_device_info *device_info; 622 const struct kfd2kgd_calls *f2g; 623 624 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2) 625 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) { 626 dev_err(kfd_device, "asic_type %d out of range\n", asic_type); 627 return NULL; /* asic_type out of range */ 628 } 629 630 device_info = kfd_supported_devices[asic_type][vf]; 631 f2g = kfd2kgd_funcs[asic_type]; 632 633 if (!device_info || !f2g) { 634 dev_err(kfd_device, "%s %s not supported in kfd\n", 635 amdgpu_asic_name[asic_type], vf ? "VF" : ""); 636 return NULL; 637 } 638 639 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 640 if (!kfd) 641 return NULL; 642 643 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 644 * 32 and 64-bit requests are possible and must be 645 * supported. 646 */ 647 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd); 648 if (device_info->needs_pci_atomics && 649 !kfd->pci_atomic_requested) { 650 dev_info(kfd_device, 651 "skipped device %x:%x, PCI rejects atomics\n", 652 pdev->vendor, pdev->device); 653 kfree(kfd); 654 return NULL; 655 } 656 657 kfd->kgd = kgd; 658 kfd->device_info = device_info; 659 kfd->pdev = pdev; 660 kfd->init_complete = false; 661 kfd->kfd2kgd = f2g; 662 atomic_set(&kfd->compute_profile, 0); 663 664 mutex_init(&kfd->doorbell_mutex); 665 memset(&kfd->doorbell_available_index, 0, 666 sizeof(kfd->doorbell_available_index)); 667 668 atomic_set(&kfd->sram_ecc_flag, 0); 669 670 ida_init(&kfd->doorbell_ida); 671 672 return kfd; 673 } 674 675 static void kfd_cwsr_init(struct kfd_dev *kfd) 676 { 677 if (cwsr_enable && kfd->device_info->supports_cwsr) { 678 if (kfd->device_info->asic_family < CHIP_VEGA10) { 679 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 680 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 681 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 682 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) { 683 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 684 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 685 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 686 } else if (kfd->device_info->asic_family == CHIP_ALDEBARAN) { 687 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 688 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 689 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 690 } else if (kfd->device_info->asic_family < CHIP_NAVI10) { 691 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 692 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 693 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 694 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) { 695 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 696 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 697 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 698 } else { 699 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 700 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 701 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 702 } 703 704 kfd->cwsr_enabled = true; 705 } 706 } 707 708 static int kfd_gws_init(struct kfd_dev *kfd) 709 { 710 int ret = 0; 711 712 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 713 return 0; 714 715 if (hws_gws_support 716 || (kfd->device_info->asic_family == CHIP_VEGA10 717 && kfd->mec2_fw_version >= 0x81b3) 718 || (kfd->device_info->asic_family >= CHIP_VEGA12 719 && kfd->device_info->asic_family <= CHIP_RAVEN 720 && kfd->mec2_fw_version >= 0x1b3) 721 || (kfd->device_info->asic_family == CHIP_ARCTURUS 722 && kfd->mec2_fw_version >= 0x30) 723 || (kfd->device_info->asic_family == CHIP_ALDEBARAN 724 && kfd->mec2_fw_version >= 0x28)) 725 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd, 726 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws); 727 728 return ret; 729 } 730 731 static void kfd_smi_init(struct kfd_dev *dev) { 732 INIT_LIST_HEAD(&dev->smi_clients); 733 spin_lock_init(&dev->smi_lock); 734 } 735 736 bool kgd2kfd_device_init(struct kfd_dev *kfd, 737 struct drm_device *ddev, 738 const struct kgd2kfd_shared_resources *gpu_resources) 739 { 740 unsigned int size, map_process_packet_size; 741 742 kfd->ddev = ddev; 743 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 744 KGD_ENGINE_MEC1); 745 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 746 KGD_ENGINE_MEC2); 747 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 748 KGD_ENGINE_SDMA1); 749 kfd->shared_resources = *gpu_resources; 750 751 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 752 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 753 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 754 - kfd->vm_info.first_vmid_kfd + 1; 755 756 /* Verify module parameters regarding mapped process number*/ 757 if ((hws_max_conc_proc < 0) 758 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 759 dev_err(kfd_device, 760 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 761 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 762 kfd->vm_info.vmid_num_kfd); 763 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 764 } else 765 kfd->max_proc_per_quantum = hws_max_conc_proc; 766 767 /* calculate max size of mqds needed for queues */ 768 size = max_num_of_queues_per_device * 769 kfd->device_info->mqd_size_aligned; 770 771 /* 772 * calculate max size of runlist packet. 773 * There can be only 2 packets at once 774 */ 775 map_process_packet_size = 776 kfd->device_info->asic_family == CHIP_ALDEBARAN ? 777 sizeof(struct pm4_mes_map_process_aldebaran) : 778 sizeof(struct pm4_mes_map_process); 779 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 780 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 781 + sizeof(struct pm4_mes_runlist)) * 2; 782 783 /* Add size of HIQ & DIQ */ 784 size += KFD_KERNEL_QUEUE_SIZE * 2; 785 786 /* add another 512KB for all other allocations on gart (HPD, fences) */ 787 size += 512 * 1024; 788 789 if (amdgpu_amdkfd_alloc_gtt_mem( 790 kfd->kgd, size, &kfd->gtt_mem, 791 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 792 false)) { 793 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 794 goto alloc_gtt_mem_failure; 795 } 796 797 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 798 799 /* Initialize GTT sa with 512 byte chunk size */ 800 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 801 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 802 goto kfd_gtt_sa_init_error; 803 } 804 805 if (kfd_doorbell_init(kfd)) { 806 dev_err(kfd_device, 807 "Error initializing doorbell aperture\n"); 808 goto kfd_doorbell_error; 809 } 810 811 kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd); 812 813 kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd); 814 815 if (kfd_interrupt_init(kfd)) { 816 dev_err(kfd_device, "Error initializing interrupts\n"); 817 goto kfd_interrupt_error; 818 } 819 820 kfd->dqm = device_queue_manager_init(kfd); 821 if (!kfd->dqm) { 822 dev_err(kfd_device, "Error initializing queue manager\n"); 823 goto device_queue_manager_error; 824 } 825 826 /* If supported on this device, allocate global GWS that is shared 827 * by all KFD processes 828 */ 829 if (kfd_gws_init(kfd)) { 830 dev_err(kfd_device, "Could not allocate %d gws\n", 831 amdgpu_amdkfd_get_num_gws(kfd->kgd)); 832 goto gws_error; 833 } 834 835 /* If CRAT is broken, won't set iommu enabled */ 836 kfd_double_confirm_iommu_support(kfd); 837 838 if (kfd_iommu_device_init(kfd)) { 839 dev_err(kfd_device, "Error initializing iommuv2\n"); 840 goto device_iommu_error; 841 } 842 843 kfd_cwsr_init(kfd); 844 845 svm_migrate_init((struct amdgpu_device *)kfd->kgd); 846 847 if (kfd_resume(kfd)) 848 goto kfd_resume_error; 849 850 kfd->dbgmgr = NULL; 851 852 if (kfd_topology_add_device(kfd)) { 853 dev_err(kfd_device, "Error adding device to topology\n"); 854 goto kfd_topology_add_device_error; 855 } 856 857 kfd_smi_init(kfd); 858 859 kfd->init_complete = true; 860 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 861 kfd->pdev->device); 862 863 pr_debug("Starting kfd with the following scheduling policy %d\n", 864 kfd->dqm->sched_policy); 865 866 goto out; 867 868 kfd_topology_add_device_error: 869 kfd_resume_error: 870 device_iommu_error: 871 gws_error: 872 device_queue_manager_uninit(kfd->dqm); 873 device_queue_manager_error: 874 kfd_interrupt_exit(kfd); 875 kfd_interrupt_error: 876 kfd_doorbell_fini(kfd); 877 kfd_doorbell_error: 878 kfd_gtt_sa_fini(kfd); 879 kfd_gtt_sa_init_error: 880 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 881 alloc_gtt_mem_failure: 882 if (kfd->gws) 883 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 884 dev_err(kfd_device, 885 "device %x:%x NOT added due to errors\n", 886 kfd->pdev->vendor, kfd->pdev->device); 887 out: 888 return kfd->init_complete; 889 } 890 891 void kgd2kfd_device_exit(struct kfd_dev *kfd) 892 { 893 if (kfd->init_complete) { 894 svm_migrate_fini((struct amdgpu_device *)kfd->kgd); 895 device_queue_manager_uninit(kfd->dqm); 896 kfd_interrupt_exit(kfd); 897 kfd_topology_remove_device(kfd); 898 kfd_doorbell_fini(kfd); 899 ida_destroy(&kfd->doorbell_ida); 900 kfd_gtt_sa_fini(kfd); 901 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 902 if (kfd->gws) 903 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 904 } 905 906 kfree(kfd); 907 } 908 909 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 910 { 911 if (!kfd->init_complete) 912 return 0; 913 914 kfd_smi_event_update_gpu_reset(kfd, false); 915 916 kfd->dqm->ops.pre_reset(kfd->dqm); 917 918 kgd2kfd_suspend(kfd, false); 919 920 kfd_signal_reset_event(kfd); 921 return 0; 922 } 923 924 /* 925 * Fix me. KFD won't be able to resume existing process for now. 926 * We will keep all existing process in a evicted state and 927 * wait the process to be terminated. 928 */ 929 930 int kgd2kfd_post_reset(struct kfd_dev *kfd) 931 { 932 int ret; 933 934 if (!kfd->init_complete) 935 return 0; 936 937 ret = kfd_resume(kfd); 938 if (ret) 939 return ret; 940 atomic_dec(&kfd_locked); 941 942 atomic_set(&kfd->sram_ecc_flag, 0); 943 944 kfd_smi_event_update_gpu_reset(kfd, true); 945 946 return 0; 947 } 948 949 bool kfd_is_locked(void) 950 { 951 return (atomic_read(&kfd_locked) > 0); 952 } 953 954 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 955 { 956 if (!kfd->init_complete) 957 return; 958 959 /* for runtime suspend, skip locking kfd */ 960 if (!run_pm) { 961 /* For first KFD device suspend all the KFD processes */ 962 if (atomic_inc_return(&kfd_locked) == 1) 963 kfd_suspend_all_processes(); 964 } 965 966 kfd->dqm->ops.stop(kfd->dqm); 967 kfd_iommu_suspend(kfd); 968 } 969 970 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 971 { 972 int ret, count; 973 974 if (!kfd->init_complete) 975 return 0; 976 977 ret = kfd_resume(kfd); 978 if (ret) 979 return ret; 980 981 /* for runtime resume, skip unlocking kfd */ 982 if (!run_pm) { 983 count = atomic_dec_return(&kfd_locked); 984 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 985 if (count == 0) 986 ret = kfd_resume_all_processes(); 987 } 988 989 return ret; 990 } 991 992 static int kfd_resume(struct kfd_dev *kfd) 993 { 994 int err = 0; 995 996 err = kfd_iommu_resume(kfd); 997 if (err) { 998 dev_err(kfd_device, 999 "Failed to resume IOMMU for device %x:%x\n", 1000 kfd->pdev->vendor, kfd->pdev->device); 1001 return err; 1002 } 1003 1004 err = kfd->dqm->ops.start(kfd->dqm); 1005 if (err) { 1006 dev_err(kfd_device, 1007 "Error starting queue manager for device %x:%x\n", 1008 kfd->pdev->vendor, kfd->pdev->device); 1009 goto dqm_start_error; 1010 } 1011 1012 return err; 1013 1014 dqm_start_error: 1015 kfd_iommu_suspend(kfd); 1016 return err; 1017 } 1018 1019 static inline void kfd_queue_work(struct workqueue_struct *wq, 1020 struct work_struct *work) 1021 { 1022 int cpu, new_cpu; 1023 1024 cpu = new_cpu = smp_processor_id(); 1025 do { 1026 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1027 if (cpu_to_node(new_cpu) == numa_node_id()) 1028 break; 1029 } while (cpu != new_cpu); 1030 1031 queue_work_on(new_cpu, wq, work); 1032 } 1033 1034 /* This is called directly from KGD at ISR. */ 1035 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1036 { 1037 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 1038 bool is_patched = false; 1039 unsigned long flags; 1040 1041 if (!kfd->init_complete) 1042 return; 1043 1044 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 1045 dev_err_once(kfd_device, "Ring entry too small\n"); 1046 return; 1047 } 1048 1049 spin_lock_irqsave(&kfd->interrupt_lock, flags); 1050 1051 if (kfd->interrupts_active 1052 && interrupt_is_wanted(kfd, ih_ring_entry, 1053 patched_ihre, &is_patched) 1054 && enqueue_ih_ring_entry(kfd, 1055 is_patched ? patched_ihre : ih_ring_entry)) 1056 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 1057 1058 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 1059 } 1060 1061 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 1062 { 1063 struct kfd_process *p; 1064 int r; 1065 1066 /* Because we are called from arbitrary context (workqueue) as opposed 1067 * to process context, kfd_process could attempt to exit while we are 1068 * running so the lookup function increments the process ref count. 1069 */ 1070 p = kfd_lookup_process_by_mm(mm); 1071 if (!p) 1072 return -ESRCH; 1073 1074 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1075 r = kfd_process_evict_queues(p); 1076 1077 kfd_unref_process(p); 1078 return r; 1079 } 1080 1081 int kgd2kfd_resume_mm(struct mm_struct *mm) 1082 { 1083 struct kfd_process *p; 1084 int r; 1085 1086 /* Because we are called from arbitrary context (workqueue) as opposed 1087 * to process context, kfd_process could attempt to exit while we are 1088 * running so the lookup function increments the process ref count. 1089 */ 1090 p = kfd_lookup_process_by_mm(mm); 1091 if (!p) 1092 return -ESRCH; 1093 1094 r = kfd_process_restore_queues(p); 1095 1096 kfd_unref_process(p); 1097 return r; 1098 } 1099 1100 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1101 * prepare for safe eviction of KFD BOs that belong to the specified 1102 * process. 1103 * 1104 * @mm: mm_struct that identifies the specified KFD process 1105 * @fence: eviction fence attached to KFD process BOs 1106 * 1107 */ 1108 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1109 struct dma_fence *fence) 1110 { 1111 struct kfd_process *p; 1112 unsigned long active_time; 1113 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1114 1115 if (!fence) 1116 return -EINVAL; 1117 1118 if (dma_fence_is_signaled(fence)) 1119 return 0; 1120 1121 p = kfd_lookup_process_by_mm(mm); 1122 if (!p) 1123 return -ENODEV; 1124 1125 if (fence->seqno == p->last_eviction_seqno) 1126 goto out; 1127 1128 p->last_eviction_seqno = fence->seqno; 1129 1130 /* Avoid KFD process starvation. Wait for at least 1131 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1132 */ 1133 active_time = get_jiffies_64() - p->last_restore_timestamp; 1134 if (delay_jiffies > active_time) 1135 delay_jiffies -= active_time; 1136 else 1137 delay_jiffies = 0; 1138 1139 /* During process initialization eviction_work.dwork is initialized 1140 * to kfd_evict_bo_worker 1141 */ 1142 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1143 p->lead_thread->pid, delay_jiffies); 1144 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1145 out: 1146 kfd_unref_process(p); 1147 return 0; 1148 } 1149 1150 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1151 unsigned int chunk_size) 1152 { 1153 unsigned int num_of_longs; 1154 1155 if (WARN_ON(buf_size < chunk_size)) 1156 return -EINVAL; 1157 if (WARN_ON(buf_size == 0)) 1158 return -EINVAL; 1159 if (WARN_ON(chunk_size == 0)) 1160 return -EINVAL; 1161 1162 kfd->gtt_sa_chunk_size = chunk_size; 1163 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1164 1165 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 1166 BITS_PER_LONG; 1167 1168 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 1169 1170 if (!kfd->gtt_sa_bitmap) 1171 return -ENOMEM; 1172 1173 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1174 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1175 1176 mutex_init(&kfd->gtt_sa_lock); 1177 1178 return 0; 1179 1180 } 1181 1182 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1183 { 1184 mutex_destroy(&kfd->gtt_sa_lock); 1185 kfree(kfd->gtt_sa_bitmap); 1186 } 1187 1188 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1189 unsigned int bit_num, 1190 unsigned int chunk_size) 1191 { 1192 return start_addr + bit_num * chunk_size; 1193 } 1194 1195 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1196 unsigned int bit_num, 1197 unsigned int chunk_size) 1198 { 1199 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1200 } 1201 1202 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 1203 struct kfd_mem_obj **mem_obj) 1204 { 1205 unsigned int found, start_search, cur_size; 1206 1207 if (size == 0) 1208 return -EINVAL; 1209 1210 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1211 return -ENOMEM; 1212 1213 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1214 if (!(*mem_obj)) 1215 return -ENOMEM; 1216 1217 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1218 1219 start_search = 0; 1220 1221 mutex_lock(&kfd->gtt_sa_lock); 1222 1223 kfd_gtt_restart_search: 1224 /* Find the first chunk that is free */ 1225 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1226 kfd->gtt_sa_num_of_chunks, 1227 start_search); 1228 1229 pr_debug("Found = %d\n", found); 1230 1231 /* If there wasn't any free chunk, bail out */ 1232 if (found == kfd->gtt_sa_num_of_chunks) 1233 goto kfd_gtt_no_free_chunk; 1234 1235 /* Update fields of mem_obj */ 1236 (*mem_obj)->range_start = found; 1237 (*mem_obj)->range_end = found; 1238 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1239 kfd->gtt_start_gpu_addr, 1240 found, 1241 kfd->gtt_sa_chunk_size); 1242 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1243 kfd->gtt_start_cpu_ptr, 1244 found, 1245 kfd->gtt_sa_chunk_size); 1246 1247 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1248 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1249 1250 /* If we need only one chunk, mark it as allocated and get out */ 1251 if (size <= kfd->gtt_sa_chunk_size) { 1252 pr_debug("Single bit\n"); 1253 set_bit(found, kfd->gtt_sa_bitmap); 1254 goto kfd_gtt_out; 1255 } 1256 1257 /* Otherwise, try to see if we have enough contiguous chunks */ 1258 cur_size = size - kfd->gtt_sa_chunk_size; 1259 do { 1260 (*mem_obj)->range_end = 1261 find_next_zero_bit(kfd->gtt_sa_bitmap, 1262 kfd->gtt_sa_num_of_chunks, ++found); 1263 /* 1264 * If next free chunk is not contiguous than we need to 1265 * restart our search from the last free chunk we found (which 1266 * wasn't contiguous to the previous ones 1267 */ 1268 if ((*mem_obj)->range_end != found) { 1269 start_search = found; 1270 goto kfd_gtt_restart_search; 1271 } 1272 1273 /* 1274 * If we reached end of buffer, bail out with error 1275 */ 1276 if (found == kfd->gtt_sa_num_of_chunks) 1277 goto kfd_gtt_no_free_chunk; 1278 1279 /* Check if we don't need another chunk */ 1280 if (cur_size <= kfd->gtt_sa_chunk_size) 1281 cur_size = 0; 1282 else 1283 cur_size -= kfd->gtt_sa_chunk_size; 1284 1285 } while (cur_size > 0); 1286 1287 pr_debug("range_start = %d, range_end = %d\n", 1288 (*mem_obj)->range_start, (*mem_obj)->range_end); 1289 1290 /* Mark the chunks as allocated */ 1291 for (found = (*mem_obj)->range_start; 1292 found <= (*mem_obj)->range_end; 1293 found++) 1294 set_bit(found, kfd->gtt_sa_bitmap); 1295 1296 kfd_gtt_out: 1297 mutex_unlock(&kfd->gtt_sa_lock); 1298 return 0; 1299 1300 kfd_gtt_no_free_chunk: 1301 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1302 mutex_unlock(&kfd->gtt_sa_lock); 1303 kfree(*mem_obj); 1304 return -ENOMEM; 1305 } 1306 1307 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1308 { 1309 unsigned int bit; 1310 1311 /* Act like kfree when trying to free a NULL object */ 1312 if (!mem_obj) 1313 return 0; 1314 1315 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1316 mem_obj, mem_obj->range_start, mem_obj->range_end); 1317 1318 mutex_lock(&kfd->gtt_sa_lock); 1319 1320 /* Mark the chunks as free */ 1321 for (bit = mem_obj->range_start; 1322 bit <= mem_obj->range_end; 1323 bit++) 1324 clear_bit(bit, kfd->gtt_sa_bitmap); 1325 1326 mutex_unlock(&kfd->gtt_sa_lock); 1327 1328 kfree(mem_obj); 1329 return 0; 1330 } 1331 1332 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1333 { 1334 if (kfd) 1335 atomic_inc(&kfd->sram_ecc_flag); 1336 } 1337 1338 void kfd_inc_compute_active(struct kfd_dev *kfd) 1339 { 1340 if (atomic_inc_return(&kfd->compute_profile) == 1) 1341 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1342 } 1343 1344 void kfd_dec_compute_active(struct kfd_dev *kfd) 1345 { 1346 int count = atomic_dec_return(&kfd->compute_profile); 1347 1348 if (count == 0) 1349 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1350 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1351 } 1352 1353 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask) 1354 { 1355 if (kfd && kfd->init_complete) 1356 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1357 } 1358 1359 #if defined(CONFIG_DEBUG_FS) 1360 1361 /* This function will send a package to HIQ to hang the HWS 1362 * which will trigger a GPU reset and bring the HWS back to normal state 1363 */ 1364 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1365 { 1366 int r = 0; 1367 1368 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1369 pr_err("HWS is not enabled"); 1370 return -EINVAL; 1371 } 1372 1373 r = pm_debugfs_hang_hws(&dev->dqm->packets); 1374 if (!r) 1375 r = dqm_debugfs_execute_queues(dev->dqm); 1376 1377 return r; 1378 } 1379 1380 #endif 1381