1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(4, 4, 5): 88 case IP_VERSION(5, 0, 0):/* NAVI10 */ 89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 90 case IP_VERSION(5, 0, 2):/* NAVI14 */ 91 case IP_VERSION(5, 0, 5):/* NAVI12 */ 92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 96 case IP_VERSION(6, 0, 0): 97 case IP_VERSION(6, 0, 1): 98 case IP_VERSION(6, 0, 2): 99 case IP_VERSION(6, 0, 3): 100 case IP_VERSION(6, 1, 0): 101 case IP_VERSION(6, 1, 1): 102 case IP_VERSION(6, 1, 2): 103 case IP_VERSION(7, 0, 0): 104 case IP_VERSION(7, 0, 1): 105 kfd->device_info.num_sdma_queues_per_engine = 8; 106 break; 107 default: 108 dev_warn(kfd_device, 109 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 110 sdma_version); 111 kfd->device_info.num_sdma_queues_per_engine = 8; 112 } 113 114 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 115 116 switch (sdma_version) { 117 case IP_VERSION(6, 0, 0): 118 case IP_VERSION(6, 0, 1): 119 case IP_VERSION(6, 0, 2): 120 case IP_VERSION(6, 0, 3): 121 case IP_VERSION(6, 1, 0): 122 case IP_VERSION(6, 1, 1): 123 case IP_VERSION(6, 1, 2): 124 case IP_VERSION(7, 0, 0): 125 case IP_VERSION(7, 0, 1): 126 /* Reserve 1 for paging and 1 for gfx */ 127 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 128 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 129 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 130 kfd->adev->sdma.num_instances * 131 kfd->device_info.num_reserved_sdma_queues_per_engine); 132 break; 133 default: 134 break; 135 } 136 } 137 138 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 139 { 140 uint32_t gc_version = KFD_GC_VERSION(kfd); 141 142 switch (gc_version) { 143 case IP_VERSION(9, 0, 1): /* VEGA10 */ 144 case IP_VERSION(9, 1, 0): /* RAVEN */ 145 case IP_VERSION(9, 2, 1): /* VEGA12 */ 146 case IP_VERSION(9, 2, 2): /* RAVEN */ 147 case IP_VERSION(9, 3, 0): /* RENOIR */ 148 case IP_VERSION(9, 4, 0): /* VEGA20 */ 149 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 150 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 151 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 152 break; 153 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 154 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 155 kfd->device_info.event_interrupt_class = 156 &event_interrupt_class_v9_4_3; 157 break; 158 case IP_VERSION(10, 3, 1): /* VANGOGH */ 159 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 160 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 161 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 162 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 163 case IP_VERSION(10, 1, 4): 164 case IP_VERSION(10, 1, 10): /* NAVI10 */ 165 case IP_VERSION(10, 1, 2): /* NAVI12 */ 166 case IP_VERSION(10, 1, 1): /* NAVI14 */ 167 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 168 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 169 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 170 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 171 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 172 break; 173 case IP_VERSION(11, 0, 0): 174 case IP_VERSION(11, 0, 1): 175 case IP_VERSION(11, 0, 2): 176 case IP_VERSION(11, 0, 3): 177 case IP_VERSION(11, 0, 4): 178 case IP_VERSION(11, 5, 0): 179 case IP_VERSION(11, 5, 1): 180 case IP_VERSION(11, 5, 2): 181 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 182 break; 183 case IP_VERSION(12, 0, 0): 184 case IP_VERSION(12, 0, 1): 185 /* GFX12_TODO: Change to v12 version. */ 186 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 187 break; 188 default: 189 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 190 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 191 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 192 } 193 } 194 195 static void kfd_device_info_init(struct kfd_dev *kfd, 196 bool vf, uint32_t gfx_target_version) 197 { 198 uint32_t gc_version = KFD_GC_VERSION(kfd); 199 uint32_t asic_type = kfd->adev->asic_type; 200 201 kfd->device_info.max_pasid_bits = 16; 202 kfd->device_info.max_no_of_hqd = 24; 203 kfd->device_info.num_of_watch_points = 4; 204 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 205 kfd->device_info.gfx_target_version = gfx_target_version; 206 207 if (KFD_IS_SOC15(kfd)) { 208 kfd->device_info.doorbell_size = 8; 209 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 210 kfd->device_info.supports_cwsr = true; 211 212 kfd_device_info_set_sdma_info(kfd); 213 214 kfd_device_info_set_event_interrupt_class(kfd); 215 216 if (gc_version < IP_VERSION(11, 0, 0)) { 217 /* Navi2x+, Navi1x+ */ 218 if (gc_version == IP_VERSION(10, 3, 6)) 219 kfd->device_info.no_atomic_fw_version = 14; 220 else if (gc_version == IP_VERSION(10, 3, 7)) 221 kfd->device_info.no_atomic_fw_version = 3; 222 else if (gc_version >= IP_VERSION(10, 3, 0)) 223 kfd->device_info.no_atomic_fw_version = 92; 224 else if (gc_version >= IP_VERSION(10, 1, 1)) 225 kfd->device_info.no_atomic_fw_version = 145; 226 227 /* Navi1x+ */ 228 if (gc_version >= IP_VERSION(10, 1, 1)) 229 kfd->device_info.needs_pci_atomics = true; 230 } else if (gc_version < IP_VERSION(12, 0, 0)) { 231 /* 232 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 233 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 234 * PCIe atomics support. 235 */ 236 kfd->device_info.needs_pci_atomics = true; 237 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 238 } else { 239 kfd->device_info.needs_pci_atomics = true; 240 } 241 } else { 242 kfd->device_info.doorbell_size = 4; 243 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 244 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 245 kfd->device_info.num_sdma_queues_per_engine = 2; 246 247 if (asic_type != CHIP_KAVERI && 248 asic_type != CHIP_HAWAII && 249 asic_type != CHIP_TONGA) 250 kfd->device_info.supports_cwsr = true; 251 252 if (asic_type != CHIP_HAWAII && !vf) 253 kfd->device_info.needs_pci_atomics = true; 254 } 255 } 256 257 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 258 { 259 struct kfd_dev *kfd = NULL; 260 const struct kfd2kgd_calls *f2g = NULL; 261 uint32_t gfx_target_version = 0; 262 263 switch (adev->asic_type) { 264 #ifdef CONFIG_DRM_AMDGPU_CIK 265 case CHIP_KAVERI: 266 gfx_target_version = 70000; 267 if (!vf) 268 f2g = &gfx_v7_kfd2kgd; 269 break; 270 #endif 271 case CHIP_CARRIZO: 272 gfx_target_version = 80001; 273 if (!vf) 274 f2g = &gfx_v8_kfd2kgd; 275 break; 276 #ifdef CONFIG_DRM_AMDGPU_CIK 277 case CHIP_HAWAII: 278 gfx_target_version = 70001; 279 if (!amdgpu_exp_hw_support) 280 pr_info( 281 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 282 ); 283 else if (!vf) 284 f2g = &gfx_v7_kfd2kgd; 285 break; 286 #endif 287 case CHIP_TONGA: 288 gfx_target_version = 80002; 289 if (!vf) 290 f2g = &gfx_v8_kfd2kgd; 291 break; 292 case CHIP_FIJI: 293 case CHIP_POLARIS10: 294 gfx_target_version = 80003; 295 f2g = &gfx_v8_kfd2kgd; 296 break; 297 case CHIP_POLARIS11: 298 case CHIP_POLARIS12: 299 case CHIP_VEGAM: 300 gfx_target_version = 80003; 301 if (!vf) 302 f2g = &gfx_v8_kfd2kgd; 303 break; 304 default: 305 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 306 /* Vega 10 */ 307 case IP_VERSION(9, 0, 1): 308 gfx_target_version = 90000; 309 f2g = &gfx_v9_kfd2kgd; 310 break; 311 /* Raven */ 312 case IP_VERSION(9, 1, 0): 313 case IP_VERSION(9, 2, 2): 314 gfx_target_version = 90002; 315 if (!vf) 316 f2g = &gfx_v9_kfd2kgd; 317 break; 318 /* Vega12 */ 319 case IP_VERSION(9, 2, 1): 320 gfx_target_version = 90004; 321 if (!vf) 322 f2g = &gfx_v9_kfd2kgd; 323 break; 324 /* Renoir */ 325 case IP_VERSION(9, 3, 0): 326 gfx_target_version = 90012; 327 if (!vf) 328 f2g = &gfx_v9_kfd2kgd; 329 break; 330 /* Vega20 */ 331 case IP_VERSION(9, 4, 0): 332 gfx_target_version = 90006; 333 if (!vf) 334 f2g = &gfx_v9_kfd2kgd; 335 break; 336 /* Arcturus */ 337 case IP_VERSION(9, 4, 1): 338 gfx_target_version = 90008; 339 f2g = &arcturus_kfd2kgd; 340 break; 341 /* Aldebaran */ 342 case IP_VERSION(9, 4, 2): 343 gfx_target_version = 90010; 344 f2g = &aldebaran_kfd2kgd; 345 break; 346 case IP_VERSION(9, 4, 3): 347 gfx_target_version = adev->rev_id >= 1 ? 90402 348 : adev->flags & AMD_IS_APU ? 90400 349 : 90401; 350 f2g = &gc_9_4_3_kfd2kgd; 351 break; 352 case IP_VERSION(9, 4, 4): 353 gfx_target_version = 90402; 354 f2g = &gc_9_4_3_kfd2kgd; 355 break; 356 /* Navi10 */ 357 case IP_VERSION(10, 1, 10): 358 gfx_target_version = 100100; 359 if (!vf) 360 f2g = &gfx_v10_kfd2kgd; 361 break; 362 /* Navi12 */ 363 case IP_VERSION(10, 1, 2): 364 gfx_target_version = 100101; 365 f2g = &gfx_v10_kfd2kgd; 366 break; 367 /* Navi14 */ 368 case IP_VERSION(10, 1, 1): 369 gfx_target_version = 100102; 370 if (!vf) 371 f2g = &gfx_v10_kfd2kgd; 372 break; 373 /* Cyan Skillfish */ 374 case IP_VERSION(10, 1, 3): 375 case IP_VERSION(10, 1, 4): 376 gfx_target_version = 100103; 377 if (!vf) 378 f2g = &gfx_v10_kfd2kgd; 379 break; 380 /* Sienna Cichlid */ 381 case IP_VERSION(10, 3, 0): 382 gfx_target_version = 100300; 383 f2g = &gfx_v10_3_kfd2kgd; 384 break; 385 /* Navy Flounder */ 386 case IP_VERSION(10, 3, 2): 387 gfx_target_version = 100301; 388 f2g = &gfx_v10_3_kfd2kgd; 389 break; 390 /* Van Gogh */ 391 case IP_VERSION(10, 3, 1): 392 gfx_target_version = 100303; 393 if (!vf) 394 f2g = &gfx_v10_3_kfd2kgd; 395 break; 396 /* Dimgrey Cavefish */ 397 case IP_VERSION(10, 3, 4): 398 gfx_target_version = 100302; 399 f2g = &gfx_v10_3_kfd2kgd; 400 break; 401 /* Beige Goby */ 402 case IP_VERSION(10, 3, 5): 403 gfx_target_version = 100304; 404 f2g = &gfx_v10_3_kfd2kgd; 405 break; 406 /* Yellow Carp */ 407 case IP_VERSION(10, 3, 3): 408 gfx_target_version = 100305; 409 if (!vf) 410 f2g = &gfx_v10_3_kfd2kgd; 411 break; 412 case IP_VERSION(10, 3, 6): 413 case IP_VERSION(10, 3, 7): 414 gfx_target_version = 100306; 415 if (!vf) 416 f2g = &gfx_v10_3_kfd2kgd; 417 break; 418 case IP_VERSION(11, 0, 0): 419 gfx_target_version = 110000; 420 f2g = &gfx_v11_kfd2kgd; 421 break; 422 case IP_VERSION(11, 0, 1): 423 case IP_VERSION(11, 0, 4): 424 gfx_target_version = 110003; 425 f2g = &gfx_v11_kfd2kgd; 426 break; 427 case IP_VERSION(11, 0, 2): 428 gfx_target_version = 110002; 429 f2g = &gfx_v11_kfd2kgd; 430 break; 431 case IP_VERSION(11, 0, 3): 432 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 433 gfx_target_version = 110001; 434 f2g = &gfx_v11_kfd2kgd; 435 break; 436 case IP_VERSION(11, 5, 0): 437 gfx_target_version = 110500; 438 f2g = &gfx_v11_kfd2kgd; 439 break; 440 case IP_VERSION(11, 5, 1): 441 gfx_target_version = 110501; 442 f2g = &gfx_v11_kfd2kgd; 443 break; 444 case IP_VERSION(11, 5, 2): 445 gfx_target_version = 110502; 446 f2g = &gfx_v11_kfd2kgd; 447 break; 448 case IP_VERSION(12, 0, 0): 449 gfx_target_version = 120000; 450 f2g = &gfx_v12_kfd2kgd; 451 break; 452 case IP_VERSION(12, 0, 1): 453 gfx_target_version = 120001; 454 f2g = &gfx_v12_kfd2kgd; 455 break; 456 default: 457 break; 458 } 459 break; 460 } 461 462 if (!f2g) { 463 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 464 dev_info(kfd_device, 465 "GC IP %06x %s not supported in kfd\n", 466 amdgpu_ip_version(adev, GC_HWIP, 0), 467 vf ? "VF" : ""); 468 else 469 dev_info(kfd_device, "%s %s not supported in kfd\n", 470 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 471 return NULL; 472 } 473 474 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 475 if (!kfd) 476 return NULL; 477 478 kfd->adev = adev; 479 kfd_device_info_init(kfd, vf, gfx_target_version); 480 kfd->init_complete = false; 481 kfd->kfd2kgd = f2g; 482 atomic_set(&kfd->compute_profile, 0); 483 484 mutex_init(&kfd->doorbell_mutex); 485 486 ida_init(&kfd->doorbell_ida); 487 488 return kfd; 489 } 490 491 static void kfd_cwsr_init(struct kfd_dev *kfd) 492 { 493 if (cwsr_enable && kfd->device_info.supports_cwsr) { 494 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 495 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 496 > KFD_CWSR_TMA_OFFSET); 497 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 498 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 499 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 500 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 501 > KFD_CWSR_TMA_OFFSET); 502 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 503 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 504 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 505 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 506 > KFD_CWSR_TMA_OFFSET); 507 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 508 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 509 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 510 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 511 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 512 > KFD_CWSR_TMA_OFFSET); 513 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 514 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 515 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 516 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 517 > KFD_CWSR_TMA_OFFSET); 518 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 519 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 520 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 521 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 522 > KFD_CWSR_TMA_OFFSET); 523 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 524 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 525 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 526 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 527 > KFD_CWSR_TMA_OFFSET); 528 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 529 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 530 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 531 /* The gfx11 cwsr trap handler must fit inside a single 532 page. */ 533 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 534 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 535 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 536 } else { 537 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 538 > KFD_CWSR_TMA_OFFSET); 539 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 540 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 541 } 542 543 kfd->cwsr_enabled = true; 544 } 545 } 546 547 static int kfd_gws_init(struct kfd_node *node) 548 { 549 int ret = 0; 550 struct kfd_dev *kfd = node->kfd; 551 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 552 553 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 554 return 0; 555 556 if (hws_gws_support || (KFD_IS_SOC15(node) && 557 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 558 && kfd->mec2_fw_version >= 0x81b3) || 559 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 560 && kfd->mec2_fw_version >= 0x1b3) || 561 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 562 && kfd->mec2_fw_version >= 0x30) || 563 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 564 && kfd->mec2_fw_version >= 0x28) || 565 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 566 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 567 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 568 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 569 && kfd->mec2_fw_version >= 0x6b) || 570 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 571 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 572 && mes_rev >= 68)))) 573 ret = amdgpu_amdkfd_alloc_gws(node->adev, 574 node->adev->gds.gws_size, &node->gws); 575 576 return ret; 577 } 578 579 static void kfd_smi_init(struct kfd_node *dev) 580 { 581 INIT_LIST_HEAD(&dev->smi_clients); 582 spin_lock_init(&dev->smi_lock); 583 } 584 585 static int kfd_init_node(struct kfd_node *node) 586 { 587 int err = -1; 588 589 if (kfd_interrupt_init(node)) { 590 dev_err(kfd_device, "Error initializing interrupts\n"); 591 goto kfd_interrupt_error; 592 } 593 594 node->dqm = device_queue_manager_init(node); 595 if (!node->dqm) { 596 dev_err(kfd_device, "Error initializing queue manager\n"); 597 goto device_queue_manager_error; 598 } 599 600 if (kfd_gws_init(node)) { 601 dev_err(kfd_device, "Could not allocate %d gws\n", 602 node->adev->gds.gws_size); 603 goto gws_error; 604 } 605 606 if (kfd_resume(node)) 607 goto kfd_resume_error; 608 609 if (kfd_topology_add_device(node)) { 610 dev_err(kfd_device, "Error adding device to topology\n"); 611 goto kfd_topology_add_device_error; 612 } 613 614 kfd_smi_init(node); 615 616 return 0; 617 618 kfd_topology_add_device_error: 619 kfd_resume_error: 620 gws_error: 621 device_queue_manager_uninit(node->dqm); 622 device_queue_manager_error: 623 kfd_interrupt_exit(node); 624 kfd_interrupt_error: 625 if (node->gws) 626 amdgpu_amdkfd_free_gws(node->adev, node->gws); 627 628 /* Cleanup the node memory here */ 629 kfree(node); 630 return err; 631 } 632 633 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 634 { 635 struct kfd_node *knode; 636 unsigned int i; 637 638 for (i = 0; i < num_nodes; i++) { 639 knode = kfd->nodes[i]; 640 device_queue_manager_uninit(knode->dqm); 641 kfd_interrupt_exit(knode); 642 kfd_topology_remove_device(knode); 643 if (knode->gws) 644 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 645 kfree(knode); 646 kfd->nodes[i] = NULL; 647 } 648 } 649 650 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 651 unsigned int kfd_node_idx) 652 { 653 struct amdgpu_device *adev = node->adev; 654 uint32_t xcc_mask = node->xcc_mask; 655 uint32_t xcc, mapped_xcc; 656 /* 657 * Interrupt bitmap is setup for processing interrupts from 658 * different XCDs and AIDs. 659 * Interrupt bitmap is defined as follows: 660 * 1. Bits 0-15 - correspond to the NodeId field. 661 * Each bit corresponds to NodeId number. For example, if 662 * a KFD node has interrupt bitmap set to 0x7, then this 663 * KFD node will process interrupts with NodeId = 0, 1 and 2 664 * in the IH cookie. 665 * 2. Bits 16-31 - unused. 666 * 667 * Please note that the kfd_node_idx argument passed to this 668 * function is not related to NodeId field received in the 669 * IH cookie. 670 * 671 * In CPX mode, a KFD node will process an interrupt if: 672 * - the Node Id matches the corresponding bit set in 673 * Bits 0-15. 674 * - AND VMID reported in the interrupt lies within the 675 * VMID range of the node. 676 */ 677 for_each_inst(xcc, xcc_mask) { 678 mapped_xcc = GET_INST(GC, xcc); 679 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 680 } 681 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 682 node->interrupt_bitmap); 683 } 684 685 bool kgd2kfd_device_init(struct kfd_dev *kfd, 686 const struct kgd2kfd_shared_resources *gpu_resources) 687 { 688 unsigned int size, map_process_packet_size, i; 689 struct kfd_node *node; 690 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 691 unsigned int max_proc_per_quantum; 692 int partition_mode; 693 int xcp_idx; 694 695 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 696 KGD_ENGINE_MEC1); 697 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 698 KGD_ENGINE_MEC2); 699 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 700 KGD_ENGINE_SDMA1); 701 kfd->shared_resources = *gpu_resources; 702 703 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 704 705 if (kfd->num_nodes == 0) { 706 dev_err(kfd_device, 707 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 708 kfd->adev->gfx.num_xcc_per_xcp); 709 goto out; 710 } 711 712 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 713 * 32 and 64-bit requests are possible and must be 714 * supported. 715 */ 716 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 717 if (!kfd->pci_atomic_requested && 718 kfd->device_info.needs_pci_atomics && 719 (!kfd->device_info.no_atomic_fw_version || 720 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 721 dev_info(kfd_device, 722 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 723 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 724 kfd->mec_fw_version, 725 kfd->device_info.no_atomic_fw_version); 726 return false; 727 } 728 729 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 730 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 731 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 732 733 /* For GFX9.4.3, we need special handling for VMIDs depending on 734 * partition mode. 735 * In CPX mode, the VMID range needs to be shared between XCDs. 736 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 737 * divide them equally, we change starting VMID to 4 and not use 738 * VMID 3. 739 * If the VMID range changes for GFX9.4.3, then this code MUST be 740 * revisited. 741 */ 742 if (kfd->adev->xcp_mgr) { 743 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 744 AMDGPU_XCP_FL_LOCKED); 745 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 746 kfd->num_nodes != 1) { 747 vmid_num_kfd /= 2; 748 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 749 } 750 } 751 752 /* Verify module parameters regarding mapped process number*/ 753 if (hws_max_conc_proc >= 0) 754 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 755 else 756 max_proc_per_quantum = vmid_num_kfd; 757 758 /* calculate max size of mqds needed for queues */ 759 size = max_num_of_queues_per_device * 760 kfd->device_info.mqd_size_aligned; 761 762 /* 763 * calculate max size of runlist packet. 764 * There can be only 2 packets at once 765 */ 766 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 767 sizeof(struct pm4_mes_map_process_aldebaran) : 768 sizeof(struct pm4_mes_map_process); 769 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 770 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 771 + sizeof(struct pm4_mes_runlist)) * 2; 772 773 /* Add size of HIQ & DIQ */ 774 size += KFD_KERNEL_QUEUE_SIZE * 2; 775 776 /* add another 512KB for all other allocations on gart (HPD, fences) */ 777 size += 512 * 1024; 778 779 if (amdgpu_amdkfd_alloc_gtt_mem( 780 kfd->adev, size, &kfd->gtt_mem, 781 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 782 false)) { 783 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 784 goto alloc_gtt_mem_failure; 785 } 786 787 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 788 789 /* Initialize GTT sa with 512 byte chunk size */ 790 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 791 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 792 goto kfd_gtt_sa_init_error; 793 } 794 795 if (kfd_doorbell_init(kfd)) { 796 dev_err(kfd_device, 797 "Error initializing doorbell aperture\n"); 798 goto kfd_doorbell_error; 799 } 800 801 if (amdgpu_use_xgmi_p2p) 802 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 803 804 /* 805 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 806 * xGMI connected in the topology so assign a unique hive id per 807 * device based on the pci device location if device is in PCIe mode. 808 */ 809 if (!kfd->hive_id && 810 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 811 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) && 812 kfd->num_nodes > 1) 813 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 814 815 kfd->noretry = kfd->adev->gmc.noretry; 816 817 kfd_cwsr_init(kfd); 818 819 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 820 kfd->num_nodes); 821 822 /* Allocate the KFD nodes */ 823 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 824 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 825 if (!node) 826 goto node_alloc_error; 827 828 node->node_id = i; 829 node->adev = kfd->adev; 830 node->kfd = kfd; 831 node->kfd2kgd = kfd->kfd2kgd; 832 node->vm_info.vmid_num_kfd = vmid_num_kfd; 833 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 834 /* TODO : Check if error handling is needed */ 835 if (node->xcp) { 836 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 837 &node->xcc_mask); 838 ++xcp_idx; 839 } else { 840 node->xcc_mask = 841 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 842 } 843 844 if (node->xcp) { 845 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 846 node->node_id, node->xcp->mem_id, 847 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 848 } 849 850 if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 851 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) && 852 partition_mode == AMDGPU_CPX_PARTITION_MODE && 853 kfd->num_nodes != 1) { 854 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 855 * 4-9 and second XCD gets VMID range 10-15. 856 */ 857 858 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 859 first_vmid_kfd : 860 first_vmid_kfd+vmid_num_kfd; 861 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 862 last_vmid_kfd-vmid_num_kfd : 863 last_vmid_kfd; 864 node->compute_vmid_bitmap = 865 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 866 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 867 } else { 868 node->vm_info.first_vmid_kfd = first_vmid_kfd; 869 node->vm_info.last_vmid_kfd = last_vmid_kfd; 870 node->compute_vmid_bitmap = 871 gpu_resources->compute_vmid_bitmap; 872 } 873 node->max_proc_per_quantum = max_proc_per_quantum; 874 atomic_set(&node->sram_ecc_flag, 0); 875 876 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 877 &node->local_mem_info, node->xcp); 878 879 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 880 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) 881 kfd_setup_interrupt_bitmap(node, i); 882 883 /* Initialize the KFD node */ 884 if (kfd_init_node(node)) { 885 dev_err(kfd_device, "Error initializing KFD node\n"); 886 goto node_init_error; 887 } 888 889 spin_lock_init(&node->watch_points_lock); 890 891 kfd->nodes[i] = node; 892 } 893 894 svm_range_set_max_pages(kfd->adev); 895 896 kfd->init_complete = true; 897 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 898 kfd->adev->pdev->device); 899 900 pr_debug("Starting kfd with the following scheduling policy %d\n", 901 node->dqm->sched_policy); 902 903 goto out; 904 905 node_init_error: 906 node_alloc_error: 907 kfd_cleanup_nodes(kfd, i); 908 kfd_doorbell_fini(kfd); 909 kfd_doorbell_error: 910 kfd_gtt_sa_fini(kfd); 911 kfd_gtt_sa_init_error: 912 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 913 alloc_gtt_mem_failure: 914 dev_err(kfd_device, 915 "device %x:%x NOT added due to errors\n", 916 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 917 out: 918 return kfd->init_complete; 919 } 920 921 void kgd2kfd_device_exit(struct kfd_dev *kfd) 922 { 923 if (kfd->init_complete) { 924 /* Cleanup KFD nodes */ 925 kfd_cleanup_nodes(kfd, kfd->num_nodes); 926 /* Cleanup common/shared resources */ 927 kfd_doorbell_fini(kfd); 928 ida_destroy(&kfd->doorbell_ida); 929 kfd_gtt_sa_fini(kfd); 930 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 931 } 932 933 kfree(kfd); 934 } 935 936 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 937 struct amdgpu_reset_context *reset_context) 938 { 939 struct kfd_node *node; 940 int i; 941 942 if (!kfd->init_complete) 943 return 0; 944 945 for (i = 0; i < kfd->num_nodes; i++) { 946 node = kfd->nodes[i]; 947 kfd_smi_event_update_gpu_reset(node, false, reset_context); 948 } 949 950 kgd2kfd_suspend(kfd, false); 951 952 for (i = 0; i < kfd->num_nodes; i++) 953 kfd_signal_reset_event(kfd->nodes[i]); 954 955 return 0; 956 } 957 958 /* 959 * Fix me. KFD won't be able to resume existing process for now. 960 * We will keep all existing process in a evicted state and 961 * wait the process to be terminated. 962 */ 963 964 int kgd2kfd_post_reset(struct kfd_dev *kfd) 965 { 966 int ret; 967 struct kfd_node *node; 968 int i; 969 970 if (!kfd->init_complete) 971 return 0; 972 973 for (i = 0; i < kfd->num_nodes; i++) { 974 ret = kfd_resume(kfd->nodes[i]); 975 if (ret) 976 return ret; 977 } 978 979 mutex_lock(&kfd_processes_mutex); 980 --kfd_locked; 981 mutex_unlock(&kfd_processes_mutex); 982 983 for (i = 0; i < kfd->num_nodes; i++) { 984 node = kfd->nodes[i]; 985 atomic_set(&node->sram_ecc_flag, 0); 986 kfd_smi_event_update_gpu_reset(node, true, NULL); 987 } 988 989 return 0; 990 } 991 992 bool kfd_is_locked(void) 993 { 994 lockdep_assert_held(&kfd_processes_mutex); 995 return (kfd_locked > 0); 996 } 997 998 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 999 { 1000 struct kfd_node *node; 1001 int i; 1002 1003 if (!kfd->init_complete) 1004 return; 1005 1006 /* for runtime suspend, skip locking kfd */ 1007 if (!run_pm) { 1008 mutex_lock(&kfd_processes_mutex); 1009 /* For first KFD device suspend all the KFD processes */ 1010 if (++kfd_locked == 1) 1011 kfd_suspend_all_processes(); 1012 mutex_unlock(&kfd_processes_mutex); 1013 } 1014 1015 for (i = 0; i < kfd->num_nodes; i++) { 1016 node = kfd->nodes[i]; 1017 node->dqm->ops.stop(node->dqm); 1018 } 1019 } 1020 1021 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1022 { 1023 int ret, i; 1024 1025 if (!kfd->init_complete) 1026 return 0; 1027 1028 for (i = 0; i < kfd->num_nodes; i++) { 1029 ret = kfd_resume(kfd->nodes[i]); 1030 if (ret) 1031 return ret; 1032 } 1033 1034 /* for runtime resume, skip unlocking kfd */ 1035 if (!run_pm) { 1036 mutex_lock(&kfd_processes_mutex); 1037 if (--kfd_locked == 0) 1038 ret = kfd_resume_all_processes(); 1039 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1040 mutex_unlock(&kfd_processes_mutex); 1041 } 1042 1043 return ret; 1044 } 1045 1046 static int kfd_resume(struct kfd_node *node) 1047 { 1048 int err = 0; 1049 1050 err = node->dqm->ops.start(node->dqm); 1051 if (err) 1052 dev_err(kfd_device, 1053 "Error starting queue manager for device %x:%x\n", 1054 node->adev->pdev->vendor, node->adev->pdev->device); 1055 1056 return err; 1057 } 1058 1059 static inline void kfd_queue_work(struct workqueue_struct *wq, 1060 struct work_struct *work) 1061 { 1062 int cpu, new_cpu; 1063 1064 cpu = new_cpu = smp_processor_id(); 1065 do { 1066 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1067 if (cpu_to_node(new_cpu) == numa_node_id()) 1068 break; 1069 } while (cpu != new_cpu); 1070 1071 queue_work_on(new_cpu, wq, work); 1072 } 1073 1074 /* This is called directly from KGD at ISR. */ 1075 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1076 { 1077 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1078 bool is_patched = false; 1079 unsigned long flags; 1080 struct kfd_node *node; 1081 1082 if (!kfd->init_complete) 1083 return; 1084 1085 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1086 dev_err_once(kfd_device, "Ring entry too small\n"); 1087 return; 1088 } 1089 1090 for (i = 0; i < kfd->num_nodes; i++) { 1091 node = kfd->nodes[i]; 1092 spin_lock_irqsave(&node->interrupt_lock, flags); 1093 1094 if (node->interrupts_active 1095 && interrupt_is_wanted(node, ih_ring_entry, 1096 patched_ihre, &is_patched) 1097 && enqueue_ih_ring_entry(node, 1098 is_patched ? patched_ihre : ih_ring_entry)) { 1099 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1100 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1101 return; 1102 } 1103 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1104 } 1105 1106 } 1107 1108 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1109 { 1110 struct kfd_process *p; 1111 int r; 1112 1113 /* Because we are called from arbitrary context (workqueue) as opposed 1114 * to process context, kfd_process could attempt to exit while we are 1115 * running so the lookup function increments the process ref count. 1116 */ 1117 p = kfd_lookup_process_by_mm(mm); 1118 if (!p) 1119 return -ESRCH; 1120 1121 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1122 r = kfd_process_evict_queues(p, trigger); 1123 1124 kfd_unref_process(p); 1125 return r; 1126 } 1127 1128 int kgd2kfd_resume_mm(struct mm_struct *mm) 1129 { 1130 struct kfd_process *p; 1131 int r; 1132 1133 /* Because we are called from arbitrary context (workqueue) as opposed 1134 * to process context, kfd_process could attempt to exit while we are 1135 * running so the lookup function increments the process ref count. 1136 */ 1137 p = kfd_lookup_process_by_mm(mm); 1138 if (!p) 1139 return -ESRCH; 1140 1141 r = kfd_process_restore_queues(p); 1142 1143 kfd_unref_process(p); 1144 return r; 1145 } 1146 1147 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1148 * prepare for safe eviction of KFD BOs that belong to the specified 1149 * process. 1150 * 1151 * @mm: mm_struct that identifies the specified KFD process 1152 * @fence: eviction fence attached to KFD process BOs 1153 * 1154 */ 1155 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1156 struct dma_fence *fence) 1157 { 1158 struct kfd_process *p; 1159 unsigned long active_time; 1160 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1161 1162 if (!fence) 1163 return -EINVAL; 1164 1165 if (dma_fence_is_signaled(fence)) 1166 return 0; 1167 1168 p = kfd_lookup_process_by_mm(mm); 1169 if (!p) 1170 return -ENODEV; 1171 1172 if (fence->seqno == p->last_eviction_seqno) 1173 goto out; 1174 1175 p->last_eviction_seqno = fence->seqno; 1176 1177 /* Avoid KFD process starvation. Wait for at least 1178 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1179 */ 1180 active_time = get_jiffies_64() - p->last_restore_timestamp; 1181 if (delay_jiffies > active_time) 1182 delay_jiffies -= active_time; 1183 else 1184 delay_jiffies = 0; 1185 1186 /* During process initialization eviction_work.dwork is initialized 1187 * to kfd_evict_bo_worker 1188 */ 1189 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1190 p->lead_thread->pid, delay_jiffies); 1191 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1192 out: 1193 kfd_unref_process(p); 1194 return 0; 1195 } 1196 1197 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1198 unsigned int chunk_size) 1199 { 1200 if (WARN_ON(buf_size < chunk_size)) 1201 return -EINVAL; 1202 if (WARN_ON(buf_size == 0)) 1203 return -EINVAL; 1204 if (WARN_ON(chunk_size == 0)) 1205 return -EINVAL; 1206 1207 kfd->gtt_sa_chunk_size = chunk_size; 1208 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1209 1210 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1211 GFP_KERNEL); 1212 if (!kfd->gtt_sa_bitmap) 1213 return -ENOMEM; 1214 1215 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1216 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1217 1218 mutex_init(&kfd->gtt_sa_lock); 1219 1220 return 0; 1221 } 1222 1223 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1224 { 1225 mutex_destroy(&kfd->gtt_sa_lock); 1226 bitmap_free(kfd->gtt_sa_bitmap); 1227 } 1228 1229 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1230 unsigned int bit_num, 1231 unsigned int chunk_size) 1232 { 1233 return start_addr + bit_num * chunk_size; 1234 } 1235 1236 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1237 unsigned int bit_num, 1238 unsigned int chunk_size) 1239 { 1240 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1241 } 1242 1243 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1244 struct kfd_mem_obj **mem_obj) 1245 { 1246 unsigned int found, start_search, cur_size; 1247 struct kfd_dev *kfd = node->kfd; 1248 1249 if (size == 0) 1250 return -EINVAL; 1251 1252 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1253 return -ENOMEM; 1254 1255 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1256 if (!(*mem_obj)) 1257 return -ENOMEM; 1258 1259 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1260 1261 start_search = 0; 1262 1263 mutex_lock(&kfd->gtt_sa_lock); 1264 1265 kfd_gtt_restart_search: 1266 /* Find the first chunk that is free */ 1267 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1268 kfd->gtt_sa_num_of_chunks, 1269 start_search); 1270 1271 pr_debug("Found = %d\n", found); 1272 1273 /* If there wasn't any free chunk, bail out */ 1274 if (found == kfd->gtt_sa_num_of_chunks) 1275 goto kfd_gtt_no_free_chunk; 1276 1277 /* Update fields of mem_obj */ 1278 (*mem_obj)->range_start = found; 1279 (*mem_obj)->range_end = found; 1280 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1281 kfd->gtt_start_gpu_addr, 1282 found, 1283 kfd->gtt_sa_chunk_size); 1284 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1285 kfd->gtt_start_cpu_ptr, 1286 found, 1287 kfd->gtt_sa_chunk_size); 1288 1289 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1290 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1291 1292 /* If we need only one chunk, mark it as allocated and get out */ 1293 if (size <= kfd->gtt_sa_chunk_size) { 1294 pr_debug("Single bit\n"); 1295 __set_bit(found, kfd->gtt_sa_bitmap); 1296 goto kfd_gtt_out; 1297 } 1298 1299 /* Otherwise, try to see if we have enough contiguous chunks */ 1300 cur_size = size - kfd->gtt_sa_chunk_size; 1301 do { 1302 (*mem_obj)->range_end = 1303 find_next_zero_bit(kfd->gtt_sa_bitmap, 1304 kfd->gtt_sa_num_of_chunks, ++found); 1305 /* 1306 * If next free chunk is not contiguous than we need to 1307 * restart our search from the last free chunk we found (which 1308 * wasn't contiguous to the previous ones 1309 */ 1310 if ((*mem_obj)->range_end != found) { 1311 start_search = found; 1312 goto kfd_gtt_restart_search; 1313 } 1314 1315 /* 1316 * If we reached end of buffer, bail out with error 1317 */ 1318 if (found == kfd->gtt_sa_num_of_chunks) 1319 goto kfd_gtt_no_free_chunk; 1320 1321 /* Check if we don't need another chunk */ 1322 if (cur_size <= kfd->gtt_sa_chunk_size) 1323 cur_size = 0; 1324 else 1325 cur_size -= kfd->gtt_sa_chunk_size; 1326 1327 } while (cur_size > 0); 1328 1329 pr_debug("range_start = %d, range_end = %d\n", 1330 (*mem_obj)->range_start, (*mem_obj)->range_end); 1331 1332 /* Mark the chunks as allocated */ 1333 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1334 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1335 1336 kfd_gtt_out: 1337 mutex_unlock(&kfd->gtt_sa_lock); 1338 return 0; 1339 1340 kfd_gtt_no_free_chunk: 1341 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1342 mutex_unlock(&kfd->gtt_sa_lock); 1343 kfree(*mem_obj); 1344 return -ENOMEM; 1345 } 1346 1347 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1348 { 1349 struct kfd_dev *kfd = node->kfd; 1350 1351 /* Act like kfree when trying to free a NULL object */ 1352 if (!mem_obj) 1353 return 0; 1354 1355 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1356 mem_obj, mem_obj->range_start, mem_obj->range_end); 1357 1358 mutex_lock(&kfd->gtt_sa_lock); 1359 1360 /* Mark the chunks as free */ 1361 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1362 mem_obj->range_end - mem_obj->range_start + 1); 1363 1364 mutex_unlock(&kfd->gtt_sa_lock); 1365 1366 kfree(mem_obj); 1367 return 0; 1368 } 1369 1370 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1371 { 1372 /* 1373 * TODO: Currently update SRAM ECC flag for first node. 1374 * This needs to be updated later when we can 1375 * identify SRAM ECC error on other nodes also. 1376 */ 1377 if (kfd) 1378 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1379 } 1380 1381 void kfd_inc_compute_active(struct kfd_node *node) 1382 { 1383 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1384 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1385 } 1386 1387 void kfd_dec_compute_active(struct kfd_node *node) 1388 { 1389 int count = atomic_dec_return(&node->kfd->compute_profile); 1390 1391 if (count == 0) 1392 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1393 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1394 } 1395 1396 static bool kfd_compute_active(struct kfd_node *node) 1397 { 1398 if (atomic_read(&node->kfd->compute_profile)) 1399 return true; 1400 return false; 1401 } 1402 1403 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1404 { 1405 /* 1406 * TODO: For now, raise the throttling event only on first node. 1407 * This will need to change after we are able to determine 1408 * which node raised the throttling event. 1409 */ 1410 if (kfd && kfd->init_complete) 1411 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1412 throttle_bitmask); 1413 } 1414 1415 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1416 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1417 * When the device has more than two engines, we reserve two for PCIe to enable 1418 * full-duplex and the rest are used as XGMI. 1419 */ 1420 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1421 { 1422 /* If XGMI is not supported, all SDMA engines are PCIe */ 1423 if (!node->adev->gmc.xgmi.supported) 1424 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1425 1426 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1427 } 1428 1429 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1430 { 1431 /* After reserved for PCIe, the rest of engines are XGMI */ 1432 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1433 kfd_get_num_sdma_engines(node); 1434 } 1435 1436 int kgd2kfd_check_and_lock_kfd(void) 1437 { 1438 mutex_lock(&kfd_processes_mutex); 1439 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1440 mutex_unlock(&kfd_processes_mutex); 1441 return -EBUSY; 1442 } 1443 1444 ++kfd_locked; 1445 mutex_unlock(&kfd_processes_mutex); 1446 1447 return 0; 1448 } 1449 1450 void kgd2kfd_unlock_kfd(void) 1451 { 1452 mutex_lock(&kfd_processes_mutex); 1453 --kfd_locked; 1454 mutex_unlock(&kfd_processes_mutex); 1455 } 1456 1457 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1458 { 1459 struct kfd_node *node; 1460 int ret; 1461 1462 if (!kfd->init_complete) 1463 return 0; 1464 1465 if (node_id >= kfd->num_nodes) { 1466 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1467 node_id, kfd->num_nodes - 1); 1468 return -EINVAL; 1469 } 1470 node = kfd->nodes[node_id]; 1471 1472 ret = node->dqm->ops.unhalt(node->dqm); 1473 if (ret) 1474 dev_err(kfd_device, "Error in starting scheduler\n"); 1475 1476 return ret; 1477 } 1478 1479 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1480 { 1481 struct kfd_node *node; 1482 1483 if (!kfd->init_complete) 1484 return 0; 1485 1486 if (node_id >= kfd->num_nodes) { 1487 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1488 node_id, kfd->num_nodes - 1); 1489 return -EINVAL; 1490 } 1491 1492 node = kfd->nodes[node_id]; 1493 return node->dqm->ops.halt(node->dqm); 1494 } 1495 1496 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1497 { 1498 struct kfd_node *node; 1499 1500 if (!kfd->init_complete) 1501 return false; 1502 1503 if (node_id >= kfd->num_nodes) { 1504 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1505 node_id, kfd->num_nodes - 1); 1506 return false; 1507 } 1508 1509 node = kfd->nodes[node_id]; 1510 1511 return kfd_compute_active(node); 1512 } 1513 1514 #if defined(CONFIG_DEBUG_FS) 1515 1516 /* This function will send a package to HIQ to hang the HWS 1517 * which will trigger a GPU reset and bring the HWS back to normal state 1518 */ 1519 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1520 { 1521 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1522 pr_err("HWS is not enabled"); 1523 return -EINVAL; 1524 } 1525 1526 return dqm_debugfs_hang_hws(dev->dqm); 1527 } 1528 1529 #endif 1530