1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(4, 4, 5): 88 case IP_VERSION(5, 0, 0):/* NAVI10 */ 89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 90 case IP_VERSION(5, 0, 2):/* NAVI14 */ 91 case IP_VERSION(5, 0, 5):/* NAVI12 */ 92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 96 case IP_VERSION(6, 0, 0): 97 case IP_VERSION(6, 0, 1): 98 case IP_VERSION(6, 0, 2): 99 case IP_VERSION(6, 0, 3): 100 case IP_VERSION(6, 1, 0): 101 case IP_VERSION(6, 1, 1): 102 case IP_VERSION(7, 0, 0): 103 case IP_VERSION(7, 0, 1): 104 kfd->device_info.num_sdma_queues_per_engine = 8; 105 break; 106 default: 107 dev_warn(kfd_device, 108 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 109 sdma_version); 110 kfd->device_info.num_sdma_queues_per_engine = 8; 111 } 112 113 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 114 115 switch (sdma_version) { 116 case IP_VERSION(6, 0, 0): 117 case IP_VERSION(6, 0, 1): 118 case IP_VERSION(6, 0, 2): 119 case IP_VERSION(6, 0, 3): 120 case IP_VERSION(6, 1, 0): 121 case IP_VERSION(6, 1, 1): 122 case IP_VERSION(7, 0, 0): 123 case IP_VERSION(7, 0, 1): 124 /* Reserve 1 for paging and 1 for gfx */ 125 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 126 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 127 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 128 kfd->adev->sdma.num_instances * 129 kfd->device_info.num_reserved_sdma_queues_per_engine); 130 break; 131 default: 132 break; 133 } 134 } 135 136 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 137 { 138 uint32_t gc_version = KFD_GC_VERSION(kfd); 139 140 switch (gc_version) { 141 case IP_VERSION(9, 0, 1): /* VEGA10 */ 142 case IP_VERSION(9, 1, 0): /* RAVEN */ 143 case IP_VERSION(9, 2, 1): /* VEGA12 */ 144 case IP_VERSION(9, 2, 2): /* RAVEN */ 145 case IP_VERSION(9, 3, 0): /* RENOIR */ 146 case IP_VERSION(9, 4, 0): /* VEGA20 */ 147 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 148 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 149 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 150 break; 151 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 152 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 153 kfd->device_info.event_interrupt_class = 154 &event_interrupt_class_v9_4_3; 155 break; 156 case IP_VERSION(10, 3, 1): /* VANGOGH */ 157 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 158 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 159 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 160 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 161 case IP_VERSION(10, 1, 4): 162 case IP_VERSION(10, 1, 10): /* NAVI10 */ 163 case IP_VERSION(10, 1, 2): /* NAVI12 */ 164 case IP_VERSION(10, 1, 1): /* NAVI14 */ 165 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 166 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 167 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 168 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 169 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 170 break; 171 case IP_VERSION(11, 0, 0): 172 case IP_VERSION(11, 0, 1): 173 case IP_VERSION(11, 0, 2): 174 case IP_VERSION(11, 0, 3): 175 case IP_VERSION(11, 0, 4): 176 case IP_VERSION(11, 5, 0): 177 case IP_VERSION(11, 5, 1): 178 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 179 break; 180 case IP_VERSION(12, 0, 0): 181 case IP_VERSION(12, 0, 1): 182 /* GFX12_TODO: Change to v12 version. */ 183 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 184 break; 185 default: 186 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 187 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 188 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 189 } 190 } 191 192 static void kfd_device_info_init(struct kfd_dev *kfd, 193 bool vf, uint32_t gfx_target_version) 194 { 195 uint32_t gc_version = KFD_GC_VERSION(kfd); 196 uint32_t asic_type = kfd->adev->asic_type; 197 198 kfd->device_info.max_pasid_bits = 16; 199 kfd->device_info.max_no_of_hqd = 24; 200 kfd->device_info.num_of_watch_points = 4; 201 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 202 kfd->device_info.gfx_target_version = gfx_target_version; 203 204 if (KFD_IS_SOC15(kfd)) { 205 kfd->device_info.doorbell_size = 8; 206 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 207 kfd->device_info.supports_cwsr = true; 208 209 kfd_device_info_set_sdma_info(kfd); 210 211 kfd_device_info_set_event_interrupt_class(kfd); 212 213 if (gc_version < IP_VERSION(11, 0, 0)) { 214 /* Navi2x+, Navi1x+ */ 215 if (gc_version == IP_VERSION(10, 3, 6)) 216 kfd->device_info.no_atomic_fw_version = 14; 217 else if (gc_version == IP_VERSION(10, 3, 7)) 218 kfd->device_info.no_atomic_fw_version = 3; 219 else if (gc_version >= IP_VERSION(10, 3, 0)) 220 kfd->device_info.no_atomic_fw_version = 92; 221 else if (gc_version >= IP_VERSION(10, 1, 1)) 222 kfd->device_info.no_atomic_fw_version = 145; 223 224 /* Navi1x+ */ 225 if (gc_version >= IP_VERSION(10, 1, 1)) 226 kfd->device_info.needs_pci_atomics = true; 227 } else if (gc_version < IP_VERSION(12, 0, 0)) { 228 /* 229 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 230 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 231 * PCIe atomics support. 232 */ 233 kfd->device_info.needs_pci_atomics = true; 234 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 235 } else { 236 kfd->device_info.needs_pci_atomics = true; 237 } 238 } else { 239 kfd->device_info.doorbell_size = 4; 240 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 241 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 242 kfd->device_info.num_sdma_queues_per_engine = 2; 243 244 if (asic_type != CHIP_KAVERI && 245 asic_type != CHIP_HAWAII && 246 asic_type != CHIP_TONGA) 247 kfd->device_info.supports_cwsr = true; 248 249 if (asic_type != CHIP_HAWAII && !vf) 250 kfd->device_info.needs_pci_atomics = true; 251 } 252 } 253 254 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 255 { 256 struct kfd_dev *kfd = NULL; 257 const struct kfd2kgd_calls *f2g = NULL; 258 uint32_t gfx_target_version = 0; 259 260 switch (adev->asic_type) { 261 #ifdef CONFIG_DRM_AMDGPU_CIK 262 case CHIP_KAVERI: 263 gfx_target_version = 70000; 264 if (!vf) 265 f2g = &gfx_v7_kfd2kgd; 266 break; 267 #endif 268 case CHIP_CARRIZO: 269 gfx_target_version = 80001; 270 if (!vf) 271 f2g = &gfx_v8_kfd2kgd; 272 break; 273 #ifdef CONFIG_DRM_AMDGPU_CIK 274 case CHIP_HAWAII: 275 gfx_target_version = 70001; 276 if (!amdgpu_exp_hw_support) 277 pr_info( 278 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 279 ); 280 else if (!vf) 281 f2g = &gfx_v7_kfd2kgd; 282 break; 283 #endif 284 case CHIP_TONGA: 285 gfx_target_version = 80002; 286 if (!vf) 287 f2g = &gfx_v8_kfd2kgd; 288 break; 289 case CHIP_FIJI: 290 case CHIP_POLARIS10: 291 gfx_target_version = 80003; 292 f2g = &gfx_v8_kfd2kgd; 293 break; 294 case CHIP_POLARIS11: 295 case CHIP_POLARIS12: 296 case CHIP_VEGAM: 297 gfx_target_version = 80003; 298 if (!vf) 299 f2g = &gfx_v8_kfd2kgd; 300 break; 301 default: 302 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 303 /* Vega 10 */ 304 case IP_VERSION(9, 0, 1): 305 gfx_target_version = 90000; 306 f2g = &gfx_v9_kfd2kgd; 307 break; 308 /* Raven */ 309 case IP_VERSION(9, 1, 0): 310 case IP_VERSION(9, 2, 2): 311 gfx_target_version = 90002; 312 if (!vf) 313 f2g = &gfx_v9_kfd2kgd; 314 break; 315 /* Vega12 */ 316 case IP_VERSION(9, 2, 1): 317 gfx_target_version = 90004; 318 if (!vf) 319 f2g = &gfx_v9_kfd2kgd; 320 break; 321 /* Renoir */ 322 case IP_VERSION(9, 3, 0): 323 gfx_target_version = 90012; 324 if (!vf) 325 f2g = &gfx_v9_kfd2kgd; 326 break; 327 /* Vega20 */ 328 case IP_VERSION(9, 4, 0): 329 gfx_target_version = 90006; 330 if (!vf) 331 f2g = &gfx_v9_kfd2kgd; 332 break; 333 /* Arcturus */ 334 case IP_VERSION(9, 4, 1): 335 gfx_target_version = 90008; 336 f2g = &arcturus_kfd2kgd; 337 break; 338 /* Aldebaran */ 339 case IP_VERSION(9, 4, 2): 340 gfx_target_version = 90010; 341 f2g = &aldebaran_kfd2kgd; 342 break; 343 case IP_VERSION(9, 4, 3): 344 gfx_target_version = adev->rev_id >= 1 ? 90402 345 : adev->flags & AMD_IS_APU ? 90400 346 : 90401; 347 f2g = &gc_9_4_3_kfd2kgd; 348 break; 349 case IP_VERSION(9, 4, 4): 350 gfx_target_version = 90402; 351 f2g = &gc_9_4_3_kfd2kgd; 352 break; 353 /* Navi10 */ 354 case IP_VERSION(10, 1, 10): 355 gfx_target_version = 100100; 356 if (!vf) 357 f2g = &gfx_v10_kfd2kgd; 358 break; 359 /* Navi12 */ 360 case IP_VERSION(10, 1, 2): 361 gfx_target_version = 100101; 362 f2g = &gfx_v10_kfd2kgd; 363 break; 364 /* Navi14 */ 365 case IP_VERSION(10, 1, 1): 366 gfx_target_version = 100102; 367 if (!vf) 368 f2g = &gfx_v10_kfd2kgd; 369 break; 370 /* Cyan Skillfish */ 371 case IP_VERSION(10, 1, 3): 372 case IP_VERSION(10, 1, 4): 373 gfx_target_version = 100103; 374 if (!vf) 375 f2g = &gfx_v10_kfd2kgd; 376 break; 377 /* Sienna Cichlid */ 378 case IP_VERSION(10, 3, 0): 379 gfx_target_version = 100300; 380 f2g = &gfx_v10_3_kfd2kgd; 381 break; 382 /* Navy Flounder */ 383 case IP_VERSION(10, 3, 2): 384 gfx_target_version = 100301; 385 f2g = &gfx_v10_3_kfd2kgd; 386 break; 387 /* Van Gogh */ 388 case IP_VERSION(10, 3, 1): 389 gfx_target_version = 100303; 390 if (!vf) 391 f2g = &gfx_v10_3_kfd2kgd; 392 break; 393 /* Dimgrey Cavefish */ 394 case IP_VERSION(10, 3, 4): 395 gfx_target_version = 100302; 396 f2g = &gfx_v10_3_kfd2kgd; 397 break; 398 /* Beige Goby */ 399 case IP_VERSION(10, 3, 5): 400 gfx_target_version = 100304; 401 f2g = &gfx_v10_3_kfd2kgd; 402 break; 403 /* Yellow Carp */ 404 case IP_VERSION(10, 3, 3): 405 gfx_target_version = 100305; 406 if (!vf) 407 f2g = &gfx_v10_3_kfd2kgd; 408 break; 409 case IP_VERSION(10, 3, 6): 410 case IP_VERSION(10, 3, 7): 411 gfx_target_version = 100306; 412 if (!vf) 413 f2g = &gfx_v10_3_kfd2kgd; 414 break; 415 case IP_VERSION(11, 0, 0): 416 gfx_target_version = 110000; 417 f2g = &gfx_v11_kfd2kgd; 418 break; 419 case IP_VERSION(11, 0, 1): 420 case IP_VERSION(11, 0, 4): 421 gfx_target_version = 110003; 422 f2g = &gfx_v11_kfd2kgd; 423 break; 424 case IP_VERSION(11, 0, 2): 425 gfx_target_version = 110002; 426 f2g = &gfx_v11_kfd2kgd; 427 break; 428 case IP_VERSION(11, 0, 3): 429 if ((adev->pdev->device == 0x7460 && 430 adev->pdev->revision == 0x00) || 431 (adev->pdev->device == 0x7461 && 432 adev->pdev->revision == 0x00)) 433 /* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */ 434 gfx_target_version = 110005; 435 else 436 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 437 gfx_target_version = 110001; 438 f2g = &gfx_v11_kfd2kgd; 439 break; 440 case IP_VERSION(11, 5, 0): 441 gfx_target_version = 110500; 442 f2g = &gfx_v11_kfd2kgd; 443 break; 444 case IP_VERSION(11, 5, 1): 445 gfx_target_version = 110501; 446 f2g = &gfx_v11_kfd2kgd; 447 break; 448 case IP_VERSION(12, 0, 0): 449 gfx_target_version = 120000; 450 f2g = &gfx_v12_kfd2kgd; 451 break; 452 case IP_VERSION(12, 0, 1): 453 gfx_target_version = 120001; 454 f2g = &gfx_v12_kfd2kgd; 455 break; 456 default: 457 break; 458 } 459 break; 460 } 461 462 if (!f2g) { 463 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 464 dev_info(kfd_device, 465 "GC IP %06x %s not supported in kfd\n", 466 amdgpu_ip_version(adev, GC_HWIP, 0), 467 vf ? "VF" : ""); 468 else 469 dev_info(kfd_device, "%s %s not supported in kfd\n", 470 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 471 return NULL; 472 } 473 474 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 475 if (!kfd) 476 return NULL; 477 478 kfd->adev = adev; 479 kfd_device_info_init(kfd, vf, gfx_target_version); 480 kfd->init_complete = false; 481 kfd->kfd2kgd = f2g; 482 atomic_set(&kfd->compute_profile, 0); 483 484 mutex_init(&kfd->doorbell_mutex); 485 486 ida_init(&kfd->doorbell_ida); 487 488 return kfd; 489 } 490 491 static void kfd_cwsr_init(struct kfd_dev *kfd) 492 { 493 if (cwsr_enable && kfd->device_info.supports_cwsr) { 494 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 495 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 496 > KFD_CWSR_TMA_OFFSET); 497 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 498 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 499 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 500 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 501 > KFD_CWSR_TMA_OFFSET); 502 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 503 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 504 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 505 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 506 > KFD_CWSR_TMA_OFFSET); 507 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 508 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 509 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 510 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 511 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 512 > KFD_CWSR_TMA_OFFSET); 513 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 514 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 515 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 516 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 517 > KFD_CWSR_TMA_OFFSET); 518 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 519 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 520 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 521 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 522 > KFD_CWSR_TMA_OFFSET); 523 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 524 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 525 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 526 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 527 > KFD_CWSR_TMA_OFFSET); 528 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 529 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 530 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 531 /* The gfx11 cwsr trap handler must fit inside a single 532 page. */ 533 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 534 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 535 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 536 } else { 537 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) > PAGE_SIZE); 538 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 539 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 540 } 541 542 kfd->cwsr_enabled = true; 543 } 544 } 545 546 static int kfd_gws_init(struct kfd_node *node) 547 { 548 int ret = 0; 549 struct kfd_dev *kfd = node->kfd; 550 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 551 552 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 553 return 0; 554 555 if (hws_gws_support || (KFD_IS_SOC15(node) && 556 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 557 && kfd->mec2_fw_version >= 0x81b3) || 558 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 559 && kfd->mec2_fw_version >= 0x1b3) || 560 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 561 && kfd->mec2_fw_version >= 0x30) || 562 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 563 && kfd->mec2_fw_version >= 0x28) || 564 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 565 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 566 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 567 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 568 && kfd->mec2_fw_version >= 0x6b) || 569 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 570 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 571 && mes_rev >= 68)))) 572 ret = amdgpu_amdkfd_alloc_gws(node->adev, 573 node->adev->gds.gws_size, &node->gws); 574 575 return ret; 576 } 577 578 static void kfd_smi_init(struct kfd_node *dev) 579 { 580 INIT_LIST_HEAD(&dev->smi_clients); 581 spin_lock_init(&dev->smi_lock); 582 } 583 584 static int kfd_init_node(struct kfd_node *node) 585 { 586 int err = -1; 587 588 if (kfd_interrupt_init(node)) { 589 dev_err(kfd_device, "Error initializing interrupts\n"); 590 goto kfd_interrupt_error; 591 } 592 593 node->dqm = device_queue_manager_init(node); 594 if (!node->dqm) { 595 dev_err(kfd_device, "Error initializing queue manager\n"); 596 goto device_queue_manager_error; 597 } 598 599 if (kfd_gws_init(node)) { 600 dev_err(kfd_device, "Could not allocate %d gws\n", 601 node->adev->gds.gws_size); 602 goto gws_error; 603 } 604 605 if (kfd_resume(node)) 606 goto kfd_resume_error; 607 608 if (kfd_topology_add_device(node)) { 609 dev_err(kfd_device, "Error adding device to topology\n"); 610 goto kfd_topology_add_device_error; 611 } 612 613 kfd_smi_init(node); 614 615 return 0; 616 617 kfd_topology_add_device_error: 618 kfd_resume_error: 619 gws_error: 620 device_queue_manager_uninit(node->dqm); 621 device_queue_manager_error: 622 kfd_interrupt_exit(node); 623 kfd_interrupt_error: 624 if (node->gws) 625 amdgpu_amdkfd_free_gws(node->adev, node->gws); 626 627 /* Cleanup the node memory here */ 628 kfree(node); 629 return err; 630 } 631 632 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 633 { 634 struct kfd_node *knode; 635 unsigned int i; 636 637 for (i = 0; i < num_nodes; i++) { 638 knode = kfd->nodes[i]; 639 device_queue_manager_uninit(knode->dqm); 640 kfd_interrupt_exit(knode); 641 kfd_topology_remove_device(knode); 642 if (knode->gws) 643 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 644 kfree(knode); 645 kfd->nodes[i] = NULL; 646 } 647 } 648 649 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 650 unsigned int kfd_node_idx) 651 { 652 struct amdgpu_device *adev = node->adev; 653 uint32_t xcc_mask = node->xcc_mask; 654 uint32_t xcc, mapped_xcc; 655 /* 656 * Interrupt bitmap is setup for processing interrupts from 657 * different XCDs and AIDs. 658 * Interrupt bitmap is defined as follows: 659 * 1. Bits 0-15 - correspond to the NodeId field. 660 * Each bit corresponds to NodeId number. For example, if 661 * a KFD node has interrupt bitmap set to 0x7, then this 662 * KFD node will process interrupts with NodeId = 0, 1 and 2 663 * in the IH cookie. 664 * 2. Bits 16-31 - unused. 665 * 666 * Please note that the kfd_node_idx argument passed to this 667 * function is not related to NodeId field received in the 668 * IH cookie. 669 * 670 * In CPX mode, a KFD node will process an interrupt if: 671 * - the Node Id matches the corresponding bit set in 672 * Bits 0-15. 673 * - AND VMID reported in the interrupt lies within the 674 * VMID range of the node. 675 */ 676 for_each_inst(xcc, xcc_mask) { 677 mapped_xcc = GET_INST(GC, xcc); 678 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 679 } 680 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 681 node->interrupt_bitmap); 682 } 683 684 bool kgd2kfd_device_init(struct kfd_dev *kfd, 685 const struct kgd2kfd_shared_resources *gpu_resources) 686 { 687 unsigned int size, map_process_packet_size, i; 688 struct kfd_node *node; 689 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 690 unsigned int max_proc_per_quantum; 691 int partition_mode; 692 int xcp_idx; 693 694 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 695 KGD_ENGINE_MEC1); 696 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 697 KGD_ENGINE_MEC2); 698 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 699 KGD_ENGINE_SDMA1); 700 kfd->shared_resources = *gpu_resources; 701 702 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 703 704 if (kfd->num_nodes == 0) { 705 dev_err(kfd_device, 706 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 707 kfd->adev->gfx.num_xcc_per_xcp); 708 goto out; 709 } 710 711 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 712 * 32 and 64-bit requests are possible and must be 713 * supported. 714 */ 715 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 716 if (!kfd->pci_atomic_requested && 717 kfd->device_info.needs_pci_atomics && 718 (!kfd->device_info.no_atomic_fw_version || 719 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 720 dev_info(kfd_device, 721 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 722 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 723 kfd->mec_fw_version, 724 kfd->device_info.no_atomic_fw_version); 725 return false; 726 } 727 728 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 729 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 730 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 731 732 /* For GFX9.4.3, we need special handling for VMIDs depending on 733 * partition mode. 734 * In CPX mode, the VMID range needs to be shared between XCDs. 735 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 736 * divide them equally, we change starting VMID to 4 and not use 737 * VMID 3. 738 * If the VMID range changes for GFX9.4.3, then this code MUST be 739 * revisited. 740 */ 741 if (kfd->adev->xcp_mgr) { 742 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 743 AMDGPU_XCP_FL_LOCKED); 744 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 745 kfd->num_nodes != 1) { 746 vmid_num_kfd /= 2; 747 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 748 } 749 } 750 751 /* Verify module parameters regarding mapped process number*/ 752 if (hws_max_conc_proc >= 0) 753 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 754 else 755 max_proc_per_quantum = vmid_num_kfd; 756 757 /* calculate max size of mqds needed for queues */ 758 size = max_num_of_queues_per_device * 759 kfd->device_info.mqd_size_aligned; 760 761 /* 762 * calculate max size of runlist packet. 763 * There can be only 2 packets at once 764 */ 765 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 766 sizeof(struct pm4_mes_map_process_aldebaran) : 767 sizeof(struct pm4_mes_map_process); 768 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 769 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 770 + sizeof(struct pm4_mes_runlist)) * 2; 771 772 /* Add size of HIQ & DIQ */ 773 size += KFD_KERNEL_QUEUE_SIZE * 2; 774 775 /* add another 512KB for all other allocations on gart (HPD, fences) */ 776 size += 512 * 1024; 777 778 if (amdgpu_amdkfd_alloc_gtt_mem( 779 kfd->adev, size, &kfd->gtt_mem, 780 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 781 false)) { 782 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 783 goto alloc_gtt_mem_failure; 784 } 785 786 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 787 788 /* Initialize GTT sa with 512 byte chunk size */ 789 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 790 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 791 goto kfd_gtt_sa_init_error; 792 } 793 794 if (kfd_doorbell_init(kfd)) { 795 dev_err(kfd_device, 796 "Error initializing doorbell aperture\n"); 797 goto kfd_doorbell_error; 798 } 799 800 if (amdgpu_use_xgmi_p2p) 801 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 802 803 /* 804 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 805 * xGMI connected in the topology so assign a unique hive id per 806 * device based on the pci device location if device is in PCIe mode. 807 */ 808 if (!kfd->hive_id && 809 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 810 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) && 811 kfd->num_nodes > 1) 812 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 813 814 kfd->noretry = kfd->adev->gmc.noretry; 815 816 kfd_cwsr_init(kfd); 817 818 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 819 kfd->num_nodes); 820 821 /* Allocate the KFD nodes */ 822 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 823 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 824 if (!node) 825 goto node_alloc_error; 826 827 node->node_id = i; 828 node->adev = kfd->adev; 829 node->kfd = kfd; 830 node->kfd2kgd = kfd->kfd2kgd; 831 node->vm_info.vmid_num_kfd = vmid_num_kfd; 832 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 833 /* TODO : Check if error handling is needed */ 834 if (node->xcp) { 835 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 836 &node->xcc_mask); 837 ++xcp_idx; 838 } else { 839 node->xcc_mask = 840 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 841 } 842 843 if (node->xcp) { 844 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 845 node->node_id, node->xcp->mem_id, 846 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 847 } 848 849 if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 850 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) && 851 partition_mode == AMDGPU_CPX_PARTITION_MODE && 852 kfd->num_nodes != 1) { 853 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 854 * 4-9 and second XCD gets VMID range 10-15. 855 */ 856 857 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 858 first_vmid_kfd : 859 first_vmid_kfd+vmid_num_kfd; 860 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 861 last_vmid_kfd-vmid_num_kfd : 862 last_vmid_kfd; 863 node->compute_vmid_bitmap = 864 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 865 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 866 } else { 867 node->vm_info.first_vmid_kfd = first_vmid_kfd; 868 node->vm_info.last_vmid_kfd = last_vmid_kfd; 869 node->compute_vmid_bitmap = 870 gpu_resources->compute_vmid_bitmap; 871 } 872 node->max_proc_per_quantum = max_proc_per_quantum; 873 atomic_set(&node->sram_ecc_flag, 0); 874 875 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 876 &node->local_mem_info, node->xcp); 877 878 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 879 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) 880 kfd_setup_interrupt_bitmap(node, i); 881 882 /* Initialize the KFD node */ 883 if (kfd_init_node(node)) { 884 dev_err(kfd_device, "Error initializing KFD node\n"); 885 goto node_init_error; 886 } 887 kfd->nodes[i] = node; 888 } 889 890 svm_range_set_max_pages(kfd->adev); 891 892 spin_lock_init(&kfd->watch_points_lock); 893 894 kfd->init_complete = true; 895 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 896 kfd->adev->pdev->device); 897 898 pr_debug("Starting kfd with the following scheduling policy %d\n", 899 node->dqm->sched_policy); 900 901 goto out; 902 903 node_init_error: 904 node_alloc_error: 905 kfd_cleanup_nodes(kfd, i); 906 kfd_doorbell_fini(kfd); 907 kfd_doorbell_error: 908 kfd_gtt_sa_fini(kfd); 909 kfd_gtt_sa_init_error: 910 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 911 alloc_gtt_mem_failure: 912 dev_err(kfd_device, 913 "device %x:%x NOT added due to errors\n", 914 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 915 out: 916 return kfd->init_complete; 917 } 918 919 void kgd2kfd_device_exit(struct kfd_dev *kfd) 920 { 921 if (kfd->init_complete) { 922 /* Cleanup KFD nodes */ 923 kfd_cleanup_nodes(kfd, kfd->num_nodes); 924 /* Cleanup common/shared resources */ 925 kfd_doorbell_fini(kfd); 926 ida_destroy(&kfd->doorbell_ida); 927 kfd_gtt_sa_fini(kfd); 928 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 929 } 930 931 kfree(kfd); 932 } 933 934 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 935 { 936 struct kfd_node *node; 937 int i; 938 939 if (!kfd->init_complete) 940 return 0; 941 942 for (i = 0; i < kfd->num_nodes; i++) { 943 node = kfd->nodes[i]; 944 kfd_smi_event_update_gpu_reset(node, false); 945 node->dqm->ops.pre_reset(node->dqm); 946 } 947 948 kgd2kfd_suspend(kfd, false); 949 950 for (i = 0; i < kfd->num_nodes; i++) 951 kfd_signal_reset_event(kfd->nodes[i]); 952 953 return 0; 954 } 955 956 /* 957 * Fix me. KFD won't be able to resume existing process for now. 958 * We will keep all existing process in a evicted state and 959 * wait the process to be terminated. 960 */ 961 962 int kgd2kfd_post_reset(struct kfd_dev *kfd) 963 { 964 int ret; 965 struct kfd_node *node; 966 int i; 967 968 if (!kfd->init_complete) 969 return 0; 970 971 for (i = 0; i < kfd->num_nodes; i++) { 972 ret = kfd_resume(kfd->nodes[i]); 973 if (ret) 974 return ret; 975 } 976 977 mutex_lock(&kfd_processes_mutex); 978 --kfd_locked; 979 mutex_unlock(&kfd_processes_mutex); 980 981 for (i = 0; i < kfd->num_nodes; i++) { 982 node = kfd->nodes[i]; 983 atomic_set(&node->sram_ecc_flag, 0); 984 kfd_smi_event_update_gpu_reset(node, true); 985 } 986 987 return 0; 988 } 989 990 bool kfd_is_locked(void) 991 { 992 lockdep_assert_held(&kfd_processes_mutex); 993 return (kfd_locked > 0); 994 } 995 996 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 997 { 998 struct kfd_node *node; 999 int i; 1000 1001 if (!kfd->init_complete) 1002 return; 1003 1004 /* for runtime suspend, skip locking kfd */ 1005 if (!run_pm) { 1006 mutex_lock(&kfd_processes_mutex); 1007 /* For first KFD device suspend all the KFD processes */ 1008 if (++kfd_locked == 1) 1009 kfd_suspend_all_processes(); 1010 mutex_unlock(&kfd_processes_mutex); 1011 } 1012 1013 for (i = 0; i < kfd->num_nodes; i++) { 1014 node = kfd->nodes[i]; 1015 node->dqm->ops.stop(node->dqm); 1016 } 1017 } 1018 1019 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1020 { 1021 int ret, i; 1022 1023 if (!kfd->init_complete) 1024 return 0; 1025 1026 for (i = 0; i < kfd->num_nodes; i++) { 1027 ret = kfd_resume(kfd->nodes[i]); 1028 if (ret) 1029 return ret; 1030 } 1031 1032 /* for runtime resume, skip unlocking kfd */ 1033 if (!run_pm) { 1034 mutex_lock(&kfd_processes_mutex); 1035 if (--kfd_locked == 0) 1036 ret = kfd_resume_all_processes(); 1037 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1038 mutex_unlock(&kfd_processes_mutex); 1039 } 1040 1041 return ret; 1042 } 1043 1044 static int kfd_resume(struct kfd_node *node) 1045 { 1046 int err = 0; 1047 1048 err = node->dqm->ops.start(node->dqm); 1049 if (err) 1050 dev_err(kfd_device, 1051 "Error starting queue manager for device %x:%x\n", 1052 node->adev->pdev->vendor, node->adev->pdev->device); 1053 1054 return err; 1055 } 1056 1057 static inline void kfd_queue_work(struct workqueue_struct *wq, 1058 struct work_struct *work) 1059 { 1060 int cpu, new_cpu; 1061 1062 cpu = new_cpu = smp_processor_id(); 1063 do { 1064 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1065 if (cpu_to_node(new_cpu) == numa_node_id()) 1066 break; 1067 } while (cpu != new_cpu); 1068 1069 queue_work_on(new_cpu, wq, work); 1070 } 1071 1072 /* This is called directly from KGD at ISR. */ 1073 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1074 { 1075 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1076 bool is_patched = false; 1077 unsigned long flags; 1078 struct kfd_node *node; 1079 1080 if (!kfd->init_complete) 1081 return; 1082 1083 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1084 dev_err_once(kfd_device, "Ring entry too small\n"); 1085 return; 1086 } 1087 1088 for (i = 0; i < kfd->num_nodes; i++) { 1089 node = kfd->nodes[i]; 1090 spin_lock_irqsave(&node->interrupt_lock, flags); 1091 1092 if (node->interrupts_active 1093 && interrupt_is_wanted(node, ih_ring_entry, 1094 patched_ihre, &is_patched) 1095 && enqueue_ih_ring_entry(node, 1096 is_patched ? patched_ihre : ih_ring_entry)) { 1097 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1098 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1099 return; 1100 } 1101 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1102 } 1103 1104 } 1105 1106 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1107 { 1108 struct kfd_process *p; 1109 int r; 1110 1111 /* Because we are called from arbitrary context (workqueue) as opposed 1112 * to process context, kfd_process could attempt to exit while we are 1113 * running so the lookup function increments the process ref count. 1114 */ 1115 p = kfd_lookup_process_by_mm(mm); 1116 if (!p) 1117 return -ESRCH; 1118 1119 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1120 r = kfd_process_evict_queues(p, trigger); 1121 1122 kfd_unref_process(p); 1123 return r; 1124 } 1125 1126 int kgd2kfd_resume_mm(struct mm_struct *mm) 1127 { 1128 struct kfd_process *p; 1129 int r; 1130 1131 /* Because we are called from arbitrary context (workqueue) as opposed 1132 * to process context, kfd_process could attempt to exit while we are 1133 * running so the lookup function increments the process ref count. 1134 */ 1135 p = kfd_lookup_process_by_mm(mm); 1136 if (!p) 1137 return -ESRCH; 1138 1139 r = kfd_process_restore_queues(p); 1140 1141 kfd_unref_process(p); 1142 return r; 1143 } 1144 1145 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1146 * prepare for safe eviction of KFD BOs that belong to the specified 1147 * process. 1148 * 1149 * @mm: mm_struct that identifies the specified KFD process 1150 * @fence: eviction fence attached to KFD process BOs 1151 * 1152 */ 1153 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1154 struct dma_fence *fence) 1155 { 1156 struct kfd_process *p; 1157 unsigned long active_time; 1158 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1159 1160 if (!fence) 1161 return -EINVAL; 1162 1163 if (dma_fence_is_signaled(fence)) 1164 return 0; 1165 1166 p = kfd_lookup_process_by_mm(mm); 1167 if (!p) 1168 return -ENODEV; 1169 1170 if (fence->seqno == p->last_eviction_seqno) 1171 goto out; 1172 1173 p->last_eviction_seqno = fence->seqno; 1174 1175 /* Avoid KFD process starvation. Wait for at least 1176 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1177 */ 1178 active_time = get_jiffies_64() - p->last_restore_timestamp; 1179 if (delay_jiffies > active_time) 1180 delay_jiffies -= active_time; 1181 else 1182 delay_jiffies = 0; 1183 1184 /* During process initialization eviction_work.dwork is initialized 1185 * to kfd_evict_bo_worker 1186 */ 1187 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1188 p->lead_thread->pid, delay_jiffies); 1189 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1190 out: 1191 kfd_unref_process(p); 1192 return 0; 1193 } 1194 1195 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1196 unsigned int chunk_size) 1197 { 1198 if (WARN_ON(buf_size < chunk_size)) 1199 return -EINVAL; 1200 if (WARN_ON(buf_size == 0)) 1201 return -EINVAL; 1202 if (WARN_ON(chunk_size == 0)) 1203 return -EINVAL; 1204 1205 kfd->gtt_sa_chunk_size = chunk_size; 1206 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1207 1208 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1209 GFP_KERNEL); 1210 if (!kfd->gtt_sa_bitmap) 1211 return -ENOMEM; 1212 1213 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1214 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1215 1216 mutex_init(&kfd->gtt_sa_lock); 1217 1218 return 0; 1219 } 1220 1221 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1222 { 1223 mutex_destroy(&kfd->gtt_sa_lock); 1224 bitmap_free(kfd->gtt_sa_bitmap); 1225 } 1226 1227 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1228 unsigned int bit_num, 1229 unsigned int chunk_size) 1230 { 1231 return start_addr + bit_num * chunk_size; 1232 } 1233 1234 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1235 unsigned int bit_num, 1236 unsigned int chunk_size) 1237 { 1238 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1239 } 1240 1241 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1242 struct kfd_mem_obj **mem_obj) 1243 { 1244 unsigned int found, start_search, cur_size; 1245 struct kfd_dev *kfd = node->kfd; 1246 1247 if (size == 0) 1248 return -EINVAL; 1249 1250 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1251 return -ENOMEM; 1252 1253 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1254 if (!(*mem_obj)) 1255 return -ENOMEM; 1256 1257 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1258 1259 start_search = 0; 1260 1261 mutex_lock(&kfd->gtt_sa_lock); 1262 1263 kfd_gtt_restart_search: 1264 /* Find the first chunk that is free */ 1265 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1266 kfd->gtt_sa_num_of_chunks, 1267 start_search); 1268 1269 pr_debug("Found = %d\n", found); 1270 1271 /* If there wasn't any free chunk, bail out */ 1272 if (found == kfd->gtt_sa_num_of_chunks) 1273 goto kfd_gtt_no_free_chunk; 1274 1275 /* Update fields of mem_obj */ 1276 (*mem_obj)->range_start = found; 1277 (*mem_obj)->range_end = found; 1278 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1279 kfd->gtt_start_gpu_addr, 1280 found, 1281 kfd->gtt_sa_chunk_size); 1282 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1283 kfd->gtt_start_cpu_ptr, 1284 found, 1285 kfd->gtt_sa_chunk_size); 1286 1287 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1288 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1289 1290 /* If we need only one chunk, mark it as allocated and get out */ 1291 if (size <= kfd->gtt_sa_chunk_size) { 1292 pr_debug("Single bit\n"); 1293 __set_bit(found, kfd->gtt_sa_bitmap); 1294 goto kfd_gtt_out; 1295 } 1296 1297 /* Otherwise, try to see if we have enough contiguous chunks */ 1298 cur_size = size - kfd->gtt_sa_chunk_size; 1299 do { 1300 (*mem_obj)->range_end = 1301 find_next_zero_bit(kfd->gtt_sa_bitmap, 1302 kfd->gtt_sa_num_of_chunks, ++found); 1303 /* 1304 * If next free chunk is not contiguous than we need to 1305 * restart our search from the last free chunk we found (which 1306 * wasn't contiguous to the previous ones 1307 */ 1308 if ((*mem_obj)->range_end != found) { 1309 start_search = found; 1310 goto kfd_gtt_restart_search; 1311 } 1312 1313 /* 1314 * If we reached end of buffer, bail out with error 1315 */ 1316 if (found == kfd->gtt_sa_num_of_chunks) 1317 goto kfd_gtt_no_free_chunk; 1318 1319 /* Check if we don't need another chunk */ 1320 if (cur_size <= kfd->gtt_sa_chunk_size) 1321 cur_size = 0; 1322 else 1323 cur_size -= kfd->gtt_sa_chunk_size; 1324 1325 } while (cur_size > 0); 1326 1327 pr_debug("range_start = %d, range_end = %d\n", 1328 (*mem_obj)->range_start, (*mem_obj)->range_end); 1329 1330 /* Mark the chunks as allocated */ 1331 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1332 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1333 1334 kfd_gtt_out: 1335 mutex_unlock(&kfd->gtt_sa_lock); 1336 return 0; 1337 1338 kfd_gtt_no_free_chunk: 1339 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1340 mutex_unlock(&kfd->gtt_sa_lock); 1341 kfree(*mem_obj); 1342 return -ENOMEM; 1343 } 1344 1345 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1346 { 1347 struct kfd_dev *kfd = node->kfd; 1348 1349 /* Act like kfree when trying to free a NULL object */ 1350 if (!mem_obj) 1351 return 0; 1352 1353 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1354 mem_obj, mem_obj->range_start, mem_obj->range_end); 1355 1356 mutex_lock(&kfd->gtt_sa_lock); 1357 1358 /* Mark the chunks as free */ 1359 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1360 mem_obj->range_end - mem_obj->range_start + 1); 1361 1362 mutex_unlock(&kfd->gtt_sa_lock); 1363 1364 kfree(mem_obj); 1365 return 0; 1366 } 1367 1368 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1369 { 1370 /* 1371 * TODO: Currently update SRAM ECC flag for first node. 1372 * This needs to be updated later when we can 1373 * identify SRAM ECC error on other nodes also. 1374 */ 1375 if (kfd) 1376 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1377 } 1378 1379 void kfd_inc_compute_active(struct kfd_node *node) 1380 { 1381 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1382 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1383 } 1384 1385 void kfd_dec_compute_active(struct kfd_node *node) 1386 { 1387 int count = atomic_dec_return(&node->kfd->compute_profile); 1388 1389 if (count == 0) 1390 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1391 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1392 } 1393 1394 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1395 { 1396 /* 1397 * TODO: For now, raise the throttling event only on first node. 1398 * This will need to change after we are able to determine 1399 * which node raised the throttling event. 1400 */ 1401 if (kfd && kfd->init_complete) 1402 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1403 throttle_bitmask); 1404 } 1405 1406 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1407 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1408 * When the device has more than two engines, we reserve two for PCIe to enable 1409 * full-duplex and the rest are used as XGMI. 1410 */ 1411 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1412 { 1413 /* If XGMI is not supported, all SDMA engines are PCIe */ 1414 if (!node->adev->gmc.xgmi.supported) 1415 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1416 1417 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1418 } 1419 1420 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1421 { 1422 /* After reserved for PCIe, the rest of engines are XGMI */ 1423 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1424 kfd_get_num_sdma_engines(node); 1425 } 1426 1427 int kgd2kfd_check_and_lock_kfd(void) 1428 { 1429 mutex_lock(&kfd_processes_mutex); 1430 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1431 mutex_unlock(&kfd_processes_mutex); 1432 return -EBUSY; 1433 } 1434 1435 ++kfd_locked; 1436 mutex_unlock(&kfd_processes_mutex); 1437 1438 return 0; 1439 } 1440 1441 void kgd2kfd_unlock_kfd(void) 1442 { 1443 mutex_lock(&kfd_processes_mutex); 1444 --kfd_locked; 1445 mutex_unlock(&kfd_processes_mutex); 1446 } 1447 1448 #if defined(CONFIG_DEBUG_FS) 1449 1450 /* This function will send a package to HIQ to hang the HWS 1451 * which will trigger a GPU reset and bring the HWS back to normal state 1452 */ 1453 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1454 { 1455 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1456 pr_err("HWS is not enabled"); 1457 return -EINVAL; 1458 } 1459 1460 return dqm_debugfs_hang_hws(dev->dqm); 1461 } 1462 1463 #endif 1464