1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(4, 4, 5): 88 case IP_VERSION(4, 4, 4): 89 case IP_VERSION(5, 0, 0):/* NAVI10 */ 90 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 91 case IP_VERSION(5, 0, 2):/* NAVI14 */ 92 case IP_VERSION(5, 0, 5):/* NAVI12 */ 93 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 94 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 95 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 96 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 97 kfd->device_info.num_sdma_queues_per_engine = 8; 98 break; 99 case IP_VERSION(6, 0, 0): 100 case IP_VERSION(6, 0, 1): 101 case IP_VERSION(6, 0, 2): 102 case IP_VERSION(6, 0, 3): 103 case IP_VERSION(6, 1, 0): 104 case IP_VERSION(6, 1, 1): 105 case IP_VERSION(6, 1, 2): 106 case IP_VERSION(6, 1, 3): 107 case IP_VERSION(7, 0, 0): 108 case IP_VERSION(7, 0, 1): 109 case IP_VERSION(7, 1, 0): 110 kfd->device_info.num_sdma_queues_per_engine = 8; 111 /* Reserve 1 for paging and 1 for gfx */ 112 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 113 break; 114 default: 115 dev_warn(kfd_device, 116 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 117 sdma_version); 118 kfd->device_info.num_sdma_queues_per_engine = 8; 119 } 120 } 121 122 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 123 { 124 uint32_t gc_version = KFD_GC_VERSION(kfd); 125 126 switch (gc_version) { 127 case IP_VERSION(9, 0, 1): /* VEGA10 */ 128 case IP_VERSION(9, 1, 0): /* RAVEN */ 129 case IP_VERSION(9, 2, 1): /* VEGA12 */ 130 case IP_VERSION(9, 2, 2): /* RAVEN */ 131 case IP_VERSION(9, 3, 0): /* RENOIR */ 132 case IP_VERSION(9, 4, 0): /* VEGA20 */ 133 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 134 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 135 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 136 break; 137 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 138 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 139 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */ 140 kfd->device_info.event_interrupt_class = 141 &event_interrupt_class_v9_4_3; 142 break; 143 case IP_VERSION(10, 3, 1): /* VANGOGH */ 144 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 145 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 146 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 147 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 148 case IP_VERSION(10, 1, 4): 149 case IP_VERSION(10, 1, 10): /* NAVI10 */ 150 case IP_VERSION(10, 1, 2): /* NAVI12 */ 151 case IP_VERSION(10, 1, 1): /* NAVI14 */ 152 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 153 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 154 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 155 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 156 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 157 break; 158 case IP_VERSION(11, 0, 0): 159 case IP_VERSION(11, 0, 1): 160 case IP_VERSION(11, 0, 2): 161 case IP_VERSION(11, 0, 3): 162 case IP_VERSION(11, 0, 4): 163 case IP_VERSION(11, 5, 0): 164 case IP_VERSION(11, 5, 1): 165 case IP_VERSION(11, 5, 2): 166 case IP_VERSION(11, 5, 3): 167 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 168 break; 169 case IP_VERSION(12, 0, 0): 170 case IP_VERSION(12, 0, 1): 171 /* GFX12_TODO: Change to v12 version. */ 172 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 173 break; 174 case IP_VERSION(12, 1, 0): 175 kfd->device_info.event_interrupt_class = 176 &event_interrupt_class_v12_1; 177 break; 178 default: 179 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 180 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 181 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 182 } 183 } 184 185 static void kfd_device_info_init(struct kfd_dev *kfd, 186 bool vf, uint32_t gfx_target_version) 187 { 188 uint32_t gc_version = KFD_GC_VERSION(kfd); 189 uint32_t asic_type = kfd->adev->asic_type; 190 191 kfd->device_info.max_pasid_bits = 16; 192 kfd->device_info.max_no_of_hqd = 24; 193 kfd->device_info.num_of_watch_points = 4; 194 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 195 kfd->device_info.gfx_target_version = gfx_target_version; 196 197 if (KFD_IS_SOC15(kfd)) { 198 kfd->device_info.doorbell_size = 8; 199 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 200 kfd->device_info.supports_cwsr = true; 201 202 kfd_device_info_set_sdma_info(kfd); 203 204 kfd_device_info_set_event_interrupt_class(kfd); 205 206 if (gc_version < IP_VERSION(11, 0, 0)) { 207 /* Navi2x+, Navi1x+ */ 208 if (gc_version == IP_VERSION(10, 3, 6)) 209 kfd->device_info.no_atomic_fw_version = 14; 210 else if (gc_version == IP_VERSION(10, 3, 7)) 211 kfd->device_info.no_atomic_fw_version = 3; 212 else if (gc_version >= IP_VERSION(10, 3, 0)) 213 kfd->device_info.no_atomic_fw_version = 92; 214 else if (gc_version >= IP_VERSION(10, 1, 1)) 215 kfd->device_info.no_atomic_fw_version = 145; 216 217 /* Navi1x+ */ 218 if (gc_version >= IP_VERSION(10, 1, 1)) 219 kfd->device_info.needs_pci_atomics = true; 220 } else if (gc_version < IP_VERSION(12, 0, 0)) { 221 /* 222 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 223 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 224 * PCIe atomics support. 225 */ 226 kfd->device_info.needs_pci_atomics = true; 227 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 228 } else if (gc_version < IP_VERSION(13, 0, 0)) { 229 kfd->device_info.needs_pci_atomics = true; 230 kfd->device_info.no_atomic_fw_version = 2090; 231 } else { 232 kfd->device_info.needs_pci_atomics = true; 233 } 234 } else { 235 kfd->device_info.doorbell_size = 4; 236 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 237 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 238 kfd->device_info.num_sdma_queues_per_engine = 2; 239 240 if (asic_type != CHIP_KAVERI && 241 asic_type != CHIP_HAWAII && 242 asic_type != CHIP_TONGA) 243 kfd->device_info.supports_cwsr = true; 244 245 if (asic_type != CHIP_HAWAII && !vf) 246 kfd->device_info.needs_pci_atomics = true; 247 } 248 } 249 250 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 251 { 252 struct kfd_dev *kfd = NULL; 253 const struct kfd2kgd_calls *f2g = NULL; 254 uint32_t gfx_target_version = 0; 255 256 switch (adev->asic_type) { 257 #ifdef CONFIG_DRM_AMDGPU_CIK 258 case CHIP_KAVERI: 259 gfx_target_version = 70000; 260 if (!vf) 261 f2g = &gfx_v7_kfd2kgd; 262 break; 263 #endif 264 case CHIP_CARRIZO: 265 gfx_target_version = 80001; 266 if (!vf) 267 f2g = &gfx_v8_kfd2kgd; 268 break; 269 #ifdef CONFIG_DRM_AMDGPU_CIK 270 case CHIP_HAWAII: 271 gfx_target_version = 70001; 272 if (!amdgpu_exp_hw_support) 273 pr_info( 274 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 275 ); 276 else if (!vf) 277 f2g = &gfx_v7_kfd2kgd; 278 break; 279 #endif 280 case CHIP_TONGA: 281 gfx_target_version = 80002; 282 if (!vf) 283 f2g = &gfx_v8_kfd2kgd; 284 break; 285 case CHIP_FIJI: 286 case CHIP_POLARIS10: 287 gfx_target_version = 80003; 288 f2g = &gfx_v8_kfd2kgd; 289 break; 290 case CHIP_POLARIS11: 291 case CHIP_POLARIS12: 292 case CHIP_VEGAM: 293 gfx_target_version = 80003; 294 if (!vf) 295 f2g = &gfx_v8_kfd2kgd; 296 break; 297 default: 298 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 299 /* Vega 10 */ 300 case IP_VERSION(9, 0, 1): 301 gfx_target_version = 90000; 302 f2g = &gfx_v9_kfd2kgd; 303 break; 304 /* Raven */ 305 case IP_VERSION(9, 1, 0): 306 case IP_VERSION(9, 2, 2): 307 gfx_target_version = 90002; 308 if (!vf) 309 f2g = &gfx_v9_kfd2kgd; 310 break; 311 /* Vega12 */ 312 case IP_VERSION(9, 2, 1): 313 gfx_target_version = 90004; 314 if (!vf) 315 f2g = &gfx_v9_kfd2kgd; 316 break; 317 /* Renoir */ 318 case IP_VERSION(9, 3, 0): 319 gfx_target_version = 90012; 320 if (!vf) 321 f2g = &gfx_v9_kfd2kgd; 322 break; 323 /* Vega20 */ 324 case IP_VERSION(9, 4, 0): 325 gfx_target_version = 90006; 326 if (!vf) 327 f2g = &gfx_v9_kfd2kgd; 328 break; 329 /* Arcturus */ 330 case IP_VERSION(9, 4, 1): 331 gfx_target_version = 90008; 332 f2g = &arcturus_kfd2kgd; 333 break; 334 /* Aldebaran */ 335 case IP_VERSION(9, 4, 2): 336 gfx_target_version = 90010; 337 f2g = &aldebaran_kfd2kgd; 338 break; 339 case IP_VERSION(9, 4, 3): 340 case IP_VERSION(9, 4, 4): 341 gfx_target_version = 90402; 342 f2g = &gc_9_4_3_kfd2kgd; 343 break; 344 case IP_VERSION(9, 5, 0): 345 gfx_target_version = 90500; 346 f2g = &gc_9_4_3_kfd2kgd; 347 break; 348 /* Navi10 */ 349 case IP_VERSION(10, 1, 10): 350 gfx_target_version = 100100; 351 if (!vf) 352 f2g = &gfx_v10_kfd2kgd; 353 break; 354 /* Navi12 */ 355 case IP_VERSION(10, 1, 2): 356 gfx_target_version = 100101; 357 f2g = &gfx_v10_kfd2kgd; 358 break; 359 /* Navi14 */ 360 case IP_VERSION(10, 1, 1): 361 gfx_target_version = 100102; 362 if (!vf) 363 f2g = &gfx_v10_kfd2kgd; 364 break; 365 /* Cyan Skillfish */ 366 case IP_VERSION(10, 1, 3): 367 case IP_VERSION(10, 1, 4): 368 gfx_target_version = 100103; 369 if (!vf) 370 f2g = &gfx_v10_kfd2kgd; 371 break; 372 /* Sienna Cichlid */ 373 case IP_VERSION(10, 3, 0): 374 gfx_target_version = 100300; 375 f2g = &gfx_v10_3_kfd2kgd; 376 break; 377 /* Navy Flounder */ 378 case IP_VERSION(10, 3, 2): 379 gfx_target_version = 100301; 380 f2g = &gfx_v10_3_kfd2kgd; 381 break; 382 /* Van Gogh */ 383 case IP_VERSION(10, 3, 1): 384 gfx_target_version = 100303; 385 if (!vf) 386 f2g = &gfx_v10_3_kfd2kgd; 387 break; 388 /* Dimgrey Cavefish */ 389 case IP_VERSION(10, 3, 4): 390 gfx_target_version = 100302; 391 f2g = &gfx_v10_3_kfd2kgd; 392 break; 393 /* Beige Goby */ 394 case IP_VERSION(10, 3, 5): 395 gfx_target_version = 100304; 396 f2g = &gfx_v10_3_kfd2kgd; 397 break; 398 /* Yellow Carp */ 399 case IP_VERSION(10, 3, 3): 400 gfx_target_version = 100305; 401 if (!vf) 402 f2g = &gfx_v10_3_kfd2kgd; 403 break; 404 case IP_VERSION(10, 3, 6): 405 case IP_VERSION(10, 3, 7): 406 gfx_target_version = 100306; 407 if (!vf) 408 f2g = &gfx_v10_3_kfd2kgd; 409 break; 410 case IP_VERSION(11, 0, 0): 411 gfx_target_version = 110000; 412 f2g = &gfx_v11_kfd2kgd; 413 break; 414 case IP_VERSION(11, 0, 1): 415 case IP_VERSION(11, 0, 4): 416 gfx_target_version = 110003; 417 f2g = &gfx_v11_kfd2kgd; 418 break; 419 case IP_VERSION(11, 0, 2): 420 gfx_target_version = 110002; 421 f2g = &gfx_v11_kfd2kgd; 422 break; 423 case IP_VERSION(11, 0, 3): 424 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 425 gfx_target_version = 110001; 426 f2g = &gfx_v11_kfd2kgd; 427 break; 428 case IP_VERSION(11, 5, 0): 429 gfx_target_version = 110500; 430 f2g = &gfx_v11_kfd2kgd; 431 break; 432 case IP_VERSION(11, 5, 1): 433 gfx_target_version = 110501; 434 f2g = &gfx_v11_kfd2kgd; 435 break; 436 case IP_VERSION(11, 5, 2): 437 gfx_target_version = 110502; 438 f2g = &gfx_v11_kfd2kgd; 439 break; 440 case IP_VERSION(11, 5, 3): 441 gfx_target_version = 110503; 442 f2g = &gfx_v11_kfd2kgd; 443 break; 444 case IP_VERSION(12, 0, 0): 445 gfx_target_version = 120000; 446 f2g = &gfx_v12_kfd2kgd; 447 break; 448 case IP_VERSION(12, 0, 1): 449 gfx_target_version = 120001; 450 f2g = &gfx_v12_kfd2kgd; 451 break; 452 case IP_VERSION(12, 1, 0): 453 gfx_target_version = 120500; 454 f2g = &gfx_v12_kfd2kgd; 455 break; 456 default: 457 break; 458 } 459 break; 460 } 461 462 if (!f2g) { 463 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 464 dev_info(kfd_device, 465 "GC IP %06x %s not supported in kfd\n", 466 amdgpu_ip_version(adev, GC_HWIP, 0), 467 vf ? "VF" : ""); 468 else 469 dev_info(kfd_device, "%s %s not supported in kfd\n", 470 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 471 return NULL; 472 } 473 474 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 475 if (!kfd) 476 return NULL; 477 478 kfd->adev = adev; 479 kfd_device_info_init(kfd, vf, gfx_target_version); 480 kfd->init_complete = false; 481 kfd->kfd2kgd = f2g; 482 atomic_set(&kfd->compute_profile, 0); 483 484 mutex_init(&kfd->doorbell_mutex); 485 486 ida_init(&kfd->doorbell_ida); 487 atomic_set(&kfd->kfd_processes_count, 0); 488 489 return kfd; 490 } 491 492 static void kfd_cwsr_init(struct kfd_dev *kfd) 493 { 494 if (cwsr_enable && kfd->device_info.supports_cwsr) { 495 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 496 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 497 > KFD_CWSR_TMA_OFFSET); 498 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 499 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 500 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 501 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 502 > KFD_CWSR_TMA_OFFSET); 503 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 504 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 505 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 506 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 507 > KFD_CWSR_TMA_OFFSET); 508 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 509 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 510 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 511 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 512 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 513 > KFD_CWSR_TMA_OFFSET); 514 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 515 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 516 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) { 517 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE); 518 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex; 519 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex); 520 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 521 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 522 > KFD_CWSR_TMA_OFFSET); 523 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 524 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 525 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 526 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 527 > KFD_CWSR_TMA_OFFSET); 528 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 529 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 530 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 531 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 532 > KFD_CWSR_TMA_OFFSET); 533 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 534 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 535 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 536 /* The gfx11 cwsr trap handler must fit inside a single 537 page. */ 538 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 539 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 540 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 541 } else { 542 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 543 > KFD_CWSR_TMA_OFFSET); 544 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 545 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 546 } 547 548 kfd->cwsr_enabled = true; 549 } 550 } 551 552 static int kfd_gws_init(struct kfd_node *node) 553 { 554 int ret = 0; 555 struct kfd_dev *kfd = node->kfd; 556 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 557 558 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 559 return 0; 560 561 if (hws_gws_support || (KFD_IS_SOC15(node) && 562 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 563 && kfd->mec2_fw_version >= 0x81b3) || 564 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 565 && kfd->mec2_fw_version >= 0x1b3) || 566 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 567 && kfd->mec2_fw_version >= 0x30) || 568 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 569 && kfd->mec2_fw_version >= 0x28) || 570 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 571 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 572 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) || 573 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 574 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 575 && kfd->mec2_fw_version >= 0x6b) || 576 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 577 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 578 && mes_rev >= 68) || 579 (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))))) { 580 if (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0)) 581 node->adev->gds.gws_size = 64; 582 ret = amdgpu_amdkfd_alloc_gws(node->adev, 583 node->adev->gds.gws_size, &node->gws); 584 } 585 586 return ret; 587 } 588 589 static void kfd_smi_init(struct kfd_node *dev) 590 { 591 INIT_LIST_HEAD(&dev->smi_clients); 592 spin_lock_init(&dev->smi_lock); 593 } 594 595 static int kfd_init_node(struct kfd_node *node) 596 { 597 int err = -1; 598 599 if (kfd_interrupt_init(node)) { 600 dev_err(kfd_device, "Error initializing interrupts\n"); 601 goto kfd_interrupt_error; 602 } 603 604 node->dqm = device_queue_manager_init(node); 605 if (!node->dqm) { 606 dev_err(kfd_device, "Error initializing queue manager\n"); 607 goto device_queue_manager_error; 608 } 609 610 if (kfd_gws_init(node)) { 611 dev_err(kfd_device, "Could not allocate %d gws\n", 612 node->adev->gds.gws_size); 613 goto gws_error; 614 } 615 616 if (kfd_resume(node)) 617 goto kfd_resume_error; 618 619 if (kfd_topology_add_device(node)) { 620 dev_err(kfd_device, "Error adding device to topology\n"); 621 goto kfd_topology_add_device_error; 622 } 623 624 kfd_smi_init(node); 625 626 return 0; 627 628 kfd_topology_add_device_error: 629 kfd_resume_error: 630 gws_error: 631 device_queue_manager_uninit(node->dqm); 632 device_queue_manager_error: 633 kfd_interrupt_exit(node); 634 kfd_interrupt_error: 635 if (node->gws) 636 amdgpu_amdkfd_free_gws(node->adev, node->gws); 637 638 /* Cleanup the node memory here */ 639 kfree(node); 640 return err; 641 } 642 643 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 644 { 645 struct kfd_node *knode; 646 unsigned int i; 647 648 /* 649 * flush_work ensures that there are no outstanding 650 * work-queue items that will access interrupt_ring. New work items 651 * can't be created because we stopped interrupt handling above. 652 */ 653 flush_workqueue(kfd->ih_wq); 654 destroy_workqueue(kfd->ih_wq); 655 656 for (i = 0; i < num_nodes; i++) { 657 knode = kfd->nodes[i]; 658 device_queue_manager_uninit(knode->dqm); 659 kfd_interrupt_exit(knode); 660 kfd_topology_remove_device(knode); 661 if (knode->gws) 662 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 663 kfree(knode); 664 kfd->nodes[i] = NULL; 665 } 666 } 667 668 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 669 unsigned int kfd_node_idx) 670 { 671 struct amdgpu_device *adev = node->adev; 672 uint32_t xcc_mask = node->xcc_mask; 673 uint32_t xcc, mapped_xcc; 674 uint32_t bitmap; 675 /* 676 * Interrupt bitmap is setup for processing interrupts from 677 * different XCDs and AIDs. 678 * Interrupt bitmap is defined as follows: 679 * 1. Bits 0-15 - correspond to the NodeId field. 680 * Each bit corresponds to NodeId number. For example, if 681 * a KFD node has interrupt bitmap set to 0x7, then this 682 * KFD node will process interrupts with NodeId = 0, 1 and 2 683 * in the IH cookie. 684 * 2. Bits 16-31 - unused. 685 * 686 * Please note that the kfd_node_idx argument passed to this 687 * function is not related to NodeId field received in the 688 * IH cookie. 689 * 690 * In CPX mode, a KFD node will process an interrupt if: 691 * - the Node Id matches the corresponding bit set in 692 * Bits 0-15. 693 * - AND VMID reported in the interrupt lies within the 694 * VMID range of the node. 695 */ 696 switch (KFD_GC_VERSION(node)) { 697 case IP_VERSION(12, 1, 0): 698 for_each_inst(xcc, xcc_mask) { 699 mapped_xcc = GET_INST(GC, xcc); 700 bitmap = 0x2 | (0x4 << (mapped_xcc % 4)); 701 if (mapped_xcc/4) 702 bitmap = bitmap << 8; 703 node->interrupt_bitmap |= bitmap; 704 } 705 break; 706 default: 707 for_each_inst(xcc, xcc_mask) { 708 mapped_xcc = GET_INST(GC, xcc); 709 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 710 } 711 break; 712 } 713 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 714 node->interrupt_bitmap); 715 } 716 717 bool kgd2kfd_device_init(struct kfd_dev *kfd, 718 const struct kgd2kfd_shared_resources *gpu_resources) 719 { 720 unsigned int size, map_process_packet_size, i; 721 struct kfd_node *node; 722 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 723 unsigned int max_proc_per_quantum; 724 int partition_mode; 725 int xcp_idx; 726 727 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 728 KGD_ENGINE_MEC1); 729 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 730 KGD_ENGINE_MEC2); 731 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 732 KGD_ENGINE_SDMA1); 733 kfd->shared_resources = *gpu_resources; 734 735 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 736 737 if (kfd->num_nodes == 0) { 738 dev_err(kfd_device, 739 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 740 kfd->adev->gfx.num_xcc_per_xcp); 741 goto out; 742 } 743 744 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 745 * 32 and 64-bit requests are possible and must be 746 * supported. 747 */ 748 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 749 if (!kfd->pci_atomic_requested && 750 kfd->device_info.needs_pci_atomics && 751 (!kfd->device_info.no_atomic_fw_version || 752 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 753 dev_info(kfd_device, 754 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 755 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 756 kfd->mec_fw_version, 757 kfd->device_info.no_atomic_fw_version); 758 return false; 759 } 760 761 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 762 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 763 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 764 765 /* For multi-partition capable GPUs, we need special handling for VMIDs 766 * depending on partition mode. 767 * In CPX mode, the VMID range needs to be shared between XCDs. 768 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 769 * divide them equally, we change starting VMID to 4 and not use 770 * VMID 3. 771 * If the VMID range changes for multi-partition capable GPUs, then 772 * this code MUST be revisited. 773 */ 774 if (kfd->adev->xcp_mgr && (KFD_GC_VERSION(kfd) != IP_VERSION(12, 1, 0))) { 775 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 776 AMDGPU_XCP_FL_LOCKED); 777 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 778 kfd->num_nodes != 1) { 779 vmid_num_kfd /= 2; 780 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 781 } 782 } 783 784 /* Verify module parameters regarding mapped process number*/ 785 if (hws_max_conc_proc >= 0) 786 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 787 else 788 max_proc_per_quantum = vmid_num_kfd; 789 790 /* calculate max size of mqds needed for queues */ 791 size = max_num_of_queues_per_device * 792 kfd->device_info.mqd_size_aligned; 793 794 /* 795 * calculate max size of runlist packet. 796 * There can be only 2 packets at once 797 */ 798 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 799 sizeof(struct pm4_mes_map_process_aldebaran) : 800 sizeof(struct pm4_mes_map_process); 801 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 802 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 803 + sizeof(struct pm4_mes_runlist)) * 2; 804 805 /* Add size of HIQ & DIQ */ 806 size += KFD_KERNEL_QUEUE_SIZE * 2; 807 808 /* add another 512KB for all other allocations on gart (HPD, fences) */ 809 size += 512 * 1024; 810 811 if (amdgpu_amdkfd_alloc_gtt_mem( 812 kfd->adev, size, &kfd->gtt_mem, 813 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 814 false)) { 815 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 816 goto alloc_gtt_mem_failure; 817 } 818 819 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 820 821 /* Initialize GTT sa with 512 byte chunk size */ 822 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 823 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 824 goto kfd_gtt_sa_init_error; 825 } 826 827 if (kfd_doorbell_init(kfd)) { 828 dev_err(kfd_device, 829 "Error initializing doorbell aperture\n"); 830 goto kfd_doorbell_error; 831 } 832 833 if (amdgpu_use_xgmi_p2p) 834 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 835 836 /* 837 * For multi-partition capable GPUs, the KFD abstracts all partitions 838 * within a socket as xGMI connected in the topology so assign a unique 839 * hive id per device based on the pci device location if device is in 840 * PCIe mode. 841 */ 842 if (!kfd->hive_id && kfd->num_nodes > 1) 843 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 844 845 kfd->noretry = kfd->adev->gmc.noretry; 846 847 kfd_cwsr_init(kfd); 848 849 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 850 kfd->num_nodes); 851 852 /* Allocate the KFD nodes */ 853 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 854 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 855 if (!node) 856 goto node_alloc_error; 857 858 node->node_id = i; 859 node->adev = kfd->adev; 860 node->kfd = kfd; 861 node->kfd2kgd = kfd->kfd2kgd; 862 node->vm_info.vmid_num_kfd = vmid_num_kfd; 863 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 864 /* TODO : Check if error handling is needed */ 865 if (node->xcp) { 866 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 867 &node->xcc_mask); 868 ++xcp_idx; 869 } else { 870 node->xcc_mask = 871 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 872 } 873 874 if (node->xcp) { 875 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 876 node->node_id, node->xcp->mem_id, 877 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 878 } 879 880 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 881 kfd->num_nodes != 1) { 882 /* For multi-partition capable GPUs and CPX mode, first 883 * XCD gets VMID range 4-9 and second XCD gets VMID 884 * range 10-15. 885 */ 886 887 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 888 first_vmid_kfd : 889 first_vmid_kfd+vmid_num_kfd; 890 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 891 last_vmid_kfd-vmid_num_kfd : 892 last_vmid_kfd; 893 node->compute_vmid_bitmap = 894 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 895 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 896 } else { 897 node->vm_info.first_vmid_kfd = first_vmid_kfd; 898 node->vm_info.last_vmid_kfd = last_vmid_kfd; 899 node->compute_vmid_bitmap = 900 gpu_resources->compute_vmid_bitmap; 901 } 902 node->max_proc_per_quantum = max_proc_per_quantum; 903 atomic_set(&node->sram_ecc_flag, 0); 904 905 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 906 &node->local_mem_info, node->xcp); 907 908 if (kfd->adev->xcp_mgr) 909 kfd_setup_interrupt_bitmap(node, i); 910 911 /* Initialize the KFD node */ 912 if (kfd_init_node(node)) { 913 dev_err(kfd_device, "Error initializing KFD node\n"); 914 goto node_init_error; 915 } 916 917 spin_lock_init(&node->watch_points_lock); 918 919 kfd->nodes[i] = node; 920 } 921 922 svm_range_set_max_pages(kfd->adev); 923 924 kfd->init_complete = true; 925 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 926 kfd->adev->pdev->device); 927 928 pr_debug("Starting kfd with the following scheduling policy %d\n", 929 node->dqm->sched_policy); 930 931 goto out; 932 933 node_init_error: 934 node_alloc_error: 935 kfd_cleanup_nodes(kfd, i); 936 kfd_doorbell_fini(kfd); 937 kfd_doorbell_error: 938 kfd_gtt_sa_fini(kfd); 939 kfd_gtt_sa_init_error: 940 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 941 alloc_gtt_mem_failure: 942 dev_err(kfd_device, 943 "device %x:%x NOT added due to errors\n", 944 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 945 out: 946 return kfd->init_complete; 947 } 948 949 void kgd2kfd_device_exit(struct kfd_dev *kfd) 950 { 951 if (kfd->init_complete) { 952 /* Cleanup KFD nodes */ 953 kfd_cleanup_nodes(kfd, kfd->num_nodes); 954 /* Cleanup common/shared resources */ 955 kfd_doorbell_fini(kfd); 956 ida_destroy(&kfd->doorbell_ida); 957 kfd_gtt_sa_fini(kfd); 958 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 959 } 960 961 kfree(kfd); 962 } 963 964 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 965 struct amdgpu_reset_context *reset_context) 966 { 967 struct kfd_node *node; 968 int i; 969 970 if (!kfd->init_complete) 971 return 0; 972 973 for (i = 0; i < kfd->num_nodes; i++) { 974 node = kfd->nodes[i]; 975 kfd_smi_event_update_gpu_reset(node, false, reset_context); 976 } 977 978 kgd2kfd_suspend(kfd, true); 979 980 for (i = 0; i < kfd->num_nodes; i++) 981 kfd_signal_reset_event(kfd->nodes[i]); 982 983 return 0; 984 } 985 986 /* 987 * Fix me. KFD won't be able to resume existing process for now. 988 * We will keep all existing process in a evicted state and 989 * wait the process to be terminated. 990 */ 991 992 int kgd2kfd_post_reset(struct kfd_dev *kfd) 993 { 994 int ret; 995 struct kfd_node *node; 996 int i; 997 998 if (!kfd->init_complete) 999 return 0; 1000 1001 for (i = 0; i < kfd->num_nodes; i++) { 1002 ret = kfd_resume(kfd->nodes[i]); 1003 if (ret) 1004 return ret; 1005 } 1006 1007 mutex_lock(&kfd_processes_mutex); 1008 --kfd_locked; 1009 mutex_unlock(&kfd_processes_mutex); 1010 1011 for (i = 0; i < kfd->num_nodes; i++) { 1012 node = kfd->nodes[i]; 1013 atomic_set(&node->sram_ecc_flag, 0); 1014 kfd_smi_event_update_gpu_reset(node, true, NULL); 1015 } 1016 1017 return 0; 1018 } 1019 1020 bool kfd_is_locked(struct kfd_dev *kfd) 1021 { 1022 uint8_t id = 0; 1023 struct kfd_node *dev; 1024 1025 lockdep_assert_held(&kfd_processes_mutex); 1026 1027 /* check reset/suspend lock */ 1028 if (kfd_locked > 0) 1029 return true; 1030 1031 if (kfd) 1032 return kfd->kfd_dev_lock > 0; 1033 1034 /* check lock on all cgroup accessible devices */ 1035 while (kfd_topology_enum_kfd_devices(id++, &dev) == 0) { 1036 if (!dev || kfd_devcgroup_check_permission(dev)) 1037 continue; 1038 1039 if (dev->kfd->kfd_dev_lock > 0) 1040 return true; 1041 } 1042 1043 return false; 1044 } 1045 1046 void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) 1047 { 1048 struct kfd_node *node; 1049 int i; 1050 1051 if (!kfd->init_complete) 1052 return; 1053 1054 if (suspend_proc) 1055 kgd2kfd_suspend_process(kfd); 1056 1057 for (i = 0; i < kfd->num_nodes; i++) { 1058 node = kfd->nodes[i]; 1059 node->dqm->ops.stop(node->dqm); 1060 } 1061 } 1062 1063 int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) 1064 { 1065 int ret = 0, i; 1066 1067 if (!kfd->init_complete) 1068 return 0; 1069 1070 for (i = 0; i < kfd->num_nodes; i++) { 1071 ret = kfd_resume(kfd->nodes[i]); 1072 if (ret) 1073 return ret; 1074 } 1075 1076 if (resume_proc) 1077 ret = kgd2kfd_resume_process(kfd); 1078 1079 return ret; 1080 } 1081 1082 void kgd2kfd_suspend_process(struct kfd_dev *kfd) 1083 { 1084 if (!kfd->init_complete) 1085 return; 1086 1087 mutex_lock(&kfd_processes_mutex); 1088 /* For first KFD device suspend all the KFD processes */ 1089 if (++kfd_locked == 1) 1090 kfd_suspend_all_processes(); 1091 mutex_unlock(&kfd_processes_mutex); 1092 } 1093 1094 int kgd2kfd_resume_process(struct kfd_dev *kfd) 1095 { 1096 int ret = 0; 1097 1098 if (!kfd->init_complete) 1099 return 0; 1100 1101 mutex_lock(&kfd_processes_mutex); 1102 if (--kfd_locked == 0) 1103 ret = kfd_resume_all_processes(); 1104 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1105 mutex_unlock(&kfd_processes_mutex); 1106 1107 return ret; 1108 } 1109 1110 static int kfd_resume(struct kfd_node *node) 1111 { 1112 int err = 0; 1113 1114 err = node->dqm->ops.start(node->dqm); 1115 if (err) 1116 dev_err(kfd_device, 1117 "Error starting queue manager for device %x:%x\n", 1118 node->adev->pdev->vendor, node->adev->pdev->device); 1119 1120 return err; 1121 } 1122 1123 /* This is called directly from KGD at ISR. */ 1124 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1125 { 1126 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1127 bool is_patched = false; 1128 unsigned long flags; 1129 struct kfd_node *node; 1130 1131 if (!kfd->init_complete) 1132 return; 1133 1134 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1135 dev_err_once(kfd_device, "Ring entry too small\n"); 1136 return; 1137 } 1138 1139 for (i = 0; i < kfd->num_nodes; i++) { 1140 /* Race if another thread in b/w 1141 * kfd_cleanup_nodes and kfree(kfd), 1142 * when kfd->nodes[i] = NULL 1143 */ 1144 if (kfd->nodes[i]) 1145 node = kfd->nodes[i]; 1146 else 1147 return; 1148 1149 spin_lock_irqsave(&node->interrupt_lock, flags); 1150 1151 if (node->interrupts_active 1152 && interrupt_is_wanted(node, ih_ring_entry, 1153 patched_ihre, &is_patched) 1154 && enqueue_ih_ring_entry(node, 1155 is_patched ? patched_ihre : ih_ring_entry)) { 1156 queue_work(node->kfd->ih_wq, &node->interrupt_work); 1157 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1158 return; 1159 } 1160 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1161 } 1162 1163 } 1164 1165 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1166 { 1167 struct kfd_process *p; 1168 int r; 1169 1170 /* Because we are called from arbitrary context (workqueue) as opposed 1171 * to process context, kfd_process could attempt to exit while we are 1172 * running so the lookup function increments the process ref count. 1173 */ 1174 p = kfd_lookup_process_by_mm(mm); 1175 if (!p) 1176 return -ESRCH; 1177 1178 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1179 r = kfd_process_evict_queues(p, trigger); 1180 1181 kfd_unref_process(p); 1182 return r; 1183 } 1184 1185 int kgd2kfd_resume_mm(struct mm_struct *mm) 1186 { 1187 struct kfd_process *p; 1188 int r; 1189 1190 /* Because we are called from arbitrary context (workqueue) as opposed 1191 * to process context, kfd_process could attempt to exit while we are 1192 * running so the lookup function increments the process ref count. 1193 */ 1194 p = kfd_lookup_process_by_mm(mm); 1195 if (!p) 1196 return -ESRCH; 1197 1198 r = kfd_process_restore_queues(p); 1199 1200 kfd_unref_process(p); 1201 return r; 1202 } 1203 1204 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1205 * prepare for safe eviction of KFD BOs that belong to the specified 1206 * process. 1207 * 1208 * @mm: mm_struct that identifies a group of KFD processes 1209 * @context_id: an id that identifies a specific KFD context in the above kfd process group 1210 * @fence: eviction fence attached to KFD process BOs 1211 * 1212 */ 1213 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1214 u16 context_id, struct dma_fence *fence) 1215 { 1216 struct kfd_process *p; 1217 unsigned long active_time; 1218 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1219 1220 if (!fence) 1221 return -EINVAL; 1222 1223 if (dma_fence_is_signaled(fence)) 1224 return 0; 1225 1226 p = kfd_lookup_process_by_id(mm, context_id); 1227 if (!p) 1228 return -ENODEV; 1229 1230 if (fence->seqno == p->last_eviction_seqno) 1231 goto out; 1232 1233 p->last_eviction_seqno = fence->seqno; 1234 1235 /* Avoid KFD process starvation. Wait for at least 1236 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1237 */ 1238 active_time = get_jiffies_64() - p->last_restore_timestamp; 1239 if (delay_jiffies > active_time) 1240 delay_jiffies -= active_time; 1241 else 1242 delay_jiffies = 0; 1243 1244 /* During process initialization eviction_work.dwork is initialized 1245 * to kfd_evict_bo_worker 1246 */ 1247 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1248 p->lead_thread->pid, delay_jiffies); 1249 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1250 out: 1251 kfd_unref_process(p); 1252 return 0; 1253 } 1254 1255 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1256 unsigned int chunk_size) 1257 { 1258 if (WARN_ON(buf_size < chunk_size)) 1259 return -EINVAL; 1260 if (WARN_ON(buf_size == 0)) 1261 return -EINVAL; 1262 if (WARN_ON(chunk_size == 0)) 1263 return -EINVAL; 1264 1265 kfd->gtt_sa_chunk_size = chunk_size; 1266 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1267 1268 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1269 GFP_KERNEL); 1270 if (!kfd->gtt_sa_bitmap) 1271 return -ENOMEM; 1272 1273 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1274 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1275 1276 mutex_init(&kfd->gtt_sa_lock); 1277 1278 return 0; 1279 } 1280 1281 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1282 { 1283 mutex_destroy(&kfd->gtt_sa_lock); 1284 bitmap_free(kfd->gtt_sa_bitmap); 1285 } 1286 1287 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1288 unsigned int bit_num, 1289 unsigned int chunk_size) 1290 { 1291 return start_addr + bit_num * chunk_size; 1292 } 1293 1294 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1295 unsigned int bit_num, 1296 unsigned int chunk_size) 1297 { 1298 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1299 } 1300 1301 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1302 struct kfd_mem_obj **mem_obj) 1303 { 1304 unsigned int found, start_search, cur_size; 1305 struct kfd_dev *kfd = node->kfd; 1306 1307 if (size == 0) 1308 return -EINVAL; 1309 1310 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1311 return -ENOMEM; 1312 1313 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1314 if (!(*mem_obj)) 1315 return -ENOMEM; 1316 1317 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1318 1319 start_search = 0; 1320 1321 mutex_lock(&kfd->gtt_sa_lock); 1322 1323 kfd_gtt_restart_search: 1324 /* Find the first chunk that is free */ 1325 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1326 kfd->gtt_sa_num_of_chunks, 1327 start_search); 1328 1329 pr_debug("Found = %d\n", found); 1330 1331 /* If there wasn't any free chunk, bail out */ 1332 if (found == kfd->gtt_sa_num_of_chunks) 1333 goto kfd_gtt_no_free_chunk; 1334 1335 /* Update fields of mem_obj */ 1336 (*mem_obj)->range_start = found; 1337 (*mem_obj)->range_end = found; 1338 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1339 kfd->gtt_start_gpu_addr, 1340 found, 1341 kfd->gtt_sa_chunk_size); 1342 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1343 kfd->gtt_start_cpu_ptr, 1344 found, 1345 kfd->gtt_sa_chunk_size); 1346 1347 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1348 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1349 1350 /* If we need only one chunk, mark it as allocated and get out */ 1351 if (size <= kfd->gtt_sa_chunk_size) { 1352 pr_debug("Single bit\n"); 1353 __set_bit(found, kfd->gtt_sa_bitmap); 1354 goto kfd_gtt_out; 1355 } 1356 1357 /* Otherwise, try to see if we have enough contiguous chunks */ 1358 cur_size = size - kfd->gtt_sa_chunk_size; 1359 do { 1360 (*mem_obj)->range_end = 1361 find_next_zero_bit(kfd->gtt_sa_bitmap, 1362 kfd->gtt_sa_num_of_chunks, ++found); 1363 /* 1364 * If next free chunk is not contiguous than we need to 1365 * restart our search from the last free chunk we found (which 1366 * wasn't contiguous to the previous ones 1367 */ 1368 if ((*mem_obj)->range_end != found) { 1369 start_search = found; 1370 goto kfd_gtt_restart_search; 1371 } 1372 1373 /* 1374 * If we reached end of buffer, bail out with error 1375 */ 1376 if (found == kfd->gtt_sa_num_of_chunks) 1377 goto kfd_gtt_no_free_chunk; 1378 1379 /* Check if we don't need another chunk */ 1380 if (cur_size <= kfd->gtt_sa_chunk_size) 1381 cur_size = 0; 1382 else 1383 cur_size -= kfd->gtt_sa_chunk_size; 1384 1385 } while (cur_size > 0); 1386 1387 pr_debug("range_start = %d, range_end = %d\n", 1388 (*mem_obj)->range_start, (*mem_obj)->range_end); 1389 1390 /* Mark the chunks as allocated */ 1391 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1392 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1393 1394 kfd_gtt_out: 1395 mutex_unlock(&kfd->gtt_sa_lock); 1396 return 0; 1397 1398 kfd_gtt_no_free_chunk: 1399 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1400 mutex_unlock(&kfd->gtt_sa_lock); 1401 kfree(*mem_obj); 1402 return -ENOMEM; 1403 } 1404 1405 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1406 { 1407 struct kfd_dev *kfd = node->kfd; 1408 1409 /* Act like kfree when trying to free a NULL object */ 1410 if (!mem_obj) 1411 return 0; 1412 1413 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1414 mem_obj, mem_obj->range_start, mem_obj->range_end); 1415 1416 mutex_lock(&kfd->gtt_sa_lock); 1417 1418 /* Mark the chunks as free */ 1419 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1420 mem_obj->range_end - mem_obj->range_start + 1); 1421 1422 mutex_unlock(&kfd->gtt_sa_lock); 1423 1424 kfree(mem_obj); 1425 return 0; 1426 } 1427 1428 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1429 { 1430 /* 1431 * TODO: Currently update SRAM ECC flag for first node. 1432 * This needs to be updated later when we can 1433 * identify SRAM ECC error on other nodes also. 1434 */ 1435 if (kfd) 1436 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1437 } 1438 1439 void kfd_inc_compute_active(struct kfd_node *node) 1440 { 1441 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1442 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1443 } 1444 1445 void kfd_dec_compute_active(struct kfd_node *node) 1446 { 1447 int count = atomic_dec_return(&node->kfd->compute_profile); 1448 1449 if (count == 0) 1450 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1451 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1452 } 1453 1454 static bool kfd_compute_active(struct kfd_node *node) 1455 { 1456 if (atomic_read(&node->kfd->compute_profile)) 1457 return true; 1458 return false; 1459 } 1460 1461 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1462 { 1463 /* 1464 * TODO: For now, raise the throttling event only on first node. 1465 * This will need to change after we are able to determine 1466 * which node raised the throttling event. 1467 */ 1468 if (kfd && kfd->init_complete) 1469 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1470 throttle_bitmask); 1471 } 1472 1473 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1474 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1475 * When the device has more than two engines, we reserve two for PCIe to enable 1476 * full-duplex and the rest are used as XGMI. 1477 */ 1478 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1479 { 1480 /* If XGMI is not supported, all SDMA engines are PCIe */ 1481 if (!node->adev->gmc.xgmi.supported) 1482 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1483 1484 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1485 } 1486 1487 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1488 { 1489 /* After reserved for PCIe, the rest of engines are XGMI */ 1490 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1491 kfd_get_num_sdma_engines(node); 1492 } 1493 1494 int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) 1495 { 1496 struct kfd_process *p; 1497 int r = 0, temp, idx; 1498 1499 mutex_lock(&kfd_processes_mutex); 1500 1501 /* kfd_processes_count is per kfd_dev, return -EBUSY without 1502 * further check 1503 */ 1504 if (!!atomic_read(&kfd->kfd_processes_count)) { 1505 pr_debug("process_wq_release not finished\n"); 1506 r = -EBUSY; 1507 goto out; 1508 } 1509 1510 if (hash_empty(kfd_processes_table) && !kfd_is_locked(kfd)) 1511 goto out; 1512 1513 /* fail under system reset/resume or kfd device is partition switching. */ 1514 if (kfd_is_locked(kfd)) { 1515 r = -EBUSY; 1516 goto out; 1517 } 1518 1519 /* 1520 * ensure all running processes are cgroup excluded from device before mode switch. 1521 * i.e. no pdd was created on the process socket. 1522 */ 1523 idx = srcu_read_lock(&kfd_processes_srcu); 1524 hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { 1525 int i; 1526 1527 for (i = 0; i < p->n_pdds; i++) { 1528 if (p->pdds[i]->dev->kfd != kfd) 1529 continue; 1530 1531 r = -EBUSY; 1532 goto proc_check_unlock; 1533 } 1534 } 1535 1536 proc_check_unlock: 1537 srcu_read_unlock(&kfd_processes_srcu, idx); 1538 out: 1539 if (!r) 1540 ++kfd->kfd_dev_lock; 1541 mutex_unlock(&kfd_processes_mutex); 1542 1543 return r; 1544 } 1545 1546 void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) 1547 { 1548 mutex_lock(&kfd_processes_mutex); 1549 --kfd->kfd_dev_lock; 1550 mutex_unlock(&kfd_processes_mutex); 1551 } 1552 1553 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1554 { 1555 struct kfd_node *node; 1556 int ret; 1557 1558 if (!kfd->init_complete) 1559 return 0; 1560 1561 if (node_id >= kfd->num_nodes) { 1562 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1563 node_id, kfd->num_nodes - 1); 1564 return -EINVAL; 1565 } 1566 node = kfd->nodes[node_id]; 1567 1568 ret = node->dqm->ops.unhalt(node->dqm); 1569 if (ret) 1570 dev_err(kfd_device, "Error in starting scheduler\n"); 1571 1572 return ret; 1573 } 1574 1575 int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) 1576 { 1577 struct kfd_node *node; 1578 int i, r; 1579 1580 if (!kfd->init_complete) 1581 return 0; 1582 1583 for (i = 0; i < kfd->num_nodes; i++) { 1584 node = kfd->nodes[i]; 1585 r = node->dqm->ops.unhalt(node->dqm); 1586 if (r) { 1587 dev_err(kfd_device, "Error in starting scheduler\n"); 1588 return r; 1589 } 1590 } 1591 return 0; 1592 } 1593 1594 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1595 { 1596 struct kfd_node *node; 1597 1598 if (!kfd->init_complete) 1599 return 0; 1600 1601 if (node_id >= kfd->num_nodes) { 1602 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1603 node_id, kfd->num_nodes - 1); 1604 return -EINVAL; 1605 } 1606 1607 node = kfd->nodes[node_id]; 1608 return node->dqm->ops.halt(node->dqm); 1609 } 1610 1611 int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) 1612 { 1613 struct kfd_node *node; 1614 int i, r; 1615 1616 if (!kfd->init_complete) 1617 return 0; 1618 1619 for (i = 0; i < kfd->num_nodes; i++) { 1620 node = kfd->nodes[i]; 1621 r = node->dqm->ops.halt(node->dqm); 1622 if (r) 1623 return r; 1624 } 1625 return 0; 1626 } 1627 1628 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1629 { 1630 struct kfd_node *node; 1631 1632 if (!kfd->init_complete) 1633 return false; 1634 1635 if (node_id >= kfd->num_nodes) { 1636 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1637 node_id, kfd->num_nodes - 1); 1638 return false; 1639 } 1640 1641 node = kfd->nodes[node_id]; 1642 1643 return kfd_compute_active(node); 1644 } 1645 1646 /** 1647 * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9 1648 * @adev: amdgpu device 1649 * @entry: vm fault interrupt vector 1650 * @retry_fault: if this is retry fault 1651 * 1652 * retry fault - 1653 * with CAM enabled, adev primary ring 1654 * | gmc_v9_0_process_interrupt() 1655 * adev soft_ring 1656 * | gmc_v9_0_process_interrupt() worker failed to recover page fault 1657 * KFD node ih_fifo 1658 * | KFD interrupt_wq worker 1659 * kfd_signal_vm_fault_event 1660 * 1661 * without CAM, adev primary ring1 1662 * | gmc_v9_0_process_interrupt worker failed to recvoer page fault 1663 * KFD node ih_fifo 1664 * | KFD interrupt_wq worker 1665 * kfd_signal_vm_fault_event 1666 * 1667 * no-retry fault - 1668 * adev primary ring 1669 * | gmc_v9_0_process_interrupt() 1670 * KFD node ih_fifo 1671 * | KFD interrupt_wq worker 1672 * kfd_signal_vm_fault_event 1673 * 1674 * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault 1675 * of same process, don't copy interrupt to KFD node ih_fifo. 1676 * With gdb debugger enabled, need convert the retry fault to no-retry fault for 1677 * debugger, cannot use the fast path. 1678 * 1679 * Return: 1680 * true - use the fast path to handle this fault 1681 * false - use normal path to handle it 1682 */ 1683 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 1684 bool retry_fault) 1685 { 1686 struct kfd_process *p; 1687 u32 cam_index; 1688 u32 src_data_idx; 1689 1690 src_data_idx = (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) ? 1691 3 : 2; 1692 1693 if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) { 1694 p = kfd_lookup_process_by_pasid(entry->pasid, NULL); 1695 if (!p) 1696 return true; 1697 1698 if (p->gpu_page_fault && !p->debug_trap_enabled) { 1699 if (retry_fault && adev->irq.retry_cam_enabled) { 1700 cam_index = entry->src_data[src_data_idx] & 0x3ff; 1701 1702 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 1703 } 1704 1705 kfd_unref_process(p); 1706 return true; 1707 } 1708 1709 /* 1710 * This is the first page fault, set flag and then signal user space 1711 */ 1712 p->gpu_page_fault = true; 1713 kfd_unref_process(p); 1714 } 1715 return false; 1716 } 1717 1718 #if defined(CONFIG_DEBUG_FS) 1719 1720 /* This function will send a package to HIQ to hang the HWS 1721 * which will trigger a GPU reset and bring the HWS back to normal state 1722 */ 1723 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1724 { 1725 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1726 pr_err("HWS is not enabled"); 1727 return -EINVAL; 1728 } 1729 1730 if (dev->kfd->shared_resources.enable_mes) { 1731 dev_err(dev->adev->dev, "Inducing MES hang is not supported\n"); 1732 return -EINVAL; 1733 } 1734 1735 return dqm_debugfs_hang_hws(dev->dqm); 1736 } 1737 1738 #endif 1739