1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(4, 4, 5): 88 case IP_VERSION(5, 0, 0):/* NAVI10 */ 89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 90 case IP_VERSION(5, 0, 2):/* NAVI14 */ 91 case IP_VERSION(5, 0, 5):/* NAVI12 */ 92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 96 case IP_VERSION(6, 0, 0): 97 case IP_VERSION(6, 0, 1): 98 case IP_VERSION(6, 0, 2): 99 case IP_VERSION(6, 0, 3): 100 case IP_VERSION(6, 1, 0): 101 case IP_VERSION(6, 1, 1): 102 case IP_VERSION(7, 0, 0): 103 case IP_VERSION(7, 0, 1): 104 kfd->device_info.num_sdma_queues_per_engine = 8; 105 break; 106 default: 107 dev_warn(kfd_device, 108 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 109 sdma_version); 110 kfd->device_info.num_sdma_queues_per_engine = 8; 111 } 112 113 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 114 115 switch (sdma_version) { 116 case IP_VERSION(6, 0, 0): 117 case IP_VERSION(6, 0, 1): 118 case IP_VERSION(6, 0, 2): 119 case IP_VERSION(6, 0, 3): 120 case IP_VERSION(6, 1, 0): 121 case IP_VERSION(6, 1, 1): 122 case IP_VERSION(7, 0, 0): 123 case IP_VERSION(7, 0, 1): 124 /* Reserve 1 for paging and 1 for gfx */ 125 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 126 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 127 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 128 kfd->adev->sdma.num_instances * 129 kfd->device_info.num_reserved_sdma_queues_per_engine); 130 break; 131 default: 132 break; 133 } 134 } 135 136 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 137 { 138 uint32_t gc_version = KFD_GC_VERSION(kfd); 139 140 switch (gc_version) { 141 case IP_VERSION(9, 0, 1): /* VEGA10 */ 142 case IP_VERSION(9, 1, 0): /* RAVEN */ 143 case IP_VERSION(9, 2, 1): /* VEGA12 */ 144 case IP_VERSION(9, 2, 2): /* RAVEN */ 145 case IP_VERSION(9, 3, 0): /* RENOIR */ 146 case IP_VERSION(9, 4, 0): /* VEGA20 */ 147 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 148 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 149 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 150 break; 151 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 152 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 153 kfd->device_info.event_interrupt_class = 154 &event_interrupt_class_v9_4_3; 155 break; 156 case IP_VERSION(10, 3, 1): /* VANGOGH */ 157 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 158 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 159 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 160 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 161 case IP_VERSION(10, 1, 4): 162 case IP_VERSION(10, 1, 10): /* NAVI10 */ 163 case IP_VERSION(10, 1, 2): /* NAVI12 */ 164 case IP_VERSION(10, 1, 1): /* NAVI14 */ 165 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 166 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 167 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 168 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 169 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 170 break; 171 case IP_VERSION(11, 0, 0): 172 case IP_VERSION(11, 0, 1): 173 case IP_VERSION(11, 0, 2): 174 case IP_VERSION(11, 0, 3): 175 case IP_VERSION(11, 0, 4): 176 case IP_VERSION(11, 5, 0): 177 case IP_VERSION(11, 5, 1): 178 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 179 break; 180 case IP_VERSION(12, 0, 0): 181 case IP_VERSION(12, 0, 1): 182 /* GFX12_TODO: Change to v12 version. */ 183 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 184 break; 185 default: 186 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 187 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 188 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 189 } 190 } 191 192 static void kfd_device_info_init(struct kfd_dev *kfd, 193 bool vf, uint32_t gfx_target_version) 194 { 195 uint32_t gc_version = KFD_GC_VERSION(kfd); 196 uint32_t asic_type = kfd->adev->asic_type; 197 198 kfd->device_info.max_pasid_bits = 16; 199 kfd->device_info.max_no_of_hqd = 24; 200 kfd->device_info.num_of_watch_points = 4; 201 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 202 kfd->device_info.gfx_target_version = gfx_target_version; 203 204 if (KFD_IS_SOC15(kfd)) { 205 kfd->device_info.doorbell_size = 8; 206 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 207 kfd->device_info.supports_cwsr = true; 208 209 kfd_device_info_set_sdma_info(kfd); 210 211 kfd_device_info_set_event_interrupt_class(kfd); 212 213 if (gc_version < IP_VERSION(11, 0, 0)) { 214 /* Navi2x+, Navi1x+ */ 215 if (gc_version == IP_VERSION(10, 3, 6)) 216 kfd->device_info.no_atomic_fw_version = 14; 217 else if (gc_version == IP_VERSION(10, 3, 7)) 218 kfd->device_info.no_atomic_fw_version = 3; 219 else if (gc_version >= IP_VERSION(10, 3, 0)) 220 kfd->device_info.no_atomic_fw_version = 92; 221 else if (gc_version >= IP_VERSION(10, 1, 1)) 222 kfd->device_info.no_atomic_fw_version = 145; 223 224 /* Navi1x+ */ 225 if (gc_version >= IP_VERSION(10, 1, 1)) 226 kfd->device_info.needs_pci_atomics = true; 227 } else if (gc_version < IP_VERSION(12, 0, 0)) { 228 /* 229 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 230 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 231 * PCIe atomics support. 232 */ 233 kfd->device_info.needs_pci_atomics = true; 234 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 235 } else { 236 kfd->device_info.needs_pci_atomics = true; 237 } 238 } else { 239 kfd->device_info.doorbell_size = 4; 240 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 241 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 242 kfd->device_info.num_sdma_queues_per_engine = 2; 243 244 if (asic_type != CHIP_KAVERI && 245 asic_type != CHIP_HAWAII && 246 asic_type != CHIP_TONGA) 247 kfd->device_info.supports_cwsr = true; 248 249 if (asic_type != CHIP_HAWAII && !vf) 250 kfd->device_info.needs_pci_atomics = true; 251 } 252 } 253 254 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 255 { 256 struct kfd_dev *kfd = NULL; 257 const struct kfd2kgd_calls *f2g = NULL; 258 uint32_t gfx_target_version = 0; 259 260 switch (adev->asic_type) { 261 #ifdef CONFIG_DRM_AMDGPU_CIK 262 case CHIP_KAVERI: 263 gfx_target_version = 70000; 264 if (!vf) 265 f2g = &gfx_v7_kfd2kgd; 266 break; 267 #endif 268 case CHIP_CARRIZO: 269 gfx_target_version = 80001; 270 if (!vf) 271 f2g = &gfx_v8_kfd2kgd; 272 break; 273 #ifdef CONFIG_DRM_AMDGPU_CIK 274 case CHIP_HAWAII: 275 gfx_target_version = 70001; 276 if (!amdgpu_exp_hw_support) 277 pr_info( 278 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 279 ); 280 else if (!vf) 281 f2g = &gfx_v7_kfd2kgd; 282 break; 283 #endif 284 case CHIP_TONGA: 285 gfx_target_version = 80002; 286 if (!vf) 287 f2g = &gfx_v8_kfd2kgd; 288 break; 289 case CHIP_FIJI: 290 case CHIP_POLARIS10: 291 gfx_target_version = 80003; 292 f2g = &gfx_v8_kfd2kgd; 293 break; 294 case CHIP_POLARIS11: 295 case CHIP_POLARIS12: 296 case CHIP_VEGAM: 297 gfx_target_version = 80003; 298 if (!vf) 299 f2g = &gfx_v8_kfd2kgd; 300 break; 301 default: 302 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 303 /* Vega 10 */ 304 case IP_VERSION(9, 0, 1): 305 gfx_target_version = 90000; 306 f2g = &gfx_v9_kfd2kgd; 307 break; 308 /* Raven */ 309 case IP_VERSION(9, 1, 0): 310 case IP_VERSION(9, 2, 2): 311 gfx_target_version = 90002; 312 if (!vf) 313 f2g = &gfx_v9_kfd2kgd; 314 break; 315 /* Vega12 */ 316 case IP_VERSION(9, 2, 1): 317 gfx_target_version = 90004; 318 if (!vf) 319 f2g = &gfx_v9_kfd2kgd; 320 break; 321 /* Renoir */ 322 case IP_VERSION(9, 3, 0): 323 gfx_target_version = 90012; 324 if (!vf) 325 f2g = &gfx_v9_kfd2kgd; 326 break; 327 /* Vega20 */ 328 case IP_VERSION(9, 4, 0): 329 gfx_target_version = 90006; 330 if (!vf) 331 f2g = &gfx_v9_kfd2kgd; 332 break; 333 /* Arcturus */ 334 case IP_VERSION(9, 4, 1): 335 gfx_target_version = 90008; 336 f2g = &arcturus_kfd2kgd; 337 break; 338 /* Aldebaran */ 339 case IP_VERSION(9, 4, 2): 340 gfx_target_version = 90010; 341 f2g = &aldebaran_kfd2kgd; 342 break; 343 case IP_VERSION(9, 4, 3): 344 gfx_target_version = adev->rev_id >= 1 ? 90402 345 : adev->flags & AMD_IS_APU ? 90400 346 : 90401; 347 f2g = &gc_9_4_3_kfd2kgd; 348 break; 349 case IP_VERSION(9, 4, 4): 350 gfx_target_version = 90402; 351 f2g = &gc_9_4_3_kfd2kgd; 352 break; 353 /* Navi10 */ 354 case IP_VERSION(10, 1, 10): 355 gfx_target_version = 100100; 356 if (!vf) 357 f2g = &gfx_v10_kfd2kgd; 358 break; 359 /* Navi12 */ 360 case IP_VERSION(10, 1, 2): 361 gfx_target_version = 100101; 362 f2g = &gfx_v10_kfd2kgd; 363 break; 364 /* Navi14 */ 365 case IP_VERSION(10, 1, 1): 366 gfx_target_version = 100102; 367 if (!vf) 368 f2g = &gfx_v10_kfd2kgd; 369 break; 370 /* Cyan Skillfish */ 371 case IP_VERSION(10, 1, 3): 372 case IP_VERSION(10, 1, 4): 373 gfx_target_version = 100103; 374 if (!vf) 375 f2g = &gfx_v10_kfd2kgd; 376 break; 377 /* Sienna Cichlid */ 378 case IP_VERSION(10, 3, 0): 379 gfx_target_version = 100300; 380 f2g = &gfx_v10_3_kfd2kgd; 381 break; 382 /* Navy Flounder */ 383 case IP_VERSION(10, 3, 2): 384 gfx_target_version = 100301; 385 f2g = &gfx_v10_3_kfd2kgd; 386 break; 387 /* Van Gogh */ 388 case IP_VERSION(10, 3, 1): 389 gfx_target_version = 100303; 390 if (!vf) 391 f2g = &gfx_v10_3_kfd2kgd; 392 break; 393 /* Dimgrey Cavefish */ 394 case IP_VERSION(10, 3, 4): 395 gfx_target_version = 100302; 396 f2g = &gfx_v10_3_kfd2kgd; 397 break; 398 /* Beige Goby */ 399 case IP_VERSION(10, 3, 5): 400 gfx_target_version = 100304; 401 f2g = &gfx_v10_3_kfd2kgd; 402 break; 403 /* Yellow Carp */ 404 case IP_VERSION(10, 3, 3): 405 gfx_target_version = 100305; 406 if (!vf) 407 f2g = &gfx_v10_3_kfd2kgd; 408 break; 409 case IP_VERSION(10, 3, 6): 410 case IP_VERSION(10, 3, 7): 411 gfx_target_version = 100306; 412 if (!vf) 413 f2g = &gfx_v10_3_kfd2kgd; 414 break; 415 case IP_VERSION(11, 0, 0): 416 gfx_target_version = 110000; 417 f2g = &gfx_v11_kfd2kgd; 418 break; 419 case IP_VERSION(11, 0, 1): 420 case IP_VERSION(11, 0, 4): 421 gfx_target_version = 110003; 422 f2g = &gfx_v11_kfd2kgd; 423 break; 424 case IP_VERSION(11, 0, 2): 425 gfx_target_version = 110002; 426 f2g = &gfx_v11_kfd2kgd; 427 break; 428 case IP_VERSION(11, 0, 3): 429 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 430 gfx_target_version = 110001; 431 f2g = &gfx_v11_kfd2kgd; 432 break; 433 case IP_VERSION(11, 5, 0): 434 gfx_target_version = 110500; 435 f2g = &gfx_v11_kfd2kgd; 436 break; 437 case IP_VERSION(11, 5, 1): 438 gfx_target_version = 110501; 439 f2g = &gfx_v11_kfd2kgd; 440 break; 441 case IP_VERSION(12, 0, 0): 442 gfx_target_version = 120000; 443 f2g = &gfx_v12_kfd2kgd; 444 break; 445 case IP_VERSION(12, 0, 1): 446 gfx_target_version = 120001; 447 f2g = &gfx_v12_kfd2kgd; 448 break; 449 default: 450 break; 451 } 452 break; 453 } 454 455 if (!f2g) { 456 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 457 dev_info(kfd_device, 458 "GC IP %06x %s not supported in kfd\n", 459 amdgpu_ip_version(adev, GC_HWIP, 0), 460 vf ? "VF" : ""); 461 else 462 dev_info(kfd_device, "%s %s not supported in kfd\n", 463 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 464 return NULL; 465 } 466 467 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 468 if (!kfd) 469 return NULL; 470 471 kfd->adev = adev; 472 kfd_device_info_init(kfd, vf, gfx_target_version); 473 kfd->init_complete = false; 474 kfd->kfd2kgd = f2g; 475 atomic_set(&kfd->compute_profile, 0); 476 477 mutex_init(&kfd->doorbell_mutex); 478 479 ida_init(&kfd->doorbell_ida); 480 481 return kfd; 482 } 483 484 static void kfd_cwsr_init(struct kfd_dev *kfd) 485 { 486 if (cwsr_enable && kfd->device_info.supports_cwsr) { 487 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 488 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 489 > KFD_CWSR_TMA_OFFSET); 490 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 491 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 492 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 493 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 494 > KFD_CWSR_TMA_OFFSET); 495 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 496 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 497 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 498 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 499 > KFD_CWSR_TMA_OFFSET); 500 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 501 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 502 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 503 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 504 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 505 > KFD_CWSR_TMA_OFFSET); 506 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 507 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 508 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 509 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 510 > KFD_CWSR_TMA_OFFSET); 511 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 512 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 513 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 514 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 515 > KFD_CWSR_TMA_OFFSET); 516 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 517 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 518 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 519 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 520 > KFD_CWSR_TMA_OFFSET); 521 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 522 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 523 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 524 /* The gfx11 cwsr trap handler must fit inside a single 525 page. */ 526 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 527 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 528 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 529 } else { 530 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) > PAGE_SIZE); 531 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 532 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 533 } 534 535 kfd->cwsr_enabled = true; 536 } 537 } 538 539 static int kfd_gws_init(struct kfd_node *node) 540 { 541 int ret = 0; 542 struct kfd_dev *kfd = node->kfd; 543 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 544 545 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 546 return 0; 547 548 if (hws_gws_support || (KFD_IS_SOC15(node) && 549 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 550 && kfd->mec2_fw_version >= 0x81b3) || 551 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 552 && kfd->mec2_fw_version >= 0x1b3) || 553 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 554 && kfd->mec2_fw_version >= 0x30) || 555 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 556 && kfd->mec2_fw_version >= 0x28) || 557 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 558 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 559 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 560 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 561 && kfd->mec2_fw_version >= 0x6b) || 562 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 563 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 564 && mes_rev >= 68)))) 565 ret = amdgpu_amdkfd_alloc_gws(node->adev, 566 node->adev->gds.gws_size, &node->gws); 567 568 return ret; 569 } 570 571 static void kfd_smi_init(struct kfd_node *dev) 572 { 573 INIT_LIST_HEAD(&dev->smi_clients); 574 spin_lock_init(&dev->smi_lock); 575 } 576 577 static int kfd_init_node(struct kfd_node *node) 578 { 579 int err = -1; 580 581 if (kfd_interrupt_init(node)) { 582 dev_err(kfd_device, "Error initializing interrupts\n"); 583 goto kfd_interrupt_error; 584 } 585 586 node->dqm = device_queue_manager_init(node); 587 if (!node->dqm) { 588 dev_err(kfd_device, "Error initializing queue manager\n"); 589 goto device_queue_manager_error; 590 } 591 592 if (kfd_gws_init(node)) { 593 dev_err(kfd_device, "Could not allocate %d gws\n", 594 node->adev->gds.gws_size); 595 goto gws_error; 596 } 597 598 if (kfd_resume(node)) 599 goto kfd_resume_error; 600 601 if (kfd_topology_add_device(node)) { 602 dev_err(kfd_device, "Error adding device to topology\n"); 603 goto kfd_topology_add_device_error; 604 } 605 606 kfd_smi_init(node); 607 608 return 0; 609 610 kfd_topology_add_device_error: 611 kfd_resume_error: 612 gws_error: 613 device_queue_manager_uninit(node->dqm); 614 device_queue_manager_error: 615 kfd_interrupt_exit(node); 616 kfd_interrupt_error: 617 if (node->gws) 618 amdgpu_amdkfd_free_gws(node->adev, node->gws); 619 620 /* Cleanup the node memory here */ 621 kfree(node); 622 return err; 623 } 624 625 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 626 { 627 struct kfd_node *knode; 628 unsigned int i; 629 630 for (i = 0; i < num_nodes; i++) { 631 knode = kfd->nodes[i]; 632 device_queue_manager_uninit(knode->dqm); 633 kfd_interrupt_exit(knode); 634 kfd_topology_remove_device(knode); 635 if (knode->gws) 636 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 637 kfree(knode); 638 kfd->nodes[i] = NULL; 639 } 640 } 641 642 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 643 unsigned int kfd_node_idx) 644 { 645 struct amdgpu_device *adev = node->adev; 646 uint32_t xcc_mask = node->xcc_mask; 647 uint32_t xcc, mapped_xcc; 648 /* 649 * Interrupt bitmap is setup for processing interrupts from 650 * different XCDs and AIDs. 651 * Interrupt bitmap is defined as follows: 652 * 1. Bits 0-15 - correspond to the NodeId field. 653 * Each bit corresponds to NodeId number. For example, if 654 * a KFD node has interrupt bitmap set to 0x7, then this 655 * KFD node will process interrupts with NodeId = 0, 1 and 2 656 * in the IH cookie. 657 * 2. Bits 16-31 - unused. 658 * 659 * Please note that the kfd_node_idx argument passed to this 660 * function is not related to NodeId field received in the 661 * IH cookie. 662 * 663 * In CPX mode, a KFD node will process an interrupt if: 664 * - the Node Id matches the corresponding bit set in 665 * Bits 0-15. 666 * - AND VMID reported in the interrupt lies within the 667 * VMID range of the node. 668 */ 669 for_each_inst(xcc, xcc_mask) { 670 mapped_xcc = GET_INST(GC, xcc); 671 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 672 } 673 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 674 node->interrupt_bitmap); 675 } 676 677 bool kgd2kfd_device_init(struct kfd_dev *kfd, 678 const struct kgd2kfd_shared_resources *gpu_resources) 679 { 680 unsigned int size, map_process_packet_size, i; 681 struct kfd_node *node; 682 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 683 unsigned int max_proc_per_quantum; 684 int partition_mode; 685 int xcp_idx; 686 687 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 688 KGD_ENGINE_MEC1); 689 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 690 KGD_ENGINE_MEC2); 691 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 692 KGD_ENGINE_SDMA1); 693 kfd->shared_resources = *gpu_resources; 694 695 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 696 697 if (kfd->num_nodes == 0) { 698 dev_err(kfd_device, 699 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 700 kfd->adev->gfx.num_xcc_per_xcp); 701 goto out; 702 } 703 704 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 705 * 32 and 64-bit requests are possible and must be 706 * supported. 707 */ 708 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 709 if (!kfd->pci_atomic_requested && 710 kfd->device_info.needs_pci_atomics && 711 (!kfd->device_info.no_atomic_fw_version || 712 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 713 dev_info(kfd_device, 714 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 715 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 716 kfd->mec_fw_version, 717 kfd->device_info.no_atomic_fw_version); 718 return false; 719 } 720 721 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 722 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 723 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 724 725 /* For GFX9.4.3, we need special handling for VMIDs depending on 726 * partition mode. 727 * In CPX mode, the VMID range needs to be shared between XCDs. 728 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 729 * divide them equally, we change starting VMID to 4 and not use 730 * VMID 3. 731 * If the VMID range changes for GFX9.4.3, then this code MUST be 732 * revisited. 733 */ 734 if (kfd->adev->xcp_mgr) { 735 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 736 AMDGPU_XCP_FL_LOCKED); 737 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 738 kfd->num_nodes != 1) { 739 vmid_num_kfd /= 2; 740 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 741 } 742 } 743 744 /* Verify module parameters regarding mapped process number*/ 745 if (hws_max_conc_proc >= 0) 746 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 747 else 748 max_proc_per_quantum = vmid_num_kfd; 749 750 /* calculate max size of mqds needed for queues */ 751 size = max_num_of_queues_per_device * 752 kfd->device_info.mqd_size_aligned; 753 754 /* 755 * calculate max size of runlist packet. 756 * There can be only 2 packets at once 757 */ 758 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 759 sizeof(struct pm4_mes_map_process_aldebaran) : 760 sizeof(struct pm4_mes_map_process); 761 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 762 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 763 + sizeof(struct pm4_mes_runlist)) * 2; 764 765 /* Add size of HIQ & DIQ */ 766 size += KFD_KERNEL_QUEUE_SIZE * 2; 767 768 /* add another 512KB for all other allocations on gart (HPD, fences) */ 769 size += 512 * 1024; 770 771 if (amdgpu_amdkfd_alloc_gtt_mem( 772 kfd->adev, size, &kfd->gtt_mem, 773 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 774 false)) { 775 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 776 goto alloc_gtt_mem_failure; 777 } 778 779 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 780 781 /* Initialize GTT sa with 512 byte chunk size */ 782 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 783 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 784 goto kfd_gtt_sa_init_error; 785 } 786 787 if (kfd_doorbell_init(kfd)) { 788 dev_err(kfd_device, 789 "Error initializing doorbell aperture\n"); 790 goto kfd_doorbell_error; 791 } 792 793 if (amdgpu_use_xgmi_p2p) 794 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 795 796 /* 797 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 798 * xGMI connected in the topology so assign a unique hive id per 799 * device based on the pci device location if device is in PCIe mode. 800 */ 801 if (!kfd->hive_id && 802 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 803 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) && 804 kfd->num_nodes > 1) 805 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 806 807 kfd->noretry = kfd->adev->gmc.noretry; 808 809 kfd_cwsr_init(kfd); 810 811 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 812 kfd->num_nodes); 813 814 /* Allocate the KFD nodes */ 815 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 816 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 817 if (!node) 818 goto node_alloc_error; 819 820 node->node_id = i; 821 node->adev = kfd->adev; 822 node->kfd = kfd; 823 node->kfd2kgd = kfd->kfd2kgd; 824 node->vm_info.vmid_num_kfd = vmid_num_kfd; 825 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 826 /* TODO : Check if error handling is needed */ 827 if (node->xcp) { 828 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 829 &node->xcc_mask); 830 ++xcp_idx; 831 } else { 832 node->xcc_mask = 833 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 834 } 835 836 if (node->xcp) { 837 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 838 node->node_id, node->xcp->mem_id, 839 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 840 } 841 842 if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 843 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) && 844 partition_mode == AMDGPU_CPX_PARTITION_MODE && 845 kfd->num_nodes != 1) { 846 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 847 * 4-9 and second XCD gets VMID range 10-15. 848 */ 849 850 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 851 first_vmid_kfd : 852 first_vmid_kfd+vmid_num_kfd; 853 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 854 last_vmid_kfd-vmid_num_kfd : 855 last_vmid_kfd; 856 node->compute_vmid_bitmap = 857 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 858 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 859 } else { 860 node->vm_info.first_vmid_kfd = first_vmid_kfd; 861 node->vm_info.last_vmid_kfd = last_vmid_kfd; 862 node->compute_vmid_bitmap = 863 gpu_resources->compute_vmid_bitmap; 864 } 865 node->max_proc_per_quantum = max_proc_per_quantum; 866 atomic_set(&node->sram_ecc_flag, 0); 867 868 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 869 &node->local_mem_info, node->xcp); 870 871 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 872 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) 873 kfd_setup_interrupt_bitmap(node, i); 874 875 /* Initialize the KFD node */ 876 if (kfd_init_node(node)) { 877 dev_err(kfd_device, "Error initializing KFD node\n"); 878 goto node_init_error; 879 } 880 kfd->nodes[i] = node; 881 } 882 883 svm_range_set_max_pages(kfd->adev); 884 885 spin_lock_init(&kfd->watch_points_lock); 886 887 kfd->init_complete = true; 888 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 889 kfd->adev->pdev->device); 890 891 pr_debug("Starting kfd with the following scheduling policy %d\n", 892 node->dqm->sched_policy); 893 894 goto out; 895 896 node_init_error: 897 node_alloc_error: 898 kfd_cleanup_nodes(kfd, i); 899 kfd_doorbell_fini(kfd); 900 kfd_doorbell_error: 901 kfd_gtt_sa_fini(kfd); 902 kfd_gtt_sa_init_error: 903 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 904 alloc_gtt_mem_failure: 905 dev_err(kfd_device, 906 "device %x:%x NOT added due to errors\n", 907 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 908 out: 909 return kfd->init_complete; 910 } 911 912 void kgd2kfd_device_exit(struct kfd_dev *kfd) 913 { 914 if (kfd->init_complete) { 915 /* Cleanup KFD nodes */ 916 kfd_cleanup_nodes(kfd, kfd->num_nodes); 917 /* Cleanup common/shared resources */ 918 kfd_doorbell_fini(kfd); 919 ida_destroy(&kfd->doorbell_ida); 920 kfd_gtt_sa_fini(kfd); 921 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 922 } 923 924 kfree(kfd); 925 } 926 927 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 928 struct amdgpu_reset_context *reset_context) 929 { 930 struct kfd_node *node; 931 int i; 932 933 if (!kfd->init_complete) 934 return 0; 935 936 for (i = 0; i < kfd->num_nodes; i++) { 937 node = kfd->nodes[i]; 938 kfd_smi_event_update_gpu_reset(node, false, reset_context); 939 } 940 941 kgd2kfd_suspend(kfd, false); 942 943 for (i = 0; i < kfd->num_nodes; i++) 944 kfd_signal_reset_event(kfd->nodes[i]); 945 946 return 0; 947 } 948 949 /* 950 * Fix me. KFD won't be able to resume existing process for now. 951 * We will keep all existing process in a evicted state and 952 * wait the process to be terminated. 953 */ 954 955 int kgd2kfd_post_reset(struct kfd_dev *kfd) 956 { 957 int ret; 958 struct kfd_node *node; 959 int i; 960 961 if (!kfd->init_complete) 962 return 0; 963 964 for (i = 0; i < kfd->num_nodes; i++) { 965 ret = kfd_resume(kfd->nodes[i]); 966 if (ret) 967 return ret; 968 } 969 970 mutex_lock(&kfd_processes_mutex); 971 --kfd_locked; 972 mutex_unlock(&kfd_processes_mutex); 973 974 for (i = 0; i < kfd->num_nodes; i++) { 975 node = kfd->nodes[i]; 976 atomic_set(&node->sram_ecc_flag, 0); 977 kfd_smi_event_update_gpu_reset(node, true, NULL); 978 } 979 980 return 0; 981 } 982 983 bool kfd_is_locked(void) 984 { 985 lockdep_assert_held(&kfd_processes_mutex); 986 return (kfd_locked > 0); 987 } 988 989 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 990 { 991 struct kfd_node *node; 992 int i; 993 994 if (!kfd->init_complete) 995 return; 996 997 /* for runtime suspend, skip locking kfd */ 998 if (!run_pm) { 999 mutex_lock(&kfd_processes_mutex); 1000 /* For first KFD device suspend all the KFD processes */ 1001 if (++kfd_locked == 1) 1002 kfd_suspend_all_processes(); 1003 mutex_unlock(&kfd_processes_mutex); 1004 } 1005 1006 for (i = 0; i < kfd->num_nodes; i++) { 1007 node = kfd->nodes[i]; 1008 node->dqm->ops.stop(node->dqm); 1009 } 1010 } 1011 1012 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1013 { 1014 int ret, i; 1015 1016 if (!kfd->init_complete) 1017 return 0; 1018 1019 for (i = 0; i < kfd->num_nodes; i++) { 1020 ret = kfd_resume(kfd->nodes[i]); 1021 if (ret) 1022 return ret; 1023 } 1024 1025 /* for runtime resume, skip unlocking kfd */ 1026 if (!run_pm) { 1027 mutex_lock(&kfd_processes_mutex); 1028 if (--kfd_locked == 0) 1029 ret = kfd_resume_all_processes(); 1030 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1031 mutex_unlock(&kfd_processes_mutex); 1032 } 1033 1034 return ret; 1035 } 1036 1037 static int kfd_resume(struct kfd_node *node) 1038 { 1039 int err = 0; 1040 1041 err = node->dqm->ops.start(node->dqm); 1042 if (err) 1043 dev_err(kfd_device, 1044 "Error starting queue manager for device %x:%x\n", 1045 node->adev->pdev->vendor, node->adev->pdev->device); 1046 1047 return err; 1048 } 1049 1050 static inline void kfd_queue_work(struct workqueue_struct *wq, 1051 struct work_struct *work) 1052 { 1053 int cpu, new_cpu; 1054 1055 cpu = new_cpu = smp_processor_id(); 1056 do { 1057 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1058 if (cpu_to_node(new_cpu) == numa_node_id()) 1059 break; 1060 } while (cpu != new_cpu); 1061 1062 queue_work_on(new_cpu, wq, work); 1063 } 1064 1065 /* This is called directly from KGD at ISR. */ 1066 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1067 { 1068 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1069 bool is_patched = false; 1070 unsigned long flags; 1071 struct kfd_node *node; 1072 1073 if (!kfd->init_complete) 1074 return; 1075 1076 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1077 dev_err_once(kfd_device, "Ring entry too small\n"); 1078 return; 1079 } 1080 1081 for (i = 0; i < kfd->num_nodes; i++) { 1082 node = kfd->nodes[i]; 1083 spin_lock_irqsave(&node->interrupt_lock, flags); 1084 1085 if (node->interrupts_active 1086 && interrupt_is_wanted(node, ih_ring_entry, 1087 patched_ihre, &is_patched) 1088 && enqueue_ih_ring_entry(node, 1089 is_patched ? patched_ihre : ih_ring_entry)) { 1090 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1091 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1092 return; 1093 } 1094 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1095 } 1096 1097 } 1098 1099 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1100 { 1101 struct kfd_process *p; 1102 int r; 1103 1104 /* Because we are called from arbitrary context (workqueue) as opposed 1105 * to process context, kfd_process could attempt to exit while we are 1106 * running so the lookup function increments the process ref count. 1107 */ 1108 p = kfd_lookup_process_by_mm(mm); 1109 if (!p) 1110 return -ESRCH; 1111 1112 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1113 r = kfd_process_evict_queues(p, trigger); 1114 1115 kfd_unref_process(p); 1116 return r; 1117 } 1118 1119 int kgd2kfd_resume_mm(struct mm_struct *mm) 1120 { 1121 struct kfd_process *p; 1122 int r; 1123 1124 /* Because we are called from arbitrary context (workqueue) as opposed 1125 * to process context, kfd_process could attempt to exit while we are 1126 * running so the lookup function increments the process ref count. 1127 */ 1128 p = kfd_lookup_process_by_mm(mm); 1129 if (!p) 1130 return -ESRCH; 1131 1132 r = kfd_process_restore_queues(p); 1133 1134 kfd_unref_process(p); 1135 return r; 1136 } 1137 1138 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1139 * prepare for safe eviction of KFD BOs that belong to the specified 1140 * process. 1141 * 1142 * @mm: mm_struct that identifies the specified KFD process 1143 * @fence: eviction fence attached to KFD process BOs 1144 * 1145 */ 1146 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1147 struct dma_fence *fence) 1148 { 1149 struct kfd_process *p; 1150 unsigned long active_time; 1151 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1152 1153 if (!fence) 1154 return -EINVAL; 1155 1156 if (dma_fence_is_signaled(fence)) 1157 return 0; 1158 1159 p = kfd_lookup_process_by_mm(mm); 1160 if (!p) 1161 return -ENODEV; 1162 1163 if (fence->seqno == p->last_eviction_seqno) 1164 goto out; 1165 1166 p->last_eviction_seqno = fence->seqno; 1167 1168 /* Avoid KFD process starvation. Wait for at least 1169 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1170 */ 1171 active_time = get_jiffies_64() - p->last_restore_timestamp; 1172 if (delay_jiffies > active_time) 1173 delay_jiffies -= active_time; 1174 else 1175 delay_jiffies = 0; 1176 1177 /* During process initialization eviction_work.dwork is initialized 1178 * to kfd_evict_bo_worker 1179 */ 1180 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1181 p->lead_thread->pid, delay_jiffies); 1182 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1183 out: 1184 kfd_unref_process(p); 1185 return 0; 1186 } 1187 1188 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1189 unsigned int chunk_size) 1190 { 1191 if (WARN_ON(buf_size < chunk_size)) 1192 return -EINVAL; 1193 if (WARN_ON(buf_size == 0)) 1194 return -EINVAL; 1195 if (WARN_ON(chunk_size == 0)) 1196 return -EINVAL; 1197 1198 kfd->gtt_sa_chunk_size = chunk_size; 1199 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1200 1201 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1202 GFP_KERNEL); 1203 if (!kfd->gtt_sa_bitmap) 1204 return -ENOMEM; 1205 1206 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1207 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1208 1209 mutex_init(&kfd->gtt_sa_lock); 1210 1211 return 0; 1212 } 1213 1214 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1215 { 1216 mutex_destroy(&kfd->gtt_sa_lock); 1217 bitmap_free(kfd->gtt_sa_bitmap); 1218 } 1219 1220 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1221 unsigned int bit_num, 1222 unsigned int chunk_size) 1223 { 1224 return start_addr + bit_num * chunk_size; 1225 } 1226 1227 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1228 unsigned int bit_num, 1229 unsigned int chunk_size) 1230 { 1231 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1232 } 1233 1234 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1235 struct kfd_mem_obj **mem_obj) 1236 { 1237 unsigned int found, start_search, cur_size; 1238 struct kfd_dev *kfd = node->kfd; 1239 1240 if (size == 0) 1241 return -EINVAL; 1242 1243 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1244 return -ENOMEM; 1245 1246 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1247 if (!(*mem_obj)) 1248 return -ENOMEM; 1249 1250 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1251 1252 start_search = 0; 1253 1254 mutex_lock(&kfd->gtt_sa_lock); 1255 1256 kfd_gtt_restart_search: 1257 /* Find the first chunk that is free */ 1258 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1259 kfd->gtt_sa_num_of_chunks, 1260 start_search); 1261 1262 pr_debug("Found = %d\n", found); 1263 1264 /* If there wasn't any free chunk, bail out */ 1265 if (found == kfd->gtt_sa_num_of_chunks) 1266 goto kfd_gtt_no_free_chunk; 1267 1268 /* Update fields of mem_obj */ 1269 (*mem_obj)->range_start = found; 1270 (*mem_obj)->range_end = found; 1271 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1272 kfd->gtt_start_gpu_addr, 1273 found, 1274 kfd->gtt_sa_chunk_size); 1275 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1276 kfd->gtt_start_cpu_ptr, 1277 found, 1278 kfd->gtt_sa_chunk_size); 1279 1280 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1281 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1282 1283 /* If we need only one chunk, mark it as allocated and get out */ 1284 if (size <= kfd->gtt_sa_chunk_size) { 1285 pr_debug("Single bit\n"); 1286 __set_bit(found, kfd->gtt_sa_bitmap); 1287 goto kfd_gtt_out; 1288 } 1289 1290 /* Otherwise, try to see if we have enough contiguous chunks */ 1291 cur_size = size - kfd->gtt_sa_chunk_size; 1292 do { 1293 (*mem_obj)->range_end = 1294 find_next_zero_bit(kfd->gtt_sa_bitmap, 1295 kfd->gtt_sa_num_of_chunks, ++found); 1296 /* 1297 * If next free chunk is not contiguous than we need to 1298 * restart our search from the last free chunk we found (which 1299 * wasn't contiguous to the previous ones 1300 */ 1301 if ((*mem_obj)->range_end != found) { 1302 start_search = found; 1303 goto kfd_gtt_restart_search; 1304 } 1305 1306 /* 1307 * If we reached end of buffer, bail out with error 1308 */ 1309 if (found == kfd->gtt_sa_num_of_chunks) 1310 goto kfd_gtt_no_free_chunk; 1311 1312 /* Check if we don't need another chunk */ 1313 if (cur_size <= kfd->gtt_sa_chunk_size) 1314 cur_size = 0; 1315 else 1316 cur_size -= kfd->gtt_sa_chunk_size; 1317 1318 } while (cur_size > 0); 1319 1320 pr_debug("range_start = %d, range_end = %d\n", 1321 (*mem_obj)->range_start, (*mem_obj)->range_end); 1322 1323 /* Mark the chunks as allocated */ 1324 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1325 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1326 1327 kfd_gtt_out: 1328 mutex_unlock(&kfd->gtt_sa_lock); 1329 return 0; 1330 1331 kfd_gtt_no_free_chunk: 1332 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1333 mutex_unlock(&kfd->gtt_sa_lock); 1334 kfree(*mem_obj); 1335 return -ENOMEM; 1336 } 1337 1338 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1339 { 1340 struct kfd_dev *kfd = node->kfd; 1341 1342 /* Act like kfree when trying to free a NULL object */ 1343 if (!mem_obj) 1344 return 0; 1345 1346 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1347 mem_obj, mem_obj->range_start, mem_obj->range_end); 1348 1349 mutex_lock(&kfd->gtt_sa_lock); 1350 1351 /* Mark the chunks as free */ 1352 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1353 mem_obj->range_end - mem_obj->range_start + 1); 1354 1355 mutex_unlock(&kfd->gtt_sa_lock); 1356 1357 kfree(mem_obj); 1358 return 0; 1359 } 1360 1361 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1362 { 1363 /* 1364 * TODO: Currently update SRAM ECC flag for first node. 1365 * This needs to be updated later when we can 1366 * identify SRAM ECC error on other nodes also. 1367 */ 1368 if (kfd) 1369 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1370 } 1371 1372 void kfd_inc_compute_active(struct kfd_node *node) 1373 { 1374 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1375 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1376 } 1377 1378 void kfd_dec_compute_active(struct kfd_node *node) 1379 { 1380 int count = atomic_dec_return(&node->kfd->compute_profile); 1381 1382 if (count == 0) 1383 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1384 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1385 } 1386 1387 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1388 { 1389 /* 1390 * TODO: For now, raise the throttling event only on first node. 1391 * This will need to change after we are able to determine 1392 * which node raised the throttling event. 1393 */ 1394 if (kfd && kfd->init_complete) 1395 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1396 throttle_bitmask); 1397 } 1398 1399 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1400 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1401 * When the device has more than two engines, we reserve two for PCIe to enable 1402 * full-duplex and the rest are used as XGMI. 1403 */ 1404 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1405 { 1406 /* If XGMI is not supported, all SDMA engines are PCIe */ 1407 if (!node->adev->gmc.xgmi.supported) 1408 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1409 1410 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1411 } 1412 1413 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1414 { 1415 /* After reserved for PCIe, the rest of engines are XGMI */ 1416 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1417 kfd_get_num_sdma_engines(node); 1418 } 1419 1420 int kgd2kfd_check_and_lock_kfd(void) 1421 { 1422 mutex_lock(&kfd_processes_mutex); 1423 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1424 mutex_unlock(&kfd_processes_mutex); 1425 return -EBUSY; 1426 } 1427 1428 ++kfd_locked; 1429 mutex_unlock(&kfd_processes_mutex); 1430 1431 return 0; 1432 } 1433 1434 void kgd2kfd_unlock_kfd(void) 1435 { 1436 mutex_lock(&kfd_processes_mutex); 1437 --kfd_locked; 1438 mutex_unlock(&kfd_processes_mutex); 1439 } 1440 1441 #if defined(CONFIG_DEBUG_FS) 1442 1443 /* This function will send a package to HIQ to hang the HWS 1444 * which will trigger a GPU reset and bring the HWS back to normal state 1445 */ 1446 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1447 { 1448 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1449 pr_err("HWS is not enabled"); 1450 return -EINVAL; 1451 } 1452 1453 return dqm_debugfs_hang_hws(dev->dqm); 1454 } 1455 1456 #endif 1457