1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(4, 4, 5): 88 case IP_VERSION(5, 0, 0):/* NAVI10 */ 89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 90 case IP_VERSION(5, 0, 2):/* NAVI14 */ 91 case IP_VERSION(5, 0, 5):/* NAVI12 */ 92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 96 case IP_VERSION(6, 0, 0): 97 case IP_VERSION(6, 0, 1): 98 case IP_VERSION(6, 0, 2): 99 case IP_VERSION(6, 0, 3): 100 case IP_VERSION(6, 1, 0): 101 case IP_VERSION(6, 1, 1): 102 case IP_VERSION(6, 1, 2): 103 case IP_VERSION(7, 0, 0): 104 case IP_VERSION(7, 0, 1): 105 kfd->device_info.num_sdma_queues_per_engine = 8; 106 break; 107 default: 108 dev_warn(kfd_device, 109 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 110 sdma_version); 111 kfd->device_info.num_sdma_queues_per_engine = 8; 112 } 113 114 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 115 116 switch (sdma_version) { 117 case IP_VERSION(6, 0, 0): 118 case IP_VERSION(6, 0, 1): 119 case IP_VERSION(6, 0, 2): 120 case IP_VERSION(6, 0, 3): 121 case IP_VERSION(6, 1, 0): 122 case IP_VERSION(6, 1, 1): 123 case IP_VERSION(6, 1, 2): 124 case IP_VERSION(7, 0, 0): 125 case IP_VERSION(7, 0, 1): 126 /* Reserve 1 for paging and 1 for gfx */ 127 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 128 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 129 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 130 kfd->adev->sdma.num_instances * 131 kfd->device_info.num_reserved_sdma_queues_per_engine); 132 break; 133 default: 134 break; 135 } 136 } 137 138 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 139 { 140 uint32_t gc_version = KFD_GC_VERSION(kfd); 141 142 switch (gc_version) { 143 case IP_VERSION(9, 0, 1): /* VEGA10 */ 144 case IP_VERSION(9, 1, 0): /* RAVEN */ 145 case IP_VERSION(9, 2, 1): /* VEGA12 */ 146 case IP_VERSION(9, 2, 2): /* RAVEN */ 147 case IP_VERSION(9, 3, 0): /* RENOIR */ 148 case IP_VERSION(9, 4, 0): /* VEGA20 */ 149 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 150 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 151 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 152 break; 153 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 154 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 155 kfd->device_info.event_interrupt_class = 156 &event_interrupt_class_v9_4_3; 157 break; 158 case IP_VERSION(10, 3, 1): /* VANGOGH */ 159 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 160 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 161 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 162 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 163 case IP_VERSION(10, 1, 4): 164 case IP_VERSION(10, 1, 10): /* NAVI10 */ 165 case IP_VERSION(10, 1, 2): /* NAVI12 */ 166 case IP_VERSION(10, 1, 1): /* NAVI14 */ 167 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 168 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 169 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 170 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 171 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 172 break; 173 case IP_VERSION(11, 0, 0): 174 case IP_VERSION(11, 0, 1): 175 case IP_VERSION(11, 0, 2): 176 case IP_VERSION(11, 0, 3): 177 case IP_VERSION(11, 0, 4): 178 case IP_VERSION(11, 5, 0): 179 case IP_VERSION(11, 5, 1): 180 case IP_VERSION(11, 5, 2): 181 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 182 break; 183 case IP_VERSION(12, 0, 0): 184 case IP_VERSION(12, 0, 1): 185 /* GFX12_TODO: Change to v12 version. */ 186 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 187 break; 188 default: 189 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 190 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 191 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 192 } 193 } 194 195 static void kfd_device_info_init(struct kfd_dev *kfd, 196 bool vf, uint32_t gfx_target_version) 197 { 198 uint32_t gc_version = KFD_GC_VERSION(kfd); 199 uint32_t asic_type = kfd->adev->asic_type; 200 201 kfd->device_info.max_pasid_bits = 16; 202 kfd->device_info.max_no_of_hqd = 24; 203 kfd->device_info.num_of_watch_points = 4; 204 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 205 kfd->device_info.gfx_target_version = gfx_target_version; 206 207 if (KFD_IS_SOC15(kfd)) { 208 kfd->device_info.doorbell_size = 8; 209 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 210 kfd->device_info.supports_cwsr = true; 211 212 kfd_device_info_set_sdma_info(kfd); 213 214 kfd_device_info_set_event_interrupt_class(kfd); 215 216 if (gc_version < IP_VERSION(11, 0, 0)) { 217 /* Navi2x+, Navi1x+ */ 218 if (gc_version == IP_VERSION(10, 3, 6)) 219 kfd->device_info.no_atomic_fw_version = 14; 220 else if (gc_version == IP_VERSION(10, 3, 7)) 221 kfd->device_info.no_atomic_fw_version = 3; 222 else if (gc_version >= IP_VERSION(10, 3, 0)) 223 kfd->device_info.no_atomic_fw_version = 92; 224 else if (gc_version >= IP_VERSION(10, 1, 1)) 225 kfd->device_info.no_atomic_fw_version = 145; 226 227 /* Navi1x+ */ 228 if (gc_version >= IP_VERSION(10, 1, 1)) 229 kfd->device_info.needs_pci_atomics = true; 230 } else if (gc_version < IP_VERSION(12, 0, 0)) { 231 /* 232 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 233 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 234 * PCIe atomics support. 235 */ 236 kfd->device_info.needs_pci_atomics = true; 237 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 238 } else if (gc_version < IP_VERSION(13, 0, 0)) { 239 kfd->device_info.needs_pci_atomics = true; 240 kfd->device_info.no_atomic_fw_version = 2090; 241 } else { 242 kfd->device_info.needs_pci_atomics = true; 243 } 244 } else { 245 kfd->device_info.doorbell_size = 4; 246 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 247 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 248 kfd->device_info.num_sdma_queues_per_engine = 2; 249 250 if (asic_type != CHIP_KAVERI && 251 asic_type != CHIP_HAWAII && 252 asic_type != CHIP_TONGA) 253 kfd->device_info.supports_cwsr = true; 254 255 if (asic_type != CHIP_HAWAII && !vf) 256 kfd->device_info.needs_pci_atomics = true; 257 } 258 } 259 260 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 261 { 262 struct kfd_dev *kfd = NULL; 263 const struct kfd2kgd_calls *f2g = NULL; 264 uint32_t gfx_target_version = 0; 265 266 switch (adev->asic_type) { 267 #ifdef CONFIG_DRM_AMDGPU_CIK 268 case CHIP_KAVERI: 269 gfx_target_version = 70000; 270 if (!vf) 271 f2g = &gfx_v7_kfd2kgd; 272 break; 273 #endif 274 case CHIP_CARRIZO: 275 gfx_target_version = 80001; 276 if (!vf) 277 f2g = &gfx_v8_kfd2kgd; 278 break; 279 #ifdef CONFIG_DRM_AMDGPU_CIK 280 case CHIP_HAWAII: 281 gfx_target_version = 70001; 282 if (!amdgpu_exp_hw_support) 283 pr_info( 284 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 285 ); 286 else if (!vf) 287 f2g = &gfx_v7_kfd2kgd; 288 break; 289 #endif 290 case CHIP_TONGA: 291 gfx_target_version = 80002; 292 if (!vf) 293 f2g = &gfx_v8_kfd2kgd; 294 break; 295 case CHIP_FIJI: 296 case CHIP_POLARIS10: 297 gfx_target_version = 80003; 298 f2g = &gfx_v8_kfd2kgd; 299 break; 300 case CHIP_POLARIS11: 301 case CHIP_POLARIS12: 302 case CHIP_VEGAM: 303 gfx_target_version = 80003; 304 if (!vf) 305 f2g = &gfx_v8_kfd2kgd; 306 break; 307 default: 308 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 309 /* Vega 10 */ 310 case IP_VERSION(9, 0, 1): 311 gfx_target_version = 90000; 312 f2g = &gfx_v9_kfd2kgd; 313 break; 314 /* Raven */ 315 case IP_VERSION(9, 1, 0): 316 case IP_VERSION(9, 2, 2): 317 gfx_target_version = 90002; 318 if (!vf) 319 f2g = &gfx_v9_kfd2kgd; 320 break; 321 /* Vega12 */ 322 case IP_VERSION(9, 2, 1): 323 gfx_target_version = 90004; 324 if (!vf) 325 f2g = &gfx_v9_kfd2kgd; 326 break; 327 /* Renoir */ 328 case IP_VERSION(9, 3, 0): 329 gfx_target_version = 90012; 330 if (!vf) 331 f2g = &gfx_v9_kfd2kgd; 332 break; 333 /* Vega20 */ 334 case IP_VERSION(9, 4, 0): 335 gfx_target_version = 90006; 336 if (!vf) 337 f2g = &gfx_v9_kfd2kgd; 338 break; 339 /* Arcturus */ 340 case IP_VERSION(9, 4, 1): 341 gfx_target_version = 90008; 342 f2g = &arcturus_kfd2kgd; 343 break; 344 /* Aldebaran */ 345 case IP_VERSION(9, 4, 2): 346 gfx_target_version = 90010; 347 f2g = &aldebaran_kfd2kgd; 348 break; 349 case IP_VERSION(9, 4, 3): 350 gfx_target_version = adev->rev_id >= 1 ? 90402 351 : adev->flags & AMD_IS_APU ? 90400 352 : 90401; 353 f2g = &gc_9_4_3_kfd2kgd; 354 break; 355 case IP_VERSION(9, 4, 4): 356 gfx_target_version = 90402; 357 f2g = &gc_9_4_3_kfd2kgd; 358 break; 359 /* Navi10 */ 360 case IP_VERSION(10, 1, 10): 361 gfx_target_version = 100100; 362 if (!vf) 363 f2g = &gfx_v10_kfd2kgd; 364 break; 365 /* Navi12 */ 366 case IP_VERSION(10, 1, 2): 367 gfx_target_version = 100101; 368 f2g = &gfx_v10_kfd2kgd; 369 break; 370 /* Navi14 */ 371 case IP_VERSION(10, 1, 1): 372 gfx_target_version = 100102; 373 if (!vf) 374 f2g = &gfx_v10_kfd2kgd; 375 break; 376 /* Cyan Skillfish */ 377 case IP_VERSION(10, 1, 3): 378 case IP_VERSION(10, 1, 4): 379 gfx_target_version = 100103; 380 if (!vf) 381 f2g = &gfx_v10_kfd2kgd; 382 break; 383 /* Sienna Cichlid */ 384 case IP_VERSION(10, 3, 0): 385 gfx_target_version = 100300; 386 f2g = &gfx_v10_3_kfd2kgd; 387 break; 388 /* Navy Flounder */ 389 case IP_VERSION(10, 3, 2): 390 gfx_target_version = 100301; 391 f2g = &gfx_v10_3_kfd2kgd; 392 break; 393 /* Van Gogh */ 394 case IP_VERSION(10, 3, 1): 395 gfx_target_version = 100303; 396 if (!vf) 397 f2g = &gfx_v10_3_kfd2kgd; 398 break; 399 /* Dimgrey Cavefish */ 400 case IP_VERSION(10, 3, 4): 401 gfx_target_version = 100302; 402 f2g = &gfx_v10_3_kfd2kgd; 403 break; 404 /* Beige Goby */ 405 case IP_VERSION(10, 3, 5): 406 gfx_target_version = 100304; 407 f2g = &gfx_v10_3_kfd2kgd; 408 break; 409 /* Yellow Carp */ 410 case IP_VERSION(10, 3, 3): 411 gfx_target_version = 100305; 412 if (!vf) 413 f2g = &gfx_v10_3_kfd2kgd; 414 break; 415 case IP_VERSION(10, 3, 6): 416 case IP_VERSION(10, 3, 7): 417 gfx_target_version = 100306; 418 if (!vf) 419 f2g = &gfx_v10_3_kfd2kgd; 420 break; 421 case IP_VERSION(11, 0, 0): 422 gfx_target_version = 110000; 423 f2g = &gfx_v11_kfd2kgd; 424 break; 425 case IP_VERSION(11, 0, 1): 426 case IP_VERSION(11, 0, 4): 427 gfx_target_version = 110003; 428 f2g = &gfx_v11_kfd2kgd; 429 break; 430 case IP_VERSION(11, 0, 2): 431 gfx_target_version = 110002; 432 f2g = &gfx_v11_kfd2kgd; 433 break; 434 case IP_VERSION(11, 0, 3): 435 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 436 gfx_target_version = 110001; 437 f2g = &gfx_v11_kfd2kgd; 438 break; 439 case IP_VERSION(11, 5, 0): 440 gfx_target_version = 110500; 441 f2g = &gfx_v11_kfd2kgd; 442 break; 443 case IP_VERSION(11, 5, 1): 444 gfx_target_version = 110501; 445 f2g = &gfx_v11_kfd2kgd; 446 break; 447 case IP_VERSION(11, 5, 2): 448 gfx_target_version = 110502; 449 f2g = &gfx_v11_kfd2kgd; 450 break; 451 case IP_VERSION(12, 0, 0): 452 gfx_target_version = 120000; 453 f2g = &gfx_v12_kfd2kgd; 454 break; 455 case IP_VERSION(12, 0, 1): 456 gfx_target_version = 120001; 457 f2g = &gfx_v12_kfd2kgd; 458 break; 459 default: 460 break; 461 } 462 break; 463 } 464 465 if (!f2g) { 466 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 467 dev_info(kfd_device, 468 "GC IP %06x %s not supported in kfd\n", 469 amdgpu_ip_version(adev, GC_HWIP, 0), 470 vf ? "VF" : ""); 471 else 472 dev_info(kfd_device, "%s %s not supported in kfd\n", 473 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 474 return NULL; 475 } 476 477 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 478 if (!kfd) 479 return NULL; 480 481 kfd->adev = adev; 482 kfd_device_info_init(kfd, vf, gfx_target_version); 483 kfd->init_complete = false; 484 kfd->kfd2kgd = f2g; 485 atomic_set(&kfd->compute_profile, 0); 486 487 mutex_init(&kfd->doorbell_mutex); 488 489 ida_init(&kfd->doorbell_ida); 490 491 return kfd; 492 } 493 494 static void kfd_cwsr_init(struct kfd_dev *kfd) 495 { 496 if (cwsr_enable && kfd->device_info.supports_cwsr) { 497 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 498 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 499 > KFD_CWSR_TMA_OFFSET); 500 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 501 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 502 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 503 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 504 > KFD_CWSR_TMA_OFFSET); 505 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 506 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 507 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 508 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 509 > KFD_CWSR_TMA_OFFSET); 510 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 511 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 512 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 513 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 514 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 515 > KFD_CWSR_TMA_OFFSET); 516 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 517 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 518 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 519 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 520 > KFD_CWSR_TMA_OFFSET); 521 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 522 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 523 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 524 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 525 > KFD_CWSR_TMA_OFFSET); 526 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 527 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 528 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 529 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 530 > KFD_CWSR_TMA_OFFSET); 531 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 532 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 533 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 534 /* The gfx11 cwsr trap handler must fit inside a single 535 page. */ 536 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 537 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 538 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 539 } else { 540 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 541 > KFD_CWSR_TMA_OFFSET); 542 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 543 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 544 } 545 546 kfd->cwsr_enabled = true; 547 } 548 } 549 550 static int kfd_gws_init(struct kfd_node *node) 551 { 552 int ret = 0; 553 struct kfd_dev *kfd = node->kfd; 554 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 555 556 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 557 return 0; 558 559 if (hws_gws_support || (KFD_IS_SOC15(node) && 560 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 561 && kfd->mec2_fw_version >= 0x81b3) || 562 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 563 && kfd->mec2_fw_version >= 0x1b3) || 564 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 565 && kfd->mec2_fw_version >= 0x30) || 566 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 567 && kfd->mec2_fw_version >= 0x28) || 568 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 569 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 570 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 571 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 572 && kfd->mec2_fw_version >= 0x6b) || 573 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 574 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 575 && mes_rev >= 68)))) 576 ret = amdgpu_amdkfd_alloc_gws(node->adev, 577 node->adev->gds.gws_size, &node->gws); 578 579 return ret; 580 } 581 582 static void kfd_smi_init(struct kfd_node *dev) 583 { 584 INIT_LIST_HEAD(&dev->smi_clients); 585 spin_lock_init(&dev->smi_lock); 586 } 587 588 static int kfd_init_node(struct kfd_node *node) 589 { 590 int err = -1; 591 592 if (kfd_interrupt_init(node)) { 593 dev_err(kfd_device, "Error initializing interrupts\n"); 594 goto kfd_interrupt_error; 595 } 596 597 node->dqm = device_queue_manager_init(node); 598 if (!node->dqm) { 599 dev_err(kfd_device, "Error initializing queue manager\n"); 600 goto device_queue_manager_error; 601 } 602 603 if (kfd_gws_init(node)) { 604 dev_err(kfd_device, "Could not allocate %d gws\n", 605 node->adev->gds.gws_size); 606 goto gws_error; 607 } 608 609 if (kfd_resume(node)) 610 goto kfd_resume_error; 611 612 if (kfd_topology_add_device(node)) { 613 dev_err(kfd_device, "Error adding device to topology\n"); 614 goto kfd_topology_add_device_error; 615 } 616 617 kfd_smi_init(node); 618 619 return 0; 620 621 kfd_topology_add_device_error: 622 kfd_resume_error: 623 gws_error: 624 device_queue_manager_uninit(node->dqm); 625 device_queue_manager_error: 626 kfd_interrupt_exit(node); 627 kfd_interrupt_error: 628 if (node->gws) 629 amdgpu_amdkfd_free_gws(node->adev, node->gws); 630 631 /* Cleanup the node memory here */ 632 kfree(node); 633 return err; 634 } 635 636 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 637 { 638 struct kfd_node *knode; 639 unsigned int i; 640 641 for (i = 0; i < num_nodes; i++) { 642 knode = kfd->nodes[i]; 643 device_queue_manager_uninit(knode->dqm); 644 kfd_interrupt_exit(knode); 645 kfd_topology_remove_device(knode); 646 if (knode->gws) 647 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 648 kfree(knode); 649 kfd->nodes[i] = NULL; 650 } 651 } 652 653 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 654 unsigned int kfd_node_idx) 655 { 656 struct amdgpu_device *adev = node->adev; 657 uint32_t xcc_mask = node->xcc_mask; 658 uint32_t xcc, mapped_xcc; 659 /* 660 * Interrupt bitmap is setup for processing interrupts from 661 * different XCDs and AIDs. 662 * Interrupt bitmap is defined as follows: 663 * 1. Bits 0-15 - correspond to the NodeId field. 664 * Each bit corresponds to NodeId number. For example, if 665 * a KFD node has interrupt bitmap set to 0x7, then this 666 * KFD node will process interrupts with NodeId = 0, 1 and 2 667 * in the IH cookie. 668 * 2. Bits 16-31 - unused. 669 * 670 * Please note that the kfd_node_idx argument passed to this 671 * function is not related to NodeId field received in the 672 * IH cookie. 673 * 674 * In CPX mode, a KFD node will process an interrupt if: 675 * - the Node Id matches the corresponding bit set in 676 * Bits 0-15. 677 * - AND VMID reported in the interrupt lies within the 678 * VMID range of the node. 679 */ 680 for_each_inst(xcc, xcc_mask) { 681 mapped_xcc = GET_INST(GC, xcc); 682 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 683 } 684 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 685 node->interrupt_bitmap); 686 } 687 688 bool kgd2kfd_device_init(struct kfd_dev *kfd, 689 const struct kgd2kfd_shared_resources *gpu_resources) 690 { 691 unsigned int size, map_process_packet_size, i; 692 struct kfd_node *node; 693 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 694 unsigned int max_proc_per_quantum; 695 int partition_mode; 696 int xcp_idx; 697 698 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 699 KGD_ENGINE_MEC1); 700 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 701 KGD_ENGINE_MEC2); 702 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 703 KGD_ENGINE_SDMA1); 704 kfd->shared_resources = *gpu_resources; 705 706 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 707 708 if (kfd->num_nodes == 0) { 709 dev_err(kfd_device, 710 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 711 kfd->adev->gfx.num_xcc_per_xcp); 712 goto out; 713 } 714 715 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 716 * 32 and 64-bit requests are possible and must be 717 * supported. 718 */ 719 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 720 if (!kfd->pci_atomic_requested && 721 kfd->device_info.needs_pci_atomics && 722 (!kfd->device_info.no_atomic_fw_version || 723 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 724 dev_info(kfd_device, 725 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 726 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 727 kfd->mec_fw_version, 728 kfd->device_info.no_atomic_fw_version); 729 return false; 730 } 731 732 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 733 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 734 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 735 736 /* For GFX9.4.3, we need special handling for VMIDs depending on 737 * partition mode. 738 * In CPX mode, the VMID range needs to be shared between XCDs. 739 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 740 * divide them equally, we change starting VMID to 4 and not use 741 * VMID 3. 742 * If the VMID range changes for GFX9.4.3, then this code MUST be 743 * revisited. 744 */ 745 if (kfd->adev->xcp_mgr) { 746 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 747 AMDGPU_XCP_FL_LOCKED); 748 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 749 kfd->num_nodes != 1) { 750 vmid_num_kfd /= 2; 751 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 752 } 753 } 754 755 /* Verify module parameters regarding mapped process number*/ 756 if (hws_max_conc_proc >= 0) 757 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 758 else 759 max_proc_per_quantum = vmid_num_kfd; 760 761 /* calculate max size of mqds needed for queues */ 762 size = max_num_of_queues_per_device * 763 kfd->device_info.mqd_size_aligned; 764 765 /* 766 * calculate max size of runlist packet. 767 * There can be only 2 packets at once 768 */ 769 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 770 sizeof(struct pm4_mes_map_process_aldebaran) : 771 sizeof(struct pm4_mes_map_process); 772 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 773 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 774 + sizeof(struct pm4_mes_runlist)) * 2; 775 776 /* Add size of HIQ & DIQ */ 777 size += KFD_KERNEL_QUEUE_SIZE * 2; 778 779 /* add another 512KB for all other allocations on gart (HPD, fences) */ 780 size += 512 * 1024; 781 782 if (amdgpu_amdkfd_alloc_gtt_mem( 783 kfd->adev, size, &kfd->gtt_mem, 784 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 785 false)) { 786 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 787 goto alloc_gtt_mem_failure; 788 } 789 790 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 791 792 /* Initialize GTT sa with 512 byte chunk size */ 793 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 794 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 795 goto kfd_gtt_sa_init_error; 796 } 797 798 if (kfd_doorbell_init(kfd)) { 799 dev_err(kfd_device, 800 "Error initializing doorbell aperture\n"); 801 goto kfd_doorbell_error; 802 } 803 804 if (amdgpu_use_xgmi_p2p) 805 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 806 807 /* 808 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 809 * xGMI connected in the topology so assign a unique hive id per 810 * device based on the pci device location if device is in PCIe mode. 811 */ 812 if (!kfd->hive_id && 813 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 814 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) && 815 kfd->num_nodes > 1) 816 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 817 818 kfd->noretry = kfd->adev->gmc.noretry; 819 820 kfd_cwsr_init(kfd); 821 822 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 823 kfd->num_nodes); 824 825 /* Allocate the KFD nodes */ 826 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 827 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 828 if (!node) 829 goto node_alloc_error; 830 831 node->node_id = i; 832 node->adev = kfd->adev; 833 node->kfd = kfd; 834 node->kfd2kgd = kfd->kfd2kgd; 835 node->vm_info.vmid_num_kfd = vmid_num_kfd; 836 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 837 /* TODO : Check if error handling is needed */ 838 if (node->xcp) { 839 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 840 &node->xcc_mask); 841 ++xcp_idx; 842 } else { 843 node->xcc_mask = 844 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 845 } 846 847 if (node->xcp) { 848 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 849 node->node_id, node->xcp->mem_id, 850 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 851 } 852 853 if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 854 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) && 855 partition_mode == AMDGPU_CPX_PARTITION_MODE && 856 kfd->num_nodes != 1) { 857 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 858 * 4-9 and second XCD gets VMID range 10-15. 859 */ 860 861 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 862 first_vmid_kfd : 863 first_vmid_kfd+vmid_num_kfd; 864 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 865 last_vmid_kfd-vmid_num_kfd : 866 last_vmid_kfd; 867 node->compute_vmid_bitmap = 868 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 869 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 870 } else { 871 node->vm_info.first_vmid_kfd = first_vmid_kfd; 872 node->vm_info.last_vmid_kfd = last_vmid_kfd; 873 node->compute_vmid_bitmap = 874 gpu_resources->compute_vmid_bitmap; 875 } 876 node->max_proc_per_quantum = max_proc_per_quantum; 877 atomic_set(&node->sram_ecc_flag, 0); 878 879 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 880 &node->local_mem_info, node->xcp); 881 882 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 883 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) 884 kfd_setup_interrupt_bitmap(node, i); 885 886 /* Initialize the KFD node */ 887 if (kfd_init_node(node)) { 888 dev_err(kfd_device, "Error initializing KFD node\n"); 889 goto node_init_error; 890 } 891 892 spin_lock_init(&node->watch_points_lock); 893 894 kfd->nodes[i] = node; 895 } 896 897 svm_range_set_max_pages(kfd->adev); 898 899 kfd->init_complete = true; 900 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 901 kfd->adev->pdev->device); 902 903 pr_debug("Starting kfd with the following scheduling policy %d\n", 904 node->dqm->sched_policy); 905 906 goto out; 907 908 node_init_error: 909 node_alloc_error: 910 kfd_cleanup_nodes(kfd, i); 911 kfd_doorbell_fini(kfd); 912 kfd_doorbell_error: 913 kfd_gtt_sa_fini(kfd); 914 kfd_gtt_sa_init_error: 915 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 916 alloc_gtt_mem_failure: 917 dev_err(kfd_device, 918 "device %x:%x NOT added due to errors\n", 919 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 920 out: 921 return kfd->init_complete; 922 } 923 924 void kgd2kfd_device_exit(struct kfd_dev *kfd) 925 { 926 if (kfd->init_complete) { 927 /* Cleanup KFD nodes */ 928 kfd_cleanup_nodes(kfd, kfd->num_nodes); 929 /* Cleanup common/shared resources */ 930 kfd_doorbell_fini(kfd); 931 ida_destroy(&kfd->doorbell_ida); 932 kfd_gtt_sa_fini(kfd); 933 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 934 } 935 936 kfree(kfd); 937 } 938 939 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 940 struct amdgpu_reset_context *reset_context) 941 { 942 struct kfd_node *node; 943 int i; 944 945 if (!kfd->init_complete) 946 return 0; 947 948 for (i = 0; i < kfd->num_nodes; i++) { 949 node = kfd->nodes[i]; 950 kfd_smi_event_update_gpu_reset(node, false, reset_context); 951 } 952 953 kgd2kfd_suspend(kfd, false); 954 955 for (i = 0; i < kfd->num_nodes; i++) 956 kfd_signal_reset_event(kfd->nodes[i]); 957 958 return 0; 959 } 960 961 /* 962 * Fix me. KFD won't be able to resume existing process for now. 963 * We will keep all existing process in a evicted state and 964 * wait the process to be terminated. 965 */ 966 967 int kgd2kfd_post_reset(struct kfd_dev *kfd) 968 { 969 int ret; 970 struct kfd_node *node; 971 int i; 972 973 if (!kfd->init_complete) 974 return 0; 975 976 for (i = 0; i < kfd->num_nodes; i++) { 977 ret = kfd_resume(kfd->nodes[i]); 978 if (ret) 979 return ret; 980 } 981 982 mutex_lock(&kfd_processes_mutex); 983 --kfd_locked; 984 mutex_unlock(&kfd_processes_mutex); 985 986 for (i = 0; i < kfd->num_nodes; i++) { 987 node = kfd->nodes[i]; 988 atomic_set(&node->sram_ecc_flag, 0); 989 kfd_smi_event_update_gpu_reset(node, true, NULL); 990 } 991 992 return 0; 993 } 994 995 bool kfd_is_locked(void) 996 { 997 lockdep_assert_held(&kfd_processes_mutex); 998 return (kfd_locked > 0); 999 } 1000 1001 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 1002 { 1003 struct kfd_node *node; 1004 int i; 1005 1006 if (!kfd->init_complete) 1007 return; 1008 1009 /* for runtime suspend, skip locking kfd */ 1010 if (!run_pm) { 1011 mutex_lock(&kfd_processes_mutex); 1012 /* For first KFD device suspend all the KFD processes */ 1013 if (++kfd_locked == 1) 1014 kfd_suspend_all_processes(); 1015 mutex_unlock(&kfd_processes_mutex); 1016 } 1017 1018 for (i = 0; i < kfd->num_nodes; i++) { 1019 node = kfd->nodes[i]; 1020 node->dqm->ops.stop(node->dqm); 1021 } 1022 } 1023 1024 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1025 { 1026 int ret, i; 1027 1028 if (!kfd->init_complete) 1029 return 0; 1030 1031 for (i = 0; i < kfd->num_nodes; i++) { 1032 ret = kfd_resume(kfd->nodes[i]); 1033 if (ret) 1034 return ret; 1035 } 1036 1037 /* for runtime resume, skip unlocking kfd */ 1038 if (!run_pm) { 1039 mutex_lock(&kfd_processes_mutex); 1040 if (--kfd_locked == 0) 1041 ret = kfd_resume_all_processes(); 1042 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1043 mutex_unlock(&kfd_processes_mutex); 1044 } 1045 1046 return ret; 1047 } 1048 1049 static int kfd_resume(struct kfd_node *node) 1050 { 1051 int err = 0; 1052 1053 err = node->dqm->ops.start(node->dqm); 1054 if (err) 1055 dev_err(kfd_device, 1056 "Error starting queue manager for device %x:%x\n", 1057 node->adev->pdev->vendor, node->adev->pdev->device); 1058 1059 return err; 1060 } 1061 1062 static inline void kfd_queue_work(struct workqueue_struct *wq, 1063 struct work_struct *work) 1064 { 1065 int cpu, new_cpu; 1066 1067 cpu = new_cpu = smp_processor_id(); 1068 do { 1069 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1070 if (cpu_to_node(new_cpu) == numa_node_id()) 1071 break; 1072 } while (cpu != new_cpu); 1073 1074 queue_work_on(new_cpu, wq, work); 1075 } 1076 1077 /* This is called directly from KGD at ISR. */ 1078 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1079 { 1080 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1081 bool is_patched = false; 1082 unsigned long flags; 1083 struct kfd_node *node; 1084 1085 if (!kfd->init_complete) 1086 return; 1087 1088 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1089 dev_err_once(kfd_device, "Ring entry too small\n"); 1090 return; 1091 } 1092 1093 for (i = 0; i < kfd->num_nodes; i++) { 1094 node = kfd->nodes[i]; 1095 spin_lock_irqsave(&node->interrupt_lock, flags); 1096 1097 if (node->interrupts_active 1098 && interrupt_is_wanted(node, ih_ring_entry, 1099 patched_ihre, &is_patched) 1100 && enqueue_ih_ring_entry(node, 1101 is_patched ? patched_ihre : ih_ring_entry)) { 1102 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1103 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1104 return; 1105 } 1106 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1107 } 1108 1109 } 1110 1111 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1112 { 1113 struct kfd_process *p; 1114 int r; 1115 1116 /* Because we are called from arbitrary context (workqueue) as opposed 1117 * to process context, kfd_process could attempt to exit while we are 1118 * running so the lookup function increments the process ref count. 1119 */ 1120 p = kfd_lookup_process_by_mm(mm); 1121 if (!p) 1122 return -ESRCH; 1123 1124 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1125 r = kfd_process_evict_queues(p, trigger); 1126 1127 kfd_unref_process(p); 1128 return r; 1129 } 1130 1131 int kgd2kfd_resume_mm(struct mm_struct *mm) 1132 { 1133 struct kfd_process *p; 1134 int r; 1135 1136 /* Because we are called from arbitrary context (workqueue) as opposed 1137 * to process context, kfd_process could attempt to exit while we are 1138 * running so the lookup function increments the process ref count. 1139 */ 1140 p = kfd_lookup_process_by_mm(mm); 1141 if (!p) 1142 return -ESRCH; 1143 1144 r = kfd_process_restore_queues(p); 1145 1146 kfd_unref_process(p); 1147 return r; 1148 } 1149 1150 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1151 * prepare for safe eviction of KFD BOs that belong to the specified 1152 * process. 1153 * 1154 * @mm: mm_struct that identifies the specified KFD process 1155 * @fence: eviction fence attached to KFD process BOs 1156 * 1157 */ 1158 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1159 struct dma_fence *fence) 1160 { 1161 struct kfd_process *p; 1162 unsigned long active_time; 1163 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1164 1165 if (!fence) 1166 return -EINVAL; 1167 1168 if (dma_fence_is_signaled(fence)) 1169 return 0; 1170 1171 p = kfd_lookup_process_by_mm(mm); 1172 if (!p) 1173 return -ENODEV; 1174 1175 if (fence->seqno == p->last_eviction_seqno) 1176 goto out; 1177 1178 p->last_eviction_seqno = fence->seqno; 1179 1180 /* Avoid KFD process starvation. Wait for at least 1181 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1182 */ 1183 active_time = get_jiffies_64() - p->last_restore_timestamp; 1184 if (delay_jiffies > active_time) 1185 delay_jiffies -= active_time; 1186 else 1187 delay_jiffies = 0; 1188 1189 /* During process initialization eviction_work.dwork is initialized 1190 * to kfd_evict_bo_worker 1191 */ 1192 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1193 p->lead_thread->pid, delay_jiffies); 1194 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1195 out: 1196 kfd_unref_process(p); 1197 return 0; 1198 } 1199 1200 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1201 unsigned int chunk_size) 1202 { 1203 if (WARN_ON(buf_size < chunk_size)) 1204 return -EINVAL; 1205 if (WARN_ON(buf_size == 0)) 1206 return -EINVAL; 1207 if (WARN_ON(chunk_size == 0)) 1208 return -EINVAL; 1209 1210 kfd->gtt_sa_chunk_size = chunk_size; 1211 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1212 1213 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1214 GFP_KERNEL); 1215 if (!kfd->gtt_sa_bitmap) 1216 return -ENOMEM; 1217 1218 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1219 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1220 1221 mutex_init(&kfd->gtt_sa_lock); 1222 1223 return 0; 1224 } 1225 1226 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1227 { 1228 mutex_destroy(&kfd->gtt_sa_lock); 1229 bitmap_free(kfd->gtt_sa_bitmap); 1230 } 1231 1232 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1233 unsigned int bit_num, 1234 unsigned int chunk_size) 1235 { 1236 return start_addr + bit_num * chunk_size; 1237 } 1238 1239 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1240 unsigned int bit_num, 1241 unsigned int chunk_size) 1242 { 1243 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1244 } 1245 1246 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1247 struct kfd_mem_obj **mem_obj) 1248 { 1249 unsigned int found, start_search, cur_size; 1250 struct kfd_dev *kfd = node->kfd; 1251 1252 if (size == 0) 1253 return -EINVAL; 1254 1255 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1256 return -ENOMEM; 1257 1258 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1259 if (!(*mem_obj)) 1260 return -ENOMEM; 1261 1262 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1263 1264 start_search = 0; 1265 1266 mutex_lock(&kfd->gtt_sa_lock); 1267 1268 kfd_gtt_restart_search: 1269 /* Find the first chunk that is free */ 1270 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1271 kfd->gtt_sa_num_of_chunks, 1272 start_search); 1273 1274 pr_debug("Found = %d\n", found); 1275 1276 /* If there wasn't any free chunk, bail out */ 1277 if (found == kfd->gtt_sa_num_of_chunks) 1278 goto kfd_gtt_no_free_chunk; 1279 1280 /* Update fields of mem_obj */ 1281 (*mem_obj)->range_start = found; 1282 (*mem_obj)->range_end = found; 1283 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1284 kfd->gtt_start_gpu_addr, 1285 found, 1286 kfd->gtt_sa_chunk_size); 1287 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1288 kfd->gtt_start_cpu_ptr, 1289 found, 1290 kfd->gtt_sa_chunk_size); 1291 1292 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1293 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1294 1295 /* If we need only one chunk, mark it as allocated and get out */ 1296 if (size <= kfd->gtt_sa_chunk_size) { 1297 pr_debug("Single bit\n"); 1298 __set_bit(found, kfd->gtt_sa_bitmap); 1299 goto kfd_gtt_out; 1300 } 1301 1302 /* Otherwise, try to see if we have enough contiguous chunks */ 1303 cur_size = size - kfd->gtt_sa_chunk_size; 1304 do { 1305 (*mem_obj)->range_end = 1306 find_next_zero_bit(kfd->gtt_sa_bitmap, 1307 kfd->gtt_sa_num_of_chunks, ++found); 1308 /* 1309 * If next free chunk is not contiguous than we need to 1310 * restart our search from the last free chunk we found (which 1311 * wasn't contiguous to the previous ones 1312 */ 1313 if ((*mem_obj)->range_end != found) { 1314 start_search = found; 1315 goto kfd_gtt_restart_search; 1316 } 1317 1318 /* 1319 * If we reached end of buffer, bail out with error 1320 */ 1321 if (found == kfd->gtt_sa_num_of_chunks) 1322 goto kfd_gtt_no_free_chunk; 1323 1324 /* Check if we don't need another chunk */ 1325 if (cur_size <= kfd->gtt_sa_chunk_size) 1326 cur_size = 0; 1327 else 1328 cur_size -= kfd->gtt_sa_chunk_size; 1329 1330 } while (cur_size > 0); 1331 1332 pr_debug("range_start = %d, range_end = %d\n", 1333 (*mem_obj)->range_start, (*mem_obj)->range_end); 1334 1335 /* Mark the chunks as allocated */ 1336 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1337 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1338 1339 kfd_gtt_out: 1340 mutex_unlock(&kfd->gtt_sa_lock); 1341 return 0; 1342 1343 kfd_gtt_no_free_chunk: 1344 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1345 mutex_unlock(&kfd->gtt_sa_lock); 1346 kfree(*mem_obj); 1347 return -ENOMEM; 1348 } 1349 1350 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1351 { 1352 struct kfd_dev *kfd = node->kfd; 1353 1354 /* Act like kfree when trying to free a NULL object */ 1355 if (!mem_obj) 1356 return 0; 1357 1358 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1359 mem_obj, mem_obj->range_start, mem_obj->range_end); 1360 1361 mutex_lock(&kfd->gtt_sa_lock); 1362 1363 /* Mark the chunks as free */ 1364 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1365 mem_obj->range_end - mem_obj->range_start + 1); 1366 1367 mutex_unlock(&kfd->gtt_sa_lock); 1368 1369 kfree(mem_obj); 1370 return 0; 1371 } 1372 1373 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1374 { 1375 /* 1376 * TODO: Currently update SRAM ECC flag for first node. 1377 * This needs to be updated later when we can 1378 * identify SRAM ECC error on other nodes also. 1379 */ 1380 if (kfd) 1381 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1382 } 1383 1384 void kfd_inc_compute_active(struct kfd_node *node) 1385 { 1386 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1387 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1388 } 1389 1390 void kfd_dec_compute_active(struct kfd_node *node) 1391 { 1392 int count = atomic_dec_return(&node->kfd->compute_profile); 1393 1394 if (count == 0) 1395 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1396 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1397 } 1398 1399 static bool kfd_compute_active(struct kfd_node *node) 1400 { 1401 if (atomic_read(&node->kfd->compute_profile)) 1402 return true; 1403 return false; 1404 } 1405 1406 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1407 { 1408 /* 1409 * TODO: For now, raise the throttling event only on first node. 1410 * This will need to change after we are able to determine 1411 * which node raised the throttling event. 1412 */ 1413 if (kfd && kfd->init_complete) 1414 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1415 throttle_bitmask); 1416 } 1417 1418 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1419 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1420 * When the device has more than two engines, we reserve two for PCIe to enable 1421 * full-duplex and the rest are used as XGMI. 1422 */ 1423 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1424 { 1425 /* If XGMI is not supported, all SDMA engines are PCIe */ 1426 if (!node->adev->gmc.xgmi.supported) 1427 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1428 1429 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1430 } 1431 1432 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1433 { 1434 /* After reserved for PCIe, the rest of engines are XGMI */ 1435 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1436 kfd_get_num_sdma_engines(node); 1437 } 1438 1439 int kgd2kfd_check_and_lock_kfd(void) 1440 { 1441 mutex_lock(&kfd_processes_mutex); 1442 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1443 mutex_unlock(&kfd_processes_mutex); 1444 return -EBUSY; 1445 } 1446 1447 ++kfd_locked; 1448 mutex_unlock(&kfd_processes_mutex); 1449 1450 return 0; 1451 } 1452 1453 void kgd2kfd_unlock_kfd(void) 1454 { 1455 mutex_lock(&kfd_processes_mutex); 1456 --kfd_locked; 1457 mutex_unlock(&kfd_processes_mutex); 1458 } 1459 1460 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1461 { 1462 struct kfd_node *node; 1463 int ret; 1464 1465 if (!kfd->init_complete) 1466 return 0; 1467 1468 if (node_id >= kfd->num_nodes) { 1469 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1470 node_id, kfd->num_nodes - 1); 1471 return -EINVAL; 1472 } 1473 node = kfd->nodes[node_id]; 1474 1475 ret = node->dqm->ops.unhalt(node->dqm); 1476 if (ret) 1477 dev_err(kfd_device, "Error in starting scheduler\n"); 1478 1479 return ret; 1480 } 1481 1482 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1483 { 1484 struct kfd_node *node; 1485 1486 if (!kfd->init_complete) 1487 return 0; 1488 1489 if (node_id >= kfd->num_nodes) { 1490 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1491 node_id, kfd->num_nodes - 1); 1492 return -EINVAL; 1493 } 1494 1495 node = kfd->nodes[node_id]; 1496 return node->dqm->ops.halt(node->dqm); 1497 } 1498 1499 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1500 { 1501 struct kfd_node *node; 1502 1503 if (!kfd->init_complete) 1504 return false; 1505 1506 if (node_id >= kfd->num_nodes) { 1507 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1508 node_id, kfd->num_nodes - 1); 1509 return false; 1510 } 1511 1512 node = kfd->nodes[node_id]; 1513 1514 return kfd_compute_active(node); 1515 } 1516 1517 #if defined(CONFIG_DEBUG_FS) 1518 1519 /* This function will send a package to HIQ to hang the HWS 1520 * which will trigger a GPU reset and bring the HWS back to normal state 1521 */ 1522 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1523 { 1524 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1525 pr_err("HWS is not enabled"); 1526 return -EINVAL; 1527 } 1528 1529 return dqm_debugfs_hang_hws(dev->dqm); 1530 } 1531 1532 #endif 1533