1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/device.h> 25 #include <linux/export.h> 26 #include <linux/err.h> 27 #include <linux/fs.h> 28 #include <linux/file.h> 29 #include <linux/sched.h> 30 #include <linux/slab.h> 31 #include <linux/uaccess.h> 32 #include <linux/compat.h> 33 #include <uapi/linux/kfd_ioctl.h> 34 #include <linux/time.h> 35 #include <linux/mm.h> 36 #include <linux/mman.h> 37 #include <linux/ptrace.h> 38 #include <linux/dma-buf.h> 39 #include <linux/processor.h> 40 #include "kfd_priv.h" 41 #include "kfd_device_queue_manager.h" 42 #include "kfd_svm.h" 43 #include "amdgpu_amdkfd.h" 44 #include "kfd_smi_events.h" 45 #include "amdgpu_dma_buf.h" 46 #include "kfd_debug.h" 47 48 static long kfd_ioctl(struct file *, unsigned int, unsigned long); 49 static int kfd_open(struct inode *, struct file *); 50 static int kfd_release(struct inode *, struct file *); 51 static int kfd_mmap(struct file *, struct vm_area_struct *); 52 53 static const char kfd_dev_name[] = "kfd"; 54 55 static const struct file_operations kfd_fops = { 56 .owner = THIS_MODULE, 57 .unlocked_ioctl = kfd_ioctl, 58 .compat_ioctl = compat_ptr_ioctl, 59 .open = kfd_open, 60 .release = kfd_release, 61 .mmap = kfd_mmap, 62 }; 63 64 static int kfd_char_dev_major = -1; 65 struct device *kfd_device; 66 static const struct class kfd_class = { 67 .name = kfd_dev_name, 68 }; 69 70 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id) 71 { 72 struct kfd_process_device *pdd; 73 74 mutex_lock(&p->mutex); 75 pdd = kfd_process_device_data_by_id(p, gpu_id); 76 77 if (pdd) 78 return pdd; 79 80 mutex_unlock(&p->mutex); 81 return NULL; 82 } 83 84 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd) 85 { 86 mutex_unlock(&pdd->process->mutex); 87 } 88 89 int kfd_chardev_init(void) 90 { 91 int err = 0; 92 93 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops); 94 err = kfd_char_dev_major; 95 if (err < 0) 96 goto err_register_chrdev; 97 98 err = class_register(&kfd_class); 99 if (err) 100 goto err_class_create; 101 102 kfd_device = device_create(&kfd_class, NULL, 103 MKDEV(kfd_char_dev_major, 0), 104 NULL, kfd_dev_name); 105 err = PTR_ERR(kfd_device); 106 if (IS_ERR(kfd_device)) 107 goto err_device_create; 108 109 return 0; 110 111 err_device_create: 112 class_unregister(&kfd_class); 113 err_class_create: 114 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 115 err_register_chrdev: 116 return err; 117 } 118 119 void kfd_chardev_exit(void) 120 { 121 device_destroy(&kfd_class, MKDEV(kfd_char_dev_major, 0)); 122 class_unregister(&kfd_class); 123 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 124 kfd_device = NULL; 125 } 126 127 128 static int kfd_open(struct inode *inode, struct file *filep) 129 { 130 struct kfd_process *process; 131 bool is_32bit_user_mode; 132 133 if (iminor(inode) != 0) 134 return -ENODEV; 135 136 is_32bit_user_mode = in_compat_syscall(); 137 138 if (is_32bit_user_mode) { 139 dev_warn(kfd_device, 140 "Process %d (32-bit) failed to open /dev/kfd\n" 141 "32-bit processes are not supported by amdkfd\n", 142 current->pid); 143 return -EPERM; 144 } 145 146 process = kfd_create_process(current); 147 if (IS_ERR(process)) 148 return PTR_ERR(process); 149 150 if (kfd_process_init_cwsr_apu(process, filep)) { 151 kfd_unref_process(process); 152 return -EFAULT; 153 } 154 155 /* filep now owns the reference returned by kfd_create_process */ 156 filep->private_data = process; 157 158 dev_dbg(kfd_device, "process pid %d opened kfd node, compat mode (32 bit) - %d\n", 159 process->lead_thread->pid, process->is_32bit_user_mode); 160 161 return 0; 162 } 163 164 static int kfd_release(struct inode *inode, struct file *filep) 165 { 166 struct kfd_process *process = filep->private_data; 167 168 if (process) 169 kfd_unref_process(process); 170 171 return 0; 172 } 173 174 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, 175 void *data) 176 { 177 struct kfd_ioctl_get_version_args *args = data; 178 179 args->major_version = KFD_IOCTL_MAJOR_VERSION; 180 args->minor_version = KFD_IOCTL_MINOR_VERSION; 181 182 return 0; 183 } 184 185 static int set_queue_properties_from_user(struct queue_properties *q_properties, 186 struct kfd_ioctl_create_queue_args *args) 187 { 188 /* 189 * Repurpose queue percentage to accommodate new features: 190 * bit 0-7: queue percentage 191 * bit 8-15: pm4_target_xcc 192 */ 193 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) { 194 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 195 return -EINVAL; 196 } 197 198 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 199 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 200 return -EINVAL; 201 } 202 203 if ((args->ring_base_address) && 204 (!access_ok((const void __user *) args->ring_base_address, 205 sizeof(uint64_t)))) { 206 pr_err("Can't access ring base address\n"); 207 return -EFAULT; 208 } 209 210 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 211 pr_err("Ring size must be a power of 2 or 0\n"); 212 return -EINVAL; 213 } 214 215 if (!access_ok((const void __user *) args->read_pointer_address, 216 sizeof(uint32_t))) { 217 pr_err("Can't access read pointer\n"); 218 return -EFAULT; 219 } 220 221 if (!access_ok((const void __user *) args->write_pointer_address, 222 sizeof(uint32_t))) { 223 pr_err("Can't access write pointer\n"); 224 return -EFAULT; 225 } 226 227 if (args->eop_buffer_address && 228 !access_ok((const void __user *) args->eop_buffer_address, 229 sizeof(uint32_t))) { 230 pr_debug("Can't access eop buffer"); 231 return -EFAULT; 232 } 233 234 if (args->ctx_save_restore_address && 235 !access_ok((const void __user *) args->ctx_save_restore_address, 236 sizeof(uint32_t))) { 237 pr_debug("Can't access ctx save restore buffer"); 238 return -EFAULT; 239 } 240 241 q_properties->is_interop = false; 242 q_properties->is_gws = false; 243 q_properties->queue_percent = args->queue_percentage & 0xFF; 244 /* bit 8-15 are repurposed to be PM4 target XCC */ 245 q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF; 246 q_properties->priority = args->queue_priority; 247 q_properties->queue_address = args->ring_base_address; 248 q_properties->queue_size = args->ring_size; 249 q_properties->read_ptr = (void __user *)args->read_pointer_address; 250 q_properties->write_ptr = (void __user *)args->write_pointer_address; 251 q_properties->eop_ring_buffer_address = args->eop_buffer_address; 252 q_properties->eop_ring_buffer_size = args->eop_buffer_size; 253 q_properties->ctx_save_restore_area_address = 254 args->ctx_save_restore_address; 255 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size; 256 q_properties->ctl_stack_size = args->ctl_stack_size; 257 q_properties->sdma_engine_id = args->sdma_engine_id; 258 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE || 259 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 260 q_properties->type = KFD_QUEUE_TYPE_COMPUTE; 261 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA) 262 q_properties->type = KFD_QUEUE_TYPE_SDMA; 263 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI) 264 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI; 265 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_BY_ENG_ID) 266 q_properties->type = KFD_QUEUE_TYPE_SDMA_BY_ENG_ID; 267 else 268 return -ENOTSUPP; 269 270 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 271 q_properties->format = KFD_QUEUE_FORMAT_AQL; 272 else 273 q_properties->format = KFD_QUEUE_FORMAT_PM4; 274 275 pr_debug("Queue Percentage: %d, %d\n", 276 q_properties->queue_percent, args->queue_percentage); 277 278 pr_debug("Queue Priority: %d, %d\n", 279 q_properties->priority, args->queue_priority); 280 281 pr_debug("Queue Address: 0x%llX, 0x%llX\n", 282 q_properties->queue_address, args->ring_base_address); 283 284 pr_debug("Queue Size: 0x%llX, %u\n", 285 q_properties->queue_size, args->ring_size); 286 287 pr_debug("Queue r/w Pointers: %px, %px\n", 288 q_properties->read_ptr, 289 q_properties->write_ptr); 290 291 pr_debug("Queue Format: %d\n", q_properties->format); 292 293 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address); 294 295 pr_debug("Queue CTX save area: 0x%llX\n", 296 q_properties->ctx_save_restore_area_address); 297 298 return 0; 299 } 300 301 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, 302 void *data) 303 { 304 struct kfd_ioctl_create_queue_args *args = data; 305 struct kfd_node *dev; 306 int err = 0; 307 unsigned int queue_id; 308 struct kfd_process_device *pdd; 309 struct queue_properties q_properties; 310 uint32_t doorbell_offset_in_process = 0; 311 312 memset(&q_properties, 0, sizeof(struct queue_properties)); 313 314 pr_debug("Creating queue ioctl\n"); 315 316 err = set_queue_properties_from_user(&q_properties, args); 317 if (err) 318 return err; 319 320 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id); 321 322 mutex_lock(&p->mutex); 323 324 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 325 if (!pdd) { 326 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 327 err = -EINVAL; 328 goto err_pdd; 329 } 330 dev = pdd->dev; 331 332 pdd = kfd_bind_process_to_device(dev, p); 333 if (IS_ERR(pdd)) { 334 err = -ESRCH; 335 goto err_bind_process; 336 } 337 338 if (q_properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 339 int max_sdma_eng_id = kfd_get_num_sdma_engines(dev) + 340 kfd_get_num_xgmi_sdma_engines(dev) - 1; 341 342 if (q_properties.sdma_engine_id > max_sdma_eng_id) { 343 err = -EINVAL; 344 pr_err("sdma_engine_id %i exceeds maximum id of %i\n", 345 q_properties.sdma_engine_id, max_sdma_eng_id); 346 goto err_sdma_engine_id; 347 } 348 } 349 350 if (!pdd->qpd.proc_doorbells) { 351 err = kfd_alloc_process_doorbells(dev->kfd, pdd); 352 if (err) { 353 pr_debug("failed to allocate process doorbells\n"); 354 goto err_bind_process; 355 } 356 } 357 358 err = kfd_queue_acquire_buffers(pdd, &q_properties); 359 if (err) { 360 pr_debug("failed to acquire user queue buffers\n"); 361 goto err_acquire_queue_buf; 362 } 363 364 pr_debug("Creating queue for process pid %d on gpu 0x%x\n", 365 p->lead_thread->pid, 366 dev->id); 367 368 err = pqm_create_queue(&p->pqm, dev, &q_properties, &queue_id, 369 NULL, NULL, NULL, &doorbell_offset_in_process); 370 if (err != 0) 371 goto err_create_queue; 372 373 args->queue_id = queue_id; 374 375 376 /* Return gpu_id as doorbell offset for mmap usage */ 377 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL; 378 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id); 379 if (KFD_IS_SOC15(dev)) 380 /* On SOC15 ASICs, include the doorbell offset within the 381 * process doorbell frame, which is 2 pages. 382 */ 383 args->doorbell_offset |= doorbell_offset_in_process; 384 385 mutex_unlock(&p->mutex); 386 387 pr_debug("Queue id %d was created successfully\n", args->queue_id); 388 389 pr_debug("Ring buffer address == 0x%016llX\n", 390 args->ring_base_address); 391 392 pr_debug("Read ptr address == 0x%016llX\n", 393 args->read_pointer_address); 394 395 pr_debug("Write ptr address == 0x%016llX\n", 396 args->write_pointer_address); 397 398 kfd_dbg_ev_raise(KFD_EC_MASK(EC_QUEUE_NEW), p, dev, queue_id, false, NULL, 0); 399 return 0; 400 401 err_create_queue: 402 kfd_queue_unref_bo_vas(pdd, &q_properties); 403 kfd_queue_release_buffers(pdd, &q_properties); 404 err_acquire_queue_buf: 405 err_sdma_engine_id: 406 err_bind_process: 407 err_pdd: 408 mutex_unlock(&p->mutex); 409 return err; 410 } 411 412 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p, 413 void *data) 414 { 415 int retval; 416 struct kfd_ioctl_destroy_queue_args *args = data; 417 418 pr_debug("Destroying queue id %d for process pid %d\n", 419 args->queue_id, 420 p->lead_thread->pid); 421 422 mutex_lock(&p->mutex); 423 424 retval = pqm_destroy_queue(&p->pqm, args->queue_id); 425 426 mutex_unlock(&p->mutex); 427 return retval; 428 } 429 430 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, 431 void *data) 432 { 433 int retval; 434 struct kfd_ioctl_update_queue_args *args = data; 435 struct queue_properties properties; 436 437 /* 438 * Repurpose queue percentage to accommodate new features: 439 * bit 0-7: queue percentage 440 * bit 8-15: pm4_target_xcc 441 */ 442 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) { 443 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 444 return -EINVAL; 445 } 446 447 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 448 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 449 return -EINVAL; 450 } 451 452 if ((args->ring_base_address) && 453 (!access_ok((const void __user *) args->ring_base_address, 454 sizeof(uint64_t)))) { 455 pr_err("Can't access ring base address\n"); 456 return -EFAULT; 457 } 458 459 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 460 pr_err("Ring size must be a power of 2 or 0\n"); 461 return -EINVAL; 462 } 463 464 properties.queue_address = args->ring_base_address; 465 properties.queue_size = args->ring_size; 466 properties.queue_percent = args->queue_percentage & 0xFF; 467 /* bit 8-15 are repurposed to be PM4 target XCC */ 468 properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF; 469 properties.priority = args->queue_priority; 470 471 pr_debug("Updating queue id %d for process pid %d\n", 472 args->queue_id, p->lead_thread->pid); 473 474 mutex_lock(&p->mutex); 475 476 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties); 477 478 mutex_unlock(&p->mutex); 479 480 return retval; 481 } 482 483 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, 484 void *data) 485 { 486 int retval; 487 const int max_num_cus = 1024; 488 struct kfd_ioctl_set_cu_mask_args *args = data; 489 struct mqd_update_info minfo = {0}; 490 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr; 491 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32); 492 493 if ((args->num_cu_mask % 32) != 0) { 494 pr_debug("num_cu_mask 0x%x must be a multiple of 32", 495 args->num_cu_mask); 496 return -EINVAL; 497 } 498 499 minfo.cu_mask.count = args->num_cu_mask; 500 if (minfo.cu_mask.count == 0) { 501 pr_debug("CU mask cannot be 0"); 502 return -EINVAL; 503 } 504 505 /* To prevent an unreasonably large CU mask size, set an arbitrary 506 * limit of max_num_cus bits. We can then just drop any CU mask bits 507 * past max_num_cus bits and just use the first max_num_cus bits. 508 */ 509 if (minfo.cu_mask.count > max_num_cus) { 510 pr_debug("CU mask cannot be greater than 1024 bits"); 511 minfo.cu_mask.count = max_num_cus; 512 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32); 513 } 514 515 minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL); 516 if (!minfo.cu_mask.ptr) 517 return -ENOMEM; 518 519 retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size); 520 if (retval) { 521 pr_debug("Could not copy CU mask from userspace"); 522 retval = -EFAULT; 523 goto out; 524 } 525 526 mutex_lock(&p->mutex); 527 528 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo); 529 530 mutex_unlock(&p->mutex); 531 532 out: 533 kfree(minfo.cu_mask.ptr); 534 return retval; 535 } 536 537 static int kfd_ioctl_get_queue_wave_state(struct file *filep, 538 struct kfd_process *p, void *data) 539 { 540 struct kfd_ioctl_get_queue_wave_state_args *args = data; 541 int r; 542 543 mutex_lock(&p->mutex); 544 545 r = pqm_get_wave_state(&p->pqm, args->queue_id, 546 (void __user *)args->ctl_stack_address, 547 &args->ctl_stack_used_size, 548 &args->save_area_used_size); 549 550 mutex_unlock(&p->mutex); 551 552 return r; 553 } 554 555 static int kfd_ioctl_set_memory_policy(struct file *filep, 556 struct kfd_process *p, void *data) 557 { 558 struct kfd_ioctl_set_memory_policy_args *args = data; 559 int err = 0; 560 struct kfd_process_device *pdd; 561 enum cache_policy default_policy, alternate_policy; 562 563 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT 564 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 565 return -EINVAL; 566 } 567 568 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT 569 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 570 return -EINVAL; 571 } 572 573 mutex_lock(&p->mutex); 574 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 575 if (!pdd) { 576 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 577 err = -EINVAL; 578 goto err_pdd; 579 } 580 581 pdd = kfd_bind_process_to_device(pdd->dev, p); 582 if (IS_ERR(pdd)) { 583 err = -ESRCH; 584 goto out; 585 } 586 587 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT) 588 ? cache_policy_coherent : cache_policy_noncoherent; 589 590 alternate_policy = 591 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT) 592 ? cache_policy_coherent : cache_policy_noncoherent; 593 594 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm, 595 &pdd->qpd, 596 default_policy, 597 alternate_policy, 598 (void __user *)args->alternate_aperture_base, 599 args->alternate_aperture_size)) 600 err = -EINVAL; 601 602 out: 603 err_pdd: 604 mutex_unlock(&p->mutex); 605 606 return err; 607 } 608 609 static int kfd_ioctl_set_trap_handler(struct file *filep, 610 struct kfd_process *p, void *data) 611 { 612 struct kfd_ioctl_set_trap_handler_args *args = data; 613 int err = 0; 614 struct kfd_process_device *pdd; 615 616 mutex_lock(&p->mutex); 617 618 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 619 if (!pdd) { 620 err = -EINVAL; 621 goto err_pdd; 622 } 623 624 pdd = kfd_bind_process_to_device(pdd->dev, p); 625 if (IS_ERR(pdd)) { 626 err = -ESRCH; 627 goto out; 628 } 629 630 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr); 631 632 out: 633 err_pdd: 634 mutex_unlock(&p->mutex); 635 636 return err; 637 } 638 639 static int kfd_ioctl_dbg_register(struct file *filep, 640 struct kfd_process *p, void *data) 641 { 642 return -EPERM; 643 } 644 645 static int kfd_ioctl_dbg_unregister(struct file *filep, 646 struct kfd_process *p, void *data) 647 { 648 return -EPERM; 649 } 650 651 static int kfd_ioctl_dbg_address_watch(struct file *filep, 652 struct kfd_process *p, void *data) 653 { 654 return -EPERM; 655 } 656 657 /* Parse and generate fixed size data structure for wave control */ 658 static int kfd_ioctl_dbg_wave_control(struct file *filep, 659 struct kfd_process *p, void *data) 660 { 661 return -EPERM; 662 } 663 664 static int kfd_ioctl_get_clock_counters(struct file *filep, 665 struct kfd_process *p, void *data) 666 { 667 struct kfd_ioctl_get_clock_counters_args *args = data; 668 struct kfd_process_device *pdd; 669 670 mutex_lock(&p->mutex); 671 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 672 mutex_unlock(&p->mutex); 673 if (pdd) 674 /* Reading GPU clock counter from KGD */ 675 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev); 676 else 677 /* Node without GPU resource */ 678 args->gpu_clock_counter = 0; 679 680 /* No access to rdtsc. Using raw monotonic time */ 681 args->cpu_clock_counter = ktime_get_raw_ns(); 682 args->system_clock_counter = ktime_get_boottime_ns(); 683 684 /* Since the counter is in nano-seconds we use 1GHz frequency */ 685 args->system_clock_freq = 1000000000; 686 687 return 0; 688 } 689 690 691 static int kfd_ioctl_get_process_apertures(struct file *filp, 692 struct kfd_process *p, void *data) 693 { 694 struct kfd_ioctl_get_process_apertures_args *args = data; 695 struct kfd_process_device_apertures *pAperture; 696 int i; 697 698 dev_dbg(kfd_device, "get apertures for process pid %d", p->lead_thread->pid); 699 700 args->num_of_nodes = 0; 701 702 mutex_lock(&p->mutex); 703 /* Run over all pdd of the process */ 704 for (i = 0; i < p->n_pdds; i++) { 705 struct kfd_process_device *pdd = p->pdds[i]; 706 707 pAperture = 708 &args->process_apertures[args->num_of_nodes]; 709 pAperture->gpu_id = pdd->dev->id; 710 pAperture->lds_base = pdd->lds_base; 711 pAperture->lds_limit = pdd->lds_limit; 712 pAperture->gpuvm_base = pdd->gpuvm_base; 713 pAperture->gpuvm_limit = pdd->gpuvm_limit; 714 pAperture->scratch_base = pdd->scratch_base; 715 pAperture->scratch_limit = pdd->scratch_limit; 716 717 dev_dbg(kfd_device, 718 "node id %u\n", args->num_of_nodes); 719 dev_dbg(kfd_device, 720 "gpu id %u\n", pdd->dev->id); 721 dev_dbg(kfd_device, 722 "lds_base %llX\n", pdd->lds_base); 723 dev_dbg(kfd_device, 724 "lds_limit %llX\n", pdd->lds_limit); 725 dev_dbg(kfd_device, 726 "gpuvm_base %llX\n", pdd->gpuvm_base); 727 dev_dbg(kfd_device, 728 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 729 dev_dbg(kfd_device, 730 "scratch_base %llX\n", pdd->scratch_base); 731 dev_dbg(kfd_device, 732 "scratch_limit %llX\n", pdd->scratch_limit); 733 734 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS) 735 break; 736 } 737 mutex_unlock(&p->mutex); 738 739 return 0; 740 } 741 742 static int kfd_ioctl_get_process_apertures_new(struct file *filp, 743 struct kfd_process *p, void *data) 744 { 745 struct kfd_ioctl_get_process_apertures_new_args *args = data; 746 struct kfd_process_device_apertures *pa; 747 int ret; 748 int i; 749 750 dev_dbg(kfd_device, "get apertures for process pid %d", 751 p->lead_thread->pid); 752 753 if (args->num_of_nodes == 0) { 754 /* Return number of nodes, so that user space can alloacate 755 * sufficient memory 756 */ 757 mutex_lock(&p->mutex); 758 args->num_of_nodes = p->n_pdds; 759 goto out_unlock; 760 } 761 762 /* Fill in process-aperture information for all available 763 * nodes, but not more than args->num_of_nodes as that is 764 * the amount of memory allocated by user 765 */ 766 pa = kcalloc(args->num_of_nodes, sizeof(struct kfd_process_device_apertures), 767 GFP_KERNEL); 768 if (!pa) 769 return -ENOMEM; 770 771 mutex_lock(&p->mutex); 772 773 if (!p->n_pdds) { 774 args->num_of_nodes = 0; 775 kfree(pa); 776 goto out_unlock; 777 } 778 779 /* Run over all pdd of the process */ 780 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) { 781 struct kfd_process_device *pdd = p->pdds[i]; 782 783 pa[i].gpu_id = pdd->dev->id; 784 pa[i].lds_base = pdd->lds_base; 785 pa[i].lds_limit = pdd->lds_limit; 786 pa[i].gpuvm_base = pdd->gpuvm_base; 787 pa[i].gpuvm_limit = pdd->gpuvm_limit; 788 pa[i].scratch_base = pdd->scratch_base; 789 pa[i].scratch_limit = pdd->scratch_limit; 790 791 dev_dbg(kfd_device, 792 "gpu id %u\n", pdd->dev->id); 793 dev_dbg(kfd_device, 794 "lds_base %llX\n", pdd->lds_base); 795 dev_dbg(kfd_device, 796 "lds_limit %llX\n", pdd->lds_limit); 797 dev_dbg(kfd_device, 798 "gpuvm_base %llX\n", pdd->gpuvm_base); 799 dev_dbg(kfd_device, 800 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 801 dev_dbg(kfd_device, 802 "scratch_base %llX\n", pdd->scratch_base); 803 dev_dbg(kfd_device, 804 "scratch_limit %llX\n", pdd->scratch_limit); 805 } 806 mutex_unlock(&p->mutex); 807 808 args->num_of_nodes = i; 809 ret = copy_to_user( 810 (void __user *)args->kfd_process_device_apertures_ptr, 811 pa, 812 (i * sizeof(struct kfd_process_device_apertures))); 813 kfree(pa); 814 return ret ? -EFAULT : 0; 815 816 out_unlock: 817 mutex_unlock(&p->mutex); 818 return 0; 819 } 820 821 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, 822 void *data) 823 { 824 struct kfd_ioctl_create_event_args *args = data; 825 int err; 826 827 /* For dGPUs the event page is allocated in user mode. The 828 * handle is passed to KFD with the first call to this IOCTL 829 * through the event_page_offset field. 830 */ 831 if (args->event_page_offset) { 832 mutex_lock(&p->mutex); 833 err = kfd_kmap_event_page(p, args->event_page_offset); 834 mutex_unlock(&p->mutex); 835 if (err) 836 return err; 837 } 838 839 err = kfd_event_create(filp, p, args->event_type, 840 args->auto_reset != 0, args->node_id, 841 &args->event_id, &args->event_trigger_data, 842 &args->event_page_offset, 843 &args->event_slot_index); 844 845 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__); 846 return err; 847 } 848 849 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p, 850 void *data) 851 { 852 struct kfd_ioctl_destroy_event_args *args = data; 853 854 return kfd_event_destroy(p, args->event_id); 855 } 856 857 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p, 858 void *data) 859 { 860 struct kfd_ioctl_set_event_args *args = data; 861 862 return kfd_set_event(p, args->event_id); 863 } 864 865 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p, 866 void *data) 867 { 868 struct kfd_ioctl_reset_event_args *args = data; 869 870 return kfd_reset_event(p, args->event_id); 871 } 872 873 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, 874 void *data) 875 { 876 struct kfd_ioctl_wait_events_args *args = data; 877 878 return kfd_wait_on_events(p, args->num_events, 879 (void __user *)args->events_ptr, 880 (args->wait_for_all != 0), 881 &args->timeout, &args->wait_result); 882 } 883 static int kfd_ioctl_set_scratch_backing_va(struct file *filep, 884 struct kfd_process *p, void *data) 885 { 886 struct kfd_ioctl_set_scratch_backing_va_args *args = data; 887 struct kfd_process_device *pdd; 888 struct kfd_node *dev; 889 long err; 890 891 mutex_lock(&p->mutex); 892 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 893 if (!pdd) { 894 err = -EINVAL; 895 goto err_pdd; 896 } 897 dev = pdd->dev; 898 899 pdd = kfd_bind_process_to_device(dev, p); 900 if (IS_ERR(pdd)) { 901 err = PTR_ERR(pdd); 902 goto bind_process_to_device_fail; 903 } 904 905 pdd->qpd.sh_hidden_private_base = args->va_addr; 906 907 mutex_unlock(&p->mutex); 908 909 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS && 910 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va) 911 dev->kfd2kgd->set_scratch_backing_va( 912 dev->adev, args->va_addr, pdd->qpd.vmid); 913 914 return 0; 915 916 bind_process_to_device_fail: 917 err_pdd: 918 mutex_unlock(&p->mutex); 919 return err; 920 } 921 922 static int kfd_ioctl_get_tile_config(struct file *filep, 923 struct kfd_process *p, void *data) 924 { 925 struct kfd_ioctl_get_tile_config_args *args = data; 926 struct kfd_process_device *pdd; 927 struct tile_config config; 928 int err = 0; 929 930 mutex_lock(&p->mutex); 931 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 932 mutex_unlock(&p->mutex); 933 if (!pdd) 934 return -EINVAL; 935 936 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config); 937 938 args->gb_addr_config = config.gb_addr_config; 939 args->num_banks = config.num_banks; 940 args->num_ranks = config.num_ranks; 941 942 if (args->num_tile_configs > config.num_tile_configs) 943 args->num_tile_configs = config.num_tile_configs; 944 err = copy_to_user((void __user *)args->tile_config_ptr, 945 config.tile_config_ptr, 946 args->num_tile_configs * sizeof(uint32_t)); 947 if (err) { 948 args->num_tile_configs = 0; 949 return -EFAULT; 950 } 951 952 if (args->num_macro_tile_configs > config.num_macro_tile_configs) 953 args->num_macro_tile_configs = 954 config.num_macro_tile_configs; 955 err = copy_to_user((void __user *)args->macro_tile_config_ptr, 956 config.macro_tile_config_ptr, 957 args->num_macro_tile_configs * sizeof(uint32_t)); 958 if (err) { 959 args->num_macro_tile_configs = 0; 960 return -EFAULT; 961 } 962 963 return 0; 964 } 965 966 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p, 967 void *data) 968 { 969 struct kfd_ioctl_acquire_vm_args *args = data; 970 struct kfd_process_device *pdd; 971 struct file *drm_file; 972 int ret; 973 974 drm_file = fget(args->drm_fd); 975 if (!drm_file) 976 return -EINVAL; 977 978 mutex_lock(&p->mutex); 979 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 980 if (!pdd) { 981 ret = -EINVAL; 982 goto err_pdd; 983 } 984 985 if (pdd->drm_file) { 986 ret = pdd->drm_file == drm_file ? 0 : -EBUSY; 987 goto err_drm_file; 988 } 989 990 ret = kfd_process_device_init_vm(pdd, drm_file); 991 if (ret) 992 goto err_unlock; 993 994 /* On success, the PDD keeps the drm_file reference */ 995 mutex_unlock(&p->mutex); 996 997 return 0; 998 999 err_unlock: 1000 err_pdd: 1001 err_drm_file: 1002 mutex_unlock(&p->mutex); 1003 fput(drm_file); 1004 return ret; 1005 } 1006 1007 bool kfd_dev_is_large_bar(struct kfd_node *dev) 1008 { 1009 if (dev->kfd->adev->debug_largebar) { 1010 pr_debug("Simulate large-bar allocation on non large-bar machine\n"); 1011 return true; 1012 } 1013 1014 if (dev->local_mem_info.local_mem_size_private == 0 && 1015 dev->local_mem_info.local_mem_size_public > 0) 1016 return true; 1017 1018 if (dev->local_mem_info.local_mem_size_public == 0 && 1019 dev->kfd->adev->gmc.is_app_apu) { 1020 pr_debug("APP APU, Consider like a large bar system\n"); 1021 return true; 1022 } 1023 1024 return false; 1025 } 1026 1027 static int kfd_ioctl_get_available_memory(struct file *filep, 1028 struct kfd_process *p, void *data) 1029 { 1030 struct kfd_ioctl_get_available_memory_args *args = data; 1031 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id); 1032 1033 if (!pdd) 1034 return -EINVAL; 1035 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev, 1036 pdd->dev->node_id); 1037 kfd_unlock_pdd(pdd); 1038 return 0; 1039 } 1040 1041 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, 1042 struct kfd_process *p, void *data) 1043 { 1044 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data; 1045 struct kfd_process_device *pdd; 1046 void *mem; 1047 struct kfd_node *dev; 1048 int idr_handle; 1049 long err; 1050 uint64_t offset = args->mmap_offset; 1051 uint32_t flags = args->flags; 1052 1053 if (args->size == 0) 1054 return -EINVAL; 1055 1056 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1057 /* Flush pending deferred work to avoid racing with deferred actions 1058 * from previous memory map changes (e.g. munmap). 1059 */ 1060 svm_range_list_lock_and_flush_work(&p->svms, current->mm); 1061 mutex_lock(&p->svms.lock); 1062 mmap_write_unlock(current->mm); 1063 if (interval_tree_iter_first(&p->svms.objects, 1064 args->va_addr >> PAGE_SHIFT, 1065 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) { 1066 pr_err("Address: 0x%llx already allocated by SVM\n", 1067 args->va_addr); 1068 mutex_unlock(&p->svms.lock); 1069 return -EADDRINUSE; 1070 } 1071 1072 /* When register user buffer check if it has been registered by svm by 1073 * buffer cpu virtual address. 1074 */ 1075 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) && 1076 interval_tree_iter_first(&p->svms.objects, 1077 args->mmap_offset >> PAGE_SHIFT, 1078 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) { 1079 pr_err("User Buffer Address: 0x%llx already allocated by SVM\n", 1080 args->mmap_offset); 1081 mutex_unlock(&p->svms.lock); 1082 return -EADDRINUSE; 1083 } 1084 1085 mutex_unlock(&p->svms.lock); 1086 #endif 1087 mutex_lock(&p->mutex); 1088 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1089 if (!pdd) { 1090 err = -EINVAL; 1091 goto err_pdd; 1092 } 1093 1094 dev = pdd->dev; 1095 1096 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) && 1097 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && 1098 !kfd_dev_is_large_bar(dev)) { 1099 pr_err("Alloc host visible vram on small bar is not allowed\n"); 1100 err = -EINVAL; 1101 goto err_large_bar; 1102 } 1103 1104 pdd = kfd_bind_process_to_device(dev, p); 1105 if (IS_ERR(pdd)) { 1106 err = PTR_ERR(pdd); 1107 goto err_unlock; 1108 } 1109 1110 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 1111 if (args->size != kfd_doorbell_process_slice(dev->kfd)) { 1112 err = -EINVAL; 1113 goto err_unlock; 1114 } 1115 offset = kfd_get_process_doorbells(pdd); 1116 if (!offset) { 1117 err = -ENOMEM; 1118 goto err_unlock; 1119 } 1120 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 1121 if (args->size != PAGE_SIZE) { 1122 err = -EINVAL; 1123 goto err_unlock; 1124 } 1125 offset = dev->adev->rmmio_remap.bus_addr; 1126 if (!offset || (PAGE_SIZE > 4096)) { 1127 err = -ENOMEM; 1128 goto err_unlock; 1129 } 1130 } 1131 1132 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 1133 dev->adev, args->va_addr, args->size, 1134 pdd->drm_priv, (struct kgd_mem **) &mem, &offset, 1135 flags, false); 1136 1137 if (err) 1138 goto err_unlock; 1139 1140 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1141 if (idr_handle < 0) { 1142 err = -EFAULT; 1143 goto err_free; 1144 } 1145 1146 /* Update the VRAM usage count */ 1147 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 1148 uint64_t size = args->size; 1149 1150 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM) 1151 size >>= 1; 1152 atomic64_add(PAGE_ALIGN(size), &pdd->vram_usage); 1153 } 1154 1155 mutex_unlock(&p->mutex); 1156 1157 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1158 args->mmap_offset = offset; 1159 1160 /* MMIO is mapped through kfd device 1161 * Generate a kfd mmap offset 1162 */ 1163 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1164 args->mmap_offset = KFD_MMAP_TYPE_MMIO 1165 | KFD_MMAP_GPU_ID(args->gpu_id); 1166 1167 return 0; 1168 1169 err_free: 1170 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, 1171 pdd->drm_priv, NULL); 1172 err_unlock: 1173 err_pdd: 1174 err_large_bar: 1175 mutex_unlock(&p->mutex); 1176 return err; 1177 } 1178 1179 static int kfd_ioctl_free_memory_of_gpu(struct file *filep, 1180 struct kfd_process *p, void *data) 1181 { 1182 struct kfd_ioctl_free_memory_of_gpu_args *args = data; 1183 struct kfd_process_device *pdd; 1184 void *mem; 1185 int ret; 1186 uint64_t size = 0; 1187 1188 mutex_lock(&p->mutex); 1189 /* 1190 * Safeguard to prevent user space from freeing signal BO. 1191 * It will be freed at process termination. 1192 */ 1193 if (p->signal_handle && (p->signal_handle == args->handle)) { 1194 pr_err("Free signal BO is not allowed\n"); 1195 ret = -EPERM; 1196 goto err_unlock; 1197 } 1198 1199 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1200 if (!pdd) { 1201 pr_err("Process device data doesn't exist\n"); 1202 ret = -EINVAL; 1203 goto err_pdd; 1204 } 1205 1206 mem = kfd_process_device_translate_handle( 1207 pdd, GET_IDR_HANDLE(args->handle)); 1208 if (!mem) { 1209 ret = -EINVAL; 1210 goto err_unlock; 1211 } 1212 1213 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, 1214 (struct kgd_mem *)mem, pdd->drm_priv, &size); 1215 1216 /* If freeing the buffer failed, leave the handle in place for 1217 * clean-up during process tear-down. 1218 */ 1219 if (!ret) 1220 kfd_process_device_remove_obj_handle( 1221 pdd, GET_IDR_HANDLE(args->handle)); 1222 1223 atomic64_sub(size, &pdd->vram_usage); 1224 1225 err_unlock: 1226 err_pdd: 1227 mutex_unlock(&p->mutex); 1228 return ret; 1229 } 1230 1231 static int kfd_ioctl_map_memory_to_gpu(struct file *filep, 1232 struct kfd_process *p, void *data) 1233 { 1234 struct kfd_ioctl_map_memory_to_gpu_args *args = data; 1235 struct kfd_process_device *pdd, *peer_pdd; 1236 void *mem; 1237 struct kfd_node *dev; 1238 long err = 0; 1239 int i; 1240 uint32_t *devices_arr = NULL; 1241 1242 if (!args->n_devices) { 1243 pr_debug("Device IDs array empty\n"); 1244 return -EINVAL; 1245 } 1246 if (args->n_success > args->n_devices) { 1247 pr_debug("n_success exceeds n_devices\n"); 1248 return -EINVAL; 1249 } 1250 1251 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1252 GFP_KERNEL); 1253 if (!devices_arr) 1254 return -ENOMEM; 1255 1256 err = copy_from_user(devices_arr, 1257 (void __user *)args->device_ids_array_ptr, 1258 args->n_devices * sizeof(*devices_arr)); 1259 if (err != 0) { 1260 err = -EFAULT; 1261 goto copy_from_user_failed; 1262 } 1263 1264 mutex_lock(&p->mutex); 1265 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1266 if (!pdd) { 1267 err = -EINVAL; 1268 goto get_process_device_data_failed; 1269 } 1270 dev = pdd->dev; 1271 1272 pdd = kfd_bind_process_to_device(dev, p); 1273 if (IS_ERR(pdd)) { 1274 err = PTR_ERR(pdd); 1275 goto bind_process_to_device_failed; 1276 } 1277 1278 mem = kfd_process_device_translate_handle(pdd, 1279 GET_IDR_HANDLE(args->handle)); 1280 if (!mem) { 1281 err = -ENOMEM; 1282 goto get_mem_obj_from_handle_failed; 1283 } 1284 1285 for (i = args->n_success; i < args->n_devices; i++) { 1286 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1287 if (!peer_pdd) { 1288 pr_debug("Getting device by id failed for 0x%x\n", 1289 devices_arr[i]); 1290 err = -EINVAL; 1291 goto get_mem_obj_from_handle_failed; 1292 } 1293 1294 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p); 1295 if (IS_ERR(peer_pdd)) { 1296 err = PTR_ERR(peer_pdd); 1297 goto get_mem_obj_from_handle_failed; 1298 } 1299 1300 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 1301 peer_pdd->dev->adev, (struct kgd_mem *)mem, 1302 peer_pdd->drm_priv); 1303 if (err) { 1304 struct pci_dev *pdev = peer_pdd->dev->adev->pdev; 1305 1306 dev_err(dev->adev->dev, 1307 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n", 1308 pci_domain_nr(pdev->bus), 1309 pdev->bus->number, 1310 PCI_SLOT(pdev->devfn), 1311 PCI_FUNC(pdev->devfn), 1312 ((struct kgd_mem *)mem)->domain); 1313 goto map_memory_to_gpu_failed; 1314 } 1315 args->n_success = i+1; 1316 } 1317 1318 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true); 1319 if (err) { 1320 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1321 goto sync_memory_failed; 1322 } 1323 1324 mutex_unlock(&p->mutex); 1325 1326 /* Flush TLBs after waiting for the page table updates to complete */ 1327 for (i = 0; i < args->n_devices; i++) { 1328 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1329 if (WARN_ON_ONCE(!peer_pdd)) 1330 continue; 1331 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); 1332 } 1333 kfree(devices_arr); 1334 1335 return err; 1336 1337 get_process_device_data_failed: 1338 bind_process_to_device_failed: 1339 get_mem_obj_from_handle_failed: 1340 map_memory_to_gpu_failed: 1341 sync_memory_failed: 1342 mutex_unlock(&p->mutex); 1343 copy_from_user_failed: 1344 kfree(devices_arr); 1345 1346 return err; 1347 } 1348 1349 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, 1350 struct kfd_process *p, void *data) 1351 { 1352 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data; 1353 struct kfd_process_device *pdd, *peer_pdd; 1354 void *mem; 1355 long err = 0; 1356 uint32_t *devices_arr = NULL, i; 1357 bool flush_tlb; 1358 1359 if (!args->n_devices) { 1360 pr_debug("Device IDs array empty\n"); 1361 return -EINVAL; 1362 } 1363 if (args->n_success > args->n_devices) { 1364 pr_debug("n_success exceeds n_devices\n"); 1365 return -EINVAL; 1366 } 1367 1368 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1369 GFP_KERNEL); 1370 if (!devices_arr) 1371 return -ENOMEM; 1372 1373 err = copy_from_user(devices_arr, 1374 (void __user *)args->device_ids_array_ptr, 1375 args->n_devices * sizeof(*devices_arr)); 1376 if (err != 0) { 1377 err = -EFAULT; 1378 goto copy_from_user_failed; 1379 } 1380 1381 mutex_lock(&p->mutex); 1382 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1383 if (!pdd) { 1384 err = -EINVAL; 1385 goto bind_process_to_device_failed; 1386 } 1387 1388 mem = kfd_process_device_translate_handle(pdd, 1389 GET_IDR_HANDLE(args->handle)); 1390 if (!mem) { 1391 err = -ENOMEM; 1392 goto get_mem_obj_from_handle_failed; 1393 } 1394 1395 for (i = args->n_success; i < args->n_devices; i++) { 1396 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1397 if (!peer_pdd) { 1398 err = -EINVAL; 1399 goto get_mem_obj_from_handle_failed; 1400 } 1401 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 1402 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv); 1403 if (err) { 1404 pr_debug("Failed to unmap from gpu %d/%d\n", i, args->n_devices); 1405 goto unmap_memory_from_gpu_failed; 1406 } 1407 args->n_success = i+1; 1408 } 1409 1410 flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev->kfd); 1411 if (flush_tlb) { 1412 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev, 1413 (struct kgd_mem *) mem, true); 1414 if (err) { 1415 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1416 goto sync_memory_failed; 1417 } 1418 } 1419 1420 /* Flush TLBs after waiting for the page table updates to complete */ 1421 for (i = 0; i < args->n_devices; i++) { 1422 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1423 if (WARN_ON_ONCE(!peer_pdd)) 1424 continue; 1425 if (flush_tlb) 1426 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); 1427 1428 /* Remove dma mapping after tlb flush to avoid IO_PAGE_FAULT */ 1429 err = amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv); 1430 if (err) 1431 goto sync_memory_failed; 1432 } 1433 1434 mutex_unlock(&p->mutex); 1435 1436 kfree(devices_arr); 1437 1438 return 0; 1439 1440 bind_process_to_device_failed: 1441 get_mem_obj_from_handle_failed: 1442 unmap_memory_from_gpu_failed: 1443 sync_memory_failed: 1444 mutex_unlock(&p->mutex); 1445 copy_from_user_failed: 1446 kfree(devices_arr); 1447 return err; 1448 } 1449 1450 static int kfd_ioctl_alloc_queue_gws(struct file *filep, 1451 struct kfd_process *p, void *data) 1452 { 1453 int retval; 1454 struct kfd_ioctl_alloc_queue_gws_args *args = data; 1455 struct queue *q; 1456 struct kfd_node *dev; 1457 1458 mutex_lock(&p->mutex); 1459 q = pqm_get_user_queue(&p->pqm, args->queue_id); 1460 1461 if (q) { 1462 dev = q->device; 1463 } else { 1464 retval = -EINVAL; 1465 goto out_unlock; 1466 } 1467 1468 if (!dev->gws) { 1469 retval = -ENODEV; 1470 goto out_unlock; 1471 } 1472 1473 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 1474 retval = -ENODEV; 1475 goto out_unlock; 1476 } 1477 1478 if (p->debug_trap_enabled && (!kfd_dbg_has_gws_support(dev) || 1479 kfd_dbg_has_cwsr_workaround(dev))) { 1480 retval = -EBUSY; 1481 goto out_unlock; 1482 } 1483 1484 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL); 1485 mutex_unlock(&p->mutex); 1486 1487 args->first_gws = 0; 1488 return retval; 1489 1490 out_unlock: 1491 mutex_unlock(&p->mutex); 1492 return retval; 1493 } 1494 1495 static int kfd_ioctl_get_dmabuf_info(struct file *filep, 1496 struct kfd_process *p, void *data) 1497 { 1498 struct kfd_ioctl_get_dmabuf_info_args *args = data; 1499 struct kfd_node *dev = NULL; 1500 struct amdgpu_device *dmabuf_adev; 1501 void *metadata_buffer = NULL; 1502 uint32_t flags; 1503 int8_t xcp_id; 1504 unsigned int i; 1505 int r; 1506 1507 /* Find a KFD GPU device that supports the get_dmabuf_info query */ 1508 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++) 1509 if (dev && !kfd_devcgroup_check_permission(dev)) 1510 break; 1511 if (!dev) 1512 return -EINVAL; 1513 1514 if (args->metadata_ptr) { 1515 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL); 1516 if (!metadata_buffer) 1517 return -ENOMEM; 1518 } 1519 1520 /* Get dmabuf info from KGD */ 1521 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd, 1522 &dmabuf_adev, &args->size, 1523 metadata_buffer, args->metadata_size, 1524 &args->metadata_size, &flags, &xcp_id); 1525 if (r) 1526 goto exit; 1527 1528 if (xcp_id >= 0) 1529 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id; 1530 else 1531 args->gpu_id = dev->id; 1532 args->flags = flags; 1533 1534 /* Copy metadata buffer to user mode */ 1535 if (metadata_buffer) { 1536 r = copy_to_user((void __user *)args->metadata_ptr, 1537 metadata_buffer, args->metadata_size); 1538 if (r != 0) 1539 r = -EFAULT; 1540 } 1541 1542 exit: 1543 kfree(metadata_buffer); 1544 1545 return r; 1546 } 1547 1548 static int kfd_ioctl_import_dmabuf(struct file *filep, 1549 struct kfd_process *p, void *data) 1550 { 1551 struct kfd_ioctl_import_dmabuf_args *args = data; 1552 struct kfd_process_device *pdd; 1553 int idr_handle; 1554 uint64_t size; 1555 void *mem; 1556 int r; 1557 1558 mutex_lock(&p->mutex); 1559 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1560 if (!pdd) { 1561 r = -EINVAL; 1562 goto err_unlock; 1563 } 1564 1565 pdd = kfd_bind_process_to_device(pdd->dev, p); 1566 if (IS_ERR(pdd)) { 1567 r = PTR_ERR(pdd); 1568 goto err_unlock; 1569 } 1570 1571 r = amdgpu_amdkfd_gpuvm_import_dmabuf_fd(pdd->dev->adev, args->dmabuf_fd, 1572 args->va_addr, pdd->drm_priv, 1573 (struct kgd_mem **)&mem, &size, 1574 NULL); 1575 if (r) 1576 goto err_unlock; 1577 1578 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1579 if (idr_handle < 0) { 1580 r = -EFAULT; 1581 goto err_free; 1582 } 1583 1584 mutex_unlock(&p->mutex); 1585 1586 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1587 1588 return 0; 1589 1590 err_free: 1591 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, 1592 pdd->drm_priv, NULL); 1593 err_unlock: 1594 mutex_unlock(&p->mutex); 1595 return r; 1596 } 1597 1598 static int kfd_ioctl_export_dmabuf(struct file *filep, 1599 struct kfd_process *p, void *data) 1600 { 1601 struct kfd_ioctl_export_dmabuf_args *args = data; 1602 struct kfd_process_device *pdd; 1603 struct dma_buf *dmabuf; 1604 struct kfd_node *dev; 1605 void *mem; 1606 int ret = 0; 1607 1608 dev = kfd_device_by_id(GET_GPU_ID(args->handle)); 1609 if (!dev) 1610 return -EINVAL; 1611 1612 mutex_lock(&p->mutex); 1613 1614 pdd = kfd_get_process_device_data(dev, p); 1615 if (!pdd) { 1616 ret = -EINVAL; 1617 goto err_unlock; 1618 } 1619 1620 mem = kfd_process_device_translate_handle(pdd, 1621 GET_IDR_HANDLE(args->handle)); 1622 if (!mem) { 1623 ret = -EINVAL; 1624 goto err_unlock; 1625 } 1626 1627 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf); 1628 mutex_unlock(&p->mutex); 1629 if (ret) 1630 goto err_out; 1631 1632 ret = dma_buf_fd(dmabuf, args->flags); 1633 if (ret < 0) { 1634 dma_buf_put(dmabuf); 1635 goto err_out; 1636 } 1637 /* dma_buf_fd assigns the reference count to the fd, no need to 1638 * put the reference here. 1639 */ 1640 args->dmabuf_fd = ret; 1641 1642 return 0; 1643 1644 err_unlock: 1645 mutex_unlock(&p->mutex); 1646 err_out: 1647 return ret; 1648 } 1649 1650 /* Handle requests for watching SMI events */ 1651 static int kfd_ioctl_smi_events(struct file *filep, 1652 struct kfd_process *p, void *data) 1653 { 1654 struct kfd_ioctl_smi_events_args *args = data; 1655 struct kfd_process_device *pdd; 1656 1657 mutex_lock(&p->mutex); 1658 1659 pdd = kfd_process_device_data_by_id(p, args->gpuid); 1660 mutex_unlock(&p->mutex); 1661 if (!pdd) 1662 return -EINVAL; 1663 1664 return kfd_smi_event_open(pdd->dev, &args->anon_fd); 1665 } 1666 1667 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1668 1669 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1670 struct kfd_process *p, void *data) 1671 { 1672 struct kfd_ioctl_set_xnack_mode_args *args = data; 1673 int r = 0; 1674 1675 mutex_lock(&p->mutex); 1676 if (args->xnack_enabled >= 0) { 1677 if (!list_empty(&p->pqm.queues)) { 1678 pr_debug("Process has user queues running\n"); 1679 r = -EBUSY; 1680 goto out_unlock; 1681 } 1682 1683 if (p->xnack_enabled == args->xnack_enabled) 1684 goto out_unlock; 1685 1686 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) { 1687 r = -EPERM; 1688 goto out_unlock; 1689 } 1690 1691 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled); 1692 } else { 1693 args->xnack_enabled = p->xnack_enabled; 1694 } 1695 1696 out_unlock: 1697 mutex_unlock(&p->mutex); 1698 1699 return r; 1700 } 1701 1702 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1703 { 1704 struct kfd_ioctl_svm_args *args = data; 1705 int r = 0; 1706 1707 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n", 1708 args->start_addr, args->size, args->op, args->nattr); 1709 1710 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK)) 1711 return -EINVAL; 1712 if (!args->start_addr || !args->size) 1713 return -EINVAL; 1714 1715 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr, 1716 args->attrs); 1717 1718 return r; 1719 } 1720 #else 1721 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1722 struct kfd_process *p, void *data) 1723 { 1724 return -EPERM; 1725 } 1726 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1727 { 1728 return -EPERM; 1729 } 1730 #endif 1731 1732 static int criu_checkpoint_process(struct kfd_process *p, 1733 uint8_t __user *user_priv_data, 1734 uint64_t *priv_offset) 1735 { 1736 struct kfd_criu_process_priv_data process_priv; 1737 int ret; 1738 1739 memset(&process_priv, 0, sizeof(process_priv)); 1740 1741 process_priv.version = KFD_CRIU_PRIV_VERSION; 1742 /* For CR, we don't consider negative xnack mode which is used for 1743 * querying without changing it, here 0 simply means disabled and 1 1744 * means enabled so retry for finding a valid PTE. 1745 */ 1746 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0; 1747 1748 ret = copy_to_user(user_priv_data + *priv_offset, 1749 &process_priv, sizeof(process_priv)); 1750 1751 if (ret) { 1752 pr_err("Failed to copy process information to user\n"); 1753 ret = -EFAULT; 1754 } 1755 1756 *priv_offset += sizeof(process_priv); 1757 return ret; 1758 } 1759 1760 static int criu_checkpoint_devices(struct kfd_process *p, 1761 uint32_t num_devices, 1762 uint8_t __user *user_addr, 1763 uint8_t __user *user_priv_data, 1764 uint64_t *priv_offset) 1765 { 1766 struct kfd_criu_device_priv_data *device_priv = NULL; 1767 struct kfd_criu_device_bucket *device_buckets = NULL; 1768 int ret = 0, i; 1769 1770 device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL); 1771 if (!device_buckets) { 1772 ret = -ENOMEM; 1773 goto exit; 1774 } 1775 1776 device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL); 1777 if (!device_priv) { 1778 ret = -ENOMEM; 1779 goto exit; 1780 } 1781 1782 for (i = 0; i < num_devices; i++) { 1783 struct kfd_process_device *pdd = p->pdds[i]; 1784 1785 device_buckets[i].user_gpu_id = pdd->user_gpu_id; 1786 device_buckets[i].actual_gpu_id = pdd->dev->id; 1787 1788 /* 1789 * priv_data does not contain useful information for now and is reserved for 1790 * future use, so we do not set its contents. 1791 */ 1792 } 1793 1794 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets)); 1795 if (ret) { 1796 pr_err("Failed to copy device information to user\n"); 1797 ret = -EFAULT; 1798 goto exit; 1799 } 1800 1801 ret = copy_to_user(user_priv_data + *priv_offset, 1802 device_priv, 1803 num_devices * sizeof(*device_priv)); 1804 if (ret) { 1805 pr_err("Failed to copy device information to user\n"); 1806 ret = -EFAULT; 1807 } 1808 *priv_offset += num_devices * sizeof(*device_priv); 1809 1810 exit: 1811 kvfree(device_buckets); 1812 kvfree(device_priv); 1813 return ret; 1814 } 1815 1816 static uint32_t get_process_num_bos(struct kfd_process *p) 1817 { 1818 uint32_t num_of_bos = 0; 1819 int i; 1820 1821 /* Run over all PDDs of the process */ 1822 for (i = 0; i < p->n_pdds; i++) { 1823 struct kfd_process_device *pdd = p->pdds[i]; 1824 void *mem; 1825 int id; 1826 1827 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 1828 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; 1829 1830 if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base) 1831 num_of_bos++; 1832 } 1833 } 1834 return num_of_bos; 1835 } 1836 1837 static int criu_get_prime_handle(struct kgd_mem *mem, 1838 int flags, u32 *shared_fd, 1839 struct file **file) 1840 { 1841 struct dma_buf *dmabuf; 1842 int ret; 1843 1844 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf); 1845 if (ret) { 1846 pr_err("dmabuf export failed for the BO\n"); 1847 return ret; 1848 } 1849 1850 ret = get_unused_fd_flags(flags); 1851 if (ret < 0) { 1852 pr_err("dmabuf create fd failed, ret:%d\n", ret); 1853 goto out_free_dmabuf; 1854 } 1855 1856 *shared_fd = ret; 1857 *file = dmabuf->file; 1858 return 0; 1859 1860 out_free_dmabuf: 1861 dma_buf_put(dmabuf); 1862 return ret; 1863 } 1864 1865 static void commit_files(struct file **files, 1866 struct kfd_criu_bo_bucket *bo_buckets, 1867 unsigned int count, 1868 int err) 1869 { 1870 while (count--) { 1871 struct file *file = files[count]; 1872 1873 if (!file) 1874 continue; 1875 if (err) { 1876 fput(file); 1877 put_unused_fd(bo_buckets[count].dmabuf_fd); 1878 } else { 1879 fd_install(bo_buckets[count].dmabuf_fd, file); 1880 } 1881 } 1882 } 1883 1884 static int criu_checkpoint_bos(struct kfd_process *p, 1885 uint32_t num_bos, 1886 uint8_t __user *user_bos, 1887 uint8_t __user *user_priv_data, 1888 uint64_t *priv_offset) 1889 { 1890 struct kfd_criu_bo_bucket *bo_buckets; 1891 struct kfd_criu_bo_priv_data *bo_privs; 1892 struct file **files = NULL; 1893 int ret = 0, pdd_index, bo_index = 0, id; 1894 void *mem; 1895 1896 bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL); 1897 if (!bo_buckets) 1898 return -ENOMEM; 1899 1900 bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL); 1901 if (!bo_privs) { 1902 ret = -ENOMEM; 1903 goto exit; 1904 } 1905 1906 files = kvzalloc(num_bos * sizeof(struct file *), GFP_KERNEL); 1907 if (!files) { 1908 ret = -ENOMEM; 1909 goto exit; 1910 } 1911 1912 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 1913 struct kfd_process_device *pdd = p->pdds[pdd_index]; 1914 struct amdgpu_bo *dumper_bo; 1915 struct kgd_mem *kgd_mem; 1916 1917 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 1918 struct kfd_criu_bo_bucket *bo_bucket; 1919 struct kfd_criu_bo_priv_data *bo_priv; 1920 int i, dev_idx = 0; 1921 1922 kgd_mem = (struct kgd_mem *)mem; 1923 dumper_bo = kgd_mem->bo; 1924 1925 /* Skip checkpointing BOs that are used for Trap handler 1926 * code and state. Currently, these BOs have a VA that 1927 * is less GPUVM Base 1928 */ 1929 if (kgd_mem->va && kgd_mem->va <= pdd->gpuvm_base) 1930 continue; 1931 1932 bo_bucket = &bo_buckets[bo_index]; 1933 bo_priv = &bo_privs[bo_index]; 1934 1935 bo_bucket->gpu_id = pdd->user_gpu_id; 1936 bo_bucket->addr = (uint64_t)kgd_mem->va; 1937 bo_bucket->size = amdgpu_bo_size(dumper_bo); 1938 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags; 1939 bo_priv->idr_handle = id; 1940 1941 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 1942 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo, 1943 &bo_priv->user_addr); 1944 if (ret) { 1945 pr_err("Failed to obtain user address for user-pointer bo\n"); 1946 goto exit; 1947 } 1948 } 1949 if (bo_bucket->alloc_flags 1950 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 1951 ret = criu_get_prime_handle(kgd_mem, 1952 bo_bucket->alloc_flags & 1953 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0, 1954 &bo_bucket->dmabuf_fd, &files[bo_index]); 1955 if (ret) 1956 goto exit; 1957 } else { 1958 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 1959 } 1960 1961 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 1962 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL | 1963 KFD_MMAP_GPU_ID(pdd->dev->id); 1964 else if (bo_bucket->alloc_flags & 1965 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1966 bo_bucket->offset = KFD_MMAP_TYPE_MMIO | 1967 KFD_MMAP_GPU_ID(pdd->dev->id); 1968 else 1969 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo); 1970 1971 for (i = 0; i < p->n_pdds; i++) { 1972 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->drm_priv, kgd_mem)) 1973 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id; 1974 } 1975 1976 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n" 1977 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x", 1978 bo_bucket->size, 1979 bo_bucket->addr, 1980 bo_bucket->offset, 1981 bo_bucket->gpu_id, 1982 bo_bucket->alloc_flags, 1983 bo_priv->idr_handle); 1984 bo_index++; 1985 } 1986 } 1987 1988 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets)); 1989 if (ret) { 1990 pr_err("Failed to copy BO information to user\n"); 1991 ret = -EFAULT; 1992 goto exit; 1993 } 1994 1995 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs)); 1996 if (ret) { 1997 pr_err("Failed to copy BO priv information to user\n"); 1998 ret = -EFAULT; 1999 goto exit; 2000 } 2001 2002 *priv_offset += num_bos * sizeof(*bo_privs); 2003 2004 exit: 2005 commit_files(files, bo_buckets, bo_index, ret); 2006 kvfree(files); 2007 kvfree(bo_buckets); 2008 kvfree(bo_privs); 2009 return ret; 2010 } 2011 2012 static int criu_get_process_object_info(struct kfd_process *p, 2013 uint32_t *num_devices, 2014 uint32_t *num_bos, 2015 uint32_t *num_objects, 2016 uint64_t *objs_priv_size) 2017 { 2018 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size; 2019 uint32_t num_queues, num_events, num_svm_ranges; 2020 int ret; 2021 2022 *num_devices = p->n_pdds; 2023 *num_bos = get_process_num_bos(p); 2024 2025 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size); 2026 if (ret) 2027 return ret; 2028 2029 num_events = kfd_get_num_events(p); 2030 2031 ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size); 2032 if (ret) 2033 return ret; 2034 2035 *num_objects = num_queues + num_events + num_svm_ranges; 2036 2037 if (objs_priv_size) { 2038 priv_size = sizeof(struct kfd_criu_process_priv_data); 2039 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data); 2040 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data); 2041 priv_size += queues_priv_data_size; 2042 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data); 2043 priv_size += svm_priv_data_size; 2044 *objs_priv_size = priv_size; 2045 } 2046 return 0; 2047 } 2048 2049 static int criu_checkpoint(struct file *filep, 2050 struct kfd_process *p, 2051 struct kfd_ioctl_criu_args *args) 2052 { 2053 int ret; 2054 uint32_t num_devices, num_bos, num_objects; 2055 uint64_t priv_size, priv_offset = 0, bo_priv_offset; 2056 2057 if (!args->devices || !args->bos || !args->priv_data) 2058 return -EINVAL; 2059 2060 mutex_lock(&p->mutex); 2061 2062 if (!p->n_pdds) { 2063 pr_err("No pdd for given process\n"); 2064 ret = -ENODEV; 2065 goto exit_unlock; 2066 } 2067 2068 /* Confirm all process queues are evicted */ 2069 if (!p->queues_paused) { 2070 pr_err("Cannot dump process when queues are not in evicted state\n"); 2071 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */ 2072 ret = -EINVAL; 2073 goto exit_unlock; 2074 } 2075 2076 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size); 2077 if (ret) 2078 goto exit_unlock; 2079 2080 if (num_devices != args->num_devices || 2081 num_bos != args->num_bos || 2082 num_objects != args->num_objects || 2083 priv_size != args->priv_data_size) { 2084 2085 ret = -EINVAL; 2086 goto exit_unlock; 2087 } 2088 2089 /* each function will store private data inside priv_data and adjust priv_offset */ 2090 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset); 2091 if (ret) 2092 goto exit_unlock; 2093 2094 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices, 2095 (uint8_t __user *)args->priv_data, &priv_offset); 2096 if (ret) 2097 goto exit_unlock; 2098 2099 /* Leave room for BOs in the private data. They need to be restored 2100 * before events, but we checkpoint them last to simplify the error 2101 * handling. 2102 */ 2103 bo_priv_offset = priv_offset; 2104 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data); 2105 2106 if (num_objects) { 2107 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data, 2108 &priv_offset); 2109 if (ret) 2110 goto exit_unlock; 2111 2112 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data, 2113 &priv_offset); 2114 if (ret) 2115 goto exit_unlock; 2116 2117 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset); 2118 if (ret) 2119 goto exit_unlock; 2120 } 2121 2122 /* This must be the last thing in this function that can fail. 2123 * Otherwise we leak dmabuf file descriptors. 2124 */ 2125 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos, 2126 (uint8_t __user *)args->priv_data, &bo_priv_offset); 2127 2128 exit_unlock: 2129 mutex_unlock(&p->mutex); 2130 if (ret) 2131 pr_err("Failed to dump CRIU ret:%d\n", ret); 2132 else 2133 pr_debug("CRIU dump ret:%d\n", ret); 2134 2135 return ret; 2136 } 2137 2138 static int criu_restore_process(struct kfd_process *p, 2139 struct kfd_ioctl_criu_args *args, 2140 uint64_t *priv_offset, 2141 uint64_t max_priv_data_size) 2142 { 2143 int ret = 0; 2144 struct kfd_criu_process_priv_data process_priv; 2145 2146 if (*priv_offset + sizeof(process_priv) > max_priv_data_size) 2147 return -EINVAL; 2148 2149 ret = copy_from_user(&process_priv, 2150 (void __user *)(args->priv_data + *priv_offset), 2151 sizeof(process_priv)); 2152 if (ret) { 2153 pr_err("Failed to copy process private information from user\n"); 2154 ret = -EFAULT; 2155 goto exit; 2156 } 2157 *priv_offset += sizeof(process_priv); 2158 2159 if (process_priv.version != KFD_CRIU_PRIV_VERSION) { 2160 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n", 2161 process_priv.version, KFD_CRIU_PRIV_VERSION); 2162 return -EINVAL; 2163 } 2164 2165 pr_debug("Setting XNACK mode\n"); 2166 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) { 2167 pr_err("xnack mode cannot be set\n"); 2168 ret = -EPERM; 2169 goto exit; 2170 } else { 2171 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode); 2172 p->xnack_enabled = process_priv.xnack_mode; 2173 } 2174 2175 exit: 2176 return ret; 2177 } 2178 2179 static int criu_restore_devices(struct kfd_process *p, 2180 struct kfd_ioctl_criu_args *args, 2181 uint64_t *priv_offset, 2182 uint64_t max_priv_data_size) 2183 { 2184 struct kfd_criu_device_bucket *device_buckets; 2185 struct kfd_criu_device_priv_data *device_privs; 2186 int ret = 0; 2187 uint32_t i; 2188 2189 if (args->num_devices != p->n_pdds) 2190 return -EINVAL; 2191 2192 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size) 2193 return -EINVAL; 2194 2195 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL); 2196 if (!device_buckets) 2197 return -ENOMEM; 2198 2199 ret = copy_from_user(device_buckets, (void __user *)args->devices, 2200 args->num_devices * sizeof(*device_buckets)); 2201 if (ret) { 2202 pr_err("Failed to copy devices buckets from user\n"); 2203 ret = -EFAULT; 2204 goto exit; 2205 } 2206 2207 for (i = 0; i < args->num_devices; i++) { 2208 struct kfd_node *dev; 2209 struct kfd_process_device *pdd; 2210 struct file *drm_file; 2211 2212 /* device private data is not currently used */ 2213 2214 if (!device_buckets[i].user_gpu_id) { 2215 pr_err("Invalid user gpu_id\n"); 2216 ret = -EINVAL; 2217 goto exit; 2218 } 2219 2220 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id); 2221 if (!dev) { 2222 pr_err("Failed to find device with gpu_id = %x\n", 2223 device_buckets[i].actual_gpu_id); 2224 ret = -EINVAL; 2225 goto exit; 2226 } 2227 2228 pdd = kfd_get_process_device_data(dev, p); 2229 if (!pdd) { 2230 pr_err("Failed to get pdd for gpu_id = %x\n", 2231 device_buckets[i].actual_gpu_id); 2232 ret = -EINVAL; 2233 goto exit; 2234 } 2235 pdd->user_gpu_id = device_buckets[i].user_gpu_id; 2236 2237 drm_file = fget(device_buckets[i].drm_fd); 2238 if (!drm_file) { 2239 pr_err("Invalid render node file descriptor sent from plugin (%d)\n", 2240 device_buckets[i].drm_fd); 2241 ret = -EINVAL; 2242 goto exit; 2243 } 2244 2245 if (pdd->drm_file) { 2246 ret = -EINVAL; 2247 goto exit; 2248 } 2249 2250 /* create the vm using render nodes for kfd pdd */ 2251 if (kfd_process_device_init_vm(pdd, drm_file)) { 2252 pr_err("could not init vm for given pdd\n"); 2253 /* On success, the PDD keeps the drm_file reference */ 2254 fput(drm_file); 2255 ret = -EINVAL; 2256 goto exit; 2257 } 2258 /* 2259 * pdd now already has the vm bound to render node so below api won't create a new 2260 * exclusive kfd mapping but use existing one with renderDXXX but is still needed 2261 * for iommu v2 binding and runtime pm. 2262 */ 2263 pdd = kfd_bind_process_to_device(dev, p); 2264 if (IS_ERR(pdd)) { 2265 ret = PTR_ERR(pdd); 2266 goto exit; 2267 } 2268 2269 if (!pdd->qpd.proc_doorbells) { 2270 ret = kfd_alloc_process_doorbells(dev->kfd, pdd); 2271 if (ret) 2272 goto exit; 2273 } 2274 } 2275 2276 /* 2277 * We are not copying device private data from user as we are not using the data for now, 2278 * but we still adjust for its private data. 2279 */ 2280 *priv_offset += args->num_devices * sizeof(*device_privs); 2281 2282 exit: 2283 kfree(device_buckets); 2284 return ret; 2285 } 2286 2287 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, 2288 struct kfd_criu_bo_bucket *bo_bucket, 2289 struct kfd_criu_bo_priv_data *bo_priv, 2290 struct kgd_mem **kgd_mem) 2291 { 2292 int idr_handle; 2293 int ret; 2294 const bool criu_resume = true; 2295 u64 offset; 2296 2297 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 2298 if (bo_bucket->size != 2299 kfd_doorbell_process_slice(pdd->dev->kfd)) 2300 return -EINVAL; 2301 2302 offset = kfd_get_process_doorbells(pdd); 2303 if (!offset) 2304 return -ENOMEM; 2305 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2306 /* MMIO BOs need remapped bus address */ 2307 if (bo_bucket->size != PAGE_SIZE) { 2308 pr_err("Invalid page size\n"); 2309 return -EINVAL; 2310 } 2311 offset = pdd->dev->adev->rmmio_remap.bus_addr; 2312 if (!offset || (PAGE_SIZE > 4096)) { 2313 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n"); 2314 return -ENOMEM; 2315 } 2316 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 2317 offset = bo_priv->user_addr; 2318 } 2319 /* Create the BO */ 2320 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr, 2321 bo_bucket->size, pdd->drm_priv, kgd_mem, 2322 &offset, bo_bucket->alloc_flags, criu_resume); 2323 if (ret) { 2324 pr_err("Could not create the BO\n"); 2325 return ret; 2326 } 2327 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n", 2328 bo_bucket->size, bo_bucket->addr, offset); 2329 2330 /* Restore previous IDR handle */ 2331 pr_debug("Restoring old IDR handle for the BO"); 2332 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle, 2333 bo_priv->idr_handle + 1, GFP_KERNEL); 2334 2335 if (idr_handle < 0) { 2336 pr_err("Could not allocate idr\n"); 2337 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, 2338 NULL); 2339 return -ENOMEM; 2340 } 2341 2342 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 2343 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id); 2344 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2345 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id); 2346 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 2347 bo_bucket->restored_offset = offset; 2348 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 2349 bo_bucket->restored_offset = offset; 2350 /* Update the VRAM usage count */ 2351 atomic64_add(bo_bucket->size, &pdd->vram_usage); 2352 } 2353 return 0; 2354 } 2355 2356 static int criu_restore_bo(struct kfd_process *p, 2357 struct kfd_criu_bo_bucket *bo_bucket, 2358 struct kfd_criu_bo_priv_data *bo_priv, 2359 struct file **file) 2360 { 2361 struct kfd_process_device *pdd; 2362 struct kgd_mem *kgd_mem; 2363 int ret; 2364 int j; 2365 2366 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n", 2367 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags, 2368 bo_priv->idr_handle); 2369 2370 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id); 2371 if (!pdd) { 2372 pr_err("Failed to get pdd\n"); 2373 return -ENODEV; 2374 } 2375 2376 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); 2377 if (ret) 2378 return ret; 2379 2380 /* now map these BOs to GPU/s */ 2381 for (j = 0; j < p->n_pdds; j++) { 2382 struct kfd_node *peer; 2383 struct kfd_process_device *peer_pdd; 2384 2385 if (!bo_priv->mapped_gpuids[j]) 2386 break; 2387 2388 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]); 2389 if (!peer_pdd) 2390 return -EINVAL; 2391 2392 peer = peer_pdd->dev; 2393 2394 peer_pdd = kfd_bind_process_to_device(peer, p); 2395 if (IS_ERR(peer_pdd)) 2396 return PTR_ERR(peer_pdd); 2397 2398 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem, 2399 peer_pdd->drm_priv); 2400 if (ret) { 2401 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds); 2402 return ret; 2403 } 2404 } 2405 2406 pr_debug("map memory was successful for the BO\n"); 2407 /* create the dmabuf object and export the bo */ 2408 if (bo_bucket->alloc_flags 2409 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 2410 ret = criu_get_prime_handle(kgd_mem, DRM_RDWR, 2411 &bo_bucket->dmabuf_fd, file); 2412 if (ret) 2413 return ret; 2414 } else { 2415 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 2416 } 2417 2418 return 0; 2419 } 2420 2421 static int criu_restore_bos(struct kfd_process *p, 2422 struct kfd_ioctl_criu_args *args, 2423 uint64_t *priv_offset, 2424 uint64_t max_priv_data_size) 2425 { 2426 struct kfd_criu_bo_bucket *bo_buckets = NULL; 2427 struct kfd_criu_bo_priv_data *bo_privs = NULL; 2428 struct file **files = NULL; 2429 int ret = 0; 2430 uint32_t i = 0; 2431 2432 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size) 2433 return -EINVAL; 2434 2435 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */ 2436 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info); 2437 2438 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL); 2439 if (!bo_buckets) 2440 return -ENOMEM; 2441 2442 files = kvzalloc(args->num_bos * sizeof(struct file *), GFP_KERNEL); 2443 if (!files) { 2444 ret = -ENOMEM; 2445 goto exit; 2446 } 2447 2448 ret = copy_from_user(bo_buckets, (void __user *)args->bos, 2449 args->num_bos * sizeof(*bo_buckets)); 2450 if (ret) { 2451 pr_err("Failed to copy BOs information from user\n"); 2452 ret = -EFAULT; 2453 goto exit; 2454 } 2455 2456 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL); 2457 if (!bo_privs) { 2458 ret = -ENOMEM; 2459 goto exit; 2460 } 2461 2462 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset, 2463 args->num_bos * sizeof(*bo_privs)); 2464 if (ret) { 2465 pr_err("Failed to copy BOs information from user\n"); 2466 ret = -EFAULT; 2467 goto exit; 2468 } 2469 *priv_offset += args->num_bos * sizeof(*bo_privs); 2470 2471 /* Create and map new BOs */ 2472 for (; i < args->num_bos; i++) { 2473 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i], &files[i]); 2474 if (ret) { 2475 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret); 2476 goto exit; 2477 } 2478 } /* done */ 2479 2480 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */ 2481 ret = copy_to_user((void __user *)args->bos, 2482 bo_buckets, 2483 (args->num_bos * sizeof(*bo_buckets))); 2484 if (ret) 2485 ret = -EFAULT; 2486 2487 exit: 2488 commit_files(files, bo_buckets, i, ret); 2489 kvfree(files); 2490 kvfree(bo_buckets); 2491 kvfree(bo_privs); 2492 return ret; 2493 } 2494 2495 static int criu_restore_objects(struct file *filep, 2496 struct kfd_process *p, 2497 struct kfd_ioctl_criu_args *args, 2498 uint64_t *priv_offset, 2499 uint64_t max_priv_data_size) 2500 { 2501 int ret = 0; 2502 uint32_t i; 2503 2504 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type)); 2505 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type)); 2506 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type)); 2507 2508 for (i = 0; i < args->num_objects; i++) { 2509 uint32_t object_type; 2510 2511 if (*priv_offset + sizeof(object_type) > max_priv_data_size) { 2512 pr_err("Invalid private data size\n"); 2513 return -EINVAL; 2514 } 2515 2516 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset)); 2517 if (ret) { 2518 pr_err("Failed to copy private information from user\n"); 2519 goto exit; 2520 } 2521 2522 switch (object_type) { 2523 case KFD_CRIU_OBJECT_TYPE_QUEUE: 2524 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data, 2525 priv_offset, max_priv_data_size); 2526 if (ret) 2527 goto exit; 2528 break; 2529 case KFD_CRIU_OBJECT_TYPE_EVENT: 2530 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data, 2531 priv_offset, max_priv_data_size); 2532 if (ret) 2533 goto exit; 2534 break; 2535 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE: 2536 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data, 2537 priv_offset, max_priv_data_size); 2538 if (ret) 2539 goto exit; 2540 break; 2541 default: 2542 pr_err("Invalid object type:%u at index:%d\n", object_type, i); 2543 ret = -EINVAL; 2544 goto exit; 2545 } 2546 } 2547 exit: 2548 return ret; 2549 } 2550 2551 static int criu_restore(struct file *filep, 2552 struct kfd_process *p, 2553 struct kfd_ioctl_criu_args *args) 2554 { 2555 uint64_t priv_offset = 0; 2556 int ret = 0; 2557 2558 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n", 2559 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size); 2560 2561 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size || 2562 !args->num_devices || !args->num_bos) 2563 return -EINVAL; 2564 2565 mutex_lock(&p->mutex); 2566 2567 /* 2568 * Set the process to evicted state to avoid running any new queues before all the memory 2569 * mappings are ready. 2570 */ 2571 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); 2572 if (ret) 2573 goto exit_unlock; 2574 2575 /* Each function will adjust priv_offset based on how many bytes they consumed */ 2576 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size); 2577 if (ret) 2578 goto exit_unlock; 2579 2580 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size); 2581 if (ret) 2582 goto exit_unlock; 2583 2584 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size); 2585 if (ret) 2586 goto exit_unlock; 2587 2588 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size); 2589 if (ret) 2590 goto exit_unlock; 2591 2592 if (priv_offset != args->priv_data_size) { 2593 pr_err("Invalid private data size\n"); 2594 ret = -EINVAL; 2595 } 2596 2597 exit_unlock: 2598 mutex_unlock(&p->mutex); 2599 if (ret) 2600 pr_err("Failed to restore CRIU ret:%d\n", ret); 2601 else 2602 pr_debug("CRIU restore successful\n"); 2603 2604 return ret; 2605 } 2606 2607 static int criu_unpause(struct file *filep, 2608 struct kfd_process *p, 2609 struct kfd_ioctl_criu_args *args) 2610 { 2611 int ret; 2612 2613 mutex_lock(&p->mutex); 2614 2615 if (!p->queues_paused) { 2616 mutex_unlock(&p->mutex); 2617 return -EINVAL; 2618 } 2619 2620 ret = kfd_process_restore_queues(p); 2621 if (ret) 2622 pr_err("Failed to unpause queues ret:%d\n", ret); 2623 else 2624 p->queues_paused = false; 2625 2626 mutex_unlock(&p->mutex); 2627 2628 return ret; 2629 } 2630 2631 static int criu_resume(struct file *filep, 2632 struct kfd_process *p, 2633 struct kfd_ioctl_criu_args *args) 2634 { 2635 struct kfd_process *target = NULL; 2636 struct pid *pid = NULL; 2637 int ret = 0; 2638 2639 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__, 2640 args->pid); 2641 2642 pid = find_get_pid(args->pid); 2643 if (!pid) { 2644 pr_err("Cannot find pid info for %i\n", args->pid); 2645 return -ESRCH; 2646 } 2647 2648 pr_debug("calling kfd_lookup_process_by_pid\n"); 2649 target = kfd_lookup_process_by_pid(pid); 2650 2651 put_pid(pid); 2652 2653 if (!target) { 2654 pr_debug("Cannot find process info for %i\n", args->pid); 2655 return -ESRCH; 2656 } 2657 2658 mutex_lock(&target->mutex); 2659 ret = kfd_criu_resume_svm(target); 2660 if (ret) { 2661 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid); 2662 goto exit; 2663 } 2664 2665 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info); 2666 if (ret) 2667 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid); 2668 2669 exit: 2670 mutex_unlock(&target->mutex); 2671 2672 kfd_unref_process(target); 2673 return ret; 2674 } 2675 2676 static int criu_process_info(struct file *filep, 2677 struct kfd_process *p, 2678 struct kfd_ioctl_criu_args *args) 2679 { 2680 int ret = 0; 2681 2682 mutex_lock(&p->mutex); 2683 2684 if (!p->n_pdds) { 2685 pr_err("No pdd for given process\n"); 2686 ret = -ENODEV; 2687 goto err_unlock; 2688 } 2689 2690 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); 2691 if (ret) 2692 goto err_unlock; 2693 2694 p->queues_paused = true; 2695 2696 args->pid = task_pid_nr_ns(p->lead_thread, 2697 task_active_pid_ns(p->lead_thread)); 2698 2699 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos, 2700 &args->num_objects, &args->priv_data_size); 2701 if (ret) 2702 goto err_unlock; 2703 2704 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n", 2705 args->num_devices, args->num_bos, args->num_objects, 2706 args->priv_data_size); 2707 2708 err_unlock: 2709 if (ret) { 2710 kfd_process_restore_queues(p); 2711 p->queues_paused = false; 2712 } 2713 mutex_unlock(&p->mutex); 2714 return ret; 2715 } 2716 2717 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data) 2718 { 2719 struct kfd_ioctl_criu_args *args = data; 2720 int ret; 2721 2722 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op); 2723 switch (args->op) { 2724 case KFD_CRIU_OP_PROCESS_INFO: 2725 ret = criu_process_info(filep, p, args); 2726 break; 2727 case KFD_CRIU_OP_CHECKPOINT: 2728 ret = criu_checkpoint(filep, p, args); 2729 break; 2730 case KFD_CRIU_OP_UNPAUSE: 2731 ret = criu_unpause(filep, p, args); 2732 break; 2733 case KFD_CRIU_OP_RESTORE: 2734 ret = criu_restore(filep, p, args); 2735 break; 2736 case KFD_CRIU_OP_RESUME: 2737 ret = criu_resume(filep, p, args); 2738 break; 2739 default: 2740 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op); 2741 ret = -EINVAL; 2742 break; 2743 } 2744 2745 if (ret) 2746 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret); 2747 2748 return ret; 2749 } 2750 2751 static int runtime_enable(struct kfd_process *p, uint64_t r_debug, 2752 bool enable_ttmp_setup) 2753 { 2754 int i = 0, ret = 0; 2755 2756 if (p->is_runtime_retry) 2757 goto retry; 2758 2759 if (p->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED) 2760 return -EBUSY; 2761 2762 for (i = 0; i < p->n_pdds; i++) { 2763 struct kfd_process_device *pdd = p->pdds[i]; 2764 2765 if (pdd->qpd.queue_count) 2766 return -EEXIST; 2767 2768 /* 2769 * Setup TTMPs by default. 2770 * Note that this call must remain here for MES ADD QUEUE to 2771 * skip_process_ctx_clear unconditionally as the first call to 2772 * SET_SHADER_DEBUGGER clears any stale process context data 2773 * saved in MES. 2774 */ 2775 if (pdd->dev->kfd->shared_resources.enable_mes) 2776 kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); 2777 } 2778 2779 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED; 2780 p->runtime_info.r_debug = r_debug; 2781 p->runtime_info.ttmp_setup = enable_ttmp_setup; 2782 2783 if (p->runtime_info.ttmp_setup) { 2784 for (i = 0; i < p->n_pdds; i++) { 2785 struct kfd_process_device *pdd = p->pdds[i]; 2786 2787 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { 2788 amdgpu_gfx_off_ctrl(pdd->dev->adev, false); 2789 pdd->dev->kfd2kgd->enable_debug_trap( 2790 pdd->dev->adev, 2791 true, 2792 pdd->dev->vm_info.last_vmid_kfd); 2793 } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { 2794 pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( 2795 pdd->dev->adev, 2796 false, 2797 0); 2798 } 2799 } 2800 } 2801 2802 retry: 2803 if (p->debug_trap_enabled) { 2804 if (!p->is_runtime_retry) { 2805 kfd_dbg_trap_activate(p); 2806 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME), 2807 p, NULL, 0, false, NULL, 0); 2808 } 2809 2810 mutex_unlock(&p->mutex); 2811 ret = down_interruptible(&p->runtime_enable_sema); 2812 mutex_lock(&p->mutex); 2813 2814 p->is_runtime_retry = !!ret; 2815 } 2816 2817 return ret; 2818 } 2819 2820 static int runtime_disable(struct kfd_process *p) 2821 { 2822 int i = 0, ret; 2823 bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED; 2824 2825 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED; 2826 p->runtime_info.r_debug = 0; 2827 2828 if (p->debug_trap_enabled) { 2829 if (was_enabled) 2830 kfd_dbg_trap_deactivate(p, false, 0); 2831 2832 if (!p->is_runtime_retry) 2833 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME), 2834 p, NULL, 0, false, NULL, 0); 2835 2836 mutex_unlock(&p->mutex); 2837 ret = down_interruptible(&p->runtime_enable_sema); 2838 mutex_lock(&p->mutex); 2839 2840 p->is_runtime_retry = !!ret; 2841 if (ret) 2842 return ret; 2843 } 2844 2845 if (was_enabled && p->runtime_info.ttmp_setup) { 2846 for (i = 0; i < p->n_pdds; i++) { 2847 struct kfd_process_device *pdd = p->pdds[i]; 2848 2849 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) 2850 amdgpu_gfx_off_ctrl(pdd->dev->adev, true); 2851 } 2852 } 2853 2854 p->runtime_info.ttmp_setup = false; 2855 2856 /* disable ttmp setup */ 2857 for (i = 0; i < p->n_pdds; i++) { 2858 struct kfd_process_device *pdd = p->pdds[i]; 2859 2860 if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { 2861 pdd->spi_dbg_override = 2862 pdd->dev->kfd2kgd->disable_debug_trap( 2863 pdd->dev->adev, 2864 false, 2865 pdd->dev->vm_info.last_vmid_kfd); 2866 2867 if (!pdd->dev->kfd->shared_resources.enable_mes) 2868 debug_refresh_runlist(pdd->dev->dqm); 2869 else 2870 kfd_dbg_set_mes_debug_mode(pdd, 2871 !kfd_dbg_has_cwsr_workaround(pdd->dev)); 2872 } 2873 } 2874 2875 return 0; 2876 } 2877 2878 static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data) 2879 { 2880 struct kfd_ioctl_runtime_enable_args *args = data; 2881 int r; 2882 2883 mutex_lock(&p->mutex); 2884 2885 if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK) 2886 r = runtime_enable(p, args->r_debug, 2887 !!(args->mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK)); 2888 else 2889 r = runtime_disable(p); 2890 2891 mutex_unlock(&p->mutex); 2892 2893 return r; 2894 } 2895 2896 static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, void *data) 2897 { 2898 struct kfd_ioctl_dbg_trap_args *args = data; 2899 struct task_struct *thread = NULL; 2900 struct mm_struct *mm = NULL; 2901 struct pid *pid = NULL; 2902 struct kfd_process *target = NULL; 2903 struct kfd_process_device *pdd = NULL; 2904 int r = 0; 2905 2906 if (sched_policy == KFD_SCHED_POLICY_NO_HWS) { 2907 pr_err("Debugging does not support sched_policy %i", sched_policy); 2908 return -EINVAL; 2909 } 2910 2911 pid = find_get_pid(args->pid); 2912 if (!pid) { 2913 pr_debug("Cannot find pid info for %i\n", args->pid); 2914 r = -ESRCH; 2915 goto out; 2916 } 2917 2918 thread = get_pid_task(pid, PIDTYPE_PID); 2919 if (!thread) { 2920 r = -ESRCH; 2921 goto out; 2922 } 2923 2924 mm = get_task_mm(thread); 2925 if (!mm) { 2926 r = -ESRCH; 2927 goto out; 2928 } 2929 2930 if (args->op == KFD_IOC_DBG_TRAP_ENABLE) { 2931 bool create_process; 2932 2933 rcu_read_lock(); 2934 create_process = thread && thread != current && ptrace_parent(thread) == current; 2935 rcu_read_unlock(); 2936 2937 target = create_process ? kfd_create_process(thread) : 2938 kfd_lookup_process_by_pid(pid); 2939 } else { 2940 target = kfd_lookup_process_by_pid(pid); 2941 } 2942 2943 if (IS_ERR_OR_NULL(target)) { 2944 pr_debug("Cannot find process PID %i to debug\n", args->pid); 2945 r = target ? PTR_ERR(target) : -ESRCH; 2946 target = NULL; 2947 goto out; 2948 } 2949 2950 /* Check if target is still PTRACED. */ 2951 rcu_read_lock(); 2952 if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE 2953 && ptrace_parent(target->lead_thread) != current) { 2954 pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid); 2955 r = -EPERM; 2956 } 2957 rcu_read_unlock(); 2958 2959 if (r) 2960 goto out; 2961 2962 mutex_lock(&target->mutex); 2963 2964 if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) { 2965 pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op); 2966 r = -EINVAL; 2967 goto unlock_out; 2968 } 2969 2970 if (target->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_ENABLED && 2971 (args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE || 2972 args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE || 2973 args->op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES || 2974 args->op == KFD_IOC_DBG_TRAP_RESUME_QUEUES || 2975 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH || 2976 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH || 2977 args->op == KFD_IOC_DBG_TRAP_SET_FLAGS)) { 2978 r = -EPERM; 2979 goto unlock_out; 2980 } 2981 2982 if (args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH || 2983 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH) { 2984 int user_gpu_id = kfd_process_get_user_gpu_id(target, 2985 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ? 2986 args->set_node_address_watch.gpu_id : 2987 args->clear_node_address_watch.gpu_id); 2988 2989 pdd = kfd_process_device_data_by_id(target, user_gpu_id); 2990 if (user_gpu_id == -EINVAL || !pdd) { 2991 r = -ENODEV; 2992 goto unlock_out; 2993 } 2994 } 2995 2996 switch (args->op) { 2997 case KFD_IOC_DBG_TRAP_ENABLE: 2998 if (target != p) 2999 target->debugger_process = p; 3000 3001 r = kfd_dbg_trap_enable(target, 3002 args->enable.dbg_fd, 3003 (void __user *)args->enable.rinfo_ptr, 3004 &args->enable.rinfo_size); 3005 if (!r) 3006 target->exception_enable_mask = args->enable.exception_mask; 3007 3008 break; 3009 case KFD_IOC_DBG_TRAP_DISABLE: 3010 r = kfd_dbg_trap_disable(target); 3011 break; 3012 case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT: 3013 r = kfd_dbg_send_exception_to_runtime(target, 3014 args->send_runtime_event.gpu_id, 3015 args->send_runtime_event.queue_id, 3016 args->send_runtime_event.exception_mask); 3017 break; 3018 case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED: 3019 kfd_dbg_set_enabled_debug_exception_mask(target, 3020 args->set_exceptions_enabled.exception_mask); 3021 break; 3022 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE: 3023 r = kfd_dbg_trap_set_wave_launch_override(target, 3024 args->launch_override.override_mode, 3025 args->launch_override.enable_mask, 3026 args->launch_override.support_request_mask, 3027 &args->launch_override.enable_mask, 3028 &args->launch_override.support_request_mask); 3029 break; 3030 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE: 3031 r = kfd_dbg_trap_set_wave_launch_mode(target, 3032 args->launch_mode.launch_mode); 3033 break; 3034 case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: 3035 r = suspend_queues(target, 3036 args->suspend_queues.num_queues, 3037 args->suspend_queues.grace_period, 3038 args->suspend_queues.exception_mask, 3039 (uint32_t *)args->suspend_queues.queue_array_ptr); 3040 3041 break; 3042 case KFD_IOC_DBG_TRAP_RESUME_QUEUES: 3043 r = resume_queues(target, args->resume_queues.num_queues, 3044 (uint32_t *)args->resume_queues.queue_array_ptr); 3045 break; 3046 case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH: 3047 r = kfd_dbg_trap_set_dev_address_watch(pdd, 3048 args->set_node_address_watch.address, 3049 args->set_node_address_watch.mask, 3050 &args->set_node_address_watch.id, 3051 args->set_node_address_watch.mode); 3052 break; 3053 case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH: 3054 r = kfd_dbg_trap_clear_dev_address_watch(pdd, 3055 args->clear_node_address_watch.id); 3056 break; 3057 case KFD_IOC_DBG_TRAP_SET_FLAGS: 3058 r = kfd_dbg_trap_set_flags(target, &args->set_flags.flags); 3059 break; 3060 case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT: 3061 r = kfd_dbg_ev_query_debug_event(target, 3062 &args->query_debug_event.queue_id, 3063 &args->query_debug_event.gpu_id, 3064 args->query_debug_event.exception_mask, 3065 &args->query_debug_event.exception_mask); 3066 break; 3067 case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: 3068 r = kfd_dbg_trap_query_exception_info(target, 3069 args->query_exception_info.source_id, 3070 args->query_exception_info.exception_code, 3071 args->query_exception_info.clear_exception, 3072 (void __user *)args->query_exception_info.info_ptr, 3073 &args->query_exception_info.info_size); 3074 break; 3075 case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: 3076 r = pqm_get_queue_snapshot(&target->pqm, 3077 args->queue_snapshot.exception_mask, 3078 (void __user *)args->queue_snapshot.snapshot_buf_ptr, 3079 &args->queue_snapshot.num_queues, 3080 &args->queue_snapshot.entry_size); 3081 break; 3082 case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: 3083 r = kfd_dbg_trap_device_snapshot(target, 3084 args->device_snapshot.exception_mask, 3085 (void __user *)args->device_snapshot.snapshot_buf_ptr, 3086 &args->device_snapshot.num_devices, 3087 &args->device_snapshot.entry_size); 3088 break; 3089 default: 3090 pr_err("Invalid option: %i\n", args->op); 3091 r = -EINVAL; 3092 } 3093 3094 unlock_out: 3095 mutex_unlock(&target->mutex); 3096 3097 out: 3098 if (thread) 3099 put_task_struct(thread); 3100 3101 if (mm) 3102 mmput(mm); 3103 3104 if (pid) 3105 put_pid(pid); 3106 3107 if (target) 3108 kfd_unref_process(target); 3109 3110 return r; 3111 } 3112 3113 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ 3114 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ 3115 .cmd_drv = 0, .name = #ioctl} 3116 3117 /** Ioctl table */ 3118 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { 3119 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION, 3120 kfd_ioctl_get_version, 0), 3121 3122 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE, 3123 kfd_ioctl_create_queue, 0), 3124 3125 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE, 3126 kfd_ioctl_destroy_queue, 0), 3127 3128 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY, 3129 kfd_ioctl_set_memory_policy, 0), 3130 3131 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS, 3132 kfd_ioctl_get_clock_counters, 0), 3133 3134 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES, 3135 kfd_ioctl_get_process_apertures, 0), 3136 3137 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE, 3138 kfd_ioctl_update_queue, 0), 3139 3140 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT, 3141 kfd_ioctl_create_event, 0), 3142 3143 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT, 3144 kfd_ioctl_destroy_event, 0), 3145 3146 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT, 3147 kfd_ioctl_set_event, 0), 3148 3149 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT, 3150 kfd_ioctl_reset_event, 0), 3151 3152 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS, 3153 kfd_ioctl_wait_events, 0), 3154 3155 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED, 3156 kfd_ioctl_dbg_register, 0), 3157 3158 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED, 3159 kfd_ioctl_dbg_unregister, 0), 3160 3161 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED, 3162 kfd_ioctl_dbg_address_watch, 0), 3163 3164 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED, 3165 kfd_ioctl_dbg_wave_control, 0), 3166 3167 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA, 3168 kfd_ioctl_set_scratch_backing_va, 0), 3169 3170 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG, 3171 kfd_ioctl_get_tile_config, 0), 3172 3173 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER, 3174 kfd_ioctl_set_trap_handler, 0), 3175 3176 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW, 3177 kfd_ioctl_get_process_apertures_new, 0), 3178 3179 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM, 3180 kfd_ioctl_acquire_vm, 0), 3181 3182 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU, 3183 kfd_ioctl_alloc_memory_of_gpu, 0), 3184 3185 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU, 3186 kfd_ioctl_free_memory_of_gpu, 0), 3187 3188 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU, 3189 kfd_ioctl_map_memory_to_gpu, 0), 3190 3191 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU, 3192 kfd_ioctl_unmap_memory_from_gpu, 0), 3193 3194 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK, 3195 kfd_ioctl_set_cu_mask, 0), 3196 3197 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE, 3198 kfd_ioctl_get_queue_wave_state, 0), 3199 3200 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO, 3201 kfd_ioctl_get_dmabuf_info, 0), 3202 3203 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF, 3204 kfd_ioctl_import_dmabuf, 0), 3205 3206 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS, 3207 kfd_ioctl_alloc_queue_gws, 0), 3208 3209 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS, 3210 kfd_ioctl_smi_events, 0), 3211 3212 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0), 3213 3214 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE, 3215 kfd_ioctl_set_xnack_mode, 0), 3216 3217 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP, 3218 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE), 3219 3220 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY, 3221 kfd_ioctl_get_available_memory, 0), 3222 3223 AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF, 3224 kfd_ioctl_export_dmabuf, 0), 3225 3226 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE, 3227 kfd_ioctl_runtime_enable, 0), 3228 3229 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP, 3230 kfd_ioctl_set_debug_trap, 0), 3231 }; 3232 3233 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) 3234 3235 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) 3236 { 3237 struct kfd_process *process; 3238 amdkfd_ioctl_t *func; 3239 const struct amdkfd_ioctl_desc *ioctl = NULL; 3240 unsigned int nr = _IOC_NR(cmd); 3241 char stack_kdata[128]; 3242 char *kdata = NULL; 3243 unsigned int usize, asize; 3244 int retcode = -EINVAL; 3245 bool ptrace_attached = false; 3246 3247 if (nr >= AMDKFD_CORE_IOCTL_COUNT) 3248 goto err_i1; 3249 3250 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { 3251 u32 amdkfd_size; 3252 3253 ioctl = &amdkfd_ioctls[nr]; 3254 3255 amdkfd_size = _IOC_SIZE(ioctl->cmd); 3256 usize = asize = _IOC_SIZE(cmd); 3257 if (amdkfd_size > asize) 3258 asize = amdkfd_size; 3259 3260 cmd = ioctl->cmd; 3261 } else 3262 goto err_i1; 3263 3264 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg); 3265 3266 /* Get the process struct from the filep. Only the process 3267 * that opened /dev/kfd can use the file descriptor. Child 3268 * processes need to create their own KFD device context. 3269 */ 3270 process = filep->private_data; 3271 3272 rcu_read_lock(); 3273 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) && 3274 ptrace_parent(process->lead_thread) == current) 3275 ptrace_attached = true; 3276 rcu_read_unlock(); 3277 3278 if (process->lead_thread != current->group_leader 3279 && !ptrace_attached) { 3280 dev_dbg(kfd_device, "Using KFD FD in wrong process\n"); 3281 retcode = -EBADF; 3282 goto err_i1; 3283 } 3284 3285 /* Do not trust userspace, use our own definition */ 3286 func = ioctl->func; 3287 3288 if (unlikely(!func)) { 3289 dev_dbg(kfd_device, "no function\n"); 3290 retcode = -EINVAL; 3291 goto err_i1; 3292 } 3293 3294 /* 3295 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support 3296 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a 3297 * more priviledged access. 3298 */ 3299 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) { 3300 if (!capable(CAP_CHECKPOINT_RESTORE) && 3301 !capable(CAP_SYS_ADMIN)) { 3302 retcode = -EACCES; 3303 goto err_i1; 3304 } 3305 } 3306 3307 if (cmd & (IOC_IN | IOC_OUT)) { 3308 if (asize <= sizeof(stack_kdata)) { 3309 kdata = stack_kdata; 3310 } else { 3311 kdata = kmalloc(asize, GFP_KERNEL); 3312 if (!kdata) { 3313 retcode = -ENOMEM; 3314 goto err_i1; 3315 } 3316 } 3317 if (asize > usize) 3318 memset(kdata + usize, 0, asize - usize); 3319 } 3320 3321 if (cmd & IOC_IN) { 3322 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) { 3323 retcode = -EFAULT; 3324 goto err_i1; 3325 } 3326 } else if (cmd & IOC_OUT) { 3327 memset(kdata, 0, usize); 3328 } 3329 3330 retcode = func(filep, process, kdata); 3331 3332 if (cmd & IOC_OUT) 3333 if (copy_to_user((void __user *)arg, kdata, usize) != 0) 3334 retcode = -EFAULT; 3335 3336 err_i1: 3337 if (!ioctl) 3338 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n", 3339 task_pid_nr(current), cmd, nr); 3340 3341 if (kdata != stack_kdata) 3342 kfree(kdata); 3343 3344 if (retcode) 3345 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n", 3346 nr, arg, retcode); 3347 3348 return retcode; 3349 } 3350 3351 static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process, 3352 struct vm_area_struct *vma) 3353 { 3354 phys_addr_t address; 3355 3356 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3357 return -EINVAL; 3358 3359 if (PAGE_SIZE > 4096) 3360 return -EINVAL; 3361 3362 address = dev->adev->rmmio_remap.bus_addr; 3363 3364 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | 3365 VM_DONTDUMP | VM_PFNMAP); 3366 3367 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3368 3369 pr_debug("process pid %d mapping mmio page\n" 3370 " target user address == 0x%08llX\n" 3371 " physical address == 0x%08llX\n" 3372 " vm_flags == 0x%04lX\n" 3373 " size == 0x%04lX\n", 3374 process->lead_thread->pid, (unsigned long long) vma->vm_start, 3375 address, vma->vm_flags, PAGE_SIZE); 3376 3377 return io_remap_pfn_range(vma, 3378 vma->vm_start, 3379 address >> PAGE_SHIFT, 3380 PAGE_SIZE, 3381 vma->vm_page_prot); 3382 } 3383 3384 3385 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma) 3386 { 3387 struct kfd_process *process; 3388 struct kfd_node *dev = NULL; 3389 unsigned long mmap_offset; 3390 unsigned int gpu_id; 3391 3392 process = kfd_get_process(current); 3393 if (IS_ERR(process)) 3394 return PTR_ERR(process); 3395 3396 mmap_offset = vma->vm_pgoff << PAGE_SHIFT; 3397 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset); 3398 if (gpu_id) 3399 dev = kfd_device_by_id(gpu_id); 3400 3401 switch (mmap_offset & KFD_MMAP_TYPE_MASK) { 3402 case KFD_MMAP_TYPE_DOORBELL: 3403 if (!dev) 3404 return -ENODEV; 3405 return kfd_doorbell_mmap(dev, process, vma); 3406 3407 case KFD_MMAP_TYPE_EVENTS: 3408 return kfd_event_mmap(process, vma); 3409 3410 case KFD_MMAP_TYPE_RESERVED_MEM: 3411 if (!dev) 3412 return -ENODEV; 3413 return kfd_reserved_mem_mmap(dev, process, vma); 3414 case KFD_MMAP_TYPE_MMIO: 3415 if (!dev) 3416 return -ENODEV; 3417 return kfd_mmio_mmap(dev, process, vma); 3418 } 3419 3420 return -EFAULT; 3421 } 3422