1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/device.h> 25 #include <linux/export.h> 26 #include <linux/err.h> 27 #include <linux/fs.h> 28 #include <linux/file.h> 29 #include <linux/sched.h> 30 #include <linux/slab.h> 31 #include <linux/uaccess.h> 32 #include <linux/compat.h> 33 #include <uapi/linux/kfd_ioctl.h> 34 #include <linux/time.h> 35 #include <linux/mm.h> 36 #include <linux/mman.h> 37 #include <linux/ptrace.h> 38 #include <linux/dma-buf.h> 39 #include <linux/fdtable.h> 40 #include <linux/processor.h> 41 #include "kfd_priv.h" 42 #include "kfd_device_queue_manager.h" 43 #include "kfd_svm.h" 44 #include "amdgpu_amdkfd.h" 45 #include "kfd_smi_events.h" 46 #include "amdgpu_dma_buf.h" 47 48 static long kfd_ioctl(struct file *, unsigned int, unsigned long); 49 static int kfd_open(struct inode *, struct file *); 50 static int kfd_release(struct inode *, struct file *); 51 static int kfd_mmap(struct file *, struct vm_area_struct *); 52 53 static const char kfd_dev_name[] = "kfd"; 54 55 static const struct file_operations kfd_fops = { 56 .owner = THIS_MODULE, 57 .unlocked_ioctl = kfd_ioctl, 58 .compat_ioctl = compat_ptr_ioctl, 59 .open = kfd_open, 60 .release = kfd_release, 61 .mmap = kfd_mmap, 62 }; 63 64 static int kfd_char_dev_major = -1; 65 static struct class *kfd_class; 66 struct device *kfd_device; 67 68 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id) 69 { 70 struct kfd_process_device *pdd; 71 72 mutex_lock(&p->mutex); 73 pdd = kfd_process_device_data_by_id(p, gpu_id); 74 75 if (pdd) 76 return pdd; 77 78 mutex_unlock(&p->mutex); 79 return NULL; 80 } 81 82 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd) 83 { 84 mutex_unlock(&pdd->process->mutex); 85 } 86 87 int kfd_chardev_init(void) 88 { 89 int err = 0; 90 91 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops); 92 err = kfd_char_dev_major; 93 if (err < 0) 94 goto err_register_chrdev; 95 96 kfd_class = class_create(THIS_MODULE, kfd_dev_name); 97 err = PTR_ERR(kfd_class); 98 if (IS_ERR(kfd_class)) 99 goto err_class_create; 100 101 kfd_device = device_create(kfd_class, NULL, 102 MKDEV(kfd_char_dev_major, 0), 103 NULL, kfd_dev_name); 104 err = PTR_ERR(kfd_device); 105 if (IS_ERR(kfd_device)) 106 goto err_device_create; 107 108 return 0; 109 110 err_device_create: 111 class_destroy(kfd_class); 112 err_class_create: 113 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 114 err_register_chrdev: 115 return err; 116 } 117 118 void kfd_chardev_exit(void) 119 { 120 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0)); 121 class_destroy(kfd_class); 122 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 123 kfd_device = NULL; 124 } 125 126 127 static int kfd_open(struct inode *inode, struct file *filep) 128 { 129 struct kfd_process *process; 130 bool is_32bit_user_mode; 131 132 if (iminor(inode) != 0) 133 return -ENODEV; 134 135 is_32bit_user_mode = in_compat_syscall(); 136 137 if (is_32bit_user_mode) { 138 dev_warn(kfd_device, 139 "Process %d (32-bit) failed to open /dev/kfd\n" 140 "32-bit processes are not supported by amdkfd\n", 141 current->pid); 142 return -EPERM; 143 } 144 145 process = kfd_create_process(filep); 146 if (IS_ERR(process)) 147 return PTR_ERR(process); 148 149 if (kfd_is_locked()) { 150 dev_dbg(kfd_device, "kfd is locked!\n" 151 "process %d unreferenced", process->pasid); 152 kfd_unref_process(process); 153 return -EAGAIN; 154 } 155 156 /* filep now owns the reference returned by kfd_create_process */ 157 filep->private_data = process; 158 159 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n", 160 process->pasid, process->is_32bit_user_mode); 161 162 return 0; 163 } 164 165 static int kfd_release(struct inode *inode, struct file *filep) 166 { 167 struct kfd_process *process = filep->private_data; 168 169 if (process) 170 kfd_unref_process(process); 171 172 return 0; 173 } 174 175 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, 176 void *data) 177 { 178 struct kfd_ioctl_get_version_args *args = data; 179 180 args->major_version = KFD_IOCTL_MAJOR_VERSION; 181 args->minor_version = KFD_IOCTL_MINOR_VERSION; 182 183 return 0; 184 } 185 186 static int set_queue_properties_from_user(struct queue_properties *q_properties, 187 struct kfd_ioctl_create_queue_args *args) 188 { 189 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { 190 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 191 return -EINVAL; 192 } 193 194 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 195 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 196 return -EINVAL; 197 } 198 199 if ((args->ring_base_address) && 200 (!access_ok((const void __user *) args->ring_base_address, 201 sizeof(uint64_t)))) { 202 pr_err("Can't access ring base address\n"); 203 return -EFAULT; 204 } 205 206 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 207 pr_err("Ring size must be a power of 2 or 0\n"); 208 return -EINVAL; 209 } 210 211 if (!access_ok((const void __user *) args->read_pointer_address, 212 sizeof(uint32_t))) { 213 pr_err("Can't access read pointer\n"); 214 return -EFAULT; 215 } 216 217 if (!access_ok((const void __user *) args->write_pointer_address, 218 sizeof(uint32_t))) { 219 pr_err("Can't access write pointer\n"); 220 return -EFAULT; 221 } 222 223 if (args->eop_buffer_address && 224 !access_ok((const void __user *) args->eop_buffer_address, 225 sizeof(uint32_t))) { 226 pr_debug("Can't access eop buffer"); 227 return -EFAULT; 228 } 229 230 if (args->ctx_save_restore_address && 231 !access_ok((const void __user *) args->ctx_save_restore_address, 232 sizeof(uint32_t))) { 233 pr_debug("Can't access ctx save restore buffer"); 234 return -EFAULT; 235 } 236 237 q_properties->is_interop = false; 238 q_properties->is_gws = false; 239 q_properties->queue_percent = args->queue_percentage; 240 q_properties->priority = args->queue_priority; 241 q_properties->queue_address = args->ring_base_address; 242 q_properties->queue_size = args->ring_size; 243 q_properties->read_ptr = (uint32_t *) args->read_pointer_address; 244 q_properties->write_ptr = (uint32_t *) args->write_pointer_address; 245 q_properties->eop_ring_buffer_address = args->eop_buffer_address; 246 q_properties->eop_ring_buffer_size = args->eop_buffer_size; 247 q_properties->ctx_save_restore_area_address = 248 args->ctx_save_restore_address; 249 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size; 250 q_properties->ctl_stack_size = args->ctl_stack_size; 251 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE || 252 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 253 q_properties->type = KFD_QUEUE_TYPE_COMPUTE; 254 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA) 255 q_properties->type = KFD_QUEUE_TYPE_SDMA; 256 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI) 257 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI; 258 else 259 return -ENOTSUPP; 260 261 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 262 q_properties->format = KFD_QUEUE_FORMAT_AQL; 263 else 264 q_properties->format = KFD_QUEUE_FORMAT_PM4; 265 266 pr_debug("Queue Percentage: %d, %d\n", 267 q_properties->queue_percent, args->queue_percentage); 268 269 pr_debug("Queue Priority: %d, %d\n", 270 q_properties->priority, args->queue_priority); 271 272 pr_debug("Queue Address: 0x%llX, 0x%llX\n", 273 q_properties->queue_address, args->ring_base_address); 274 275 pr_debug("Queue Size: 0x%llX, %u\n", 276 q_properties->queue_size, args->ring_size); 277 278 pr_debug("Queue r/w Pointers: %px, %px\n", 279 q_properties->read_ptr, 280 q_properties->write_ptr); 281 282 pr_debug("Queue Format: %d\n", q_properties->format); 283 284 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address); 285 286 pr_debug("Queue CTX save area: 0x%llX\n", 287 q_properties->ctx_save_restore_area_address); 288 289 return 0; 290 } 291 292 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, 293 void *data) 294 { 295 struct kfd_ioctl_create_queue_args *args = data; 296 struct kfd_dev *dev; 297 int err = 0; 298 unsigned int queue_id; 299 struct kfd_process_device *pdd; 300 struct queue_properties q_properties; 301 uint32_t doorbell_offset_in_process = 0; 302 struct amdgpu_bo *wptr_bo = NULL; 303 304 memset(&q_properties, 0, sizeof(struct queue_properties)); 305 306 pr_debug("Creating queue ioctl\n"); 307 308 err = set_queue_properties_from_user(&q_properties, args); 309 if (err) 310 return err; 311 312 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id); 313 314 mutex_lock(&p->mutex); 315 316 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 317 if (!pdd) { 318 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 319 err = -EINVAL; 320 goto err_pdd; 321 } 322 dev = pdd->dev; 323 324 pdd = kfd_bind_process_to_device(dev, p); 325 if (IS_ERR(pdd)) { 326 err = -ESRCH; 327 goto err_bind_process; 328 } 329 330 if (!pdd->doorbell_index && 331 kfd_alloc_process_doorbells(dev, &pdd->doorbell_index) < 0) { 332 err = -ENOMEM; 333 goto err_alloc_doorbells; 334 } 335 336 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work 337 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) 338 */ 339 if (dev->shared_resources.enable_mes && 340 ((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) 341 >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) { 342 struct amdgpu_bo_va_mapping *wptr_mapping; 343 struct amdgpu_vm *wptr_vm; 344 345 wptr_vm = drm_priv_to_vm(pdd->drm_priv); 346 err = amdgpu_bo_reserve(wptr_vm->root.bo, false); 347 if (err) 348 goto err_wptr_map_gart; 349 350 wptr_mapping = amdgpu_vm_bo_lookup_mapping( 351 wptr_vm, args->write_pointer_address >> PAGE_SHIFT); 352 amdgpu_bo_unreserve(wptr_vm->root.bo); 353 if (!wptr_mapping) { 354 pr_err("Failed to lookup wptr bo\n"); 355 err = -EINVAL; 356 goto err_wptr_map_gart; 357 } 358 359 wptr_bo = wptr_mapping->bo_va->base.bo; 360 if (wptr_bo->tbo.base.size > PAGE_SIZE) { 361 pr_err("Requested GART mapping for wptr bo larger than one page\n"); 362 err = -EINVAL; 363 goto err_wptr_map_gart; 364 } 365 366 err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo); 367 if (err) { 368 pr_err("Failed to map wptr bo to GART\n"); 369 goto err_wptr_map_gart; 370 } 371 } 372 373 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n", 374 p->pasid, 375 dev->id); 376 377 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, wptr_bo, 378 NULL, NULL, NULL, &doorbell_offset_in_process); 379 if (err != 0) 380 goto err_create_queue; 381 382 args->queue_id = queue_id; 383 384 385 /* Return gpu_id as doorbell offset for mmap usage */ 386 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL; 387 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id); 388 if (KFD_IS_SOC15(dev)) 389 /* On SOC15 ASICs, include the doorbell offset within the 390 * process doorbell frame, which is 2 pages. 391 */ 392 args->doorbell_offset |= doorbell_offset_in_process; 393 394 mutex_unlock(&p->mutex); 395 396 pr_debug("Queue id %d was created successfully\n", args->queue_id); 397 398 pr_debug("Ring buffer address == 0x%016llX\n", 399 args->ring_base_address); 400 401 pr_debug("Read ptr address == 0x%016llX\n", 402 args->read_pointer_address); 403 404 pr_debug("Write ptr address == 0x%016llX\n", 405 args->write_pointer_address); 406 407 return 0; 408 409 err_create_queue: 410 if (wptr_bo) 411 amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo); 412 err_wptr_map_gart: 413 err_alloc_doorbells: 414 err_bind_process: 415 err_pdd: 416 mutex_unlock(&p->mutex); 417 return err; 418 } 419 420 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p, 421 void *data) 422 { 423 int retval; 424 struct kfd_ioctl_destroy_queue_args *args = data; 425 426 pr_debug("Destroying queue id %d for pasid 0x%x\n", 427 args->queue_id, 428 p->pasid); 429 430 mutex_lock(&p->mutex); 431 432 retval = pqm_destroy_queue(&p->pqm, args->queue_id); 433 434 mutex_unlock(&p->mutex); 435 return retval; 436 } 437 438 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, 439 void *data) 440 { 441 int retval; 442 struct kfd_ioctl_update_queue_args *args = data; 443 struct queue_properties properties; 444 445 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { 446 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 447 return -EINVAL; 448 } 449 450 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 451 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 452 return -EINVAL; 453 } 454 455 if ((args->ring_base_address) && 456 (!access_ok((const void __user *) args->ring_base_address, 457 sizeof(uint64_t)))) { 458 pr_err("Can't access ring base address\n"); 459 return -EFAULT; 460 } 461 462 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 463 pr_err("Ring size must be a power of 2 or 0\n"); 464 return -EINVAL; 465 } 466 467 properties.queue_address = args->ring_base_address; 468 properties.queue_size = args->ring_size; 469 properties.queue_percent = args->queue_percentage; 470 properties.priority = args->queue_priority; 471 472 pr_debug("Updating queue id %d for pasid 0x%x\n", 473 args->queue_id, p->pasid); 474 475 mutex_lock(&p->mutex); 476 477 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties); 478 479 mutex_unlock(&p->mutex); 480 481 return retval; 482 } 483 484 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, 485 void *data) 486 { 487 int retval; 488 const int max_num_cus = 1024; 489 struct kfd_ioctl_set_cu_mask_args *args = data; 490 struct mqd_update_info minfo = {0}; 491 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr; 492 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32); 493 494 if ((args->num_cu_mask % 32) != 0) { 495 pr_debug("num_cu_mask 0x%x must be a multiple of 32", 496 args->num_cu_mask); 497 return -EINVAL; 498 } 499 500 minfo.cu_mask.count = args->num_cu_mask; 501 if (minfo.cu_mask.count == 0) { 502 pr_debug("CU mask cannot be 0"); 503 return -EINVAL; 504 } 505 506 /* To prevent an unreasonably large CU mask size, set an arbitrary 507 * limit of max_num_cus bits. We can then just drop any CU mask bits 508 * past max_num_cus bits and just use the first max_num_cus bits. 509 */ 510 if (minfo.cu_mask.count > max_num_cus) { 511 pr_debug("CU mask cannot be greater than 1024 bits"); 512 minfo.cu_mask.count = max_num_cus; 513 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32); 514 } 515 516 minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL); 517 if (!minfo.cu_mask.ptr) 518 return -ENOMEM; 519 520 retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size); 521 if (retval) { 522 pr_debug("Could not copy CU mask from userspace"); 523 retval = -EFAULT; 524 goto out; 525 } 526 527 minfo.update_flag = UPDATE_FLAG_CU_MASK; 528 529 mutex_lock(&p->mutex); 530 531 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo); 532 533 mutex_unlock(&p->mutex); 534 535 out: 536 kfree(minfo.cu_mask.ptr); 537 return retval; 538 } 539 540 static int kfd_ioctl_get_queue_wave_state(struct file *filep, 541 struct kfd_process *p, void *data) 542 { 543 struct kfd_ioctl_get_queue_wave_state_args *args = data; 544 int r; 545 546 mutex_lock(&p->mutex); 547 548 r = pqm_get_wave_state(&p->pqm, args->queue_id, 549 (void __user *)args->ctl_stack_address, 550 &args->ctl_stack_used_size, 551 &args->save_area_used_size); 552 553 mutex_unlock(&p->mutex); 554 555 return r; 556 } 557 558 static int kfd_ioctl_set_memory_policy(struct file *filep, 559 struct kfd_process *p, void *data) 560 { 561 struct kfd_ioctl_set_memory_policy_args *args = data; 562 int err = 0; 563 struct kfd_process_device *pdd; 564 enum cache_policy default_policy, alternate_policy; 565 566 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT 567 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 568 return -EINVAL; 569 } 570 571 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT 572 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 573 return -EINVAL; 574 } 575 576 mutex_lock(&p->mutex); 577 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 578 if (!pdd) { 579 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 580 err = -EINVAL; 581 goto err_pdd; 582 } 583 584 pdd = kfd_bind_process_to_device(pdd->dev, p); 585 if (IS_ERR(pdd)) { 586 err = -ESRCH; 587 goto out; 588 } 589 590 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT) 591 ? cache_policy_coherent : cache_policy_noncoherent; 592 593 alternate_policy = 594 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT) 595 ? cache_policy_coherent : cache_policy_noncoherent; 596 597 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm, 598 &pdd->qpd, 599 default_policy, 600 alternate_policy, 601 (void __user *)args->alternate_aperture_base, 602 args->alternate_aperture_size)) 603 err = -EINVAL; 604 605 out: 606 err_pdd: 607 mutex_unlock(&p->mutex); 608 609 return err; 610 } 611 612 static int kfd_ioctl_set_trap_handler(struct file *filep, 613 struct kfd_process *p, void *data) 614 { 615 struct kfd_ioctl_set_trap_handler_args *args = data; 616 int err = 0; 617 struct kfd_process_device *pdd; 618 619 mutex_lock(&p->mutex); 620 621 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 622 if (!pdd) { 623 err = -EINVAL; 624 goto err_pdd; 625 } 626 627 pdd = kfd_bind_process_to_device(pdd->dev, p); 628 if (IS_ERR(pdd)) { 629 err = -ESRCH; 630 goto out; 631 } 632 633 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr); 634 635 out: 636 err_pdd: 637 mutex_unlock(&p->mutex); 638 639 return err; 640 } 641 642 static int kfd_ioctl_dbg_register(struct file *filep, 643 struct kfd_process *p, void *data) 644 { 645 return -EPERM; 646 } 647 648 static int kfd_ioctl_dbg_unregister(struct file *filep, 649 struct kfd_process *p, void *data) 650 { 651 return -EPERM; 652 } 653 654 static int kfd_ioctl_dbg_address_watch(struct file *filep, 655 struct kfd_process *p, void *data) 656 { 657 return -EPERM; 658 } 659 660 /* Parse and generate fixed size data structure for wave control */ 661 static int kfd_ioctl_dbg_wave_control(struct file *filep, 662 struct kfd_process *p, void *data) 663 { 664 return -EPERM; 665 } 666 667 static int kfd_ioctl_get_clock_counters(struct file *filep, 668 struct kfd_process *p, void *data) 669 { 670 struct kfd_ioctl_get_clock_counters_args *args = data; 671 struct kfd_process_device *pdd; 672 673 mutex_lock(&p->mutex); 674 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 675 mutex_unlock(&p->mutex); 676 if (pdd) 677 /* Reading GPU clock counter from KGD */ 678 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev); 679 else 680 /* Node without GPU resource */ 681 args->gpu_clock_counter = 0; 682 683 /* No access to rdtsc. Using raw monotonic time */ 684 args->cpu_clock_counter = ktime_get_raw_ns(); 685 args->system_clock_counter = ktime_get_boottime_ns(); 686 687 /* Since the counter is in nano-seconds we use 1GHz frequency */ 688 args->system_clock_freq = 1000000000; 689 690 return 0; 691 } 692 693 694 static int kfd_ioctl_get_process_apertures(struct file *filp, 695 struct kfd_process *p, void *data) 696 { 697 struct kfd_ioctl_get_process_apertures_args *args = data; 698 struct kfd_process_device_apertures *pAperture; 699 int i; 700 701 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid); 702 703 args->num_of_nodes = 0; 704 705 mutex_lock(&p->mutex); 706 /* Run over all pdd of the process */ 707 for (i = 0; i < p->n_pdds; i++) { 708 struct kfd_process_device *pdd = p->pdds[i]; 709 710 pAperture = 711 &args->process_apertures[args->num_of_nodes]; 712 pAperture->gpu_id = pdd->dev->id; 713 pAperture->lds_base = pdd->lds_base; 714 pAperture->lds_limit = pdd->lds_limit; 715 pAperture->gpuvm_base = pdd->gpuvm_base; 716 pAperture->gpuvm_limit = pdd->gpuvm_limit; 717 pAperture->scratch_base = pdd->scratch_base; 718 pAperture->scratch_limit = pdd->scratch_limit; 719 720 dev_dbg(kfd_device, 721 "node id %u\n", args->num_of_nodes); 722 dev_dbg(kfd_device, 723 "gpu id %u\n", pdd->dev->id); 724 dev_dbg(kfd_device, 725 "lds_base %llX\n", pdd->lds_base); 726 dev_dbg(kfd_device, 727 "lds_limit %llX\n", pdd->lds_limit); 728 dev_dbg(kfd_device, 729 "gpuvm_base %llX\n", pdd->gpuvm_base); 730 dev_dbg(kfd_device, 731 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 732 dev_dbg(kfd_device, 733 "scratch_base %llX\n", pdd->scratch_base); 734 dev_dbg(kfd_device, 735 "scratch_limit %llX\n", pdd->scratch_limit); 736 737 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS) 738 break; 739 } 740 mutex_unlock(&p->mutex); 741 742 return 0; 743 } 744 745 static int kfd_ioctl_get_process_apertures_new(struct file *filp, 746 struct kfd_process *p, void *data) 747 { 748 struct kfd_ioctl_get_process_apertures_new_args *args = data; 749 struct kfd_process_device_apertures *pa; 750 int ret; 751 int i; 752 753 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid); 754 755 if (args->num_of_nodes == 0) { 756 /* Return number of nodes, so that user space can alloacate 757 * sufficient memory 758 */ 759 mutex_lock(&p->mutex); 760 args->num_of_nodes = p->n_pdds; 761 goto out_unlock; 762 } 763 764 /* Fill in process-aperture information for all available 765 * nodes, but not more than args->num_of_nodes as that is 766 * the amount of memory allocated by user 767 */ 768 pa = kzalloc((sizeof(struct kfd_process_device_apertures) * 769 args->num_of_nodes), GFP_KERNEL); 770 if (!pa) 771 return -ENOMEM; 772 773 mutex_lock(&p->mutex); 774 775 if (!p->n_pdds) { 776 args->num_of_nodes = 0; 777 kfree(pa); 778 goto out_unlock; 779 } 780 781 /* Run over all pdd of the process */ 782 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) { 783 struct kfd_process_device *pdd = p->pdds[i]; 784 785 pa[i].gpu_id = pdd->dev->id; 786 pa[i].lds_base = pdd->lds_base; 787 pa[i].lds_limit = pdd->lds_limit; 788 pa[i].gpuvm_base = pdd->gpuvm_base; 789 pa[i].gpuvm_limit = pdd->gpuvm_limit; 790 pa[i].scratch_base = pdd->scratch_base; 791 pa[i].scratch_limit = pdd->scratch_limit; 792 793 dev_dbg(kfd_device, 794 "gpu id %u\n", pdd->dev->id); 795 dev_dbg(kfd_device, 796 "lds_base %llX\n", pdd->lds_base); 797 dev_dbg(kfd_device, 798 "lds_limit %llX\n", pdd->lds_limit); 799 dev_dbg(kfd_device, 800 "gpuvm_base %llX\n", pdd->gpuvm_base); 801 dev_dbg(kfd_device, 802 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 803 dev_dbg(kfd_device, 804 "scratch_base %llX\n", pdd->scratch_base); 805 dev_dbg(kfd_device, 806 "scratch_limit %llX\n", pdd->scratch_limit); 807 } 808 mutex_unlock(&p->mutex); 809 810 args->num_of_nodes = i; 811 ret = copy_to_user( 812 (void __user *)args->kfd_process_device_apertures_ptr, 813 pa, 814 (i * sizeof(struct kfd_process_device_apertures))); 815 kfree(pa); 816 return ret ? -EFAULT : 0; 817 818 out_unlock: 819 mutex_unlock(&p->mutex); 820 return 0; 821 } 822 823 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, 824 void *data) 825 { 826 struct kfd_ioctl_create_event_args *args = data; 827 int err; 828 829 /* For dGPUs the event page is allocated in user mode. The 830 * handle is passed to KFD with the first call to this IOCTL 831 * through the event_page_offset field. 832 */ 833 if (args->event_page_offset) { 834 mutex_lock(&p->mutex); 835 err = kfd_kmap_event_page(p, args->event_page_offset); 836 mutex_unlock(&p->mutex); 837 if (err) 838 return err; 839 } 840 841 err = kfd_event_create(filp, p, args->event_type, 842 args->auto_reset != 0, args->node_id, 843 &args->event_id, &args->event_trigger_data, 844 &args->event_page_offset, 845 &args->event_slot_index); 846 847 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__); 848 return err; 849 } 850 851 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p, 852 void *data) 853 { 854 struct kfd_ioctl_destroy_event_args *args = data; 855 856 return kfd_event_destroy(p, args->event_id); 857 } 858 859 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p, 860 void *data) 861 { 862 struct kfd_ioctl_set_event_args *args = data; 863 864 return kfd_set_event(p, args->event_id); 865 } 866 867 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p, 868 void *data) 869 { 870 struct kfd_ioctl_reset_event_args *args = data; 871 872 return kfd_reset_event(p, args->event_id); 873 } 874 875 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, 876 void *data) 877 { 878 struct kfd_ioctl_wait_events_args *args = data; 879 880 return kfd_wait_on_events(p, args->num_events, 881 (void __user *)args->events_ptr, 882 (args->wait_for_all != 0), 883 &args->timeout, &args->wait_result); 884 } 885 static int kfd_ioctl_set_scratch_backing_va(struct file *filep, 886 struct kfd_process *p, void *data) 887 { 888 struct kfd_ioctl_set_scratch_backing_va_args *args = data; 889 struct kfd_process_device *pdd; 890 struct kfd_dev *dev; 891 long err; 892 893 mutex_lock(&p->mutex); 894 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 895 if (!pdd) { 896 err = -EINVAL; 897 goto err_pdd; 898 } 899 dev = pdd->dev; 900 901 pdd = kfd_bind_process_to_device(dev, p); 902 if (IS_ERR(pdd)) { 903 err = PTR_ERR(pdd); 904 goto bind_process_to_device_fail; 905 } 906 907 pdd->qpd.sh_hidden_private_base = args->va_addr; 908 909 mutex_unlock(&p->mutex); 910 911 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS && 912 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va) 913 dev->kfd2kgd->set_scratch_backing_va( 914 dev->adev, args->va_addr, pdd->qpd.vmid); 915 916 return 0; 917 918 bind_process_to_device_fail: 919 err_pdd: 920 mutex_unlock(&p->mutex); 921 return err; 922 } 923 924 static int kfd_ioctl_get_tile_config(struct file *filep, 925 struct kfd_process *p, void *data) 926 { 927 struct kfd_ioctl_get_tile_config_args *args = data; 928 struct kfd_process_device *pdd; 929 struct tile_config config; 930 int err = 0; 931 932 mutex_lock(&p->mutex); 933 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 934 mutex_unlock(&p->mutex); 935 if (!pdd) 936 return -EINVAL; 937 938 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config); 939 940 args->gb_addr_config = config.gb_addr_config; 941 args->num_banks = config.num_banks; 942 args->num_ranks = config.num_ranks; 943 944 if (args->num_tile_configs > config.num_tile_configs) 945 args->num_tile_configs = config.num_tile_configs; 946 err = copy_to_user((void __user *)args->tile_config_ptr, 947 config.tile_config_ptr, 948 args->num_tile_configs * sizeof(uint32_t)); 949 if (err) { 950 args->num_tile_configs = 0; 951 return -EFAULT; 952 } 953 954 if (args->num_macro_tile_configs > config.num_macro_tile_configs) 955 args->num_macro_tile_configs = 956 config.num_macro_tile_configs; 957 err = copy_to_user((void __user *)args->macro_tile_config_ptr, 958 config.macro_tile_config_ptr, 959 args->num_macro_tile_configs * sizeof(uint32_t)); 960 if (err) { 961 args->num_macro_tile_configs = 0; 962 return -EFAULT; 963 } 964 965 return 0; 966 } 967 968 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p, 969 void *data) 970 { 971 struct kfd_ioctl_acquire_vm_args *args = data; 972 struct kfd_process_device *pdd; 973 struct file *drm_file; 974 int ret; 975 976 drm_file = fget(args->drm_fd); 977 if (!drm_file) 978 return -EINVAL; 979 980 mutex_lock(&p->mutex); 981 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 982 if (!pdd) { 983 ret = -EINVAL; 984 goto err_pdd; 985 } 986 987 if (pdd->drm_file) { 988 ret = pdd->drm_file == drm_file ? 0 : -EBUSY; 989 goto err_drm_file; 990 } 991 992 ret = kfd_process_device_init_vm(pdd, drm_file); 993 if (ret) 994 goto err_unlock; 995 996 /* On success, the PDD keeps the drm_file reference */ 997 mutex_unlock(&p->mutex); 998 999 return 0; 1000 1001 err_unlock: 1002 err_pdd: 1003 err_drm_file: 1004 mutex_unlock(&p->mutex); 1005 fput(drm_file); 1006 return ret; 1007 } 1008 1009 bool kfd_dev_is_large_bar(struct kfd_dev *dev) 1010 { 1011 if (debug_largebar) { 1012 pr_debug("Simulate large-bar allocation on non large-bar machine\n"); 1013 return true; 1014 } 1015 1016 if (dev->use_iommu_v2) 1017 return false; 1018 1019 if (dev->local_mem_info.local_mem_size_private == 0 && 1020 dev->local_mem_info.local_mem_size_public > 0) 1021 return true; 1022 return false; 1023 } 1024 1025 static int kfd_ioctl_get_available_memory(struct file *filep, 1026 struct kfd_process *p, void *data) 1027 { 1028 struct kfd_ioctl_get_available_memory_args *args = data; 1029 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id); 1030 1031 if (!pdd) 1032 return -EINVAL; 1033 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev); 1034 kfd_unlock_pdd(pdd); 1035 return 0; 1036 } 1037 1038 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, 1039 struct kfd_process *p, void *data) 1040 { 1041 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data; 1042 struct kfd_process_device *pdd; 1043 void *mem; 1044 struct kfd_dev *dev; 1045 int idr_handle; 1046 long err; 1047 uint64_t offset = args->mmap_offset; 1048 uint32_t flags = args->flags; 1049 1050 if (args->size == 0) 1051 return -EINVAL; 1052 1053 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1054 /* Flush pending deferred work to avoid racing with deferred actions 1055 * from previous memory map changes (e.g. munmap). 1056 */ 1057 svm_range_list_lock_and_flush_work(&p->svms, current->mm); 1058 mutex_lock(&p->svms.lock); 1059 mmap_write_unlock(current->mm); 1060 if (interval_tree_iter_first(&p->svms.objects, 1061 args->va_addr >> PAGE_SHIFT, 1062 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) { 1063 pr_err("Address: 0x%llx already allocated by SVM\n", 1064 args->va_addr); 1065 mutex_unlock(&p->svms.lock); 1066 return -EADDRINUSE; 1067 } 1068 mutex_unlock(&p->svms.lock); 1069 #endif 1070 mutex_lock(&p->mutex); 1071 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1072 if (!pdd) { 1073 err = -EINVAL; 1074 goto err_pdd; 1075 } 1076 1077 dev = pdd->dev; 1078 1079 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) && 1080 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && 1081 !kfd_dev_is_large_bar(dev)) { 1082 pr_err("Alloc host visible vram on small bar is not allowed\n"); 1083 err = -EINVAL; 1084 goto err_large_bar; 1085 } 1086 1087 pdd = kfd_bind_process_to_device(dev, p); 1088 if (IS_ERR(pdd)) { 1089 err = PTR_ERR(pdd); 1090 goto err_unlock; 1091 } 1092 1093 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 1094 if (args->size != kfd_doorbell_process_slice(dev)) { 1095 err = -EINVAL; 1096 goto err_unlock; 1097 } 1098 offset = kfd_get_process_doorbells(pdd); 1099 if (!offset) { 1100 err = -ENOMEM; 1101 goto err_unlock; 1102 } 1103 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 1104 if (args->size != PAGE_SIZE) { 1105 err = -EINVAL; 1106 goto err_unlock; 1107 } 1108 offset = dev->adev->rmmio_remap.bus_addr; 1109 if (!offset) { 1110 err = -ENOMEM; 1111 goto err_unlock; 1112 } 1113 } 1114 1115 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 1116 dev->adev, args->va_addr, args->size, 1117 pdd->drm_priv, (struct kgd_mem **) &mem, &offset, 1118 flags, false); 1119 1120 if (err) 1121 goto err_unlock; 1122 1123 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1124 if (idr_handle < 0) { 1125 err = -EFAULT; 1126 goto err_free; 1127 } 1128 1129 /* Update the VRAM usage count */ 1130 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 1131 uint64_t size = args->size; 1132 1133 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM) 1134 size >>= 1; 1135 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + PAGE_ALIGN(size)); 1136 } 1137 1138 mutex_unlock(&p->mutex); 1139 1140 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1141 args->mmap_offset = offset; 1142 1143 /* MMIO is mapped through kfd device 1144 * Generate a kfd mmap offset 1145 */ 1146 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1147 args->mmap_offset = KFD_MMAP_TYPE_MMIO 1148 | KFD_MMAP_GPU_ID(args->gpu_id); 1149 1150 return 0; 1151 1152 err_free: 1153 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, 1154 pdd->drm_priv, NULL); 1155 err_unlock: 1156 err_pdd: 1157 err_large_bar: 1158 mutex_unlock(&p->mutex); 1159 return err; 1160 } 1161 1162 static int kfd_ioctl_free_memory_of_gpu(struct file *filep, 1163 struct kfd_process *p, void *data) 1164 { 1165 struct kfd_ioctl_free_memory_of_gpu_args *args = data; 1166 struct kfd_process_device *pdd; 1167 void *mem; 1168 int ret; 1169 uint64_t size = 0; 1170 1171 mutex_lock(&p->mutex); 1172 /* 1173 * Safeguard to prevent user space from freeing signal BO. 1174 * It will be freed at process termination. 1175 */ 1176 if (p->signal_handle && (p->signal_handle == args->handle)) { 1177 pr_err("Free signal BO is not allowed\n"); 1178 ret = -EPERM; 1179 goto err_unlock; 1180 } 1181 1182 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1183 if (!pdd) { 1184 pr_err("Process device data doesn't exist\n"); 1185 ret = -EINVAL; 1186 goto err_pdd; 1187 } 1188 1189 mem = kfd_process_device_translate_handle( 1190 pdd, GET_IDR_HANDLE(args->handle)); 1191 if (!mem) { 1192 ret = -EINVAL; 1193 goto err_unlock; 1194 } 1195 1196 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, 1197 (struct kgd_mem *)mem, pdd->drm_priv, &size); 1198 1199 /* If freeing the buffer failed, leave the handle in place for 1200 * clean-up during process tear-down. 1201 */ 1202 if (!ret) 1203 kfd_process_device_remove_obj_handle( 1204 pdd, GET_IDR_HANDLE(args->handle)); 1205 1206 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage - size); 1207 1208 err_unlock: 1209 err_pdd: 1210 mutex_unlock(&p->mutex); 1211 return ret; 1212 } 1213 1214 static int kfd_ioctl_map_memory_to_gpu(struct file *filep, 1215 struct kfd_process *p, void *data) 1216 { 1217 struct kfd_ioctl_map_memory_to_gpu_args *args = data; 1218 struct kfd_process_device *pdd, *peer_pdd; 1219 void *mem; 1220 struct kfd_dev *dev; 1221 long err = 0; 1222 int i; 1223 uint32_t *devices_arr = NULL; 1224 1225 if (!args->n_devices) { 1226 pr_debug("Device IDs array empty\n"); 1227 return -EINVAL; 1228 } 1229 if (args->n_success > args->n_devices) { 1230 pr_debug("n_success exceeds n_devices\n"); 1231 return -EINVAL; 1232 } 1233 1234 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1235 GFP_KERNEL); 1236 if (!devices_arr) 1237 return -ENOMEM; 1238 1239 err = copy_from_user(devices_arr, 1240 (void __user *)args->device_ids_array_ptr, 1241 args->n_devices * sizeof(*devices_arr)); 1242 if (err != 0) { 1243 err = -EFAULT; 1244 goto copy_from_user_failed; 1245 } 1246 1247 mutex_lock(&p->mutex); 1248 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1249 if (!pdd) { 1250 err = -EINVAL; 1251 goto get_process_device_data_failed; 1252 } 1253 dev = pdd->dev; 1254 1255 pdd = kfd_bind_process_to_device(dev, p); 1256 if (IS_ERR(pdd)) { 1257 err = PTR_ERR(pdd); 1258 goto bind_process_to_device_failed; 1259 } 1260 1261 mem = kfd_process_device_translate_handle(pdd, 1262 GET_IDR_HANDLE(args->handle)); 1263 if (!mem) { 1264 err = -ENOMEM; 1265 goto get_mem_obj_from_handle_failed; 1266 } 1267 1268 for (i = args->n_success; i < args->n_devices; i++) { 1269 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1270 if (!peer_pdd) { 1271 pr_debug("Getting device by id failed for 0x%x\n", 1272 devices_arr[i]); 1273 err = -EINVAL; 1274 goto get_mem_obj_from_handle_failed; 1275 } 1276 1277 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p); 1278 if (IS_ERR(peer_pdd)) { 1279 err = PTR_ERR(peer_pdd); 1280 goto get_mem_obj_from_handle_failed; 1281 } 1282 1283 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 1284 peer_pdd->dev->adev, (struct kgd_mem *)mem, 1285 peer_pdd->drm_priv); 1286 if (err) { 1287 struct pci_dev *pdev = peer_pdd->dev->adev->pdev; 1288 1289 dev_err(dev->adev->dev, 1290 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n", 1291 pci_domain_nr(pdev->bus), 1292 pdev->bus->number, 1293 PCI_SLOT(pdev->devfn), 1294 PCI_FUNC(pdev->devfn), 1295 ((struct kgd_mem *)mem)->domain); 1296 goto map_memory_to_gpu_failed; 1297 } 1298 args->n_success = i+1; 1299 } 1300 1301 mutex_unlock(&p->mutex); 1302 1303 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true); 1304 if (err) { 1305 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1306 goto sync_memory_failed; 1307 } 1308 1309 /* Flush TLBs after waiting for the page table updates to complete */ 1310 for (i = 0; i < args->n_devices; i++) { 1311 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1312 if (WARN_ON_ONCE(!peer_pdd)) 1313 continue; 1314 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); 1315 } 1316 kfree(devices_arr); 1317 1318 return err; 1319 1320 get_process_device_data_failed: 1321 bind_process_to_device_failed: 1322 get_mem_obj_from_handle_failed: 1323 map_memory_to_gpu_failed: 1324 mutex_unlock(&p->mutex); 1325 copy_from_user_failed: 1326 sync_memory_failed: 1327 kfree(devices_arr); 1328 1329 return err; 1330 } 1331 1332 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, 1333 struct kfd_process *p, void *data) 1334 { 1335 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data; 1336 struct kfd_process_device *pdd, *peer_pdd; 1337 void *mem; 1338 long err = 0; 1339 uint32_t *devices_arr = NULL, i; 1340 1341 if (!args->n_devices) { 1342 pr_debug("Device IDs array empty\n"); 1343 return -EINVAL; 1344 } 1345 if (args->n_success > args->n_devices) { 1346 pr_debug("n_success exceeds n_devices\n"); 1347 return -EINVAL; 1348 } 1349 1350 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1351 GFP_KERNEL); 1352 if (!devices_arr) 1353 return -ENOMEM; 1354 1355 err = copy_from_user(devices_arr, 1356 (void __user *)args->device_ids_array_ptr, 1357 args->n_devices * sizeof(*devices_arr)); 1358 if (err != 0) { 1359 err = -EFAULT; 1360 goto copy_from_user_failed; 1361 } 1362 1363 mutex_lock(&p->mutex); 1364 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1365 if (!pdd) { 1366 err = -EINVAL; 1367 goto bind_process_to_device_failed; 1368 } 1369 1370 mem = kfd_process_device_translate_handle(pdd, 1371 GET_IDR_HANDLE(args->handle)); 1372 if (!mem) { 1373 err = -ENOMEM; 1374 goto get_mem_obj_from_handle_failed; 1375 } 1376 1377 for (i = args->n_success; i < args->n_devices; i++) { 1378 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1379 if (!peer_pdd) { 1380 err = -EINVAL; 1381 goto get_mem_obj_from_handle_failed; 1382 } 1383 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 1384 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv); 1385 if (err) { 1386 pr_err("Failed to unmap from gpu %d/%d\n", 1387 i, args->n_devices); 1388 goto unmap_memory_from_gpu_failed; 1389 } 1390 args->n_success = i+1; 1391 } 1392 mutex_unlock(&p->mutex); 1393 1394 if (kfd_flush_tlb_after_unmap(pdd->dev)) { 1395 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev, 1396 (struct kgd_mem *) mem, true); 1397 if (err) { 1398 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1399 goto sync_memory_failed; 1400 } 1401 1402 /* Flush TLBs after waiting for the page table updates to complete */ 1403 for (i = 0; i < args->n_devices; i++) { 1404 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1405 if (WARN_ON_ONCE(!peer_pdd)) 1406 continue; 1407 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); 1408 } 1409 } 1410 kfree(devices_arr); 1411 1412 return 0; 1413 1414 bind_process_to_device_failed: 1415 get_mem_obj_from_handle_failed: 1416 unmap_memory_from_gpu_failed: 1417 mutex_unlock(&p->mutex); 1418 copy_from_user_failed: 1419 sync_memory_failed: 1420 kfree(devices_arr); 1421 return err; 1422 } 1423 1424 static int kfd_ioctl_alloc_queue_gws(struct file *filep, 1425 struct kfd_process *p, void *data) 1426 { 1427 int retval; 1428 struct kfd_ioctl_alloc_queue_gws_args *args = data; 1429 struct queue *q; 1430 struct kfd_dev *dev; 1431 1432 mutex_lock(&p->mutex); 1433 q = pqm_get_user_queue(&p->pqm, args->queue_id); 1434 1435 if (q) { 1436 dev = q->device; 1437 } else { 1438 retval = -EINVAL; 1439 goto out_unlock; 1440 } 1441 1442 if (!dev->gws) { 1443 retval = -ENODEV; 1444 goto out_unlock; 1445 } 1446 1447 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 1448 retval = -ENODEV; 1449 goto out_unlock; 1450 } 1451 1452 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL); 1453 mutex_unlock(&p->mutex); 1454 1455 args->first_gws = 0; 1456 return retval; 1457 1458 out_unlock: 1459 mutex_unlock(&p->mutex); 1460 return retval; 1461 } 1462 1463 static int kfd_ioctl_get_dmabuf_info(struct file *filep, 1464 struct kfd_process *p, void *data) 1465 { 1466 struct kfd_ioctl_get_dmabuf_info_args *args = data; 1467 struct kfd_dev *dev = NULL; 1468 struct amdgpu_device *dmabuf_adev; 1469 void *metadata_buffer = NULL; 1470 uint32_t flags; 1471 unsigned int i; 1472 int r; 1473 1474 /* Find a KFD GPU device that supports the get_dmabuf_info query */ 1475 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++) 1476 if (dev) 1477 break; 1478 if (!dev) 1479 return -EINVAL; 1480 1481 if (args->metadata_ptr) { 1482 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL); 1483 if (!metadata_buffer) 1484 return -ENOMEM; 1485 } 1486 1487 /* Get dmabuf info from KGD */ 1488 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd, 1489 &dmabuf_adev, &args->size, 1490 metadata_buffer, args->metadata_size, 1491 &args->metadata_size, &flags); 1492 if (r) 1493 goto exit; 1494 1495 /* Reverse-lookup gpu_id from kgd pointer */ 1496 dev = kfd_device_by_adev(dmabuf_adev); 1497 if (!dev) { 1498 r = -EINVAL; 1499 goto exit; 1500 } 1501 args->gpu_id = dev->id; 1502 args->flags = flags; 1503 1504 /* Copy metadata buffer to user mode */ 1505 if (metadata_buffer) { 1506 r = copy_to_user((void __user *)args->metadata_ptr, 1507 metadata_buffer, args->metadata_size); 1508 if (r != 0) 1509 r = -EFAULT; 1510 } 1511 1512 exit: 1513 kfree(metadata_buffer); 1514 1515 return r; 1516 } 1517 1518 static int kfd_ioctl_import_dmabuf(struct file *filep, 1519 struct kfd_process *p, void *data) 1520 { 1521 struct kfd_ioctl_import_dmabuf_args *args = data; 1522 struct kfd_process_device *pdd; 1523 struct dma_buf *dmabuf; 1524 int idr_handle; 1525 uint64_t size; 1526 void *mem; 1527 int r; 1528 1529 dmabuf = dma_buf_get(args->dmabuf_fd); 1530 if (IS_ERR(dmabuf)) 1531 return PTR_ERR(dmabuf); 1532 1533 mutex_lock(&p->mutex); 1534 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1535 if (!pdd) { 1536 r = -EINVAL; 1537 goto err_unlock; 1538 } 1539 1540 pdd = kfd_bind_process_to_device(pdd->dev, p); 1541 if (IS_ERR(pdd)) { 1542 r = PTR_ERR(pdd); 1543 goto err_unlock; 1544 } 1545 1546 r = amdgpu_amdkfd_gpuvm_import_dmabuf(pdd->dev->adev, dmabuf, 1547 args->va_addr, pdd->drm_priv, 1548 (struct kgd_mem **)&mem, &size, 1549 NULL); 1550 if (r) 1551 goto err_unlock; 1552 1553 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1554 if (idr_handle < 0) { 1555 r = -EFAULT; 1556 goto err_free; 1557 } 1558 1559 mutex_unlock(&p->mutex); 1560 dma_buf_put(dmabuf); 1561 1562 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1563 1564 return 0; 1565 1566 err_free: 1567 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, 1568 pdd->drm_priv, NULL); 1569 err_unlock: 1570 mutex_unlock(&p->mutex); 1571 dma_buf_put(dmabuf); 1572 return r; 1573 } 1574 1575 /* Handle requests for watching SMI events */ 1576 static int kfd_ioctl_smi_events(struct file *filep, 1577 struct kfd_process *p, void *data) 1578 { 1579 struct kfd_ioctl_smi_events_args *args = data; 1580 struct kfd_process_device *pdd; 1581 1582 mutex_lock(&p->mutex); 1583 1584 pdd = kfd_process_device_data_by_id(p, args->gpuid); 1585 mutex_unlock(&p->mutex); 1586 if (!pdd) 1587 return -EINVAL; 1588 1589 return kfd_smi_event_open(pdd->dev, &args->anon_fd); 1590 } 1591 1592 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1593 1594 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1595 struct kfd_process *p, void *data) 1596 { 1597 struct kfd_ioctl_set_xnack_mode_args *args = data; 1598 int r = 0; 1599 1600 mutex_lock(&p->mutex); 1601 if (args->xnack_enabled >= 0) { 1602 if (!list_empty(&p->pqm.queues)) { 1603 pr_debug("Process has user queues running\n"); 1604 r = -EBUSY; 1605 goto out_unlock; 1606 } 1607 1608 if (p->xnack_enabled == args->xnack_enabled) 1609 goto out_unlock; 1610 1611 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) { 1612 r = -EPERM; 1613 goto out_unlock; 1614 } 1615 1616 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled); 1617 } else { 1618 args->xnack_enabled = p->xnack_enabled; 1619 } 1620 1621 out_unlock: 1622 mutex_unlock(&p->mutex); 1623 1624 return r; 1625 } 1626 1627 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1628 { 1629 struct kfd_ioctl_svm_args *args = data; 1630 int r = 0; 1631 1632 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n", 1633 args->start_addr, args->size, args->op, args->nattr); 1634 1635 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK)) 1636 return -EINVAL; 1637 if (!args->start_addr || !args->size) 1638 return -EINVAL; 1639 1640 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr, 1641 args->attrs); 1642 1643 return r; 1644 } 1645 #else 1646 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1647 struct kfd_process *p, void *data) 1648 { 1649 return -EPERM; 1650 } 1651 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1652 { 1653 return -EPERM; 1654 } 1655 #endif 1656 1657 static int criu_checkpoint_process(struct kfd_process *p, 1658 uint8_t __user *user_priv_data, 1659 uint64_t *priv_offset) 1660 { 1661 struct kfd_criu_process_priv_data process_priv; 1662 int ret; 1663 1664 memset(&process_priv, 0, sizeof(process_priv)); 1665 1666 process_priv.version = KFD_CRIU_PRIV_VERSION; 1667 /* For CR, we don't consider negative xnack mode which is used for 1668 * querying without changing it, here 0 simply means disabled and 1 1669 * means enabled so retry for finding a valid PTE. 1670 */ 1671 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0; 1672 1673 ret = copy_to_user(user_priv_data + *priv_offset, 1674 &process_priv, sizeof(process_priv)); 1675 1676 if (ret) { 1677 pr_err("Failed to copy process information to user\n"); 1678 ret = -EFAULT; 1679 } 1680 1681 *priv_offset += sizeof(process_priv); 1682 return ret; 1683 } 1684 1685 static int criu_checkpoint_devices(struct kfd_process *p, 1686 uint32_t num_devices, 1687 uint8_t __user *user_addr, 1688 uint8_t __user *user_priv_data, 1689 uint64_t *priv_offset) 1690 { 1691 struct kfd_criu_device_priv_data *device_priv = NULL; 1692 struct kfd_criu_device_bucket *device_buckets = NULL; 1693 int ret = 0, i; 1694 1695 device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL); 1696 if (!device_buckets) { 1697 ret = -ENOMEM; 1698 goto exit; 1699 } 1700 1701 device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL); 1702 if (!device_priv) { 1703 ret = -ENOMEM; 1704 goto exit; 1705 } 1706 1707 for (i = 0; i < num_devices; i++) { 1708 struct kfd_process_device *pdd = p->pdds[i]; 1709 1710 device_buckets[i].user_gpu_id = pdd->user_gpu_id; 1711 device_buckets[i].actual_gpu_id = pdd->dev->id; 1712 1713 /* 1714 * priv_data does not contain useful information for now and is reserved for 1715 * future use, so we do not set its contents. 1716 */ 1717 } 1718 1719 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets)); 1720 if (ret) { 1721 pr_err("Failed to copy device information to user\n"); 1722 ret = -EFAULT; 1723 goto exit; 1724 } 1725 1726 ret = copy_to_user(user_priv_data + *priv_offset, 1727 device_priv, 1728 num_devices * sizeof(*device_priv)); 1729 if (ret) { 1730 pr_err("Failed to copy device information to user\n"); 1731 ret = -EFAULT; 1732 } 1733 *priv_offset += num_devices * sizeof(*device_priv); 1734 1735 exit: 1736 kvfree(device_buckets); 1737 kvfree(device_priv); 1738 return ret; 1739 } 1740 1741 static uint32_t get_process_num_bos(struct kfd_process *p) 1742 { 1743 uint32_t num_of_bos = 0; 1744 int i; 1745 1746 /* Run over all PDDs of the process */ 1747 for (i = 0; i < p->n_pdds; i++) { 1748 struct kfd_process_device *pdd = p->pdds[i]; 1749 void *mem; 1750 int id; 1751 1752 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 1753 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; 1754 1755 if ((uint64_t)kgd_mem->va > pdd->gpuvm_base) 1756 num_of_bos++; 1757 } 1758 } 1759 return num_of_bos; 1760 } 1761 1762 static int criu_get_prime_handle(struct drm_gem_object *gobj, int flags, 1763 u32 *shared_fd) 1764 { 1765 struct dma_buf *dmabuf; 1766 int ret; 1767 1768 dmabuf = amdgpu_gem_prime_export(gobj, flags); 1769 if (IS_ERR(dmabuf)) { 1770 ret = PTR_ERR(dmabuf); 1771 pr_err("dmabuf export failed for the BO\n"); 1772 return ret; 1773 } 1774 1775 ret = dma_buf_fd(dmabuf, flags); 1776 if (ret < 0) { 1777 pr_err("dmabuf create fd failed, ret:%d\n", ret); 1778 goto out_free_dmabuf; 1779 } 1780 1781 *shared_fd = ret; 1782 return 0; 1783 1784 out_free_dmabuf: 1785 dma_buf_put(dmabuf); 1786 return ret; 1787 } 1788 1789 static int criu_checkpoint_bos(struct kfd_process *p, 1790 uint32_t num_bos, 1791 uint8_t __user *user_bos, 1792 uint8_t __user *user_priv_data, 1793 uint64_t *priv_offset) 1794 { 1795 struct kfd_criu_bo_bucket *bo_buckets; 1796 struct kfd_criu_bo_priv_data *bo_privs; 1797 int ret = 0, pdd_index, bo_index = 0, id; 1798 void *mem; 1799 1800 bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL); 1801 if (!bo_buckets) 1802 return -ENOMEM; 1803 1804 bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL); 1805 if (!bo_privs) { 1806 ret = -ENOMEM; 1807 goto exit; 1808 } 1809 1810 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 1811 struct kfd_process_device *pdd = p->pdds[pdd_index]; 1812 struct amdgpu_bo *dumper_bo; 1813 struct kgd_mem *kgd_mem; 1814 1815 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 1816 struct kfd_criu_bo_bucket *bo_bucket; 1817 struct kfd_criu_bo_priv_data *bo_priv; 1818 int i, dev_idx = 0; 1819 1820 if (!mem) { 1821 ret = -ENOMEM; 1822 goto exit; 1823 } 1824 1825 kgd_mem = (struct kgd_mem *)mem; 1826 dumper_bo = kgd_mem->bo; 1827 1828 if ((uint64_t)kgd_mem->va <= pdd->gpuvm_base) 1829 continue; 1830 1831 bo_bucket = &bo_buckets[bo_index]; 1832 bo_priv = &bo_privs[bo_index]; 1833 1834 bo_bucket->gpu_id = pdd->user_gpu_id; 1835 bo_bucket->addr = (uint64_t)kgd_mem->va; 1836 bo_bucket->size = amdgpu_bo_size(dumper_bo); 1837 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags; 1838 bo_priv->idr_handle = id; 1839 1840 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 1841 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo, 1842 &bo_priv->user_addr); 1843 if (ret) { 1844 pr_err("Failed to obtain user address for user-pointer bo\n"); 1845 goto exit; 1846 } 1847 } 1848 if (bo_bucket->alloc_flags 1849 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 1850 ret = criu_get_prime_handle(&dumper_bo->tbo.base, 1851 bo_bucket->alloc_flags & 1852 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0, 1853 &bo_bucket->dmabuf_fd); 1854 if (ret) 1855 goto exit; 1856 } else { 1857 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 1858 } 1859 1860 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 1861 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL | 1862 KFD_MMAP_GPU_ID(pdd->dev->id); 1863 else if (bo_bucket->alloc_flags & 1864 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1865 bo_bucket->offset = KFD_MMAP_TYPE_MMIO | 1866 KFD_MMAP_GPU_ID(pdd->dev->id); 1867 else 1868 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo); 1869 1870 for (i = 0; i < p->n_pdds; i++) { 1871 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->dev->adev, kgd_mem)) 1872 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id; 1873 } 1874 1875 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n" 1876 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x", 1877 bo_bucket->size, 1878 bo_bucket->addr, 1879 bo_bucket->offset, 1880 bo_bucket->gpu_id, 1881 bo_bucket->alloc_flags, 1882 bo_priv->idr_handle); 1883 bo_index++; 1884 } 1885 } 1886 1887 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets)); 1888 if (ret) { 1889 pr_err("Failed to copy BO information to user\n"); 1890 ret = -EFAULT; 1891 goto exit; 1892 } 1893 1894 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs)); 1895 if (ret) { 1896 pr_err("Failed to copy BO priv information to user\n"); 1897 ret = -EFAULT; 1898 goto exit; 1899 } 1900 1901 *priv_offset += num_bos * sizeof(*bo_privs); 1902 1903 exit: 1904 while (ret && bo_index--) { 1905 if (bo_buckets[bo_index].alloc_flags 1906 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) 1907 close_fd(bo_buckets[bo_index].dmabuf_fd); 1908 } 1909 1910 kvfree(bo_buckets); 1911 kvfree(bo_privs); 1912 return ret; 1913 } 1914 1915 static int criu_get_process_object_info(struct kfd_process *p, 1916 uint32_t *num_devices, 1917 uint32_t *num_bos, 1918 uint32_t *num_objects, 1919 uint64_t *objs_priv_size) 1920 { 1921 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size; 1922 uint32_t num_queues, num_events, num_svm_ranges; 1923 int ret; 1924 1925 *num_devices = p->n_pdds; 1926 *num_bos = get_process_num_bos(p); 1927 1928 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size); 1929 if (ret) 1930 return ret; 1931 1932 num_events = kfd_get_num_events(p); 1933 1934 ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size); 1935 if (ret) 1936 return ret; 1937 1938 *num_objects = num_queues + num_events + num_svm_ranges; 1939 1940 if (objs_priv_size) { 1941 priv_size = sizeof(struct kfd_criu_process_priv_data); 1942 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data); 1943 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data); 1944 priv_size += queues_priv_data_size; 1945 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data); 1946 priv_size += svm_priv_data_size; 1947 *objs_priv_size = priv_size; 1948 } 1949 return 0; 1950 } 1951 1952 static int criu_checkpoint(struct file *filep, 1953 struct kfd_process *p, 1954 struct kfd_ioctl_criu_args *args) 1955 { 1956 int ret; 1957 uint32_t num_devices, num_bos, num_objects; 1958 uint64_t priv_size, priv_offset = 0, bo_priv_offset; 1959 1960 if (!args->devices || !args->bos || !args->priv_data) 1961 return -EINVAL; 1962 1963 mutex_lock(&p->mutex); 1964 1965 if (!p->n_pdds) { 1966 pr_err("No pdd for given process\n"); 1967 ret = -ENODEV; 1968 goto exit_unlock; 1969 } 1970 1971 /* Confirm all process queues are evicted */ 1972 if (!p->queues_paused) { 1973 pr_err("Cannot dump process when queues are not in evicted state\n"); 1974 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */ 1975 ret = -EINVAL; 1976 goto exit_unlock; 1977 } 1978 1979 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size); 1980 if (ret) 1981 goto exit_unlock; 1982 1983 if (num_devices != args->num_devices || 1984 num_bos != args->num_bos || 1985 num_objects != args->num_objects || 1986 priv_size != args->priv_data_size) { 1987 1988 ret = -EINVAL; 1989 goto exit_unlock; 1990 } 1991 1992 /* each function will store private data inside priv_data and adjust priv_offset */ 1993 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset); 1994 if (ret) 1995 goto exit_unlock; 1996 1997 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices, 1998 (uint8_t __user *)args->priv_data, &priv_offset); 1999 if (ret) 2000 goto exit_unlock; 2001 2002 /* Leave room for BOs in the private data. They need to be restored 2003 * before events, but we checkpoint them last to simplify the error 2004 * handling. 2005 */ 2006 bo_priv_offset = priv_offset; 2007 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data); 2008 2009 if (num_objects) { 2010 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data, 2011 &priv_offset); 2012 if (ret) 2013 goto exit_unlock; 2014 2015 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data, 2016 &priv_offset); 2017 if (ret) 2018 goto exit_unlock; 2019 2020 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset); 2021 if (ret) 2022 goto exit_unlock; 2023 } 2024 2025 /* This must be the last thing in this function that can fail. 2026 * Otherwise we leak dmabuf file descriptors. 2027 */ 2028 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos, 2029 (uint8_t __user *)args->priv_data, &bo_priv_offset); 2030 2031 exit_unlock: 2032 mutex_unlock(&p->mutex); 2033 if (ret) 2034 pr_err("Failed to dump CRIU ret:%d\n", ret); 2035 else 2036 pr_debug("CRIU dump ret:%d\n", ret); 2037 2038 return ret; 2039 } 2040 2041 static int criu_restore_process(struct kfd_process *p, 2042 struct kfd_ioctl_criu_args *args, 2043 uint64_t *priv_offset, 2044 uint64_t max_priv_data_size) 2045 { 2046 int ret = 0; 2047 struct kfd_criu_process_priv_data process_priv; 2048 2049 if (*priv_offset + sizeof(process_priv) > max_priv_data_size) 2050 return -EINVAL; 2051 2052 ret = copy_from_user(&process_priv, 2053 (void __user *)(args->priv_data + *priv_offset), 2054 sizeof(process_priv)); 2055 if (ret) { 2056 pr_err("Failed to copy process private information from user\n"); 2057 ret = -EFAULT; 2058 goto exit; 2059 } 2060 *priv_offset += sizeof(process_priv); 2061 2062 if (process_priv.version != KFD_CRIU_PRIV_VERSION) { 2063 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n", 2064 process_priv.version, KFD_CRIU_PRIV_VERSION); 2065 return -EINVAL; 2066 } 2067 2068 pr_debug("Setting XNACK mode\n"); 2069 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) { 2070 pr_err("xnack mode cannot be set\n"); 2071 ret = -EPERM; 2072 goto exit; 2073 } else { 2074 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode); 2075 p->xnack_enabled = process_priv.xnack_mode; 2076 } 2077 2078 exit: 2079 return ret; 2080 } 2081 2082 static int criu_restore_devices(struct kfd_process *p, 2083 struct kfd_ioctl_criu_args *args, 2084 uint64_t *priv_offset, 2085 uint64_t max_priv_data_size) 2086 { 2087 struct kfd_criu_device_bucket *device_buckets; 2088 struct kfd_criu_device_priv_data *device_privs; 2089 int ret = 0; 2090 uint32_t i; 2091 2092 if (args->num_devices != p->n_pdds) 2093 return -EINVAL; 2094 2095 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size) 2096 return -EINVAL; 2097 2098 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL); 2099 if (!device_buckets) 2100 return -ENOMEM; 2101 2102 ret = copy_from_user(device_buckets, (void __user *)args->devices, 2103 args->num_devices * sizeof(*device_buckets)); 2104 if (ret) { 2105 pr_err("Failed to copy devices buckets from user\n"); 2106 ret = -EFAULT; 2107 goto exit; 2108 } 2109 2110 for (i = 0; i < args->num_devices; i++) { 2111 struct kfd_dev *dev; 2112 struct kfd_process_device *pdd; 2113 struct file *drm_file; 2114 2115 /* device private data is not currently used */ 2116 2117 if (!device_buckets[i].user_gpu_id) { 2118 pr_err("Invalid user gpu_id\n"); 2119 ret = -EINVAL; 2120 goto exit; 2121 } 2122 2123 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id); 2124 if (!dev) { 2125 pr_err("Failed to find device with gpu_id = %x\n", 2126 device_buckets[i].actual_gpu_id); 2127 ret = -EINVAL; 2128 goto exit; 2129 } 2130 2131 pdd = kfd_get_process_device_data(dev, p); 2132 if (!pdd) { 2133 pr_err("Failed to get pdd for gpu_id = %x\n", 2134 device_buckets[i].actual_gpu_id); 2135 ret = -EINVAL; 2136 goto exit; 2137 } 2138 pdd->user_gpu_id = device_buckets[i].user_gpu_id; 2139 2140 drm_file = fget(device_buckets[i].drm_fd); 2141 if (!drm_file) { 2142 pr_err("Invalid render node file descriptor sent from plugin (%d)\n", 2143 device_buckets[i].drm_fd); 2144 ret = -EINVAL; 2145 goto exit; 2146 } 2147 2148 if (pdd->drm_file) { 2149 ret = -EINVAL; 2150 goto exit; 2151 } 2152 2153 /* create the vm using render nodes for kfd pdd */ 2154 if (kfd_process_device_init_vm(pdd, drm_file)) { 2155 pr_err("could not init vm for given pdd\n"); 2156 /* On success, the PDD keeps the drm_file reference */ 2157 fput(drm_file); 2158 ret = -EINVAL; 2159 goto exit; 2160 } 2161 /* 2162 * pdd now already has the vm bound to render node so below api won't create a new 2163 * exclusive kfd mapping but use existing one with renderDXXX but is still needed 2164 * for iommu v2 binding and runtime pm. 2165 */ 2166 pdd = kfd_bind_process_to_device(dev, p); 2167 if (IS_ERR(pdd)) { 2168 ret = PTR_ERR(pdd); 2169 goto exit; 2170 } 2171 2172 if (!pdd->doorbell_index && 2173 kfd_alloc_process_doorbells(pdd->dev, &pdd->doorbell_index) < 0) { 2174 ret = -ENOMEM; 2175 goto exit; 2176 } 2177 } 2178 2179 /* 2180 * We are not copying device private data from user as we are not using the data for now, 2181 * but we still adjust for its private data. 2182 */ 2183 *priv_offset += args->num_devices * sizeof(*device_privs); 2184 2185 exit: 2186 kfree(device_buckets); 2187 return ret; 2188 } 2189 2190 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, 2191 struct kfd_criu_bo_bucket *bo_bucket, 2192 struct kfd_criu_bo_priv_data *bo_priv, 2193 struct kgd_mem **kgd_mem) 2194 { 2195 int idr_handle; 2196 int ret; 2197 const bool criu_resume = true; 2198 u64 offset; 2199 2200 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 2201 if (bo_bucket->size != kfd_doorbell_process_slice(pdd->dev)) 2202 return -EINVAL; 2203 2204 offset = kfd_get_process_doorbells(pdd); 2205 if (!offset) 2206 return -ENOMEM; 2207 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2208 /* MMIO BOs need remapped bus address */ 2209 if (bo_bucket->size != PAGE_SIZE) { 2210 pr_err("Invalid page size\n"); 2211 return -EINVAL; 2212 } 2213 offset = pdd->dev->adev->rmmio_remap.bus_addr; 2214 if (!offset) { 2215 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n"); 2216 return -ENOMEM; 2217 } 2218 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 2219 offset = bo_priv->user_addr; 2220 } 2221 /* Create the BO */ 2222 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr, 2223 bo_bucket->size, pdd->drm_priv, kgd_mem, 2224 &offset, bo_bucket->alloc_flags, criu_resume); 2225 if (ret) { 2226 pr_err("Could not create the BO\n"); 2227 return ret; 2228 } 2229 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n", 2230 bo_bucket->size, bo_bucket->addr, offset); 2231 2232 /* Restore previous IDR handle */ 2233 pr_debug("Restoring old IDR handle for the BO"); 2234 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle, 2235 bo_priv->idr_handle + 1, GFP_KERNEL); 2236 2237 if (idr_handle < 0) { 2238 pr_err("Could not allocate idr\n"); 2239 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, 2240 NULL); 2241 return -ENOMEM; 2242 } 2243 2244 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 2245 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id); 2246 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2247 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id); 2248 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 2249 bo_bucket->restored_offset = offset; 2250 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 2251 bo_bucket->restored_offset = offset; 2252 /* Update the VRAM usage count */ 2253 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size); 2254 } 2255 return 0; 2256 } 2257 2258 static int criu_restore_bo(struct kfd_process *p, 2259 struct kfd_criu_bo_bucket *bo_bucket, 2260 struct kfd_criu_bo_priv_data *bo_priv) 2261 { 2262 struct kfd_process_device *pdd; 2263 struct kgd_mem *kgd_mem; 2264 int ret; 2265 int j; 2266 2267 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n", 2268 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags, 2269 bo_priv->idr_handle); 2270 2271 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id); 2272 if (!pdd) { 2273 pr_err("Failed to get pdd\n"); 2274 return -ENODEV; 2275 } 2276 2277 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); 2278 if (ret) 2279 return ret; 2280 2281 /* now map these BOs to GPU/s */ 2282 for (j = 0; j < p->n_pdds; j++) { 2283 struct kfd_dev *peer; 2284 struct kfd_process_device *peer_pdd; 2285 2286 if (!bo_priv->mapped_gpuids[j]) 2287 break; 2288 2289 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]); 2290 if (!peer_pdd) 2291 return -EINVAL; 2292 2293 peer = peer_pdd->dev; 2294 2295 peer_pdd = kfd_bind_process_to_device(peer, p); 2296 if (IS_ERR(peer_pdd)) 2297 return PTR_ERR(peer_pdd); 2298 2299 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem, 2300 peer_pdd->drm_priv); 2301 if (ret) { 2302 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds); 2303 return ret; 2304 } 2305 } 2306 2307 pr_debug("map memory was successful for the BO\n"); 2308 /* create the dmabuf object and export the bo */ 2309 if (bo_bucket->alloc_flags 2310 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 2311 ret = criu_get_prime_handle(&kgd_mem->bo->tbo.base, DRM_RDWR, 2312 &bo_bucket->dmabuf_fd); 2313 if (ret) 2314 return ret; 2315 } else { 2316 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 2317 } 2318 2319 return 0; 2320 } 2321 2322 static int criu_restore_bos(struct kfd_process *p, 2323 struct kfd_ioctl_criu_args *args, 2324 uint64_t *priv_offset, 2325 uint64_t max_priv_data_size) 2326 { 2327 struct kfd_criu_bo_bucket *bo_buckets = NULL; 2328 struct kfd_criu_bo_priv_data *bo_privs = NULL; 2329 int ret = 0; 2330 uint32_t i = 0; 2331 2332 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size) 2333 return -EINVAL; 2334 2335 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */ 2336 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info); 2337 2338 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL); 2339 if (!bo_buckets) 2340 return -ENOMEM; 2341 2342 ret = copy_from_user(bo_buckets, (void __user *)args->bos, 2343 args->num_bos * sizeof(*bo_buckets)); 2344 if (ret) { 2345 pr_err("Failed to copy BOs information from user\n"); 2346 ret = -EFAULT; 2347 goto exit; 2348 } 2349 2350 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL); 2351 if (!bo_privs) { 2352 ret = -ENOMEM; 2353 goto exit; 2354 } 2355 2356 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset, 2357 args->num_bos * sizeof(*bo_privs)); 2358 if (ret) { 2359 pr_err("Failed to copy BOs information from user\n"); 2360 ret = -EFAULT; 2361 goto exit; 2362 } 2363 *priv_offset += args->num_bos * sizeof(*bo_privs); 2364 2365 /* Create and map new BOs */ 2366 for (; i < args->num_bos; i++) { 2367 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i]); 2368 if (ret) { 2369 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret); 2370 goto exit; 2371 } 2372 } /* done */ 2373 2374 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */ 2375 ret = copy_to_user((void __user *)args->bos, 2376 bo_buckets, 2377 (args->num_bos * sizeof(*bo_buckets))); 2378 if (ret) 2379 ret = -EFAULT; 2380 2381 exit: 2382 while (ret && i--) { 2383 if (bo_buckets[i].alloc_flags 2384 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) 2385 close_fd(bo_buckets[i].dmabuf_fd); 2386 } 2387 kvfree(bo_buckets); 2388 kvfree(bo_privs); 2389 return ret; 2390 } 2391 2392 static int criu_restore_objects(struct file *filep, 2393 struct kfd_process *p, 2394 struct kfd_ioctl_criu_args *args, 2395 uint64_t *priv_offset, 2396 uint64_t max_priv_data_size) 2397 { 2398 int ret = 0; 2399 uint32_t i; 2400 2401 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type)); 2402 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type)); 2403 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type)); 2404 2405 for (i = 0; i < args->num_objects; i++) { 2406 uint32_t object_type; 2407 2408 if (*priv_offset + sizeof(object_type) > max_priv_data_size) { 2409 pr_err("Invalid private data size\n"); 2410 return -EINVAL; 2411 } 2412 2413 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset)); 2414 if (ret) { 2415 pr_err("Failed to copy private information from user\n"); 2416 goto exit; 2417 } 2418 2419 switch (object_type) { 2420 case KFD_CRIU_OBJECT_TYPE_QUEUE: 2421 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data, 2422 priv_offset, max_priv_data_size); 2423 if (ret) 2424 goto exit; 2425 break; 2426 case KFD_CRIU_OBJECT_TYPE_EVENT: 2427 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data, 2428 priv_offset, max_priv_data_size); 2429 if (ret) 2430 goto exit; 2431 break; 2432 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE: 2433 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data, 2434 priv_offset, max_priv_data_size); 2435 if (ret) 2436 goto exit; 2437 break; 2438 default: 2439 pr_err("Invalid object type:%u at index:%d\n", object_type, i); 2440 ret = -EINVAL; 2441 goto exit; 2442 } 2443 } 2444 exit: 2445 return ret; 2446 } 2447 2448 static int criu_restore(struct file *filep, 2449 struct kfd_process *p, 2450 struct kfd_ioctl_criu_args *args) 2451 { 2452 uint64_t priv_offset = 0; 2453 int ret = 0; 2454 2455 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n", 2456 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size); 2457 2458 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size || 2459 !args->num_devices || !args->num_bos) 2460 return -EINVAL; 2461 2462 mutex_lock(&p->mutex); 2463 2464 /* 2465 * Set the process to evicted state to avoid running any new queues before all the memory 2466 * mappings are ready. 2467 */ 2468 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); 2469 if (ret) 2470 goto exit_unlock; 2471 2472 /* Each function will adjust priv_offset based on how many bytes they consumed */ 2473 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size); 2474 if (ret) 2475 goto exit_unlock; 2476 2477 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size); 2478 if (ret) 2479 goto exit_unlock; 2480 2481 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size); 2482 if (ret) 2483 goto exit_unlock; 2484 2485 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size); 2486 if (ret) 2487 goto exit_unlock; 2488 2489 if (priv_offset != args->priv_data_size) { 2490 pr_err("Invalid private data size\n"); 2491 ret = -EINVAL; 2492 } 2493 2494 exit_unlock: 2495 mutex_unlock(&p->mutex); 2496 if (ret) 2497 pr_err("Failed to restore CRIU ret:%d\n", ret); 2498 else 2499 pr_debug("CRIU restore successful\n"); 2500 2501 return ret; 2502 } 2503 2504 static int criu_unpause(struct file *filep, 2505 struct kfd_process *p, 2506 struct kfd_ioctl_criu_args *args) 2507 { 2508 int ret; 2509 2510 mutex_lock(&p->mutex); 2511 2512 if (!p->queues_paused) { 2513 mutex_unlock(&p->mutex); 2514 return -EINVAL; 2515 } 2516 2517 ret = kfd_process_restore_queues(p); 2518 if (ret) 2519 pr_err("Failed to unpause queues ret:%d\n", ret); 2520 else 2521 p->queues_paused = false; 2522 2523 mutex_unlock(&p->mutex); 2524 2525 return ret; 2526 } 2527 2528 static int criu_resume(struct file *filep, 2529 struct kfd_process *p, 2530 struct kfd_ioctl_criu_args *args) 2531 { 2532 struct kfd_process *target = NULL; 2533 struct pid *pid = NULL; 2534 int ret = 0; 2535 2536 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__, 2537 args->pid); 2538 2539 pid = find_get_pid(args->pid); 2540 if (!pid) { 2541 pr_err("Cannot find pid info for %i\n", args->pid); 2542 return -ESRCH; 2543 } 2544 2545 pr_debug("calling kfd_lookup_process_by_pid\n"); 2546 target = kfd_lookup_process_by_pid(pid); 2547 2548 put_pid(pid); 2549 2550 if (!target) { 2551 pr_debug("Cannot find process info for %i\n", args->pid); 2552 return -ESRCH; 2553 } 2554 2555 mutex_lock(&target->mutex); 2556 ret = kfd_criu_resume_svm(target); 2557 if (ret) { 2558 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid); 2559 goto exit; 2560 } 2561 2562 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info); 2563 if (ret) 2564 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid); 2565 2566 exit: 2567 mutex_unlock(&target->mutex); 2568 2569 kfd_unref_process(target); 2570 return ret; 2571 } 2572 2573 static int criu_process_info(struct file *filep, 2574 struct kfd_process *p, 2575 struct kfd_ioctl_criu_args *args) 2576 { 2577 int ret = 0; 2578 2579 mutex_lock(&p->mutex); 2580 2581 if (!p->n_pdds) { 2582 pr_err("No pdd for given process\n"); 2583 ret = -ENODEV; 2584 goto err_unlock; 2585 } 2586 2587 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); 2588 if (ret) 2589 goto err_unlock; 2590 2591 p->queues_paused = true; 2592 2593 args->pid = task_pid_nr_ns(p->lead_thread, 2594 task_active_pid_ns(p->lead_thread)); 2595 2596 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos, 2597 &args->num_objects, &args->priv_data_size); 2598 if (ret) 2599 goto err_unlock; 2600 2601 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n", 2602 args->num_devices, args->num_bos, args->num_objects, 2603 args->priv_data_size); 2604 2605 err_unlock: 2606 if (ret) { 2607 kfd_process_restore_queues(p); 2608 p->queues_paused = false; 2609 } 2610 mutex_unlock(&p->mutex); 2611 return ret; 2612 } 2613 2614 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data) 2615 { 2616 struct kfd_ioctl_criu_args *args = data; 2617 int ret; 2618 2619 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op); 2620 switch (args->op) { 2621 case KFD_CRIU_OP_PROCESS_INFO: 2622 ret = criu_process_info(filep, p, args); 2623 break; 2624 case KFD_CRIU_OP_CHECKPOINT: 2625 ret = criu_checkpoint(filep, p, args); 2626 break; 2627 case KFD_CRIU_OP_UNPAUSE: 2628 ret = criu_unpause(filep, p, args); 2629 break; 2630 case KFD_CRIU_OP_RESTORE: 2631 ret = criu_restore(filep, p, args); 2632 break; 2633 case KFD_CRIU_OP_RESUME: 2634 ret = criu_resume(filep, p, args); 2635 break; 2636 default: 2637 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op); 2638 ret = -EINVAL; 2639 break; 2640 } 2641 2642 if (ret) 2643 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret); 2644 2645 return ret; 2646 } 2647 2648 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ 2649 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ 2650 .cmd_drv = 0, .name = #ioctl} 2651 2652 /** Ioctl table */ 2653 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { 2654 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION, 2655 kfd_ioctl_get_version, 0), 2656 2657 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE, 2658 kfd_ioctl_create_queue, 0), 2659 2660 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE, 2661 kfd_ioctl_destroy_queue, 0), 2662 2663 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY, 2664 kfd_ioctl_set_memory_policy, 0), 2665 2666 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS, 2667 kfd_ioctl_get_clock_counters, 0), 2668 2669 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES, 2670 kfd_ioctl_get_process_apertures, 0), 2671 2672 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE, 2673 kfd_ioctl_update_queue, 0), 2674 2675 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT, 2676 kfd_ioctl_create_event, 0), 2677 2678 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT, 2679 kfd_ioctl_destroy_event, 0), 2680 2681 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT, 2682 kfd_ioctl_set_event, 0), 2683 2684 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT, 2685 kfd_ioctl_reset_event, 0), 2686 2687 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS, 2688 kfd_ioctl_wait_events, 0), 2689 2690 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED, 2691 kfd_ioctl_dbg_register, 0), 2692 2693 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED, 2694 kfd_ioctl_dbg_unregister, 0), 2695 2696 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED, 2697 kfd_ioctl_dbg_address_watch, 0), 2698 2699 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED, 2700 kfd_ioctl_dbg_wave_control, 0), 2701 2702 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA, 2703 kfd_ioctl_set_scratch_backing_va, 0), 2704 2705 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG, 2706 kfd_ioctl_get_tile_config, 0), 2707 2708 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER, 2709 kfd_ioctl_set_trap_handler, 0), 2710 2711 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW, 2712 kfd_ioctl_get_process_apertures_new, 0), 2713 2714 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM, 2715 kfd_ioctl_acquire_vm, 0), 2716 2717 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU, 2718 kfd_ioctl_alloc_memory_of_gpu, 0), 2719 2720 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU, 2721 kfd_ioctl_free_memory_of_gpu, 0), 2722 2723 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU, 2724 kfd_ioctl_map_memory_to_gpu, 0), 2725 2726 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU, 2727 kfd_ioctl_unmap_memory_from_gpu, 0), 2728 2729 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK, 2730 kfd_ioctl_set_cu_mask, 0), 2731 2732 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE, 2733 kfd_ioctl_get_queue_wave_state, 0), 2734 2735 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO, 2736 kfd_ioctl_get_dmabuf_info, 0), 2737 2738 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF, 2739 kfd_ioctl_import_dmabuf, 0), 2740 2741 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS, 2742 kfd_ioctl_alloc_queue_gws, 0), 2743 2744 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS, 2745 kfd_ioctl_smi_events, 0), 2746 2747 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0), 2748 2749 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE, 2750 kfd_ioctl_set_xnack_mode, 0), 2751 2752 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP, 2753 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE), 2754 2755 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY, 2756 kfd_ioctl_get_available_memory, 0), 2757 }; 2758 2759 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) 2760 2761 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) 2762 { 2763 struct kfd_process *process; 2764 amdkfd_ioctl_t *func; 2765 const struct amdkfd_ioctl_desc *ioctl = NULL; 2766 unsigned int nr = _IOC_NR(cmd); 2767 char stack_kdata[128]; 2768 char *kdata = NULL; 2769 unsigned int usize, asize; 2770 int retcode = -EINVAL; 2771 bool ptrace_attached = false; 2772 2773 if (nr >= AMDKFD_CORE_IOCTL_COUNT) 2774 goto err_i1; 2775 2776 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { 2777 u32 amdkfd_size; 2778 2779 ioctl = &amdkfd_ioctls[nr]; 2780 2781 amdkfd_size = _IOC_SIZE(ioctl->cmd); 2782 usize = asize = _IOC_SIZE(cmd); 2783 if (amdkfd_size > asize) 2784 asize = amdkfd_size; 2785 2786 cmd = ioctl->cmd; 2787 } else 2788 goto err_i1; 2789 2790 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg); 2791 2792 /* Get the process struct from the filep. Only the process 2793 * that opened /dev/kfd can use the file descriptor. Child 2794 * processes need to create their own KFD device context. 2795 */ 2796 process = filep->private_data; 2797 2798 rcu_read_lock(); 2799 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) && 2800 ptrace_parent(process->lead_thread) == current) 2801 ptrace_attached = true; 2802 rcu_read_unlock(); 2803 2804 if (process->lead_thread != current->group_leader 2805 && !ptrace_attached) { 2806 dev_dbg(kfd_device, "Using KFD FD in wrong process\n"); 2807 retcode = -EBADF; 2808 goto err_i1; 2809 } 2810 2811 /* Do not trust userspace, use our own definition */ 2812 func = ioctl->func; 2813 2814 if (unlikely(!func)) { 2815 dev_dbg(kfd_device, "no function\n"); 2816 retcode = -EINVAL; 2817 goto err_i1; 2818 } 2819 2820 /* 2821 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support 2822 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a 2823 * more priviledged access. 2824 */ 2825 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) { 2826 if (!capable(CAP_CHECKPOINT_RESTORE) && 2827 !capable(CAP_SYS_ADMIN)) { 2828 retcode = -EACCES; 2829 goto err_i1; 2830 } 2831 } 2832 2833 if (cmd & (IOC_IN | IOC_OUT)) { 2834 if (asize <= sizeof(stack_kdata)) { 2835 kdata = stack_kdata; 2836 } else { 2837 kdata = kmalloc(asize, GFP_KERNEL); 2838 if (!kdata) { 2839 retcode = -ENOMEM; 2840 goto err_i1; 2841 } 2842 } 2843 if (asize > usize) 2844 memset(kdata + usize, 0, asize - usize); 2845 } 2846 2847 if (cmd & IOC_IN) { 2848 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) { 2849 retcode = -EFAULT; 2850 goto err_i1; 2851 } 2852 } else if (cmd & IOC_OUT) { 2853 memset(kdata, 0, usize); 2854 } 2855 2856 retcode = func(filep, process, kdata); 2857 2858 if (cmd & IOC_OUT) 2859 if (copy_to_user((void __user *)arg, kdata, usize) != 0) 2860 retcode = -EFAULT; 2861 2862 err_i1: 2863 if (!ioctl) 2864 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n", 2865 task_pid_nr(current), cmd, nr); 2866 2867 if (kdata != stack_kdata) 2868 kfree(kdata); 2869 2870 if (retcode) 2871 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n", 2872 nr, arg, retcode); 2873 2874 return retcode; 2875 } 2876 2877 static int kfd_mmio_mmap(struct kfd_dev *dev, struct kfd_process *process, 2878 struct vm_area_struct *vma) 2879 { 2880 phys_addr_t address; 2881 2882 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2883 return -EINVAL; 2884 2885 address = dev->adev->rmmio_remap.bus_addr; 2886 2887 vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | 2888 VM_DONTDUMP | VM_PFNMAP; 2889 2890 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2891 2892 pr_debug("pasid 0x%x mapping mmio page\n" 2893 " target user address == 0x%08llX\n" 2894 " physical address == 0x%08llX\n" 2895 " vm_flags == 0x%04lX\n" 2896 " size == 0x%04lX\n", 2897 process->pasid, (unsigned long long) vma->vm_start, 2898 address, vma->vm_flags, PAGE_SIZE); 2899 2900 return io_remap_pfn_range(vma, 2901 vma->vm_start, 2902 address >> PAGE_SHIFT, 2903 PAGE_SIZE, 2904 vma->vm_page_prot); 2905 } 2906 2907 2908 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma) 2909 { 2910 struct kfd_process *process; 2911 struct kfd_dev *dev = NULL; 2912 unsigned long mmap_offset; 2913 unsigned int gpu_id; 2914 2915 process = kfd_get_process(current); 2916 if (IS_ERR(process)) 2917 return PTR_ERR(process); 2918 2919 mmap_offset = vma->vm_pgoff << PAGE_SHIFT; 2920 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset); 2921 if (gpu_id) 2922 dev = kfd_device_by_id(gpu_id); 2923 2924 switch (mmap_offset & KFD_MMAP_TYPE_MASK) { 2925 case KFD_MMAP_TYPE_DOORBELL: 2926 if (!dev) 2927 return -ENODEV; 2928 return kfd_doorbell_mmap(dev, process, vma); 2929 2930 case KFD_MMAP_TYPE_EVENTS: 2931 return kfd_event_mmap(process, vma); 2932 2933 case KFD_MMAP_TYPE_RESERVED_MEM: 2934 if (!dev) 2935 return -ENODEV; 2936 return kfd_reserved_mem_mmap(dev, process, vma); 2937 case KFD_MMAP_TYPE_MMIO: 2938 if (!dev) 2939 return -ENODEV; 2940 return kfd_mmio_mmap(dev, process, vma); 2941 } 2942 2943 return -EFAULT; 2944 } 2945