1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/capability.h> 25 #include <linux/device.h> 26 #include <linux/err.h> 27 #include <linux/fs.h> 28 #include <linux/file.h> 29 #include <linux/overflow.h> 30 #include <linux/sched.h> 31 #include <linux/slab.h> 32 #include <linux/uaccess.h> 33 #include <linux/compat.h> 34 #include <uapi/linux/kfd_ioctl.h> 35 #include <linux/time.h> 36 #include <linux/mm.h> 37 #include <linux/mman.h> 38 #include <linux/pseudo_fs.h> 39 #include <linux/ptrace.h> 40 #include <linux/dma-buf.h> 41 #include <linux/processor.h> 42 #include "kfd_priv.h" 43 #include "kfd_device_queue_manager.h" 44 #include "kfd_svm.h" 45 #include "amdgpu_amdkfd.h" 46 #include "kfd_smi_events.h" 47 #include "amdgpu_dma_buf.h" 48 #include "kfd_debug.h" 49 #include "amdgpu_ptl.h" 50 51 static long kfd_ioctl(struct file *, unsigned int, unsigned long); 52 static int kfd_open(struct inode *, struct file *); 53 static int kfd_release(struct inode *, struct file *); 54 static int kfd_mmap(struct file *, struct vm_area_struct *); 55 56 static const char kfd_dev_name[] = "kfd"; 57 58 static const struct file_operations kfd_fops = { 59 .owner = THIS_MODULE, 60 .unlocked_ioctl = kfd_ioctl, 61 .compat_ioctl = compat_ptr_ioctl, 62 .open = kfd_open, 63 .release = kfd_release, 64 .mmap = kfd_mmap, 65 }; 66 67 static int kfd_char_dev_major = -1; 68 struct device *kfd_device; 69 static const struct class kfd_class = { 70 .name = kfd_dev_name, 71 }; 72 73 /* 74 * Private pseudo-filesystem for KFD, Provides a stable, module-owned 75 * inode whose address_space is the unmap target for all /dev/kfd 76 * openers during GPU reset. 77 */ 78 static struct vfsmount *kfd_fs_mnt; 79 static int kfd_fs_cnt; 80 81 static int kfd_fs_init_fs_context(struct fs_context *fc) 82 { 83 return init_pseudo(fc, 0x4b464400 /* "KFD" */) ? 0 : -ENOMEM; 84 } 85 86 static struct file_system_type kfd_fs_type = { 87 .name = "kfd", 88 .init_fs_context = kfd_fs_init_fs_context, 89 .kill_sb = kill_anon_super, 90 }; 91 92 static struct inode *kfd_fs_inode_new(void) 93 { 94 struct inode *inode; 95 int r; 96 97 r = simple_pin_fs(&kfd_fs_type, &kfd_fs_mnt, &kfd_fs_cnt); 98 if (r < 0) 99 return ERR_PTR(r); 100 101 inode = alloc_anon_inode(kfd_fs_mnt->mnt_sb); 102 if (IS_ERR(inode)) 103 simple_release_fs(&kfd_fs_mnt, &kfd_fs_cnt); 104 105 return inode; 106 } 107 108 static void kfd_fs_inode_free(struct inode *inode) 109 { 110 if (inode) { 111 iput(inode); 112 simple_release_fs(&kfd_fs_mnt, &kfd_fs_cnt); 113 } 114 } 115 116 static struct inode *kfd_anon_inode; 117 118 void kfd_dev_unmap_mapping_range(loff_t const holebegin, loff_t const holelen) 119 { 120 if (kfd_anon_inode) 121 unmap_mapping_range(kfd_anon_inode->i_mapping, holebegin, holelen, 1); 122 } 123 124 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id) 125 { 126 struct kfd_process_device *pdd; 127 128 mutex_lock(&p->mutex); 129 pdd = kfd_process_device_data_by_id(p, gpu_id); 130 131 if (pdd) 132 return pdd; 133 134 mutex_unlock(&p->mutex); 135 return NULL; 136 } 137 138 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd) 139 { 140 mutex_unlock(&pdd->process->mutex); 141 } 142 143 int kfd_chardev_init(void) 144 { 145 int err = 0; 146 147 kfd_anon_inode = kfd_fs_inode_new(); 148 if (IS_ERR(kfd_anon_inode)) { 149 err = PTR_ERR(kfd_anon_inode); 150 kfd_anon_inode = NULL; 151 return err; 152 } 153 154 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops); 155 err = kfd_char_dev_major; 156 if (err < 0) 157 goto err_register_chrdev; 158 159 err = class_register(&kfd_class); 160 if (err) 161 goto err_class_create; 162 163 kfd_device = device_create(&kfd_class, NULL, 164 MKDEV(kfd_char_dev_major, 0), 165 NULL, kfd_dev_name); 166 err = PTR_ERR(kfd_device); 167 if (IS_ERR(kfd_device)) 168 goto err_device_create; 169 170 return 0; 171 172 err_device_create: 173 class_unregister(&kfd_class); 174 err_class_create: 175 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 176 err_register_chrdev: 177 kfd_fs_inode_free(kfd_anon_inode); 178 kfd_anon_inode = NULL; 179 return err; 180 } 181 182 void kfd_chardev_exit(void) 183 { 184 device_destroy(&kfd_class, MKDEV(kfd_char_dev_major, 0)); 185 class_unregister(&kfd_class); 186 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 187 kfd_fs_inode_free(kfd_anon_inode); 188 kfd_anon_inode = NULL; 189 kfd_device = NULL; 190 } 191 192 193 static int kfd_open(struct inode *inode, struct file *filep) 194 { 195 struct kfd_process *process; 196 bool is_32bit_user_mode; 197 198 if (iminor(inode) != 0) 199 return -ENODEV; 200 201 filep->f_mapping = kfd_anon_inode->i_mapping; 202 203 is_32bit_user_mode = in_compat_syscall(); 204 205 if (is_32bit_user_mode) { 206 dev_warn(kfd_device, 207 "Process %d (32-bit) failed to open /dev/kfd\n" 208 "32-bit processes are not supported by amdkfd\n", 209 current->pid); 210 return -EPERM; 211 } 212 213 process = kfd_create_process(current); 214 if (IS_ERR(process)) 215 return PTR_ERR(process); 216 217 /* filep now owns the reference returned by kfd_create_process */ 218 filep->private_data = process; 219 220 dev_dbg(kfd_device, "process pid %d opened kfd node, compat mode (32 bit) - %d\n", 221 process->lead_thread->pid, process->is_32bit_user_mode); 222 223 return 0; 224 } 225 226 static int kfd_release(struct inode *inode, struct file *filep) 227 { 228 struct kfd_process *process = filep->private_data; 229 230 if (!process) 231 return 0; 232 233 if (process->context_id != KFD_CONTEXT_ID_PRIMARY) 234 kfd_process_notifier_release_internal(process); 235 236 kfd_unref_process(process); 237 238 return 0; 239 } 240 241 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, 242 void *data) 243 { 244 struct kfd_ioctl_get_version_args *args = data; 245 246 args->major_version = KFD_IOCTL_MAJOR_VERSION; 247 args->minor_version = KFD_IOCTL_MINOR_VERSION; 248 249 return 0; 250 } 251 252 static int set_queue_properties_from_user(struct queue_properties *q_properties, 253 struct kfd_ioctl_create_queue_args *args) 254 { 255 /* 256 * Repurpose queue percentage to accommodate new features: 257 * bit 0-7: queue percentage 258 * bit 8-15: pm4_target_xcc 259 */ 260 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) { 261 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 262 return -EINVAL; 263 } 264 265 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 266 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 267 return -EINVAL; 268 } 269 270 if ((args->ring_base_address) && 271 (!access_ok((const void __user *) args->ring_base_address, 272 sizeof(uint64_t)))) { 273 pr_err("Can't access ring base address\n"); 274 return -EFAULT; 275 } 276 277 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 278 pr_err("Ring size must be a power of 2 or 0\n"); 279 return -EINVAL; 280 } 281 282 if (args->ring_size < KFD_MIN_QUEUE_RING_SIZE) { 283 args->ring_size = KFD_MIN_QUEUE_RING_SIZE; 284 pr_debug("Size lower. clamped to KFD_MIN_QUEUE_RING_SIZE"); 285 } 286 287 if ((args->metadata_ring_size != 0) && !is_power_of_2(args->metadata_ring_size)) { 288 pr_err("Metadata ring size must be a power of 2 or 0\n"); 289 return -EINVAL; 290 } 291 292 if (!access_ok((const void __user *) args->read_pointer_address, 293 sizeof(uint32_t))) { 294 pr_err("Can't access read pointer\n"); 295 return -EFAULT; 296 } 297 298 if (!access_ok((const void __user *) args->write_pointer_address, 299 sizeof(uint32_t))) { 300 pr_err("Can't access write pointer\n"); 301 return -EFAULT; 302 } 303 304 if (args->eop_buffer_address && 305 !access_ok((const void __user *) args->eop_buffer_address, 306 sizeof(uint32_t))) { 307 pr_debug("Can't access eop buffer"); 308 return -EFAULT; 309 } 310 311 if (args->ctx_save_restore_address && 312 !access_ok((const void __user *) args->ctx_save_restore_address, 313 sizeof(uint32_t))) { 314 pr_debug("Can't access ctx save restore buffer"); 315 return -EFAULT; 316 } 317 318 q_properties->is_interop = false; 319 q_properties->is_gws = false; 320 q_properties->queue_percent = args->queue_percentage & 0xFF; 321 /* bit 8-15 are repurposed to be PM4 target XCC */ 322 q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF; 323 q_properties->priority = args->queue_priority; 324 q_properties->queue_address = args->ring_base_address; 325 q_properties->queue_size = args->ring_size; 326 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 327 q_properties->metadata_queue_size = args->metadata_ring_size; 328 329 q_properties->read_ptr = (void __user *)args->read_pointer_address; 330 q_properties->write_ptr = (void __user *)args->write_pointer_address; 331 q_properties->eop_ring_buffer_address = args->eop_buffer_address; 332 q_properties->eop_ring_buffer_size = args->eop_buffer_size; 333 q_properties->ctx_save_restore_area_address = 334 args->ctx_save_restore_address; 335 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size; 336 q_properties->ctl_stack_size = args->ctl_stack_size; 337 q_properties->sdma_engine_id = args->sdma_engine_id; 338 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE || 339 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 340 q_properties->type = KFD_QUEUE_TYPE_COMPUTE; 341 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA) 342 q_properties->type = KFD_QUEUE_TYPE_SDMA; 343 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI) 344 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI; 345 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_BY_ENG_ID) 346 q_properties->type = KFD_QUEUE_TYPE_SDMA_BY_ENG_ID; 347 else 348 return -ENOTSUPP; 349 350 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 351 q_properties->format = KFD_QUEUE_FORMAT_AQL; 352 else 353 q_properties->format = KFD_QUEUE_FORMAT_PM4; 354 355 pr_debug("Queue Percentage: %d, %d\n", 356 q_properties->queue_percent, args->queue_percentage); 357 358 pr_debug("Queue Priority: %d, %d\n", 359 q_properties->priority, args->queue_priority); 360 361 pr_debug("Queue Address: 0x%llX, 0x%llX\n", 362 q_properties->queue_address, args->ring_base_address); 363 364 pr_debug("Queue Size: 0x%llX, %u\n", 365 q_properties->queue_size, args->ring_size); 366 367 pr_debug("Queue r/w Pointers: %px, %px\n", 368 q_properties->read_ptr, 369 q_properties->write_ptr); 370 371 pr_debug("Queue Format: %d\n", q_properties->format); 372 373 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address); 374 375 pr_debug("Queue CTX save area: 0x%llX\n", 376 q_properties->ctx_save_restore_area_address); 377 378 return 0; 379 } 380 381 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, 382 void *data) 383 { 384 struct kfd_ioctl_create_queue_args *args = data; 385 struct kfd_node *dev; 386 int err = 0; 387 unsigned int queue_id; 388 struct kfd_process_device *pdd; 389 struct queue_properties q_properties; 390 uint32_t doorbell_offset_in_process = 0; 391 392 memset(&q_properties, 0, sizeof(struct queue_properties)); 393 394 pr_debug("Creating queue ioctl\n"); 395 396 err = set_queue_properties_from_user(&q_properties, args); 397 if (err) 398 return err; 399 400 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id); 401 402 mutex_lock(&p->mutex); 403 404 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 405 if (!pdd) { 406 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 407 err = -EINVAL; 408 goto err_pdd; 409 } 410 dev = pdd->dev; 411 412 pdd = kfd_bind_process_to_device(dev, p); 413 if (IS_ERR(pdd)) { 414 err = -ESRCH; 415 goto err_bind_process; 416 } 417 418 if (q_properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 419 int max_sdma_eng_id = kfd_get_num_sdma_engines(dev) + 420 kfd_get_num_xgmi_sdma_engines(dev) - 1; 421 422 if (q_properties.sdma_engine_id > max_sdma_eng_id) { 423 err = -EINVAL; 424 pr_err("sdma_engine_id %i exceeds maximum id of %i\n", 425 q_properties.sdma_engine_id, max_sdma_eng_id); 426 goto err_sdma_engine_id; 427 } 428 } 429 430 if (!pdd->qpd.proc_doorbells) { 431 err = kfd_alloc_process_doorbells(dev->kfd, pdd); 432 if (err) { 433 pr_debug("failed to allocate process doorbells\n"); 434 goto err_bind_process; 435 } 436 } 437 438 err = kfd_queue_acquire_buffers(pdd, &q_properties); 439 if (err) { 440 pr_debug("failed to acquire user queue buffers\n"); 441 goto err_acquire_queue_buf; 442 } 443 444 pr_debug("Creating queue for process pid %d on gpu 0x%x\n", 445 p->lead_thread->pid, 446 dev->id); 447 448 err = pqm_create_queue(&p->pqm, dev, &q_properties, &queue_id, 449 NULL, NULL, NULL, &doorbell_offset_in_process); 450 if (err != 0) 451 goto err_create_queue; 452 453 args->queue_id = queue_id; 454 455 456 /* Return gpu_id as doorbell offset for mmap usage */ 457 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL; 458 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id); 459 if (KFD_IS_SOC15(dev)) 460 /* On SOC15 ASICs, include the doorbell offset within the 461 * process doorbell frame, which is 2 pages. 462 */ 463 args->doorbell_offset |= doorbell_offset_in_process; 464 465 mutex_unlock(&p->mutex); 466 467 pr_debug("Queue id %d was created successfully\n", args->queue_id); 468 469 pr_debug("Ring buffer address == 0x%016llX\n", 470 args->ring_base_address); 471 472 pr_debug("Read ptr address == 0x%016llX\n", 473 args->read_pointer_address); 474 475 pr_debug("Write ptr address == 0x%016llX\n", 476 args->write_pointer_address); 477 478 kfd_dbg_ev_raise(KFD_EC_MASK(EC_QUEUE_NEW), p, dev, queue_id, false, NULL, 0); 479 return 0; 480 481 err_create_queue: 482 kfd_queue_unref_bo_vas(pdd, &q_properties); 483 kfd_queue_release_buffers(pdd, &q_properties); 484 err_acquire_queue_buf: 485 err_sdma_engine_id: 486 err_bind_process: 487 err_pdd: 488 mutex_unlock(&p->mutex); 489 return err; 490 } 491 492 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p, 493 void *data) 494 { 495 int retval; 496 struct kfd_ioctl_destroy_queue_args *args = data; 497 498 pr_debug("Destroying queue id %d for process pid %d\n", 499 args->queue_id, 500 p->lead_thread->pid); 501 502 mutex_lock(&p->mutex); 503 504 retval = pqm_destroy_queue(&p->pqm, args->queue_id); 505 506 mutex_unlock(&p->mutex); 507 return retval; 508 } 509 510 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, 511 void *data) 512 { 513 int retval; 514 struct kfd_ioctl_update_queue_args *args = data; 515 struct queue_properties properties; 516 517 /* 518 * Repurpose queue percentage to accommodate new features: 519 * bit 0-7: queue percentage 520 * bit 8-15: pm4_target_xcc 521 */ 522 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) { 523 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 524 return -EINVAL; 525 } 526 527 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 528 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 529 return -EINVAL; 530 } 531 532 if ((args->ring_base_address) && 533 (!access_ok((const void __user *) args->ring_base_address, 534 sizeof(uint64_t)))) { 535 pr_err("Can't access ring base address\n"); 536 return -EFAULT; 537 } 538 539 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 540 pr_err("Ring size must be a power of 2 or 0\n"); 541 return -EINVAL; 542 } 543 544 if (args->ring_size < KFD_MIN_QUEUE_RING_SIZE) { 545 args->ring_size = KFD_MIN_QUEUE_RING_SIZE; 546 pr_debug("Size lower. clamped to KFD_MIN_QUEUE_RING_SIZE"); 547 } 548 549 properties.queue_address = args->ring_base_address; 550 properties.queue_size = args->ring_size; 551 properties.queue_percent = args->queue_percentage & 0xFF; 552 /* bit 8-15 are repurposed to be PM4 target XCC */ 553 properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF; 554 properties.priority = args->queue_priority; 555 556 pr_debug("Updating queue id %d for process pid %d\n", 557 args->queue_id, p->lead_thread->pid); 558 559 mutex_lock(&p->mutex); 560 561 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties); 562 563 mutex_unlock(&p->mutex); 564 565 return retval; 566 } 567 568 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, 569 void *data) 570 { 571 int retval; 572 const int max_num_cus = 1024; 573 struct kfd_ioctl_set_cu_mask_args *args = data; 574 struct mqd_update_info minfo = {0}; 575 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr; 576 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32); 577 578 if ((args->num_cu_mask % 32) != 0) { 579 pr_debug("num_cu_mask 0x%x must be a multiple of 32", 580 args->num_cu_mask); 581 return -EINVAL; 582 } 583 584 minfo.cu_mask.count = args->num_cu_mask; 585 if (minfo.cu_mask.count == 0) { 586 pr_debug("CU mask cannot be 0"); 587 return -EINVAL; 588 } 589 590 /* To prevent an unreasonably large CU mask size, set an arbitrary 591 * limit of max_num_cus bits. We can then just drop any CU mask bits 592 * past max_num_cus bits and just use the first max_num_cus bits. 593 */ 594 if (minfo.cu_mask.count > max_num_cus) { 595 pr_debug("CU mask cannot be greater than 1024 bits"); 596 minfo.cu_mask.count = max_num_cus; 597 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32); 598 } 599 600 minfo.cu_mask.ptr = memdup_user(cu_mask_ptr, cu_mask_size); 601 if (IS_ERR(minfo.cu_mask.ptr)) { 602 pr_debug("Could not copy CU mask from userspace"); 603 return PTR_ERR(minfo.cu_mask.ptr); 604 } 605 606 mutex_lock(&p->mutex); 607 608 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo); 609 610 mutex_unlock(&p->mutex); 611 612 kfree(minfo.cu_mask.ptr); 613 return retval; 614 } 615 616 static int kfd_ioctl_get_queue_wave_state(struct file *filep, 617 struct kfd_process *p, void *data) 618 { 619 struct kfd_ioctl_get_queue_wave_state_args *args = data; 620 int r; 621 622 mutex_lock(&p->mutex); 623 624 r = pqm_get_wave_state(&p->pqm, args->queue_id, 625 (void __user *)args->ctl_stack_address, 626 &args->ctl_stack_used_size, 627 &args->save_area_used_size); 628 629 mutex_unlock(&p->mutex); 630 631 return r; 632 } 633 634 static int kfd_ioctl_set_memory_policy(struct file *filep, 635 struct kfd_process *p, void *data) 636 { 637 struct kfd_ioctl_set_memory_policy_args *args = data; 638 int err = 0; 639 struct kfd_process_device *pdd; 640 enum cache_policy default_policy, alternate_policy; 641 642 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT 643 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 644 return -EINVAL; 645 } 646 647 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT 648 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 649 return -EINVAL; 650 } 651 652 mutex_lock(&p->mutex); 653 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 654 if (!pdd) { 655 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 656 err = -EINVAL; 657 goto err_pdd; 658 } 659 660 pdd = kfd_bind_process_to_device(pdd->dev, p); 661 if (IS_ERR(pdd)) { 662 err = -ESRCH; 663 goto out; 664 } 665 666 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT) 667 ? cache_policy_coherent : cache_policy_noncoherent; 668 669 alternate_policy = 670 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT) 671 ? cache_policy_coherent : cache_policy_noncoherent; 672 673 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm, 674 &pdd->qpd, 675 default_policy, 676 alternate_policy, 677 (void __user *)args->alternate_aperture_base, 678 args->alternate_aperture_size, 679 args->misc_process_flag)) 680 err = -EINVAL; 681 682 out: 683 err_pdd: 684 mutex_unlock(&p->mutex); 685 686 return err; 687 } 688 689 static int kfd_ioctl_set_trap_handler(struct file *filep, 690 struct kfd_process *p, void *data) 691 { 692 struct kfd_ioctl_set_trap_handler_args *args = data; 693 int err = 0; 694 struct kfd_process_device *pdd; 695 696 mutex_lock(&p->mutex); 697 698 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 699 if (!pdd) { 700 err = -EINVAL; 701 goto err_pdd; 702 } 703 704 pdd = kfd_bind_process_to_device(pdd->dev, p); 705 if (IS_ERR(pdd)) { 706 err = -ESRCH; 707 goto out; 708 } 709 710 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr); 711 712 out: 713 err_pdd: 714 mutex_unlock(&p->mutex); 715 716 return err; 717 } 718 719 static int kfd_ioctl_dbg_register(struct file *filep, 720 struct kfd_process *p, void *data) 721 { 722 return -EPERM; 723 } 724 725 static int kfd_ioctl_dbg_unregister(struct file *filep, 726 struct kfd_process *p, void *data) 727 { 728 return -EPERM; 729 } 730 731 static int kfd_ioctl_dbg_address_watch(struct file *filep, 732 struct kfd_process *p, void *data) 733 { 734 return -EPERM; 735 } 736 737 /* Parse and generate fixed size data structure for wave control */ 738 static int kfd_ioctl_dbg_wave_control(struct file *filep, 739 struct kfd_process *p, void *data) 740 { 741 return -EPERM; 742 } 743 744 static int kfd_ioctl_get_clock_counters(struct file *filep, 745 struct kfd_process *p, void *data) 746 { 747 struct kfd_ioctl_get_clock_counters_args *args = data; 748 struct kfd_process_device *pdd; 749 750 mutex_lock(&p->mutex); 751 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 752 mutex_unlock(&p->mutex); 753 if (pdd) 754 /* Reading GPU clock counter from KGD */ 755 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev); 756 else 757 /* Node without GPU resource */ 758 args->gpu_clock_counter = 0; 759 760 /* No access to rdtsc. Using raw monotonic time */ 761 args->cpu_clock_counter = ktime_get_raw_ns(); 762 args->system_clock_counter = ktime_get_boottime_ns(); 763 764 /* Since the counter is in nano-seconds we use 1GHz frequency */ 765 args->system_clock_freq = 1000000000; 766 767 return 0; 768 } 769 770 771 static int kfd_ioctl_get_process_apertures(struct file *filp, 772 struct kfd_process *p, void *data) 773 { 774 struct kfd_ioctl_get_process_apertures_args *args = data; 775 struct kfd_process_device_apertures *pAperture; 776 int i; 777 778 dev_dbg(kfd_device, "get apertures for process pid %d", p->lead_thread->pid); 779 780 args->num_of_nodes = 0; 781 782 mutex_lock(&p->mutex); 783 /* Run over all pdd of the process */ 784 for (i = 0; i < p->n_pdds; i++) { 785 struct kfd_process_device *pdd = p->pdds[i]; 786 787 pAperture = 788 &args->process_apertures[args->num_of_nodes]; 789 pAperture->gpu_id = pdd->dev->id; 790 pAperture->lds_base = pdd->lds_base; 791 pAperture->lds_limit = pdd->lds_limit; 792 pAperture->gpuvm_base = pdd->gpuvm_base; 793 pAperture->gpuvm_limit = pdd->gpuvm_limit; 794 pAperture->scratch_base = pdd->scratch_base; 795 pAperture->scratch_limit = pdd->scratch_limit; 796 797 dev_dbg(kfd_device, 798 "node id %u\n", args->num_of_nodes); 799 dev_dbg(kfd_device, 800 "gpu id %u\n", pdd->dev->id); 801 dev_dbg(kfd_device, 802 "lds_base %llX\n", pdd->lds_base); 803 dev_dbg(kfd_device, 804 "lds_limit %llX\n", pdd->lds_limit); 805 dev_dbg(kfd_device, 806 "gpuvm_base %llX\n", pdd->gpuvm_base); 807 dev_dbg(kfd_device, 808 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 809 dev_dbg(kfd_device, 810 "scratch_base %llX\n", pdd->scratch_base); 811 dev_dbg(kfd_device, 812 "scratch_limit %llX\n", pdd->scratch_limit); 813 814 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS) 815 break; 816 } 817 mutex_unlock(&p->mutex); 818 819 return 0; 820 } 821 822 static int kfd_ioctl_get_process_apertures_new(struct file *filp, 823 struct kfd_process *p, void *data) 824 { 825 struct kfd_ioctl_get_process_apertures_new_args *args = data; 826 struct kfd_process_device_apertures *pa; 827 int ret; 828 int i; 829 830 dev_dbg(kfd_device, "get apertures for process pid %d", 831 p->lead_thread->pid); 832 833 if (args->num_of_nodes == 0) { 834 /* Return number of nodes, so that user space can alloacate 835 * sufficient memory 836 */ 837 mutex_lock(&p->mutex); 838 args->num_of_nodes = p->n_pdds; 839 goto out_unlock; 840 } 841 842 if (args->num_of_nodes > kfd_topology_get_num_devices()) 843 return -EINVAL; 844 845 /* Fill in process-aperture information for all available 846 * nodes, but not more than args->num_of_nodes as that is 847 * the amount of memory allocated by user 848 */ 849 pa = kzalloc_objs(struct kfd_process_device_apertures, 850 args->num_of_nodes); 851 if (!pa) 852 return -ENOMEM; 853 854 mutex_lock(&p->mutex); 855 856 if (!p->n_pdds) { 857 args->num_of_nodes = 0; 858 kfree(pa); 859 goto out_unlock; 860 } 861 862 /* Run over all pdd of the process */ 863 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) { 864 struct kfd_process_device *pdd = p->pdds[i]; 865 866 pa[i].gpu_id = pdd->dev->id; 867 pa[i].lds_base = pdd->lds_base; 868 pa[i].lds_limit = pdd->lds_limit; 869 pa[i].gpuvm_base = pdd->gpuvm_base; 870 pa[i].gpuvm_limit = pdd->gpuvm_limit; 871 pa[i].scratch_base = pdd->scratch_base; 872 pa[i].scratch_limit = pdd->scratch_limit; 873 874 dev_dbg(kfd_device, 875 "gpu id %u\n", pdd->dev->id); 876 dev_dbg(kfd_device, 877 "lds_base %llX\n", pdd->lds_base); 878 dev_dbg(kfd_device, 879 "lds_limit %llX\n", pdd->lds_limit); 880 dev_dbg(kfd_device, 881 "gpuvm_base %llX\n", pdd->gpuvm_base); 882 dev_dbg(kfd_device, 883 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 884 dev_dbg(kfd_device, 885 "scratch_base %llX\n", pdd->scratch_base); 886 dev_dbg(kfd_device, 887 "scratch_limit %llX\n", pdd->scratch_limit); 888 } 889 mutex_unlock(&p->mutex); 890 891 args->num_of_nodes = i; 892 ret = copy_to_user( 893 (void __user *)args->kfd_process_device_apertures_ptr, 894 pa, 895 (i * sizeof(struct kfd_process_device_apertures))); 896 kfree(pa); 897 return ret ? -EFAULT : 0; 898 899 out_unlock: 900 mutex_unlock(&p->mutex); 901 return 0; 902 } 903 904 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, 905 void *data) 906 { 907 struct kfd_ioctl_create_event_args *args = data; 908 int err; 909 910 /* For dGPUs the event page is allocated in user mode. The 911 * handle is passed to KFD with the first call to this IOCTL 912 * through the event_page_offset field. 913 */ 914 if (args->event_page_offset) { 915 mutex_lock(&p->mutex); 916 err = kfd_kmap_event_page(p, args->event_page_offset); 917 mutex_unlock(&p->mutex); 918 if (err) 919 return err; 920 } 921 922 err = kfd_event_create(filp, p, args->event_type, 923 args->auto_reset != 0, args->node_id, 924 &args->event_id, &args->event_trigger_data, 925 &args->event_page_offset, 926 &args->event_slot_index); 927 928 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__); 929 return err; 930 } 931 932 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p, 933 void *data) 934 { 935 struct kfd_ioctl_destroy_event_args *args = data; 936 937 return kfd_event_destroy(p, args->event_id); 938 } 939 940 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p, 941 void *data) 942 { 943 struct kfd_ioctl_set_event_args *args = data; 944 945 return kfd_set_event(p, args->event_id); 946 } 947 948 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p, 949 void *data) 950 { 951 struct kfd_ioctl_reset_event_args *args = data; 952 953 return kfd_reset_event(p, args->event_id); 954 } 955 956 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, 957 void *data) 958 { 959 struct kfd_ioctl_wait_events_args *args = data; 960 961 return kfd_wait_on_events(p, args->num_events, 962 (void __user *)args->events_ptr, 963 (args->wait_for_all != 0), 964 &args->timeout, &args->wait_result); 965 } 966 static int kfd_ioctl_set_scratch_backing_va(struct file *filep, 967 struct kfd_process *p, void *data) 968 { 969 struct kfd_ioctl_set_scratch_backing_va_args *args = data; 970 struct kfd_process_device *pdd; 971 struct kfd_node *dev; 972 long err; 973 974 mutex_lock(&p->mutex); 975 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 976 if (!pdd) { 977 err = -EINVAL; 978 goto err_pdd; 979 } 980 dev = pdd->dev; 981 982 pdd = kfd_bind_process_to_device(dev, p); 983 if (IS_ERR(pdd)) { 984 err = PTR_ERR(pdd); 985 goto bind_process_to_device_fail; 986 } 987 988 pdd->qpd.sh_hidden_private_base = args->va_addr; 989 990 mutex_unlock(&p->mutex); 991 992 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS && 993 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va) 994 dev->kfd2kgd->set_scratch_backing_va( 995 dev->adev, args->va_addr, pdd->qpd.vmid); 996 997 return 0; 998 999 bind_process_to_device_fail: 1000 err_pdd: 1001 mutex_unlock(&p->mutex); 1002 return err; 1003 } 1004 1005 static int kfd_ioctl_get_tile_config(struct file *filep, 1006 struct kfd_process *p, void *data) 1007 { 1008 struct kfd_ioctl_get_tile_config_args *args = data; 1009 struct kfd_process_device *pdd; 1010 struct tile_config config; 1011 int err = 0; 1012 1013 mutex_lock(&p->mutex); 1014 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1015 mutex_unlock(&p->mutex); 1016 if (!pdd) 1017 return -EINVAL; 1018 1019 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config); 1020 1021 args->gb_addr_config = config.gb_addr_config; 1022 args->num_banks = config.num_banks; 1023 args->num_ranks = config.num_ranks; 1024 1025 if (args->num_tile_configs > config.num_tile_configs) 1026 args->num_tile_configs = config.num_tile_configs; 1027 err = copy_to_user((void __user *)args->tile_config_ptr, 1028 config.tile_config_ptr, 1029 args->num_tile_configs * sizeof(uint32_t)); 1030 if (err) { 1031 args->num_tile_configs = 0; 1032 return -EFAULT; 1033 } 1034 1035 if (args->num_macro_tile_configs > config.num_macro_tile_configs) 1036 args->num_macro_tile_configs = 1037 config.num_macro_tile_configs; 1038 err = copy_to_user((void __user *)args->macro_tile_config_ptr, 1039 config.macro_tile_config_ptr, 1040 args->num_macro_tile_configs * sizeof(uint32_t)); 1041 if (err) { 1042 args->num_macro_tile_configs = 0; 1043 return -EFAULT; 1044 } 1045 1046 return 0; 1047 } 1048 1049 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p, 1050 void *data) 1051 { 1052 struct kfd_ioctl_acquire_vm_args *args = data; 1053 struct kfd_process_device *pdd; 1054 struct file *drm_file; 1055 int ret; 1056 1057 drm_file = fget(args->drm_fd); 1058 if (!drm_file) 1059 return -EINVAL; 1060 1061 mutex_lock(&p->mutex); 1062 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1063 if (!pdd) { 1064 ret = -EINVAL; 1065 goto err_pdd; 1066 } 1067 1068 if (pdd->drm_file) { 1069 ret = pdd->drm_file == drm_file ? 0 : -EBUSY; 1070 goto err_drm_file; 1071 } 1072 1073 ret = kfd_process_device_init_vm(pdd, drm_file); 1074 if (ret) 1075 goto err_unlock; 1076 1077 /* On success, the PDD keeps the drm_file reference */ 1078 mutex_unlock(&p->mutex); 1079 1080 return 0; 1081 1082 err_unlock: 1083 err_pdd: 1084 err_drm_file: 1085 mutex_unlock(&p->mutex); 1086 fput(drm_file); 1087 return ret; 1088 } 1089 1090 bool kfd_dev_is_large_bar(struct kfd_node *dev) 1091 { 1092 if (dev->kfd->adev->debug_largebar) { 1093 pr_debug("Simulate large-bar allocation on non large-bar machine\n"); 1094 return true; 1095 } 1096 1097 if (dev->local_mem_info.local_mem_size_private == 0 && 1098 dev->local_mem_info.local_mem_size_public > 0) 1099 return true; 1100 1101 if (dev->local_mem_info.local_mem_size_public == 0 && 1102 dev->kfd->adev->gmc.is_app_apu) { 1103 pr_debug("APP APU, Consider like a large bar system\n"); 1104 return true; 1105 } 1106 1107 return false; 1108 } 1109 1110 static int kfd_ioctl_get_available_memory(struct file *filep, 1111 struct kfd_process *p, void *data) 1112 { 1113 struct kfd_ioctl_get_available_memory_args *args = data; 1114 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id); 1115 1116 if (!pdd) 1117 return -EINVAL; 1118 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev, 1119 pdd->dev->node_id); 1120 kfd_unlock_pdd(pdd); 1121 return 0; 1122 } 1123 1124 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, 1125 struct kfd_process *p, void *data) 1126 { 1127 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data; 1128 struct kfd_process_device *pdd; 1129 void *mem; 1130 struct kfd_node *dev; 1131 int idr_handle; 1132 long err; 1133 uint64_t offset = args->mmap_offset; 1134 uint32_t flags = args->flags; 1135 1136 if (args->size == 0) 1137 return -EINVAL; 1138 1139 if (p->context_id != KFD_CONTEXT_ID_PRIMARY && (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)) { 1140 pr_debug("USERPTR is not supported on non-primary kfd_process\n"); 1141 1142 return -EOPNOTSUPP; 1143 } 1144 1145 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1146 /* Flush pending deferred work to avoid racing with deferred actions 1147 * from previous memory map changes (e.g. munmap). 1148 */ 1149 svm_range_list_lock_and_flush_work(&p->svms, current->mm); 1150 mutex_lock(&p->svms.lock); 1151 mmap_write_unlock(current->mm); 1152 1153 /* Skip a special case that allocates VRAM without VA, 1154 * VA will be invalid of 0. 1155 */ 1156 if (!(!args->va_addr && (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)) && 1157 interval_tree_iter_first(&p->svms.objects, 1158 args->va_addr >> PAGE_SHIFT, 1159 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) { 1160 pr_err("Address: 0x%llx already allocated by SVM\n", 1161 args->va_addr); 1162 mutex_unlock(&p->svms.lock); 1163 return -EADDRINUSE; 1164 } 1165 1166 /* When register user buffer check if it has been registered by svm by 1167 * buffer cpu virtual address. 1168 */ 1169 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) && 1170 interval_tree_iter_first(&p->svms.objects, 1171 args->mmap_offset >> PAGE_SHIFT, 1172 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) { 1173 pr_err("User Buffer Address: 0x%llx already allocated by SVM\n", 1174 args->mmap_offset); 1175 mutex_unlock(&p->svms.lock); 1176 return -EADDRINUSE; 1177 } 1178 1179 mutex_unlock(&p->svms.lock); 1180 #endif 1181 mutex_lock(&p->mutex); 1182 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1183 if (!pdd) { 1184 err = -EINVAL; 1185 goto err_pdd; 1186 } 1187 1188 dev = pdd->dev; 1189 1190 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) && 1191 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && 1192 !kfd_dev_is_large_bar(dev)) { 1193 pr_err("Alloc host visible vram on small bar is not allowed\n"); 1194 err = -EINVAL; 1195 goto err_large_bar; 1196 } 1197 1198 pdd = kfd_bind_process_to_device(dev, p); 1199 if (IS_ERR(pdd)) { 1200 err = PTR_ERR(pdd); 1201 goto err_unlock; 1202 } 1203 1204 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 1205 if (args->size != kfd_doorbell_process_slice(dev->kfd)) { 1206 err = -EINVAL; 1207 goto err_unlock; 1208 } 1209 offset = kfd_get_process_doorbells(pdd); 1210 if (!offset) { 1211 err = -ENOMEM; 1212 goto err_unlock; 1213 } 1214 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 1215 if (args->size != PAGE_SIZE) { 1216 err = -EINVAL; 1217 goto err_unlock; 1218 } 1219 offset = dev->adev->rmmio_remap.bus_addr; 1220 if (!offset || (PAGE_SIZE > 4096)) { 1221 err = -ENOMEM; 1222 goto err_unlock; 1223 } 1224 } 1225 1226 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 1227 dev->adev, args->va_addr, args->size, 1228 pdd->drm_priv, (struct kgd_mem **) &mem, &offset, 1229 flags, false); 1230 1231 if (err) 1232 goto err_unlock; 1233 1234 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1235 if (idr_handle < 0) { 1236 err = -EFAULT; 1237 goto err_free; 1238 } 1239 1240 /* Update the VRAM usage count */ 1241 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 1242 uint64_t size = args->size; 1243 1244 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM) 1245 size >>= 1; 1246 size = PAGE_ALIGN(size); 1247 atomic64_add(size, &pdd->vram_usage); 1248 } 1249 1250 mutex_unlock(&p->mutex); 1251 1252 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1253 args->mmap_offset = offset; 1254 1255 /* MMIO is mapped through kfd device 1256 * Generate a kfd mmap offset 1257 */ 1258 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1259 args->mmap_offset = KFD_MMAP_TYPE_MMIO 1260 | KFD_MMAP_GPU_ID(args->gpu_id); 1261 1262 return 0; 1263 1264 err_free: 1265 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, 1266 pdd->drm_priv, NULL); 1267 err_unlock: 1268 err_pdd: 1269 err_large_bar: 1270 mutex_unlock(&p->mutex); 1271 return err; 1272 } 1273 1274 static int kfd_ioctl_free_memory_of_gpu(struct file *filep, 1275 struct kfd_process *p, void *data) 1276 { 1277 struct kfd_ioctl_free_memory_of_gpu_args *args = data; 1278 struct kfd_process_device *pdd; 1279 void *mem; 1280 int ret; 1281 uint64_t size = 0; 1282 1283 mutex_lock(&p->mutex); 1284 /* 1285 * Safeguard to prevent user space from freeing signal BO. 1286 * It will be freed at process termination. 1287 */ 1288 if (p->signal_handle && (p->signal_handle == args->handle)) { 1289 pr_err("Free signal BO is not allowed\n"); 1290 ret = -EPERM; 1291 goto err_unlock; 1292 } 1293 1294 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1295 if (!pdd) { 1296 pr_err("Process device data doesn't exist\n"); 1297 ret = -EINVAL; 1298 goto err_pdd; 1299 } 1300 1301 mem = kfd_process_device_translate_handle( 1302 pdd, GET_IDR_HANDLE(args->handle)); 1303 if (!mem) { 1304 ret = -EINVAL; 1305 goto err_unlock; 1306 } 1307 1308 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, 1309 (struct kgd_mem *)mem, pdd->drm_priv, &size); 1310 1311 /* If freeing the buffer failed, leave the handle in place for 1312 * clean-up during process tear-down. 1313 */ 1314 if (!ret) 1315 kfd_process_device_remove_obj_handle( 1316 pdd, GET_IDR_HANDLE(args->handle)); 1317 1318 atomic64_sub(size, &pdd->vram_usage); 1319 1320 err_unlock: 1321 err_pdd: 1322 mutex_unlock(&p->mutex); 1323 return ret; 1324 } 1325 1326 static int kfd_ioctl_map_memory_to_gpu(struct file *filep, 1327 struct kfd_process *p, void *data) 1328 { 1329 struct kfd_ioctl_map_memory_to_gpu_args *args = data; 1330 struct kfd_process_device *pdd, *peer_pdd; 1331 void *mem; 1332 struct kfd_node *dev; 1333 long err = 0; 1334 int i; 1335 uint32_t *devices_arr = NULL; 1336 1337 if (!args->n_devices) { 1338 pr_debug("Device IDs array empty\n"); 1339 return -EINVAL; 1340 } 1341 if (args->n_success > args->n_devices) { 1342 pr_debug("n_success exceeds n_devices\n"); 1343 return -EINVAL; 1344 } 1345 1346 devices_arr = memdup_array_user((void *)args->device_ids_array_ptr, 1347 args->n_devices, sizeof(*devices_arr)); 1348 1349 if (IS_ERR(devices_arr)) 1350 return PTR_ERR(devices_arr); 1351 1352 mutex_lock(&p->mutex); 1353 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1354 if (!pdd) { 1355 err = -EINVAL; 1356 goto get_process_device_data_failed; 1357 } 1358 dev = pdd->dev; 1359 1360 pdd = kfd_bind_process_to_device(dev, p); 1361 if (IS_ERR(pdd)) { 1362 err = PTR_ERR(pdd); 1363 goto bind_process_to_device_failed; 1364 } 1365 1366 mem = kfd_process_device_translate_handle(pdd, 1367 GET_IDR_HANDLE(args->handle)); 1368 if (!mem) { 1369 err = -ENOMEM; 1370 goto get_mem_obj_from_handle_failed; 1371 } 1372 1373 for (i = args->n_success; i < args->n_devices; i++) { 1374 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1375 if (!peer_pdd) { 1376 pr_debug("Getting device by id failed for 0x%x\n", 1377 devices_arr[i]); 1378 err = -EINVAL; 1379 goto get_mem_obj_from_handle_failed; 1380 } 1381 1382 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p); 1383 if (IS_ERR(peer_pdd)) { 1384 err = PTR_ERR(peer_pdd); 1385 goto get_mem_obj_from_handle_failed; 1386 } 1387 1388 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 1389 peer_pdd->dev->adev, (struct kgd_mem *)mem, 1390 peer_pdd->drm_priv); 1391 if (err) { 1392 struct pci_dev *pdev = peer_pdd->dev->adev->pdev; 1393 1394 dev_err(dev->adev->dev, 1395 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n", 1396 pci_domain_nr(pdev->bus), 1397 pdev->bus->number, 1398 PCI_SLOT(pdev->devfn), 1399 PCI_FUNC(pdev->devfn), 1400 ((struct kgd_mem *)mem)->domain); 1401 goto map_memory_to_gpu_failed; 1402 } 1403 args->n_success = i+1; 1404 } 1405 1406 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true); 1407 if (err) { 1408 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1409 goto sync_memory_failed; 1410 } 1411 1412 mutex_unlock(&p->mutex); 1413 1414 /* Flush TLBs after waiting for the page table updates to complete */ 1415 for (i = 0; i < args->n_devices; i++) { 1416 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1417 if (WARN_ON_ONCE(!peer_pdd)) 1418 continue; 1419 kfd_flush_tlb(peer_pdd); 1420 } 1421 kfree(devices_arr); 1422 1423 return err; 1424 1425 get_process_device_data_failed: 1426 bind_process_to_device_failed: 1427 get_mem_obj_from_handle_failed: 1428 map_memory_to_gpu_failed: 1429 sync_memory_failed: 1430 mutex_unlock(&p->mutex); 1431 kfree(devices_arr); 1432 1433 return err; 1434 } 1435 1436 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, 1437 struct kfd_process *p, void *data) 1438 { 1439 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data; 1440 struct kfd_process_device *pdd, *peer_pdd; 1441 void *mem; 1442 long err = 0; 1443 uint32_t *devices_arr = NULL, i; 1444 bool flush_tlb; 1445 1446 if (!args->n_devices) { 1447 pr_debug("Device IDs array empty\n"); 1448 return -EINVAL; 1449 } 1450 if (args->n_success > args->n_devices) { 1451 pr_debug("n_success exceeds n_devices\n"); 1452 return -EINVAL; 1453 } 1454 1455 devices_arr = memdup_array_user((void *)args->device_ids_array_ptr, 1456 args->n_devices, sizeof(*devices_arr)); 1457 1458 if (IS_ERR(devices_arr)) 1459 return PTR_ERR(devices_arr); 1460 1461 mutex_lock(&p->mutex); 1462 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1463 if (!pdd) { 1464 err = -EINVAL; 1465 goto bind_process_to_device_failed; 1466 } 1467 1468 mem = kfd_process_device_translate_handle(pdd, 1469 GET_IDR_HANDLE(args->handle)); 1470 if (!mem) { 1471 err = -ENOMEM; 1472 goto get_mem_obj_from_handle_failed; 1473 } 1474 1475 for (i = args->n_success; i < args->n_devices; i++) { 1476 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1477 if (!peer_pdd) { 1478 err = -EINVAL; 1479 goto get_mem_obj_from_handle_failed; 1480 } 1481 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 1482 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv); 1483 if (err) { 1484 pr_debug("Failed to unmap from gpu %d/%d\n", i, args->n_devices); 1485 goto unmap_memory_from_gpu_failed; 1486 } 1487 args->n_success = i+1; 1488 } 1489 1490 flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev->kfd); 1491 if (flush_tlb) { 1492 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev, 1493 (struct kgd_mem *) mem, true); 1494 if (err) { 1495 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1496 goto sync_memory_failed; 1497 } 1498 } 1499 1500 /* Flush TLBs after waiting for the page table updates to complete */ 1501 for (i = 0; i < args->n_devices; i++) { 1502 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1503 if (WARN_ON_ONCE(!peer_pdd)) 1504 continue; 1505 if (flush_tlb) 1506 kfd_flush_tlb(peer_pdd); 1507 1508 /* Remove dma mapping after tlb flush to avoid IO_PAGE_FAULT */ 1509 err = amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv); 1510 if (err) 1511 goto sync_memory_failed; 1512 } 1513 1514 mutex_unlock(&p->mutex); 1515 1516 kfree(devices_arr); 1517 1518 return 0; 1519 1520 bind_process_to_device_failed: 1521 get_mem_obj_from_handle_failed: 1522 unmap_memory_from_gpu_failed: 1523 sync_memory_failed: 1524 mutex_unlock(&p->mutex); 1525 kfree(devices_arr); 1526 return err; 1527 } 1528 1529 static int kfd_ioctl_alloc_queue_gws(struct file *filep, 1530 struct kfd_process *p, void *data) 1531 { 1532 int retval; 1533 struct kfd_ioctl_alloc_queue_gws_args *args = data; 1534 struct queue *q; 1535 struct kfd_node *dev; 1536 1537 mutex_lock(&p->mutex); 1538 q = pqm_get_user_queue(&p->pqm, args->queue_id); 1539 1540 if (q) { 1541 dev = q->device; 1542 } else { 1543 retval = -EINVAL; 1544 goto out_unlock; 1545 } 1546 1547 if (!dev->gws) { 1548 retval = -ENODEV; 1549 goto out_unlock; 1550 } 1551 1552 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 1553 retval = -ENODEV; 1554 goto out_unlock; 1555 } 1556 1557 if (p->debug_trap_enabled && (!kfd_dbg_has_gws_support(dev) || 1558 kfd_dbg_has_cwsr_workaround(dev))) { 1559 retval = -EBUSY; 1560 goto out_unlock; 1561 } 1562 1563 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL); 1564 mutex_unlock(&p->mutex); 1565 1566 args->first_gws = 0; 1567 return retval; 1568 1569 out_unlock: 1570 mutex_unlock(&p->mutex); 1571 return retval; 1572 } 1573 1574 static int kfd_ioctl_get_dmabuf_info(struct file *filep, 1575 struct kfd_process *p, void *data) 1576 { 1577 struct kfd_ioctl_get_dmabuf_info_args *args = data; 1578 struct kfd_node *dev = NULL; 1579 struct amdgpu_device *dmabuf_adev; 1580 void *metadata_buffer = NULL; 1581 uint32_t flags; 1582 int8_t xcp_id; 1583 unsigned int i; 1584 int r; 1585 1586 /* Find a KFD GPU device that supports the get_dmabuf_info query */ 1587 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++) 1588 if (dev && !kfd_devcgroup_check_permission(dev)) 1589 break; 1590 if (!dev) 1591 return -EINVAL; 1592 1593 /* Get dmabuf info from KGD */ 1594 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd, 1595 &dmabuf_adev, &args->size, 1596 &metadata_buffer, args->metadata_size, 1597 &args->metadata_size, &flags, &xcp_id); 1598 if (r) 1599 goto exit; 1600 1601 if (xcp_id >= 0) 1602 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id; 1603 else 1604 args->gpu_id = dev->id; 1605 args->flags = flags; 1606 1607 /* Copy metadata buffer to user mode */ 1608 if (metadata_buffer && args->metadata_ptr) { 1609 r = copy_to_user((void __user *)args->metadata_ptr, 1610 metadata_buffer, args->metadata_size); 1611 if (r != 0) 1612 r = -EFAULT; 1613 } 1614 1615 exit: 1616 kfree(metadata_buffer); 1617 1618 return r; 1619 } 1620 1621 static int kfd_ioctl_import_dmabuf(struct file *filep, 1622 struct kfd_process *p, void *data) 1623 { 1624 struct kfd_ioctl_import_dmabuf_args *args = data; 1625 struct kfd_process_device *pdd; 1626 int idr_handle; 1627 uint64_t size; 1628 void *mem; 1629 int r; 1630 1631 mutex_lock(&p->mutex); 1632 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1633 if (!pdd) { 1634 r = -EINVAL; 1635 goto err_unlock; 1636 } 1637 1638 pdd = kfd_bind_process_to_device(pdd->dev, p); 1639 if (IS_ERR(pdd)) { 1640 r = PTR_ERR(pdd); 1641 goto err_unlock; 1642 } 1643 1644 r = amdgpu_amdkfd_gpuvm_import_dmabuf_fd(pdd->dev->adev, args->dmabuf_fd, 1645 args->va_addr, pdd->drm_priv, 1646 (struct kgd_mem **)&mem, &size, 1647 NULL); 1648 if (r) 1649 goto err_unlock; 1650 1651 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1652 if (idr_handle < 0) { 1653 r = -EFAULT; 1654 goto err_free; 1655 } 1656 1657 mutex_unlock(&p->mutex); 1658 1659 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1660 1661 return 0; 1662 1663 err_free: 1664 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, 1665 pdd->drm_priv, NULL); 1666 err_unlock: 1667 mutex_unlock(&p->mutex); 1668 return r; 1669 } 1670 1671 static int kfd_ioctl_export_dmabuf(struct file *filep, 1672 struct kfd_process *p, void *data) 1673 { 1674 struct kfd_ioctl_export_dmabuf_args *args = data; 1675 struct kfd_process_device *pdd; 1676 struct dma_buf *dmabuf; 1677 struct kfd_node *dev; 1678 void *mem; 1679 int ret = 0; 1680 1681 dev = kfd_device_by_id(GET_GPU_ID(args->handle)); 1682 if (!dev) 1683 return -EINVAL; 1684 1685 mutex_lock(&p->mutex); 1686 1687 pdd = kfd_get_process_device_data(dev, p); 1688 if (!pdd) { 1689 ret = -EINVAL; 1690 goto err_unlock; 1691 } 1692 1693 mem = kfd_process_device_translate_handle(pdd, 1694 GET_IDR_HANDLE(args->handle)); 1695 if (!mem) { 1696 ret = -EINVAL; 1697 goto err_unlock; 1698 } 1699 1700 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf); 1701 mutex_unlock(&p->mutex); 1702 if (ret) 1703 goto err_out; 1704 1705 ret = dma_buf_fd(dmabuf, args->flags); 1706 if (ret < 0) { 1707 dma_buf_put(dmabuf); 1708 goto err_out; 1709 } 1710 /* dma_buf_fd assigns the reference count to the fd, no need to 1711 * put the reference here. 1712 */ 1713 args->dmabuf_fd = ret; 1714 1715 return 0; 1716 1717 err_unlock: 1718 mutex_unlock(&p->mutex); 1719 err_out: 1720 return ret; 1721 } 1722 1723 /* Handle requests for watching SMI events */ 1724 static int kfd_ioctl_smi_events(struct file *filep, 1725 struct kfd_process *p, void *data) 1726 { 1727 struct kfd_ioctl_smi_events_args *args = data; 1728 struct kfd_process_device *pdd; 1729 1730 mutex_lock(&p->mutex); 1731 1732 pdd = kfd_process_device_data_by_id(p, args->gpuid); 1733 mutex_unlock(&p->mutex); 1734 if (!pdd) 1735 return -EINVAL; 1736 1737 return kfd_smi_event_open(pdd->dev, &args->anon_fd); 1738 } 1739 1740 static int kfd_ioctl_svm_validate(void *kdata, unsigned int usize) 1741 { 1742 struct kfd_ioctl_svm_args *args = kdata; 1743 size_t expected = struct_size(args, attrs, args->nattr); 1744 1745 if (expected == SIZE_MAX || usize < expected) 1746 return -EINVAL; 1747 return 0; 1748 } 1749 1750 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1751 1752 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1753 struct kfd_process *p, void *data) 1754 { 1755 struct kfd_ioctl_set_xnack_mode_args *args = data; 1756 int r = 0; 1757 1758 mutex_lock(&p->mutex); 1759 if (args->xnack_enabled >= 0) { 1760 if (!list_empty(&p->pqm.queues)) { 1761 pr_debug("Process has user queues running\n"); 1762 r = -EBUSY; 1763 goto out_unlock; 1764 } 1765 1766 if (p->xnack_enabled == args->xnack_enabled) 1767 goto out_unlock; 1768 1769 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) { 1770 r = -EPERM; 1771 goto out_unlock; 1772 } 1773 1774 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled); 1775 } else { 1776 args->xnack_enabled = p->xnack_enabled; 1777 } 1778 1779 out_unlock: 1780 mutex_unlock(&p->mutex); 1781 1782 return r; 1783 } 1784 1785 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1786 { 1787 struct kfd_ioctl_svm_args *args = data; 1788 int r = 0; 1789 1790 if (p->context_id != KFD_CONTEXT_ID_PRIMARY) { 1791 pr_debug("SVM ioctl not supported on non-primary kfd process\n"); 1792 1793 return -EOPNOTSUPP; 1794 } 1795 1796 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n", 1797 args->start_addr, args->size, args->op, args->nattr); 1798 1799 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK)) 1800 return -EINVAL; 1801 if (!args->start_addr || !args->size) 1802 return -EINVAL; 1803 1804 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr, 1805 args->attrs); 1806 1807 return r; 1808 } 1809 #else 1810 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1811 struct kfd_process *p, void *data) 1812 { 1813 return -EPERM; 1814 } 1815 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1816 { 1817 return -EPERM; 1818 } 1819 #endif 1820 1821 static int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) 1822 { 1823 struct amdgpu_device *adev = pdd->dev->adev; 1824 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1825 enum amdgpu_ptl_fmt pref_format1 = ptl->fmt1; 1826 enum amdgpu_ptl_fmt pref_format2 = ptl->fmt2; 1827 uint32_t ptl_state = enable ? 1 : 0; 1828 int ret; 1829 1830 if (ptl->hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) 1831 return -EOPNOTSUPP; 1832 1833 if (!pdd->dev->kfd2kgd || !pdd->dev->kfd2kgd->ptl_ctrl) 1834 return -EOPNOTSUPP; 1835 1836 ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, 1837 &ptl_state, 1838 &pref_format1, 1839 &pref_format2); 1840 1841 return ret; 1842 } 1843 1844 int kfd_ptl_disable_request(struct kfd_process_device *pdd, 1845 struct kfd_process *p) 1846 { 1847 struct amdgpu_device *adev = pdd->dev->adev; 1848 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1849 int ret = 0; 1850 1851 if (ptl->hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) 1852 return -EOPNOTSUPP; 1853 1854 mutex_lock(&ptl->mutex); 1855 1856 if (pdd->ptl_disable_req) 1857 goto out; 1858 1859 if (atomic_inc_return(&ptl->disable_ref) == 1) { 1860 ret = kfd_ptl_control(pdd, false); 1861 if (ret) { 1862 atomic_dec(&ptl->disable_ref); 1863 dev_warn(pdd->dev->adev->dev, 1864 "failed to disable PTL\n"); 1865 goto out; 1866 } 1867 } 1868 set_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap); 1869 pdd->ptl_disable_req = true; 1870 1871 out: 1872 mutex_unlock(&ptl->mutex); 1873 return ret; 1874 } 1875 1876 int kfd_ptl_disable_release(struct kfd_process_device *pdd, 1877 struct kfd_process *p) 1878 { 1879 struct amdgpu_device *adev = pdd->dev->adev; 1880 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1881 int ret = 0; 1882 1883 if (ptl->hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) 1884 return -EOPNOTSUPP; 1885 1886 mutex_lock(&ptl->mutex); 1887 1888 if (!pdd->ptl_disable_req) 1889 goto out; 1890 1891 if (atomic_dec_return(&ptl->disable_ref) == 0) { 1892 clear_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap); 1893 ret = kfd_ptl_control(pdd, true); 1894 if (ret) { 1895 atomic_inc(&ptl->disable_ref); 1896 set_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap); 1897 dev_warn(adev->dev, "Failed to enable PTL on release: %d\n", ret); 1898 goto out; 1899 } 1900 } 1901 pdd->ptl_disable_req = false; 1902 1903 out: 1904 mutex_unlock(&ptl->mutex); 1905 return ret; 1906 } 1907 1908 static int kfd_profiler_ptl_control(struct kfd_process *p, 1909 struct kfd_ioctl_ptl_control *args) 1910 { 1911 struct kfd_process_device *pdd; 1912 int ret; 1913 1914 mutex_lock(&p->mutex); 1915 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1916 mutex_unlock(&p->mutex); 1917 1918 if (!pdd || !pdd->dev || !pdd->dev->kfd) 1919 return -EINVAL; 1920 1921 if (args->enable == 0) 1922 ret = kfd_ptl_disable_request(pdd, p); 1923 else 1924 ret = kfd_ptl_disable_release(pdd, p); 1925 1926 return ret; 1927 } 1928 1929 static int criu_checkpoint_process(struct kfd_process *p, 1930 uint8_t __user *user_priv_data, 1931 uint64_t *priv_offset) 1932 { 1933 struct kfd_criu_process_priv_data process_priv; 1934 int ret; 1935 1936 memset(&process_priv, 0, sizeof(process_priv)); 1937 1938 process_priv.version = KFD_CRIU_PRIV_VERSION; 1939 /* For CR, we don't consider negative xnack mode which is used for 1940 * querying without changing it, here 0 simply means disabled and 1 1941 * means enabled so retry for finding a valid PTE. 1942 */ 1943 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0; 1944 1945 ret = copy_to_user(user_priv_data + *priv_offset, 1946 &process_priv, sizeof(process_priv)); 1947 1948 if (ret) { 1949 pr_err("Failed to copy process information to user\n"); 1950 ret = -EFAULT; 1951 } 1952 1953 *priv_offset += sizeof(process_priv); 1954 return ret; 1955 } 1956 1957 static int criu_checkpoint_devices(struct kfd_process *p, 1958 uint32_t num_devices, 1959 uint8_t __user *user_addr, 1960 uint8_t __user *user_priv_data, 1961 uint64_t *priv_offset) 1962 { 1963 struct kfd_criu_device_priv_data *device_priv = NULL; 1964 struct kfd_criu_device_bucket *device_buckets = NULL; 1965 int ret = 0, i; 1966 1967 device_buckets = kvzalloc_objs(*device_buckets, num_devices); 1968 if (!device_buckets) { 1969 ret = -ENOMEM; 1970 goto exit; 1971 } 1972 1973 device_priv = kvzalloc_objs(*device_priv, num_devices); 1974 if (!device_priv) { 1975 ret = -ENOMEM; 1976 goto exit; 1977 } 1978 1979 for (i = 0; i < num_devices; i++) { 1980 struct kfd_process_device *pdd = p->pdds[i]; 1981 1982 device_buckets[i].user_gpu_id = pdd->user_gpu_id; 1983 device_buckets[i].actual_gpu_id = pdd->dev->id; 1984 1985 /* 1986 * priv_data does not contain useful information for now and is reserved for 1987 * future use, so we do not set its contents. 1988 */ 1989 } 1990 1991 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets)); 1992 if (ret) { 1993 pr_err("Failed to copy device information to user\n"); 1994 ret = -EFAULT; 1995 goto exit; 1996 } 1997 1998 ret = copy_to_user(user_priv_data + *priv_offset, 1999 device_priv, 2000 num_devices * sizeof(*device_priv)); 2001 if (ret) { 2002 pr_err("Failed to copy device information to user\n"); 2003 ret = -EFAULT; 2004 } 2005 *priv_offset += num_devices * sizeof(*device_priv); 2006 2007 exit: 2008 kvfree(device_buckets); 2009 kvfree(device_priv); 2010 return ret; 2011 } 2012 2013 static uint32_t get_process_num_bos(struct kfd_process *p) 2014 { 2015 uint32_t num_of_bos = 0; 2016 int i; 2017 2018 /* Run over all PDDs of the process */ 2019 for (i = 0; i < p->n_pdds; i++) { 2020 struct kfd_process_device *pdd = p->pdds[i]; 2021 void *mem; 2022 int id; 2023 2024 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 2025 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; 2026 2027 if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base) 2028 num_of_bos++; 2029 } 2030 } 2031 return num_of_bos; 2032 } 2033 2034 static int criu_get_prime_handle(struct kgd_mem *mem, 2035 int flags, u32 *shared_fd, 2036 struct file **file) 2037 { 2038 struct dma_buf *dmabuf; 2039 int ret; 2040 2041 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf); 2042 if (ret) { 2043 pr_err("dmabuf export failed for the BO\n"); 2044 return ret; 2045 } 2046 2047 ret = get_unused_fd_flags(flags); 2048 if (ret < 0) { 2049 pr_err("dmabuf create fd failed, ret:%d\n", ret); 2050 goto out_free_dmabuf; 2051 } 2052 2053 *shared_fd = ret; 2054 *file = dmabuf->file; 2055 return 0; 2056 2057 out_free_dmabuf: 2058 dma_buf_put(dmabuf); 2059 return ret; 2060 } 2061 2062 static void commit_files(struct file **files, 2063 struct kfd_criu_bo_bucket *bo_buckets, 2064 unsigned int count, 2065 int err) 2066 { 2067 while (count--) { 2068 struct file *file = files[count]; 2069 2070 if (!file) 2071 continue; 2072 if (err) { 2073 fput(file); 2074 put_unused_fd(bo_buckets[count].dmabuf_fd); 2075 } else { 2076 fd_install(bo_buckets[count].dmabuf_fd, file); 2077 } 2078 } 2079 } 2080 2081 static int criu_checkpoint_bos(struct kfd_process *p, 2082 uint32_t num_bos, 2083 uint8_t __user *user_bos, 2084 uint8_t __user *user_priv_data, 2085 uint64_t *priv_offset) 2086 { 2087 struct kfd_criu_bo_bucket *bo_buckets; 2088 struct kfd_criu_bo_priv_data *bo_privs; 2089 struct file **files = NULL; 2090 int ret = 0, pdd_index, bo_index = 0, id; 2091 void *mem; 2092 2093 bo_buckets = kvzalloc_objs(*bo_buckets, num_bos); 2094 if (!bo_buckets) 2095 return -ENOMEM; 2096 2097 bo_privs = kvzalloc_objs(*bo_privs, num_bos); 2098 if (!bo_privs) { 2099 ret = -ENOMEM; 2100 goto exit; 2101 } 2102 2103 files = kvzalloc_objs(struct file *, num_bos); 2104 if (!files) { 2105 ret = -ENOMEM; 2106 goto exit; 2107 } 2108 2109 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 2110 struct kfd_process_device *pdd = p->pdds[pdd_index]; 2111 struct amdgpu_bo *dumper_bo; 2112 struct kgd_mem *kgd_mem; 2113 2114 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 2115 struct kfd_criu_bo_bucket *bo_bucket; 2116 struct kfd_criu_bo_priv_data *bo_priv; 2117 int i, dev_idx = 0; 2118 2119 kgd_mem = (struct kgd_mem *)mem; 2120 dumper_bo = kgd_mem->bo; 2121 2122 /* Skip checkpointing BOs that are used for Trap handler 2123 * code and state. Currently, these BOs have a VA that 2124 * is less GPUVM Base 2125 */ 2126 if (kgd_mem->va && kgd_mem->va <= pdd->gpuvm_base) 2127 continue; 2128 2129 bo_bucket = &bo_buckets[bo_index]; 2130 bo_priv = &bo_privs[bo_index]; 2131 2132 bo_bucket->gpu_id = pdd->user_gpu_id; 2133 bo_bucket->addr = (uint64_t)kgd_mem->va; 2134 bo_bucket->size = amdgpu_bo_size(dumper_bo); 2135 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags; 2136 bo_priv->idr_handle = id; 2137 2138 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 2139 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo, 2140 &bo_priv->user_addr); 2141 if (ret) { 2142 pr_err("Failed to obtain user address for user-pointer bo\n"); 2143 goto exit; 2144 } 2145 } 2146 if (bo_bucket->alloc_flags 2147 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 2148 ret = criu_get_prime_handle(kgd_mem, 2149 bo_bucket->alloc_flags & 2150 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0, 2151 &bo_bucket->dmabuf_fd, &files[bo_index]); 2152 if (ret) 2153 goto exit; 2154 } else { 2155 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 2156 } 2157 2158 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 2159 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL | 2160 KFD_MMAP_GPU_ID(pdd->dev->id); 2161 else if (bo_bucket->alloc_flags & 2162 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 2163 bo_bucket->offset = KFD_MMAP_TYPE_MMIO | 2164 KFD_MMAP_GPU_ID(pdd->dev->id); 2165 else 2166 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo); 2167 2168 for (i = 0; i < p->n_pdds; i++) { 2169 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->drm_priv, kgd_mem)) 2170 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id; 2171 } 2172 2173 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n" 2174 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x", 2175 bo_bucket->size, 2176 bo_bucket->addr, 2177 bo_bucket->offset, 2178 bo_bucket->gpu_id, 2179 bo_bucket->alloc_flags, 2180 bo_priv->idr_handle); 2181 bo_index++; 2182 } 2183 } 2184 2185 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets)); 2186 if (ret) { 2187 pr_err("Failed to copy BO information to user\n"); 2188 ret = -EFAULT; 2189 goto exit; 2190 } 2191 2192 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs)); 2193 if (ret) { 2194 pr_err("Failed to copy BO priv information to user\n"); 2195 ret = -EFAULT; 2196 goto exit; 2197 } 2198 2199 *priv_offset += num_bos * sizeof(*bo_privs); 2200 2201 exit: 2202 commit_files(files, bo_buckets, bo_index, ret); 2203 kvfree(files); 2204 kvfree(bo_buckets); 2205 kvfree(bo_privs); 2206 return ret; 2207 } 2208 2209 static int criu_get_process_object_info(struct kfd_process *p, 2210 uint32_t *num_devices, 2211 uint32_t *num_bos, 2212 uint32_t *num_objects, 2213 uint64_t *objs_priv_size) 2214 { 2215 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size; 2216 uint32_t num_queues, num_events, num_svm_ranges; 2217 int ret; 2218 2219 *num_devices = p->n_pdds; 2220 *num_bos = get_process_num_bos(p); 2221 2222 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size); 2223 if (ret) 2224 return ret; 2225 2226 num_events = kfd_get_num_events(p); 2227 2228 svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size); 2229 2230 *num_objects = num_queues + num_events + num_svm_ranges; 2231 2232 if (objs_priv_size) { 2233 priv_size = sizeof(struct kfd_criu_process_priv_data); 2234 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data); 2235 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data); 2236 priv_size += queues_priv_data_size; 2237 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data); 2238 priv_size += svm_priv_data_size; 2239 *objs_priv_size = priv_size; 2240 } 2241 return 0; 2242 } 2243 2244 static int criu_checkpoint(struct file *filep, 2245 struct kfd_process *p, 2246 struct kfd_ioctl_criu_args *args) 2247 { 2248 int ret; 2249 uint32_t num_devices, num_bos, num_objects; 2250 uint64_t priv_size, priv_offset = 0, bo_priv_offset; 2251 2252 if (!args->devices || !args->bos || !args->priv_data) 2253 return -EINVAL; 2254 2255 mutex_lock(&p->mutex); 2256 2257 if (!p->n_pdds) { 2258 pr_err("No pdd for given process\n"); 2259 ret = -ENODEV; 2260 goto exit_unlock; 2261 } 2262 2263 /* Confirm all process queues are evicted */ 2264 if (!p->queues_paused) { 2265 pr_err("Cannot dump process when queues are not in evicted state\n"); 2266 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */ 2267 ret = -EINVAL; 2268 goto exit_unlock; 2269 } 2270 2271 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size); 2272 if (ret) 2273 goto exit_unlock; 2274 2275 if (num_devices != args->num_devices || 2276 num_bos != args->num_bos || 2277 num_objects != args->num_objects || 2278 priv_size != args->priv_data_size) { 2279 2280 ret = -EINVAL; 2281 goto exit_unlock; 2282 } 2283 2284 /* each function will store private data inside priv_data and adjust priv_offset */ 2285 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset); 2286 if (ret) 2287 goto exit_unlock; 2288 2289 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices, 2290 (uint8_t __user *)args->priv_data, &priv_offset); 2291 if (ret) 2292 goto exit_unlock; 2293 2294 /* Leave room for BOs in the private data. They need to be restored 2295 * before events, but we checkpoint them last to simplify the error 2296 * handling. 2297 */ 2298 bo_priv_offset = priv_offset; 2299 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data); 2300 2301 if (num_objects) { 2302 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data, 2303 &priv_offset); 2304 if (ret) 2305 goto exit_unlock; 2306 2307 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data, 2308 &priv_offset); 2309 if (ret) 2310 goto exit_unlock; 2311 2312 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset); 2313 if (ret) 2314 goto exit_unlock; 2315 } 2316 2317 /* This must be the last thing in this function that can fail. 2318 * Otherwise we leak dmabuf file descriptors. 2319 */ 2320 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos, 2321 (uint8_t __user *)args->priv_data, &bo_priv_offset); 2322 2323 exit_unlock: 2324 mutex_unlock(&p->mutex); 2325 if (ret) 2326 pr_err("Failed to dump CRIU ret:%d\n", ret); 2327 else 2328 pr_debug("CRIU dump ret:%d\n", ret); 2329 2330 return ret; 2331 } 2332 2333 static int criu_restore_process(struct kfd_process *p, 2334 struct kfd_ioctl_criu_args *args, 2335 uint64_t *priv_offset, 2336 uint64_t max_priv_data_size) 2337 { 2338 int ret = 0; 2339 struct kfd_criu_process_priv_data process_priv; 2340 2341 if (*priv_offset + sizeof(process_priv) > max_priv_data_size) 2342 return -EINVAL; 2343 2344 ret = copy_from_user(&process_priv, 2345 (void __user *)(args->priv_data + *priv_offset), 2346 sizeof(process_priv)); 2347 if (ret) { 2348 pr_err("Failed to copy process private information from user\n"); 2349 ret = -EFAULT; 2350 goto exit; 2351 } 2352 *priv_offset += sizeof(process_priv); 2353 2354 if (process_priv.version != KFD_CRIU_PRIV_VERSION) { 2355 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n", 2356 process_priv.version, KFD_CRIU_PRIV_VERSION); 2357 return -EINVAL; 2358 } 2359 2360 pr_debug("Setting XNACK mode\n"); 2361 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) { 2362 pr_err("xnack mode cannot be set\n"); 2363 ret = -EPERM; 2364 goto exit; 2365 } else { 2366 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode); 2367 p->xnack_enabled = process_priv.xnack_mode; 2368 } 2369 2370 exit: 2371 return ret; 2372 } 2373 2374 static int criu_restore_devices(struct kfd_process *p, 2375 struct kfd_ioctl_criu_args *args, 2376 uint64_t *priv_offset, 2377 uint64_t max_priv_data_size) 2378 { 2379 struct kfd_criu_device_bucket *device_buckets; 2380 struct kfd_criu_device_priv_data *device_privs; 2381 int ret = 0; 2382 uint32_t i; 2383 2384 if (args->num_devices != p->n_pdds) 2385 return -EINVAL; 2386 2387 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size) 2388 return -EINVAL; 2389 2390 device_buckets = memdup_array_user((void *)args->devices, 2391 args->num_devices, sizeof(*device_buckets)); 2392 2393 if (IS_ERR(device_buckets)) 2394 return PTR_ERR(device_buckets); 2395 2396 for (i = 0; i < args->num_devices; i++) { 2397 struct kfd_node *dev; 2398 struct kfd_process_device *pdd; 2399 struct file *drm_file; 2400 2401 /* device private data is not currently used */ 2402 2403 if (!device_buckets[i].user_gpu_id) { 2404 pr_err("Invalid user gpu_id\n"); 2405 ret = -EINVAL; 2406 goto exit; 2407 } 2408 2409 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id); 2410 if (!dev) { 2411 pr_err("Failed to find device with gpu_id = %x\n", 2412 device_buckets[i].actual_gpu_id); 2413 ret = -EINVAL; 2414 goto exit; 2415 } 2416 2417 pdd = kfd_get_process_device_data(dev, p); 2418 if (!pdd) { 2419 pr_err("Failed to get pdd for gpu_id = %x\n", 2420 device_buckets[i].actual_gpu_id); 2421 ret = -EINVAL; 2422 goto exit; 2423 } 2424 2425 if (pdd->drm_file) { 2426 ret = -EINVAL; 2427 goto exit; 2428 } 2429 pdd->user_gpu_id = device_buckets[i].user_gpu_id; 2430 2431 drm_file = fget(device_buckets[i].drm_fd); 2432 if (!drm_file) { 2433 pr_err("Invalid render node file descriptor sent from plugin (%d)\n", 2434 device_buckets[i].drm_fd); 2435 ret = -EINVAL; 2436 goto exit; 2437 } 2438 2439 /* create the vm using render nodes for kfd pdd */ 2440 if (kfd_process_device_init_vm(pdd, drm_file)) { 2441 pr_err("could not init vm for given pdd\n"); 2442 /* On success, the PDD keeps the drm_file reference */ 2443 fput(drm_file); 2444 ret = -EINVAL; 2445 goto exit; 2446 } 2447 /* 2448 * pdd now already has the vm bound to render node so below api won't create a new 2449 * exclusive kfd mapping but use existing one with renderDXXX but is still needed 2450 * for iommu v2 binding and runtime pm. 2451 */ 2452 pdd = kfd_bind_process_to_device(dev, p); 2453 if (IS_ERR(pdd)) { 2454 ret = PTR_ERR(pdd); 2455 goto exit; 2456 } 2457 2458 if (!pdd->qpd.proc_doorbells) { 2459 ret = kfd_alloc_process_doorbells(dev->kfd, pdd); 2460 if (ret) 2461 goto exit; 2462 } 2463 } 2464 2465 /* 2466 * We are not copying device private data from user as we are not using the data for now, 2467 * but we still adjust for its private data. 2468 */ 2469 *priv_offset += args->num_devices * sizeof(*device_privs); 2470 2471 exit: 2472 kfree(device_buckets); 2473 return ret; 2474 } 2475 2476 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, 2477 struct kfd_criu_bo_bucket *bo_bucket, 2478 struct kfd_criu_bo_priv_data *bo_priv, 2479 struct kgd_mem **kgd_mem) 2480 { 2481 int idr_handle; 2482 int ret; 2483 const bool criu_resume = true; 2484 u64 offset; 2485 2486 if (bo_priv->idr_handle > INT_MAX) 2487 return -EINVAL; 2488 2489 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 2490 if (bo_bucket->size != 2491 kfd_doorbell_process_slice(pdd->dev->kfd)) 2492 return -EINVAL; 2493 2494 offset = kfd_get_process_doorbells(pdd); 2495 if (!offset) 2496 return -ENOMEM; 2497 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2498 /* MMIO BOs need remapped bus address */ 2499 if (bo_bucket->size != PAGE_SIZE) { 2500 pr_err("Invalid page size\n"); 2501 return -EINVAL; 2502 } 2503 offset = pdd->dev->adev->rmmio_remap.bus_addr; 2504 if (!offset || (PAGE_SIZE > 4096)) { 2505 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n"); 2506 return -ENOMEM; 2507 } 2508 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 2509 offset = bo_priv->user_addr; 2510 } 2511 /* Create the BO */ 2512 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr, 2513 bo_bucket->size, pdd->drm_priv, kgd_mem, 2514 &offset, bo_bucket->alloc_flags, criu_resume); 2515 if (ret) { 2516 pr_err("Could not create the BO\n"); 2517 return ret; 2518 } 2519 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n", 2520 bo_bucket->size, bo_bucket->addr, offset); 2521 2522 /* Restore previous IDR handle */ 2523 pr_debug("Restoring old IDR handle for the BO"); 2524 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle, 2525 bo_priv->idr_handle + 1, GFP_KERNEL); 2526 2527 if (idr_handle < 0) { 2528 pr_err("Could not allocate idr\n"); 2529 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, 2530 NULL); 2531 return -ENOMEM; 2532 } 2533 2534 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 2535 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id); 2536 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2537 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id); 2538 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 2539 bo_bucket->restored_offset = offset; 2540 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 2541 bo_bucket->restored_offset = offset; 2542 /* Update the VRAM usage count */ 2543 atomic64_add(bo_bucket->size, &pdd->vram_usage); 2544 } 2545 return 0; 2546 } 2547 2548 static int criu_restore_bo(struct kfd_process *p, 2549 struct kfd_criu_bo_bucket *bo_bucket, 2550 struct kfd_criu_bo_priv_data *bo_priv, 2551 struct file **file) 2552 { 2553 struct kfd_process_device *pdd; 2554 struct kgd_mem *kgd_mem; 2555 int ret; 2556 int j; 2557 2558 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n", 2559 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags, 2560 bo_priv->idr_handle); 2561 2562 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id); 2563 if (!pdd) { 2564 pr_err("Failed to get pdd\n"); 2565 return -ENODEV; 2566 } 2567 2568 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); 2569 if (ret) 2570 return ret; 2571 2572 /* now map these BOs to GPU/s */ 2573 for (j = 0; j < p->n_pdds; j++) { 2574 struct kfd_node *peer; 2575 struct kfd_process_device *peer_pdd; 2576 2577 if (!bo_priv->mapped_gpuids[j]) 2578 break; 2579 2580 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]); 2581 if (!peer_pdd) 2582 return -EINVAL; 2583 2584 peer = peer_pdd->dev; 2585 2586 peer_pdd = kfd_bind_process_to_device(peer, p); 2587 if (IS_ERR(peer_pdd)) 2588 return PTR_ERR(peer_pdd); 2589 2590 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem, 2591 peer_pdd->drm_priv); 2592 if (ret) { 2593 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds); 2594 return ret; 2595 } 2596 } 2597 2598 pr_debug("map memory was successful for the BO\n"); 2599 /* create the dmabuf object and export the bo */ 2600 if (bo_bucket->alloc_flags 2601 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 2602 ret = criu_get_prime_handle(kgd_mem, DRM_RDWR, 2603 &bo_bucket->dmabuf_fd, file); 2604 if (ret) 2605 return ret; 2606 } else { 2607 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 2608 } 2609 2610 return 0; 2611 } 2612 2613 static int criu_restore_bos(struct kfd_process *p, 2614 struct kfd_ioctl_criu_args *args, 2615 uint64_t *priv_offset, 2616 uint64_t max_priv_data_size) 2617 { 2618 struct kfd_criu_bo_bucket *bo_buckets = NULL; 2619 struct kfd_criu_bo_priv_data *bo_privs = NULL; 2620 struct file **files = NULL; 2621 int ret = 0; 2622 uint32_t i = 0; 2623 2624 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size) 2625 return -EINVAL; 2626 2627 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */ 2628 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info); 2629 2630 bo_buckets = kvmalloc_objs(*bo_buckets, args->num_bos); 2631 if (!bo_buckets) 2632 return -ENOMEM; 2633 2634 files = kvzalloc_objs(struct file *, args->num_bos); 2635 if (!files) { 2636 ret = -ENOMEM; 2637 goto exit; 2638 } 2639 2640 ret = copy_from_user(bo_buckets, (void __user *)args->bos, 2641 args->num_bos * sizeof(*bo_buckets)); 2642 if (ret) { 2643 pr_err("Failed to copy BOs information from user\n"); 2644 ret = -EFAULT; 2645 goto exit; 2646 } 2647 2648 bo_privs = kvmalloc_objs(*bo_privs, args->num_bos); 2649 if (!bo_privs) { 2650 ret = -ENOMEM; 2651 goto exit; 2652 } 2653 2654 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset, 2655 args->num_bos * sizeof(*bo_privs)); 2656 if (ret) { 2657 pr_err("Failed to copy BOs information from user\n"); 2658 ret = -EFAULT; 2659 goto exit; 2660 } 2661 *priv_offset += args->num_bos * sizeof(*bo_privs); 2662 2663 /* Create and map new BOs */ 2664 for (; i < args->num_bos; i++) { 2665 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i], &files[i]); 2666 if (ret) { 2667 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret); 2668 goto exit; 2669 } 2670 } /* done */ 2671 2672 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */ 2673 ret = copy_to_user((void __user *)args->bos, 2674 bo_buckets, 2675 (args->num_bos * sizeof(*bo_buckets))); 2676 if (ret) 2677 ret = -EFAULT; 2678 2679 exit: 2680 commit_files(files, bo_buckets, i, ret); 2681 kvfree(files); 2682 kvfree(bo_buckets); 2683 kvfree(bo_privs); 2684 return ret; 2685 } 2686 2687 static int criu_restore_objects(struct file *filep, 2688 struct kfd_process *p, 2689 struct kfd_ioctl_criu_args *args, 2690 uint64_t *priv_offset, 2691 uint64_t max_priv_data_size) 2692 { 2693 int ret = 0; 2694 uint32_t i; 2695 2696 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type)); 2697 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type)); 2698 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type)); 2699 2700 for (i = 0; i < args->num_objects; i++) { 2701 uint32_t object_type; 2702 2703 if (*priv_offset + sizeof(object_type) > max_priv_data_size) { 2704 pr_err("Invalid private data size\n"); 2705 return -EINVAL; 2706 } 2707 2708 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset)); 2709 if (ret) { 2710 pr_err("Failed to copy private information from user\n"); 2711 goto exit; 2712 } 2713 2714 switch (object_type) { 2715 case KFD_CRIU_OBJECT_TYPE_QUEUE: 2716 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data, 2717 priv_offset, max_priv_data_size); 2718 if (ret) 2719 goto exit; 2720 break; 2721 case KFD_CRIU_OBJECT_TYPE_EVENT: 2722 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data, 2723 priv_offset, max_priv_data_size); 2724 if (ret) 2725 goto exit; 2726 break; 2727 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE: 2728 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data, 2729 priv_offset, max_priv_data_size); 2730 if (ret) 2731 goto exit; 2732 break; 2733 default: 2734 pr_err("Invalid object type:%u at index:%d\n", object_type, i); 2735 ret = -EINVAL; 2736 goto exit; 2737 } 2738 } 2739 exit: 2740 return ret; 2741 } 2742 2743 static int criu_restore(struct file *filep, 2744 struct kfd_process *p, 2745 struct kfd_ioctl_criu_args *args) 2746 { 2747 uint64_t priv_offset = 0; 2748 int ret = 0; 2749 2750 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n", 2751 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size); 2752 2753 if ((args->num_bos > 0 && !args->bos) || !args->devices || !args->priv_data || 2754 !args->priv_data_size || !args->num_devices) 2755 return -EINVAL; 2756 2757 mutex_lock(&p->mutex); 2758 2759 /* 2760 * Set the process to evicted state to avoid running any new queues before all the memory 2761 * mappings are ready. 2762 */ 2763 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); 2764 if (ret) 2765 goto exit_unlock; 2766 2767 /* Each function will adjust priv_offset based on how many bytes they consumed */ 2768 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size); 2769 if (ret) 2770 goto exit_unlock; 2771 2772 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size); 2773 if (ret) 2774 goto exit_unlock; 2775 2776 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size); 2777 if (ret) 2778 goto exit_unlock; 2779 2780 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size); 2781 if (ret) 2782 goto exit_unlock; 2783 2784 if (priv_offset != args->priv_data_size) { 2785 pr_err("Invalid private data size\n"); 2786 ret = -EINVAL; 2787 } 2788 2789 exit_unlock: 2790 mutex_unlock(&p->mutex); 2791 if (ret) 2792 pr_err("Failed to restore CRIU ret:%d\n", ret); 2793 else 2794 pr_debug("CRIU restore successful\n"); 2795 2796 return ret; 2797 } 2798 2799 static int criu_unpause(struct file *filep, 2800 struct kfd_process *p, 2801 struct kfd_ioctl_criu_args *args) 2802 { 2803 int ret; 2804 2805 mutex_lock(&p->mutex); 2806 2807 if (!p->queues_paused) { 2808 mutex_unlock(&p->mutex); 2809 return -EINVAL; 2810 } 2811 2812 ret = kfd_process_restore_queues(p); 2813 if (ret) 2814 pr_err("Failed to unpause queues ret:%d\n", ret); 2815 else 2816 p->queues_paused = false; 2817 2818 mutex_unlock(&p->mutex); 2819 2820 return ret; 2821 } 2822 2823 static int criu_resume(struct file *filep, 2824 struct kfd_process *p, 2825 struct kfd_ioctl_criu_args *args) 2826 { 2827 struct kfd_process *target = NULL; 2828 struct pid *pid = NULL; 2829 int ret = 0; 2830 2831 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__, 2832 args->pid); 2833 2834 pid = find_get_pid(args->pid); 2835 if (!pid) { 2836 pr_err("Cannot find pid info for %i\n", args->pid); 2837 return -ESRCH; 2838 } 2839 2840 pr_debug("calling kfd_lookup_process_by_pid\n"); 2841 target = kfd_lookup_process_by_pid(pid); 2842 2843 put_pid(pid); 2844 2845 if (!target) { 2846 pr_debug("Cannot find process info for %i\n", args->pid); 2847 return -ESRCH; 2848 } 2849 2850 mutex_lock(&target->mutex); 2851 ret = kfd_criu_resume_svm(target); 2852 if (ret) { 2853 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid); 2854 goto exit; 2855 } 2856 2857 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info); 2858 if (ret) 2859 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid); 2860 2861 exit: 2862 mutex_unlock(&target->mutex); 2863 2864 kfd_unref_process(target); 2865 return ret; 2866 } 2867 2868 static int criu_process_info(struct file *filep, 2869 struct kfd_process *p, 2870 struct kfd_ioctl_criu_args *args) 2871 { 2872 int ret = 0; 2873 2874 mutex_lock(&p->mutex); 2875 2876 if (!p->n_pdds) { 2877 pr_err("No pdd for given process\n"); 2878 ret = -ENODEV; 2879 goto err_unlock; 2880 } 2881 2882 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); 2883 if (ret) 2884 goto err_unlock; 2885 2886 p->queues_paused = true; 2887 2888 args->pid = task_pid_nr_ns(p->lead_thread, 2889 task_active_pid_ns(p->lead_thread)); 2890 2891 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos, 2892 &args->num_objects, &args->priv_data_size); 2893 if (ret) 2894 goto err_unlock; 2895 2896 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n", 2897 args->num_devices, args->num_bos, args->num_objects, 2898 args->priv_data_size); 2899 2900 err_unlock: 2901 if (ret) { 2902 kfd_process_restore_queues(p); 2903 p->queues_paused = false; 2904 } 2905 mutex_unlock(&p->mutex); 2906 return ret; 2907 } 2908 2909 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data) 2910 { 2911 struct kfd_ioctl_criu_args *args = data; 2912 int ret; 2913 2914 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op); 2915 switch (args->op) { 2916 case KFD_CRIU_OP_PROCESS_INFO: 2917 ret = criu_process_info(filep, p, args); 2918 break; 2919 case KFD_CRIU_OP_CHECKPOINT: 2920 ret = criu_checkpoint(filep, p, args); 2921 break; 2922 case KFD_CRIU_OP_UNPAUSE: 2923 ret = criu_unpause(filep, p, args); 2924 break; 2925 case KFD_CRIU_OP_RESTORE: 2926 ret = criu_restore(filep, p, args); 2927 break; 2928 case KFD_CRIU_OP_RESUME: 2929 ret = criu_resume(filep, p, args); 2930 break; 2931 default: 2932 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op); 2933 ret = -EINVAL; 2934 break; 2935 } 2936 2937 if (ret) 2938 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret); 2939 2940 return ret; 2941 } 2942 2943 static int runtime_enable(struct kfd_process *p, uint64_t r_debug, 2944 bool enable_ttmp_setup) 2945 { 2946 int i = 0, ret = 0; 2947 2948 if (p->is_runtime_retry) 2949 goto retry; 2950 2951 if (p->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED) 2952 return -EBUSY; 2953 2954 for (i = 0; i < p->n_pdds; i++) { 2955 struct kfd_process_device *pdd = p->pdds[i]; 2956 2957 if (pdd->qpd.queue_count) 2958 return -EEXIST; 2959 2960 /* 2961 * Setup TTMPs by default. 2962 * Note that this call must remain here for MES ADD QUEUE to 2963 * skip_process_ctx_clear unconditionally as the first call to 2964 * SET_SHADER_DEBUGGER clears any stale process context data 2965 * saved in MES. 2966 */ 2967 if (pdd->dev->kfd->shared_resources.enable_mes) { 2968 ret = kfd_dbg_set_mes_debug_mode( 2969 pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); 2970 if (ret) 2971 return ret; 2972 } 2973 } 2974 2975 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED; 2976 p->runtime_info.r_debug = r_debug; 2977 p->runtime_info.ttmp_setup = enable_ttmp_setup; 2978 2979 if (p->runtime_info.ttmp_setup) { 2980 for (i = 0; i < p->n_pdds; i++) { 2981 struct kfd_process_device *pdd = p->pdds[i]; 2982 2983 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { 2984 amdgpu_gfx_off_ctrl(pdd->dev->adev, false); 2985 pdd->dev->kfd2kgd->enable_debug_trap( 2986 pdd->dev->adev, 2987 true, 2988 pdd->dev->vm_info.last_vmid_kfd); 2989 } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { 2990 pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( 2991 pdd->dev->adev, 2992 false, 2993 0); 2994 } 2995 } 2996 } 2997 2998 retry: 2999 if (p->debug_trap_enabled) { 3000 if (!p->is_runtime_retry) { 3001 kfd_dbg_trap_activate(p); 3002 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME), 3003 p, NULL, 0, false, NULL, 0); 3004 } 3005 3006 mutex_unlock(&p->mutex); 3007 ret = down_interruptible(&p->runtime_enable_sema); 3008 mutex_lock(&p->mutex); 3009 3010 p->is_runtime_retry = !!ret; 3011 } 3012 3013 return ret; 3014 } 3015 3016 static int runtime_disable(struct kfd_process *p) 3017 { 3018 int i = 0, ret = 0; 3019 bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED; 3020 3021 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED; 3022 p->runtime_info.r_debug = 0; 3023 3024 if (p->debug_trap_enabled) { 3025 if (was_enabled) 3026 kfd_dbg_trap_deactivate(p, false, 0); 3027 3028 if (!p->is_runtime_retry) 3029 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME), 3030 p, NULL, 0, false, NULL, 0); 3031 3032 mutex_unlock(&p->mutex); 3033 ret = down_interruptible(&p->runtime_enable_sema); 3034 mutex_lock(&p->mutex); 3035 3036 p->is_runtime_retry = !!ret; 3037 if (ret) 3038 return ret; 3039 } 3040 3041 if (was_enabled && p->runtime_info.ttmp_setup) { 3042 for (i = 0; i < p->n_pdds; i++) { 3043 struct kfd_process_device *pdd = p->pdds[i]; 3044 3045 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) 3046 amdgpu_gfx_off_ctrl(pdd->dev->adev, true); 3047 } 3048 } 3049 3050 p->runtime_info.ttmp_setup = false; 3051 3052 /* disable ttmp setup */ 3053 for (i = 0; i < p->n_pdds; i++) { 3054 struct kfd_process_device *pdd = p->pdds[i]; 3055 int last_err = 0; 3056 3057 if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { 3058 pdd->spi_dbg_override = 3059 pdd->dev->kfd2kgd->disable_debug_trap( 3060 pdd->dev->adev, 3061 false, 3062 pdd->dev->vm_info.last_vmid_kfd); 3063 3064 if (!pdd->dev->kfd->shared_resources.enable_mes) 3065 last_err = debug_refresh_runlist(pdd->dev->dqm); 3066 else 3067 last_err = kfd_dbg_set_mes_debug_mode(pdd, 3068 !kfd_dbg_has_cwsr_workaround(pdd->dev)); 3069 3070 if (last_err) 3071 ret = last_err; 3072 } 3073 } 3074 3075 return ret; 3076 } 3077 3078 static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data) 3079 { 3080 struct kfd_ioctl_runtime_enable_args *args = data; 3081 int r; 3082 3083 mutex_lock(&p->mutex); 3084 3085 if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK) 3086 r = runtime_enable(p, args->r_debug, 3087 !!(args->mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK)); 3088 else 3089 r = runtime_disable(p); 3090 3091 mutex_unlock(&p->mutex); 3092 3093 return r; 3094 } 3095 3096 static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, void *data) 3097 { 3098 struct kfd_ioctl_dbg_trap_args *args = data; 3099 struct task_struct *thread = NULL; 3100 struct mm_struct *mm = NULL; 3101 struct pid *pid = NULL; 3102 struct kfd_process *target = NULL; 3103 struct kfd_process_device *pdd = NULL; 3104 int r = 0; 3105 3106 if (p->context_id != KFD_CONTEXT_ID_PRIMARY) { 3107 pr_debug("Set debug trap ioctl can not be invoked on non-primary kfd process\n"); 3108 3109 return -EOPNOTSUPP; 3110 } 3111 3112 if (sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3113 pr_err("Debugging does not support sched_policy %i", sched_policy); 3114 return -EINVAL; 3115 } 3116 3117 pid = find_get_pid(args->pid); 3118 if (!pid) { 3119 pr_debug("Cannot find pid info for %i\n", args->pid); 3120 r = -ESRCH; 3121 goto out; 3122 } 3123 3124 thread = get_pid_task(pid, PIDTYPE_PID); 3125 if (!thread) { 3126 r = -ESRCH; 3127 goto out; 3128 } 3129 3130 mm = get_task_mm(thread); 3131 if (!mm) { 3132 r = -ESRCH; 3133 goto out; 3134 } 3135 3136 if (args->op == KFD_IOC_DBG_TRAP_ENABLE) { 3137 bool create_process; 3138 3139 rcu_read_lock(); 3140 create_process = thread && thread != current && ptrace_parent(thread) == current; 3141 rcu_read_unlock(); 3142 3143 target = create_process ? kfd_create_process(thread) : 3144 kfd_lookup_process_by_pid(pid); 3145 } else { 3146 target = kfd_lookup_process_by_pid(pid); 3147 } 3148 3149 if (IS_ERR_OR_NULL(target)) { 3150 pr_debug("Cannot find process PID %i to debug\n", args->pid); 3151 r = target ? PTR_ERR(target) : -ESRCH; 3152 target = NULL; 3153 goto out; 3154 } 3155 3156 if (target->context_id != KFD_CONTEXT_ID_PRIMARY) { 3157 pr_debug("Set debug trap ioctl not supported on non-primary kfd process\n"); 3158 r = -EOPNOTSUPP; 3159 goto out; 3160 } 3161 3162 /* 3163 * Verify debugger has permission to debug target process. 3164 * For cross-process debugging, require active ptrace relationship. 3165 * This applies to ALL operations to prevent unauthorized interference. 3166 */ 3167 rcu_read_lock(); 3168 if (target != p && ptrace_parent(target->lead_thread) != current 3169 && target->debugger_process != p) { 3170 pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid); 3171 r = -EPERM; 3172 } 3173 rcu_read_unlock(); 3174 3175 if (r) 3176 goto out; 3177 3178 mutex_lock(&target->mutex); 3179 3180 if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) { 3181 pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op); 3182 r = -EINVAL; 3183 goto unlock_out; 3184 } 3185 3186 if (target->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_ENABLED && 3187 (args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE || 3188 args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE || 3189 args->op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES || 3190 args->op == KFD_IOC_DBG_TRAP_RESUME_QUEUES || 3191 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH || 3192 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH || 3193 args->op == KFD_IOC_DBG_TRAP_SET_FLAGS)) { 3194 r = -EPERM; 3195 goto unlock_out; 3196 } 3197 3198 if (args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH || 3199 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH) { 3200 int user_gpu_id = kfd_process_get_user_gpu_id(target, 3201 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ? 3202 args->set_node_address_watch.gpu_id : 3203 args->clear_node_address_watch.gpu_id); 3204 3205 pdd = kfd_process_device_data_by_id(target, user_gpu_id); 3206 if (user_gpu_id == -EINVAL || !pdd) { 3207 r = -ENODEV; 3208 goto unlock_out; 3209 } 3210 } 3211 3212 switch (args->op) { 3213 case KFD_IOC_DBG_TRAP_ENABLE: 3214 if (target != p) 3215 target->debugger_process = p; 3216 3217 r = kfd_dbg_trap_enable(target, 3218 args->enable.dbg_fd, 3219 (void __user *)args->enable.rinfo_ptr, 3220 &args->enable.rinfo_size); 3221 if (!r) 3222 target->exception_enable_mask = args->enable.exception_mask; 3223 3224 break; 3225 case KFD_IOC_DBG_TRAP_DISABLE: 3226 r = kfd_dbg_trap_disable(target); 3227 break; 3228 case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT: 3229 r = kfd_dbg_send_exception_to_runtime(target, 3230 args->send_runtime_event.gpu_id, 3231 args->send_runtime_event.queue_id, 3232 args->send_runtime_event.exception_mask); 3233 break; 3234 case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED: 3235 kfd_dbg_set_enabled_debug_exception_mask(target, 3236 args->set_exceptions_enabled.exception_mask); 3237 break; 3238 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE: 3239 r = kfd_dbg_trap_set_wave_launch_override(target, 3240 args->launch_override.override_mode, 3241 args->launch_override.enable_mask, 3242 args->launch_override.support_request_mask, 3243 &args->launch_override.enable_mask, 3244 &args->launch_override.support_request_mask); 3245 break; 3246 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE: 3247 r = kfd_dbg_trap_set_wave_launch_mode(target, 3248 args->launch_mode.launch_mode); 3249 break; 3250 case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: 3251 r = suspend_queues(target, 3252 args->suspend_queues.num_queues, 3253 args->suspend_queues.grace_period, 3254 args->suspend_queues.exception_mask, 3255 (uint32_t *)args->suspend_queues.queue_array_ptr); 3256 3257 break; 3258 case KFD_IOC_DBG_TRAP_RESUME_QUEUES: 3259 r = resume_queues(target, args->resume_queues.num_queues, 3260 (uint32_t *)args->resume_queues.queue_array_ptr); 3261 break; 3262 case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH: 3263 r = kfd_dbg_trap_set_dev_address_watch(pdd, 3264 args->set_node_address_watch.address, 3265 args->set_node_address_watch.mask, 3266 &args->set_node_address_watch.id, 3267 args->set_node_address_watch.mode); 3268 break; 3269 case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH: 3270 r = kfd_dbg_trap_clear_dev_address_watch(pdd, 3271 args->clear_node_address_watch.id); 3272 break; 3273 case KFD_IOC_DBG_TRAP_SET_FLAGS: 3274 r = kfd_dbg_trap_set_flags(target, &args->set_flags.flags); 3275 break; 3276 case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT: 3277 r = kfd_dbg_ev_query_debug_event(target, 3278 &args->query_debug_event.queue_id, 3279 &args->query_debug_event.gpu_id, 3280 args->query_debug_event.exception_mask, 3281 &args->query_debug_event.exception_mask); 3282 break; 3283 case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: 3284 r = kfd_dbg_trap_query_exception_info(target, 3285 args->query_exception_info.source_id, 3286 args->query_exception_info.exception_code, 3287 args->query_exception_info.clear_exception, 3288 (void __user *)args->query_exception_info.info_ptr, 3289 &args->query_exception_info.info_size); 3290 break; 3291 case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: 3292 r = pqm_get_queue_snapshot(&target->pqm, 3293 args->queue_snapshot.exception_mask, 3294 (void __user *)args->queue_snapshot.snapshot_buf_ptr, 3295 &args->queue_snapshot.num_queues, 3296 &args->queue_snapshot.entry_size); 3297 break; 3298 case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: 3299 r = kfd_dbg_trap_device_snapshot(target, 3300 args->device_snapshot.exception_mask, 3301 (void __user *)args->device_snapshot.snapshot_buf_ptr, 3302 &args->device_snapshot.num_devices, 3303 &args->device_snapshot.entry_size); 3304 break; 3305 default: 3306 pr_err("Invalid option: %i\n", args->op); 3307 r = -EINVAL; 3308 } 3309 3310 unlock_out: 3311 mutex_unlock(&target->mutex); 3312 3313 out: 3314 if (thread) 3315 put_task_struct(thread); 3316 3317 if (mm) 3318 mmput(mm); 3319 3320 if (pid) 3321 put_pid(pid); 3322 3323 if (target) 3324 kfd_unref_process(target); 3325 3326 return r; 3327 } 3328 3329 /* userspace programs need to invoke this ioctl explicitly on a FD to 3330 * create a secondary kfd_process which replacing its primary kfd_process 3331 */ 3332 static int kfd_ioctl_create_process(struct file *filep, struct kfd_process *p, void *data) 3333 { 3334 struct kfd_process *process; 3335 int ret; 3336 3337 if (!filep->private_data || !p) 3338 return -EINVAL; 3339 3340 /* Each FD owns only one kfd_process */ 3341 if (p->context_id != KFD_CONTEXT_ID_PRIMARY) 3342 return -EINVAL; 3343 3344 mutex_lock(&kfd_processes_mutex); 3345 if (p != filep->private_data) { 3346 mutex_unlock(&kfd_processes_mutex); 3347 return -EINVAL; 3348 } 3349 3350 process = create_process(current, false); 3351 if (IS_ERR(process)) { 3352 mutex_unlock(&kfd_processes_mutex); 3353 return PTR_ERR(process); 3354 } 3355 3356 filep->private_data = process; 3357 ret = kfd_debugfs_add_process(process); 3358 if (ret) 3359 pr_warn("Failed to create debugfs entry for the kfd_process, ret = %d\n", 3360 ret); 3361 3362 mutex_unlock(&kfd_processes_mutex); 3363 3364 ret = kfd_create_process_sysfs(process); 3365 if (ret) 3366 pr_warn("Failed to create sysfs entry for the kfd_process"); 3367 3368 /* Each open() increases kref of the primary kfd_process, 3369 * so we need to reduce it here when we create a new secondary process replacing it 3370 */ 3371 kfd_unref_process(p); 3372 3373 return 0; 3374 } 3375 3376 static inline int profile_lock_device(struct kfd_process *p, 3377 uint32_t gpu_id, uint32_t op) 3378 { 3379 struct kfd_process_device *pdd; 3380 struct kfd_dev *kfd; 3381 int status = -EINVAL; 3382 struct amdgpu_ptl *ptl; 3383 3384 if (!p) 3385 return -EINVAL; 3386 3387 mutex_lock(&p->mutex); 3388 pdd = kfd_process_device_data_by_id(p, gpu_id); 3389 mutex_unlock(&p->mutex); 3390 3391 if (!pdd || !pdd->dev || !pdd->dev->kfd) 3392 return -EINVAL; 3393 3394 kfd = pdd->dev->kfd; 3395 ptl = &pdd->dev->adev->psp.ptl; 3396 3397 mutex_lock(&kfd->profiler_lock); 3398 if (op == 1) { 3399 if (!kfd->profiler_process) { 3400 kfd->profiler_process = p; 3401 status = 0; 3402 mutex_unlock(&kfd->profiler_lock); 3403 if (ptl->hw_supported_state == AMDGPU_PTL_HW_SUPPORTED) { 3404 status = kfd_ptl_disable_request(pdd, p); 3405 if (status != 0) 3406 dev_err(kfd_device, 3407 "Failed to lock device %d for profiling, error %d\n", 3408 gpu_id, status); 3409 } 3410 return status; 3411 } else if (kfd->profiler_process == p) { 3412 status = -EALREADY; 3413 } else { 3414 status = -EBUSY; 3415 } 3416 } else if (op == 0 && kfd->profiler_process == p) { 3417 kfd->profiler_process = NULL; 3418 status = 0; 3419 mutex_unlock(&kfd->profiler_lock); 3420 3421 if (ptl->hw_supported_state == AMDGPU_PTL_HW_SUPPORTED) { 3422 status = kfd_ptl_disable_release(pdd, p); 3423 if (status) 3424 dev_err(kfd_device, 3425 "Failed to unlock device %d for profiling, error %d\n", 3426 gpu_id, status); 3427 } 3428 return status; 3429 } 3430 mutex_unlock(&kfd->profiler_lock); 3431 3432 return status; 3433 } 3434 3435 static inline int kfd_profiler_pmc(struct kfd_process *p, 3436 struct kfd_ioctl_pmc_settings *args) 3437 { 3438 struct kfd_process_device *pdd; 3439 struct device_queue_manager *dqm; 3440 int status; 3441 3442 /* Check if we have the correct permissions. */ 3443 if (!perfmon_capable()) 3444 return -EPERM; 3445 3446 /* Lock/Unlock the device based on the parameter given in OP */ 3447 status = profile_lock_device(p, args->gpu_id, args->lock); 3448 if (status != 0) 3449 return status; 3450 3451 /* Enable/disable perfcount if requested */ 3452 mutex_lock(&p->mutex); 3453 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 3454 dqm = pdd->dev->dqm; 3455 mutex_unlock(&p->mutex); 3456 3457 dqm->ops.set_perfcount(dqm, args->perfcount_enable); 3458 return status; 3459 } 3460 3461 static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *data) 3462 { 3463 struct kfd_ioctl_profiler_args *args = data; 3464 3465 switch (args->op) { 3466 case KFD_IOC_PROFILER_VERSION: 3467 args->version = KFD_IOC_PROFILER_VERSION_NUM; 3468 return 0; 3469 case KFD_IOC_PROFILER_PMC: 3470 return kfd_profiler_pmc(p, &args->pmc); 3471 case KFD_IOC_PROFILER_PTL_CONTROL: 3472 return kfd_profiler_ptl_control(p, &args->ptl); 3473 } 3474 return -EINVAL; 3475 } 3476 3477 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ 3478 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ 3479 .validate = NULL, .cmd_drv = 0, .name = #ioctl} 3480 3481 #define AMDKFD_IOCTL_DEF_V(ioctl, _func, _validate, _flags) \ 3482 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ 3483 .validate = _validate, .cmd_drv = 0, .name = #ioctl} 3484 3485 /** Ioctl table */ 3486 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { 3487 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION, 3488 kfd_ioctl_get_version, 0), 3489 3490 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE, 3491 kfd_ioctl_create_queue, 0), 3492 3493 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE, 3494 kfd_ioctl_destroy_queue, 0), 3495 3496 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY, 3497 kfd_ioctl_set_memory_policy, 0), 3498 3499 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS, 3500 kfd_ioctl_get_clock_counters, 0), 3501 3502 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES, 3503 kfd_ioctl_get_process_apertures, 0), 3504 3505 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE, 3506 kfd_ioctl_update_queue, 0), 3507 3508 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT, 3509 kfd_ioctl_create_event, 0), 3510 3511 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT, 3512 kfd_ioctl_destroy_event, 0), 3513 3514 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT, 3515 kfd_ioctl_set_event, 0), 3516 3517 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT, 3518 kfd_ioctl_reset_event, 0), 3519 3520 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS, 3521 kfd_ioctl_wait_events, 0), 3522 3523 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED, 3524 kfd_ioctl_dbg_register, 0), 3525 3526 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED, 3527 kfd_ioctl_dbg_unregister, 0), 3528 3529 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED, 3530 kfd_ioctl_dbg_address_watch, 0), 3531 3532 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED, 3533 kfd_ioctl_dbg_wave_control, 0), 3534 3535 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA, 3536 kfd_ioctl_set_scratch_backing_va, 0), 3537 3538 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG, 3539 kfd_ioctl_get_tile_config, 0), 3540 3541 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER, 3542 kfd_ioctl_set_trap_handler, 0), 3543 3544 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW, 3545 kfd_ioctl_get_process_apertures_new, 0), 3546 3547 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM, 3548 kfd_ioctl_acquire_vm, 0), 3549 3550 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU, 3551 kfd_ioctl_alloc_memory_of_gpu, 0), 3552 3553 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU, 3554 kfd_ioctl_free_memory_of_gpu, 0), 3555 3556 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU, 3557 kfd_ioctl_map_memory_to_gpu, 0), 3558 3559 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU, 3560 kfd_ioctl_unmap_memory_from_gpu, 0), 3561 3562 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK, 3563 kfd_ioctl_set_cu_mask, 0), 3564 3565 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE, 3566 kfd_ioctl_get_queue_wave_state, 0), 3567 3568 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO, 3569 kfd_ioctl_get_dmabuf_info, 0), 3570 3571 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF, 3572 kfd_ioctl_import_dmabuf, 0), 3573 3574 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS, 3575 kfd_ioctl_alloc_queue_gws, 0), 3576 3577 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS, 3578 kfd_ioctl_smi_events, 0), 3579 3580 AMDKFD_IOCTL_DEF_V(AMDKFD_IOC_SVM, kfd_ioctl_svm, 3581 kfd_ioctl_svm_validate, 0), 3582 3583 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE, 3584 kfd_ioctl_set_xnack_mode, 0), 3585 3586 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP, 3587 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE), 3588 3589 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY, 3590 kfd_ioctl_get_available_memory, 0), 3591 3592 AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF, 3593 kfd_ioctl_export_dmabuf, 0), 3594 3595 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE, 3596 kfd_ioctl_runtime_enable, 0), 3597 3598 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP, 3599 kfd_ioctl_set_debug_trap, 0), 3600 3601 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_PROCESS, 3602 kfd_ioctl_create_process, 0), 3603 3604 AMDKFD_IOCTL_DEF(AMDKFD_IOC_PROFILER, 3605 kfd_ioctl_profiler, 0), 3606 }; 3607 3608 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) 3609 3610 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) 3611 { 3612 struct kfd_process *process; 3613 amdkfd_ioctl_t *func; 3614 const struct amdkfd_ioctl_desc *ioctl = NULL; 3615 unsigned int nr = _IOC_NR(cmd); 3616 char stack_kdata[128]; 3617 char *kdata = NULL; 3618 unsigned int usize, asize; 3619 int retcode = -EINVAL; 3620 bool ptrace_attached = false; 3621 3622 if (nr >= AMDKFD_CORE_IOCTL_COUNT) { 3623 retcode = -ENOTTY; 3624 goto err_i1; 3625 } 3626 3627 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { 3628 u32 amdkfd_size; 3629 3630 ioctl = &amdkfd_ioctls[nr]; 3631 3632 amdkfd_size = _IOC_SIZE(ioctl->cmd); 3633 usize = asize = _IOC_SIZE(cmd); 3634 if (amdkfd_size > asize) 3635 asize = amdkfd_size; 3636 3637 cmd = ioctl->cmd; 3638 } else { 3639 retcode = -ENOTTY; 3640 goto err_i1; 3641 } 3642 3643 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg); 3644 3645 /* Get the process struct from the filep. Only the process 3646 * that opened /dev/kfd can use the file descriptor. Child 3647 * processes need to create their own KFD device context. 3648 */ 3649 process = filep->private_data; 3650 3651 rcu_read_lock(); 3652 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) && 3653 ptrace_parent(process->lead_thread) == current) 3654 ptrace_attached = true; 3655 rcu_read_unlock(); 3656 3657 if (process->lead_thread != current->group_leader 3658 && !ptrace_attached) { 3659 dev_dbg(kfd_device, "Using KFD FD in wrong process\n"); 3660 retcode = -EBADF; 3661 goto err_i1; 3662 } 3663 3664 /* Do not trust userspace, use our own definition */ 3665 func = ioctl->func; 3666 3667 if (unlikely(!func)) { 3668 dev_dbg(kfd_device, "no function\n"); 3669 retcode = -EINVAL; 3670 goto err_i1; 3671 } 3672 3673 /* 3674 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support 3675 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a 3676 * more priviledged access. 3677 */ 3678 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) { 3679 if (!capable(CAP_CHECKPOINT_RESTORE) && 3680 !capable(CAP_SYS_ADMIN)) { 3681 retcode = -EACCES; 3682 goto err_i1; 3683 } 3684 } 3685 3686 if (cmd & (IOC_IN | IOC_OUT)) { 3687 if (asize <= sizeof(stack_kdata)) { 3688 kdata = stack_kdata; 3689 } else { 3690 kdata = kmalloc(asize, GFP_KERNEL); 3691 if (!kdata) { 3692 retcode = -ENOMEM; 3693 goto err_i1; 3694 } 3695 } 3696 if (asize > usize) 3697 memset(kdata + usize, 0, asize - usize); 3698 } 3699 3700 if (cmd & IOC_IN) { 3701 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) { 3702 retcode = -EFAULT; 3703 goto err_i1; 3704 } 3705 } else if (cmd & IOC_OUT) { 3706 memset(kdata, 0, usize); 3707 } 3708 3709 if (ioctl->validate) { 3710 retcode = ioctl->validate(kdata, usize); 3711 if (retcode) 3712 goto err_i1; 3713 } 3714 3715 retcode = func(filep, process, kdata); 3716 3717 if (cmd & IOC_OUT) 3718 if (copy_to_user((void __user *)arg, kdata, usize) != 0) 3719 retcode = -EFAULT; 3720 3721 err_i1: 3722 if (!ioctl) 3723 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n", 3724 task_pid_nr(current), cmd, nr); 3725 3726 if (kdata != stack_kdata) 3727 kfree(kdata); 3728 3729 if (retcode) 3730 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n", 3731 nr, arg, retcode); 3732 3733 return retcode; 3734 } 3735 3736 static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process, 3737 struct vm_area_struct *vma) 3738 { 3739 phys_addr_t address; 3740 3741 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3742 return -EINVAL; 3743 3744 if (PAGE_SIZE > 4096) 3745 return -EINVAL; 3746 3747 address = dev->adev->rmmio_remap.bus_addr; 3748 3749 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | 3750 VM_DONTDUMP | VM_PFNMAP); 3751 3752 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3753 3754 pr_debug("process pid %d mapping mmio page\n" 3755 " target user address == 0x%08llX\n" 3756 " physical address == 0x%08llX\n" 3757 " vm_flags == 0x%04lX\n" 3758 " size == 0x%04lX\n", 3759 process->lead_thread->pid, (unsigned long long) vma->vm_start, 3760 address, vma->vm_flags, PAGE_SIZE); 3761 3762 return io_remap_pfn_range(vma, 3763 vma->vm_start, 3764 address >> PAGE_SHIFT, 3765 PAGE_SIZE, 3766 vma->vm_page_prot); 3767 } 3768 3769 static int kfd_mmap(struct file *filep, struct vm_area_struct *vma) 3770 { 3771 struct kfd_process *process; 3772 struct kfd_process_device *pdd; 3773 struct kfd_node *dev = NULL; 3774 unsigned long mmap_offset; 3775 unsigned int gpu_id; 3776 3777 process = filep->private_data; 3778 if (!process) 3779 return -ESRCH; 3780 3781 if (process->lead_thread != current->group_leader) 3782 return -EBADF; 3783 3784 mmap_offset = vma->vm_pgoff << PAGE_SHIFT; 3785 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset); 3786 3787 pdd = kfd_process_device_data_by_id(process, gpu_id); 3788 if (pdd) 3789 dev = pdd->dev; 3790 3791 switch (mmap_offset & KFD_MMAP_TYPE_MASK) { 3792 case KFD_MMAP_TYPE_DOORBELL: 3793 if (!dev) 3794 return -ENODEV; 3795 return kfd_doorbell_mmap(dev, process, vma); 3796 3797 case KFD_MMAP_TYPE_EVENTS: 3798 pr_warn("KFD_MMAP_TYPE_EVENTS is no longer supported\n"); 3799 return -EINVAL; 3800 3801 case KFD_MMAP_TYPE_RESERVED_MEM: 3802 pr_warn("KFD_MMAP_TYPE_RESERVED_MEM is no longer supported\n"); 3803 return -EINVAL; 3804 case KFD_MMAP_TYPE_MMIO: 3805 if (!dev) 3806 return -ENODEV; 3807 return kfd_mmio_mmap(dev, process, vma); 3808 } 3809 3810 return -EFAULT; 3811 } 3812