1/* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * 25 * gfx12: 26 * cpp -DASIC_FAMILY=CHIP_GFX12 cwsr_trap_handler_gfx12.asm -P -o gfx12.sp3 27 * sp3 gfx12.sp3 -hex gfx12.hex 28 */ 29 30#define CHIP_GFX12 37 31#define CHIP_GC_12_0_3 38 32 33#define HAVE_XNACK (ASIC_FAMILY == CHIP_GC_12_0_3) 34#define HAVE_57BIT_ADDRESS (ASIC_FAMILY == CHIP_GC_12_0_3) 35#define HAVE_BANKED_VGPRS (ASIC_FAMILY == CHIP_GC_12_0_3) 36#define NUM_NAMED_BARRIERS (ASIC_FAMILY == CHIP_GC_12_0_3 ? 0x10 : 0) 37#define HAVE_CLUSTER_BARRIER (ASIC_FAMILY == CHIP_GC_12_0_3) 38#define CLUSTER_BARRIER_SERIALIZE_WORKAROUND (ASIC_FAMILY == CHIP_GC_12_0_3) 39#define RELAXED_SCHEDULING_IN_TRAP (ASIC_FAMILY == CHIP_GFX12) 40#define HAVE_INSTRUCTION_FIXUP (ASIC_FAMILY == CHIP_GC_12_0_3) 41 42#define SINGLE_STEP_MISSED_WORKAROUND 1 //workaround for lost TRAP_AFTER_INST exception when SAVECTX raised 43#define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12) 44#define WAVE32_ONLY (ASIC_FAMILY == CHIP_GC_12_0_3) 45#define SAVE_TTMPS_IN_SGPR_BLOCK (ASIC_FAMILY >= CHIP_GC_12_0_3) 46 47#if HAVE_XNACK && !WAVE32_ONLY 48# error 49#endif 50 51#define ADDRESS_HI32_NUM_BITS ((HAVE_57BIT_ADDRESS ? 57 : 48) - 32) 52#define ADDRESS_HI32_MASK ((1 << ADDRESS_HI32_NUM_BITS) - 1) 53 54var SQ_WAVE_STATE_PRIV_ALL_BARRIER_COMPLETE_MASK = 0x4 | (NUM_NAMED_BARRIERS ? 0x8 : 0) | (HAVE_CLUSTER_BARRIER ? 0x10000 : 0) 55var SQ_WAVE_STATE_PRIV_SCC_SHIFT = 9 56var SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK = 0xC00 57var SQ_WAVE_STATE_PRIV_HALT_MASK = 0x4000 58var SQ_WAVE_STATE_PRIV_POISON_ERR_MASK = 0x8000 59var SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT = 15 60var SQ_WAVE_STATUS_WAVE64_SHIFT = 29 61var SQ_WAVE_STATUS_WAVE64_SIZE = 1 62var SQ_WAVE_STATUS_NO_VGPRS_SHIFT = 24 63var SQ_WAVE_STATUS_IN_WG_SHIFT = 11 64var SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK = SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK|SQ_WAVE_STATE_PRIV_POISON_ERR_MASK 65var S_SAVE_PC_HI_TRAP_ID_MASK = 0xF0000000 66 67var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 68var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 69var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 8 70var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 12 71 72#if ASIC_FAMILY < CHIP_GC_12_0_3 73var SQ_WAVE_LDS_ALLOC_GRANULARITY = 9 74#else 75var SQ_WAVE_LDS_ALLOC_GRANULARITY = 10 76#endif 77 78var SQ_WAVE_EXCP_FLAG_PRIV_ADDR_WATCH_MASK = 0xF 79var SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_SHIFT = 4 80var SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK = 0x10 81var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT = 5 82var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK = 0x20 83var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK = 0x40 84var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT = 6 85var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK = 0x80 86var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT = 7 87var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK = 0x100 88var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT = 8 89var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK = 0x200 90var SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK = 0x800 91var SQ_WAVE_TRAP_CTRL_ADDR_WATCH_MASK = 0x80 92var SQ_WAVE_TRAP_CTRL_TRAP_AFTER_INST_MASK = 0x200 93 94var SQ_WAVE_EXCP_FLAG_PRIV_NON_MASKABLE_EXCP_MASK= SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK |\ 95 SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK |\ 96 SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK |\ 97 SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK |\ 98 SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK |\ 99 SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK 100var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_1_SIZE = SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT 101var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT 102var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SIZE = SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT - SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT 103var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT 104var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SIZE = 32 - SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT 105 106var SQ_WAVE_SCHED_MODE_DEP_MODE_SHIFT = 0 107var SQ_WAVE_SCHED_MODE_DEP_MODE_SIZE = 2 108 109var BARRIER_STATE_SIGNAL_OFFSET = 16 110var BARRIER_STATE_SIGNAL_SIZE = 7 111var BARRIER_STATE_MEMBER_OFFSET = 4 112var BARRIER_STATE_MEMBER_SIZE = 7 113var BARRIER_STATE_VALID_OFFSET = 0 114 115#if RELAXED_SCHEDULING_IN_TRAP 116var TTMP11_SCHED_MODE_SHIFT = 26 117var TTMP11_SCHED_MODE_SIZE = 2 118var TTMP11_SCHED_MODE_MASK = 0xC000000 119#endif 120 121var NAMED_BARRIERS_SR_OFFSET_FROM_HWREG = 0x80 122var S_BARRIER_INIT_MEMBERCNT_MASK = 0x7F0000 123var S_BARRIER_INIT_MEMBERCNT_SHIFT = 0x10 124 125var SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SHIFT = 18 126var SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SIZE = 1 127var SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SHIFT = 16 128var SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SIZE = 1 129var SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SHIFT = 0 130var SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SIZE = 7 131 132#if HAVE_BANKED_VGPRS 133var SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT = 12 134var SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE = 6 135#endif 136 137var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23 138var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000 139var TTMP11_FIRST_REPLAY_SHIFT = 22 140var TTMP11_FIRST_REPLAY_MASK = 0x400000 141var TTMP11_REPLAY_W64H_SHIFT = 21 142var TTMP11_REPLAY_W64H_MASK = 0x200000 143var TTMP11_FXPTR_SHIFT = 14 144var TTMP11_FXPTR_MASK = 0x1FC000 145 146// SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] 147// when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 148var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 149var S_SAVE_BUF_RSRC_WORD3_MISC = 0x10807FAC 150var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 151var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 152 153var S_SAVE_PC_HI_FIRST_WAVE_MASK = 0x80000000 154var S_SAVE_PC_HI_FIRST_WAVE_SHIFT = 31 155 156#if HAVE_BANKED_VGPRS 157var S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SHIFT = 25 158var S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SIZE = 6 159#endif 160 161var s_sgpr_save_num = 108 162 163var s_save_spi_init_lo = exec_lo 164var s_save_spi_init_hi = exec_hi 165var s_save_pc_lo = ttmp0 166var s_save_pc_hi = ttmp1 167var s_save_exec_lo = ttmp2 168var s_save_exec_hi = ttmp3 169var s_save_state_priv = ttmp12 170var s_save_excp_flag_priv = ttmp15 171var s_save_xnack_mask = s_save_exec_hi 172var s_wave_size = ttmp7 173var s_save_base_addr_lo = ttmp8 174var s_save_base_addr_hi = ttmp9 175var s_save_addr_lo = ttmp10 176var s_save_addr_hi = ttmp11 177var s_save_mem_offset = ttmp4 178var s_save_alloc_size = s_save_excp_flag_priv 179var s_save_tmp = ttmp14 180var s_save_m0 = ttmp5 181var s_save_ttmps_lo = s_save_tmp 182var s_save_ttmps_hi = s_save_excp_flag_priv 183 184var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 185var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 186var S_WAVE_SIZE = 25 187 188var s_restore_spi_init_lo = exec_lo 189var s_restore_spi_init_hi = exec_hi 190var s_restore_mem_offset = ttmp12 191var s_restore_alloc_size = ttmp3 192var s_restore_tmp = ttmp2 193var s_restore_mem_offset_save = s_restore_tmp 194var s_restore_m0 = s_restore_alloc_size 195var s_restore_mode = ttmp7 196var s_restore_flat_scratch = s_restore_tmp 197var s_restore_pc_lo = ttmp0 198var s_restore_pc_hi = ttmp1 199var s_restore_exec_lo = ttmp4 200var s_restore_exec_hi = ttmp5 201var s_restore_state_priv = ttmp14 202var s_restore_excp_flag_priv = ttmp15 203var s_restore_xnack_mask = ttmp13 204var s_restore_base_addr_lo = ttmp8 205var s_restore_base_addr_hi = ttmp9 206var s_restore_addr_lo = ttmp10 207var s_restore_addr_hi = ttmp11 208var s_restore_size = ttmp6 209var s_restore_ttmps_lo = s_restore_tmp 210var s_restore_ttmps_hi = s_restore_alloc_size 211var s_restore_spi_init_hi_save = s_restore_exec_hi 212 213#if SAVE_TTMPS_IN_SGPR_BLOCK 214var TTMP_SR_OFFSET_FROM_HWREG = -0x40 215#else 216var TTMP_SR_OFFSET_FROM_HWREG = 0x40 217#endif 218 219shader main 220 asic(DEFAULT) 221 type(CS) 222 wave_size(32) 223 224 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 225 226L_JUMP_TO_RESTORE: 227 s_branch L_RESTORE 228 229L_SKIP_RESTORE: 230#if RELAXED_SCHEDULING_IN_TRAP 231 // Assume most relaxed scheduling mode is set. Save and revert to normal mode. 232 s_getreg_b32 ttmp2, hwreg(HW_REG_WAVE_SCHED_MODE) 233 s_wait_alu 0 234 s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE, \ 235 SQ_WAVE_SCHED_MODE_DEP_MODE_SHIFT, SQ_WAVE_SCHED_MODE_DEP_MODE_SIZE), 0 236#endif 237 238 s_getreg_b32 s_save_state_priv, hwreg(HW_REG_WAVE_STATE_PRIV) //save STATUS since we will change SCC 239 240#if RELAXED_SCHEDULING_IN_TRAP 241 // Save SCHED_MODE[1:0] into ttmp11[27:26]. 242 s_andn2_b32 ttmp11, ttmp11, TTMP11_SCHED_MODE_MASK 243 s_lshl_b32 ttmp2, ttmp2, TTMP11_SCHED_MODE_SHIFT 244 s_or_b32 ttmp11, ttmp11, ttmp2 245#endif 246 247 // Clear SPI_PRIO: do not save with elevated priority. 248 // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd. 249 s_andn2_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK 250 251 s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 252 253 s_and_b32 ttmp2, s_save_state_priv, SQ_WAVE_STATE_PRIV_HALT_MASK 254 s_cbranch_scc0 L_NOT_HALTED 255 256L_HALTED: 257 // Host trap may occur while wave is halted. 258 s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK 259 s_cbranch_scc1 L_FETCH_2ND_TRAP 260 261L_CHECK_SAVE: 262 s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK 263 s_cbranch_scc1 L_SAVE 264 265 // Wave is halted but neither host trap nor SAVECTX is raised. 266 // Caused by instruction fetch memory violation. 267 // Spin wait until context saved to prevent interrupt storm. 268 s_sleep 0x10 269 s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 270 s_branch L_CHECK_SAVE 271 272L_NOT_HALTED: 273 // Let second-level handle non-SAVECTX exception or trap. 274 // Any concurrent SAVECTX will be handled upon re-entry once halted. 275 276 // Check non-maskable exceptions. memory_violation, illegal_instruction 277 // and xnack_error exceptions always cause the wave to enter the trap 278 // handler. 279 s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_NON_MASKABLE_EXCP_MASK 280 s_cbranch_scc1 L_FETCH_2ND_TRAP 281 282 // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. 283 // Maskable exceptions only cause the wave to enter the trap handler if 284 // their respective bit in mode.excp_en is set. 285 s_getreg_b32 ttmp2, hwreg(HW_REG_WAVE_EXCP_FLAG_USER) 286 s_and_b32 ttmp3, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_ADDR_WATCH_MASK 287 s_cbranch_scc0 L_NOT_ADDR_WATCH 288 s_or_b32 ttmp2, ttmp2, SQ_WAVE_TRAP_CTRL_ADDR_WATCH_MASK 289 290L_NOT_ADDR_WATCH: 291 s_getreg_b32 ttmp3, hwreg(HW_REG_WAVE_TRAP_CTRL) 292 s_and_b32 ttmp2, ttmp3, ttmp2 293 s_cbranch_scc1 L_FETCH_2ND_TRAP 294 295L_CHECK_TRAP_ID: 296 // Check trap_id != 0 297 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 298 s_cbranch_scc1 L_FETCH_2ND_TRAP 299 300#if SINGLE_STEP_MISSED_WORKAROUND 301 // Prioritize single step exception over context save. 302 // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 303 // WAVE_TRAP_CTRL is already in ttmp3. 304 s_and_b32 ttmp3, ttmp3, SQ_WAVE_TRAP_CTRL_TRAP_AFTER_INST_MASK 305 s_cbranch_scc1 L_FETCH_2ND_TRAP 306#endif 307 308 s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK 309 s_cbranch_scc1 L_SAVE 310 311L_FETCH_2ND_TRAP: 312#if HAVE_XNACK 313 save_and_clear_xnack_state_priv(ttmp14) 314#endif 315 316 // Read second-level TBA/TMA from first-level TMA and jump if available. 317 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 318 // ttmp12 holds SQ_WAVE_STATUS 319 s_sendmsg_rtn_b64 [ttmp14, ttmp15], sendmsg(MSG_RTN_GET_TMA) 320 s_wait_idle 321 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 322 323 s_bitcmp1_b32 ttmp15, (ADDRESS_HI32_NUM_BITS - 1) 324 s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA 325 s_or_b32 ttmp15, ttmp15, ~ADDRESS_HI32_MASK 326L_NO_SIGN_EXTEND_TMA: 327#if RELAXED_SCHEDULING_IN_TRAP 328 // Move SCHED_MODE[1:0] from ttmp11 to unused bits in ttmp1[27:26] (return PC_HI). 329 // The second-level trap will restore from ttmp1 for backwards compatibility. 330 s_and_b32 ttmp2, ttmp11, TTMP11_SCHED_MODE_MASK 331 s_andn2_b32 ttmp1, ttmp1, TTMP11_SCHED_MODE_MASK 332 s_or_b32 ttmp1, ttmp1, ttmp2 333#endif 334 335 s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS // debug trap enabled flag 336 s_wait_idle 337 s_lshl_b32 ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT 338 s_andn2_b32 ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK 339 s_or_b32 ttmp11, ttmp11, ttmp2 340 341 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 scope:SCOPE_SYS // second-level TBA 342 s_wait_idle 343 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 scope:SCOPE_SYS // second-level TMA 344 s_wait_idle 345 346 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 347 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 348 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 349 350L_NO_NEXT_TRAP: 351 // If not caused by trap then halt wave to prevent re-entry. 352 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 353 s_cbranch_scc1 L_TRAP_CASE 354 355 // Host trap will not cause trap re-entry. 356 s_getreg_b32 ttmp2, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 357 s_and_b32 ttmp2, ttmp2, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK 358 s_cbranch_scc1 L_EXIT_TRAP 359 s_or_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_HALT_MASK 360 361 // If the PC points to S_ENDPGM then context save will fail if STATE_PRIV.HALT is set. 362 // Rewind the PC to prevent this from occurring. 363 s_sub_u32 ttmp0, ttmp0, 0x8 364 s_subb_u32 ttmp1, ttmp1, 0x0 365 366 s_branch L_EXIT_TRAP 367 368L_TRAP_CASE: 369 // Advance past trap instruction to prevent re-entry. 370 s_add_u32 ttmp0, ttmp0, 0x4 371 s_addc_u32 ttmp1, ttmp1, 0x0 372 373L_EXIT_TRAP: 374 s_and_b32 ttmp1, ttmp1, ADDRESS_HI32_MASK 375 376#if HAVE_INSTRUCTION_FIXUP 377 s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 378 fixup_instruction() 379#endif 380 381#if HAVE_XNACK 382 restore_xnack_state_priv(s_save_tmp) 383#endif 384 385 // Restore SQ_WAVE_STATUS. 386 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 387 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 388 389 // STATE_PRIV.*BARRIER_COMPLETE may have changed since we read it. 390 // Only restore fields which the trap handler changes. 391 s_lshr_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_SCC_SHIFT 392 393#if RELAXED_SCHEDULING_IN_TRAP 394 // Assume relaxed scheduling mode after this point. 395 restore_sched_mode(ttmp2) 396#endif 397 398 s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV, SQ_WAVE_STATE_PRIV_SCC_SHIFT, \ 399 SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT - SQ_WAVE_STATE_PRIV_SCC_SHIFT + 1), s_save_state_priv 400 401 s_rfe_b64 [ttmp0, ttmp1] 402 403L_SAVE: 404 // If VGPRs have been deallocated then terminate the wavefront. 405 // It has no remaining program to run and cannot save without VGPRs. 406 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_STATUS) 407 s_bitcmp1_b32 s_save_tmp, SQ_WAVE_STATUS_NO_VGPRS_SHIFT 408 s_cbranch_scc0 L_HAVE_VGPRS 409 s_endpgm 410L_HAVE_VGPRS: 411 s_and_b32 s_save_pc_hi, s_save_pc_hi, ADDRESS_HI32_MASK 412 s_mov_b32 s_save_tmp, 0 413 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT, 1), s_save_tmp //clear saveCtx bit 414 415#if HAVE_XNACK 416 save_and_clear_xnack_state_priv(s_save_tmp) 417#endif 418 419#if HAVE_INSTRUCTION_FIXUP 420 fixup_instruction() 421#endif 422 423 /* inform SPI the readiness and wait for SPI's go signal */ 424 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 425 s_mov_b32 s_save_exec_hi, exec_hi 426 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 427 428 s_sendmsg_rtn_b64 [exec_lo, exec_hi], sendmsg(MSG_RTN_SAVE_WAVE) 429 s_wait_idle 430 431 // Save first_wave flag so we can clear high bits of save address. 432 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK 433 s_lshl_b32 s_save_tmp, s_save_tmp, (S_SAVE_PC_HI_FIRST_WAVE_SHIFT - S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT) 434 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 435 436#if HAVE_XNACK 437 s_getreg_b32 s_save_xnack_mask, hwreg(HW_REG_WAVE_XNACK_MASK) 438 s_setreg_imm32_b32 hwreg(HW_REG_WAVE_XNACK_MASK), 0 439#endif 440 441#if HAVE_BANKED_VGPRS 442 // Save and clear shader's DST/SRC0/SRC1 VGPR bank selection so we can use v[0-255]. 443 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_MODE, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE) 444 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SHIFT 445 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 446 s_mov_b32 s_save_tmp, 0 447 s_setreg_b32 hwreg(HW_REG_WAVE_MODE, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE), s_save_tmp 448#endif 449 450 // Trap temporaries must be saved via VGPR but all VGPRs are in use. 451 // There is no ttmp space to hold the resource constant for VGPR save. 452 // Save v0 by itself since it requires only two SGPRs. 453 s_mov_b32 s_save_ttmps_lo, exec_lo 454 s_and_b32 s_save_ttmps_hi, exec_hi, ADDRESS_HI32_MASK 455 s_mov_b32 exec_lo, 0xFFFFFFFF 456 s_mov_b32 exec_hi, 0xFFFFFFFF 457 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] scope:SCOPE_SYS 458 v_mov_b32 v0, 0x0 459 s_mov_b32 exec_lo, s_save_ttmps_lo 460 s_mov_b32 exec_hi, s_save_ttmps_hi 461 462 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 463 // ttmp SR memory offset: 464 // - gfx12: size(VGPR)+size(SGPR)+0x40 465 // - gfx12.5: size(VGPR)+size(SGPR)-0x40 466 get_wave_size2(s_save_ttmps_hi) 467 get_vgpr_size_bytes(s_save_ttmps_lo, s_save_ttmps_hi) 468 s_and_b32 s_save_ttmps_hi, s_save_spi_init_hi, ADDRESS_HI32_MASK 469 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, (get_sgpr_size_bytes() + TTMP_SR_OFFSET_FROM_HWREG) 470 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 471 s_addc_u32 s_save_ttmps_hi, s_save_ttmps_hi, 0x0 472 473 v_writelane_b32 v0, ttmp4, 0x4 474 v_writelane_b32 v0, ttmp5, 0x5 475 v_writelane_b32 v0, ttmp6, 0x6 476 v_writelane_b32 v0, ttmp7, 0x7 477 v_writelane_b32 v0, ttmp8, 0x8 478 v_writelane_b32 v0, ttmp9, 0x9 479 v_writelane_b32 v0, ttmp10, 0xA 480 v_writelane_b32 v0, ttmp11, 0xB 481 v_writelane_b32 v0, ttmp13, 0xD 482 v_writelane_b32 v0, exec_lo, 0xE 483 v_writelane_b32 v0, exec_hi, 0xF 484 485 s_mov_b32 exec_lo, 0x3FFF 486 s_mov_b32 exec_hi, 0x0 487 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] scope:SCOPE_SYS 488 v_readlane_b32 ttmp14, v0, 0xE 489 v_readlane_b32 ttmp15, v0, 0xF 490 s_mov_b32 exec_lo, ttmp14 491 s_mov_b32 exec_hi, ttmp15 492 493 s_mov_b32 s_save_base_addr_lo, s_save_spi_init_lo 494 s_and_b32 s_save_base_addr_hi, s_save_spi_init_hi, ADDRESS_HI32_MASK 495 s_mov_b32 s_save_m0, m0 496 497 get_wave_size2(s_wave_size) 498 499 /* save first 4 VGPRs, needed for SGPR save */ 500 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 501 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 502 s_and_b32 m0, m0, 1 503 s_cmp_eq_u32 m0, 1 504 s_cbranch_scc1 L_ENABLE_SAVE_4VGPR_EXEC_HI 505 s_mov_b32 exec_hi, 0x00000000 506 s_branch L_SAVE_4VGPR_WAVE32 507L_ENABLE_SAVE_4VGPR_EXEC_HI: 508 s_mov_b32 exec_hi, 0xFFFFFFFF 509 s_branch L_SAVE_4VGPR_WAVE64 510L_SAVE_4VGPR_WAVE32: 511 // VGPR Allocated in 4-GPR granularity 512 global_store_addtid_b32 v1, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:128 513 global_store_addtid_b32 v2, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:128*2 514 global_store_addtid_b32 v3, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:128*3 515 s_branch L_SAVE_HWREG 516 517L_SAVE_4VGPR_WAVE64: 518 // VGPR Allocated in 4-GPR granularity 519 global_store_addtid_b32 v1, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:256 520 global_store_addtid_b32 v2, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:256*2 521 global_store_addtid_b32 v3, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:256*3 522 523 /* save HW registers */ 524 525L_SAVE_HWREG: 526 // HWREG SR memory offset : size(VGPR)+size(SGPR) 527 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 528 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() 529 530 v_mov_b32 v0, 0x0 //Offset[31:0] from buffer resource 531 v_mov_b32 v1, 0x0 //Offset[63:32] from buffer resource 532 v_mov_b32 v2, 0x0 //Set of SGPRs for TCP store 533 s_mov_b32 m0, 0x0 //Next lane of v2 to write to 534 535 write_hwreg_to_v2(s_save_m0) 536 537 // Ensure no further changes to barrier or LDS state. 538 // STATE_PRIV.*BARRIER_COMPLETE may change up to this point. 539 wait_trap_barriers(s_save_tmp, s_save_m0, 1) 540 541 // Re-read final state of *BARRIER_COMPLETE fields for save. 542 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_STATE_PRIV) 543 s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_STATE_PRIV_ALL_BARRIER_COMPLETE_MASK 544 s_andn2_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_ALL_BARRIER_COMPLETE_MASK 545 s_or_b32 s_save_state_priv, s_save_state_priv, s_save_tmp 546 547 write_hwreg_to_v2(s_save_pc_lo) 548 s_and_b32 s_save_tmp, s_save_pc_hi, ADDRESS_HI32_MASK 549 write_hwreg_to_v2(s_save_tmp) 550 write_hwreg_to_v2(s_save_exec_lo) 551#if WAVE32_ONLY 552 s_mov_b32 s_save_tmp, 0 553 write_hwreg_to_v2(s_save_tmp) 554#else 555 write_hwreg_to_v2(s_save_exec_hi) 556#endif 557 write_hwreg_to_v2(s_save_state_priv) 558 559 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 560 write_hwreg_to_v2(s_save_tmp) 561 562#if HAVE_XNACK 563 write_hwreg_to_v2(s_save_xnack_mask) 564#else 565 s_mov_b32 s_save_tmp, 0 566 write_hwreg_to_v2(s_save_tmp) 567#endif 568 569 s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_MODE) 570 571#if HAVE_BANKED_VGPRS 572 s_bfe_u32 s_save_tmp, s_save_pc_hi, (S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SHIFT | (S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SIZE << 0x10)) 573 s_lshl_b32 s_save_tmp, s_save_tmp, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT 574 s_or_b32 s_save_m0, s_save_m0, s_save_tmp 575#endif 576 577 write_hwreg_to_v2(s_save_m0) 578 579 s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_SCRATCH_BASE_LO) 580 write_hwreg_to_v2(s_save_m0) 581 582 s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_SCRATCH_BASE_HI) 583 write_hwreg_to_v2(s_save_m0) 584 585 s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_EXCP_FLAG_USER) 586 write_hwreg_to_v2(s_save_m0) 587 588 s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_TRAP_CTRL) 589 write_hwreg_to_v2(s_save_m0) 590 591 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_STATUS) 592 write_hwreg_to_v2(s_save_tmp) 593 594 s_get_barrier_state s_save_tmp, -1 595 s_wait_kmcnt (0) 596 write_hwreg_to_v2(s_save_tmp) 597 598#if HAVE_CLUSTER_BARRIER 599 s_sendmsg_rtn_b32 s_save_tmp, sendmsg(MSG_RTN_GET_CLUSTER_BARRIER_STATE) 600 s_wait_kmcnt 0 601 write_hwreg_to_v2(s_save_tmp) 602#endif 603 604#if ASIC_FAMILY >= CHIP_GC_12_0_3 605 s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_SCHED_MODE) 606 write_hwreg_to_v2(s_save_tmp) 607#endif 608 609#if ! SAVE_TTMPS_IN_SGPR_BLOCK 610 // Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this. 611 s_mov_b32 exec_lo, 0xFFFF 612#else 613 // All 128 bytes are available for HWREGs. 614 s_mov_b32 exec_lo, 0xFFFFFFFF 615#endif 616 s_mov_b32 exec_hi, 0x0 617 s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset 618 s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 619 global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS 620 621 // Write SGPRs with 32 VGPR lanes. This works in wave32 and wave64 mode. 622 s_mov_b32 exec_lo, 0xFFFFFFFF 623 624#if NUM_NAMED_BARRIERS 625 v_mov_b32 v2, 0 626 627 for var bar_idx = 0; bar_idx < NUM_NAMED_BARRIERS; bar_idx ++ 628 s_get_barrier_state s_save_tmp, (bar_idx + 1) 629 s_wait_kmcnt 0 630 v_writelane_b32 v2, s_save_tmp, bar_idx 631 end 632 633 global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:NAMED_BARRIERS_SR_OFFSET_FROM_HWREG 634#endif 635 636 /* save SGPRs */ 637 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 638 639 // SGPR SR memory offset : size(VGPR) 640 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 641 642 s_mov_b32 ttmp13, 0x0 //next VGPR lane to copy SGPR into 643 644 s_mov_b32 m0, 0x0 //SGPR initial index value =0 645 s_nop 0x0 //Manually inserted wait states 646L_SAVE_SGPR_LOOP: 647 // SGPR is allocated in 16 SGPR granularity 648 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 649 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 650 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 651 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 652 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 653 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 654 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 655 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 656 657 write_16sgpr_to_v2(s0) 658 659 s_cmp_eq_u32 ttmp13, 0x20 //have 32 VGPR lanes filled? 660 s_cbranch_scc0 L_SAVE_SGPR_SKIP_TCP_STORE 661 662 s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset 663 s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 664 global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS 665 s_add_u32 s_save_mem_offset, s_save_mem_offset, 0x80 666 s_mov_b32 ttmp13, 0x0 667 v_mov_b32 v2, 0x0 668L_SAVE_SGPR_SKIP_TCP_STORE: 669 670 s_add_u32 m0, m0, 16 //next sgpr index 671 s_cmp_lt_u32 m0, 96 //scc = (m0 < first 96 SGPR) ? 1 : 0 672 s_cbranch_scc1 L_SAVE_SGPR_LOOP //first 96 SGPR save is complete? 673 674 //save the rest 12 SGPR 675 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 676 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 677 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 678 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 679 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 680 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 681 write_12sgpr_to_v2(s0) 682 683#if SAVE_TTMPS_IN_SGPR_BLOCK 684 // Last 16 dwords of the SGPR block already contain the TTMPS. Make 685 // sure to not override them. 686 s_mov_b32 exec_lo, 0xFFFF 687#endif 688 s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset 689 s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 690 global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS 691 692 /* save LDS */ 693 694L_SAVE_LDS: 695 // Change EXEC to all threads... 696 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 697 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 698 s_and_b32 m0, m0, 1 699 s_cmp_eq_u32 m0, 1 700 s_cbranch_scc1 L_ENABLE_SAVE_LDS_EXEC_HI 701 s_mov_b32 exec_hi, 0x00000000 702 s_branch L_SAVE_LDS_NORMAL 703L_ENABLE_SAVE_LDS_EXEC_HI: 704 s_mov_b32 exec_hi, 0xFFFFFFFF 705L_SAVE_LDS_NORMAL: 706 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 707 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 708 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 709 710 s_and_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK 711 s_cbranch_scc0 L_SAVE_LDS_DONE 712 713 // first wave do LDS save; 714 715 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, SQ_WAVE_LDS_ALLOC_GRANULARITY 716 717 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 718 // 719 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 720 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() 721 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 722 723 //load 0~63*4(byte address) to vgpr v0 724 v_mbcnt_lo_u32_b32 v0, -1, 0 725 v_mbcnt_hi_u32_b32 v0, -1, v0 726 v_mul_u32_u24 v0, 4, v0 727 728 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 729 s_and_b32 m0, m0, 1 730 s_cmp_eq_u32 m0, 1 731 s_mov_b32 m0, 0x0 732 s_cbranch_scc1 L_SAVE_LDS_W64 733 734L_SAVE_LDS_W32: 735 s_mov_b32 s3, 128 736 s_nop 0 737 s_nop 0 738 s_nop 0 739L_SAVE_LDS_LOOP_W32: 740 ds_read_b32 v1, v0 741 s_wait_idle 742 s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset 743 s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 744 global_store_addtid_b32 v1, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS 745 746 s_add_u32 m0, m0, s3 //every buffer_store_lds does 128 bytes 747 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 748 v_add_nc_u32 v0, v0, 128 //mem offset increased by 128 bytes 749 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 750 s_cbranch_scc1 L_SAVE_LDS_LOOP_W32 //LDS save is complete? 751 752 s_branch L_SAVE_LDS_DONE 753 754L_SAVE_LDS_W64: 755 s_mov_b32 s3, 256 756 s_nop 0 757 s_nop 0 758 s_nop 0 759L_SAVE_LDS_LOOP_W64: 760 ds_read_b32 v1, v0 761 s_wait_idle 762 s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset 763 s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 764 global_store_addtid_b32 v1, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS 765 766 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 767 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 768 v_add_nc_u32 v0, v0, 256 //mem offset increased by 256 bytes 769 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 770 s_cbranch_scc1 L_SAVE_LDS_LOOP_W64 //LDS save is complete? 771 772L_SAVE_LDS_DONE: 773 /* save VGPRs - set the Rest VGPRs */ 774L_SAVE_VGPR: 775 // VGPR SR memory offset: 0 776 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 777 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 778 s_and_b32 m0, m0, 1 779 s_cmp_eq_u32 m0, 1 780 s_cbranch_scc1 L_ENABLE_SAVE_VGPR_EXEC_HI 781 s_mov_b32 s_save_mem_offset, (0+128*4) // for the rest VGPRs 782 s_mov_b32 exec_hi, 0x00000000 783 s_branch L_SAVE_VGPR_NORMAL 784L_ENABLE_SAVE_VGPR_EXEC_HI: 785 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 786 s_mov_b32 exec_hi, 0xFFFFFFFF 787L_SAVE_VGPR_NORMAL: 788 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_WAVE_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 789 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 790 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 791 //determine it is wave32 or wave64 792 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 793 s_and_b32 m0, m0, 1 794 s_cmp_eq_u32 m0, 1 795 s_cbranch_scc1 L_SAVE_VGPR_WAVE64 796 797 // VGPR Allocated in 4-GPR granularity 798 799 // VGPR store using dw burst 800 s_mov_b32 m0, 0x4 //VGPR initial index value =4 801 s_cmp_lt_u32 m0, s_save_alloc_size 802 s_cbranch_scc0 L_SAVE_VGPR_END 803 804L_SAVE_VGPR_W32_LOOP: 805 v_movrels_b32 v0, v0 //v0 = v[0+m0] 806 v_movrels_b32 v1, v1 //v1 = v[1+m0] 807 v_movrels_b32 v2, v2 //v2 = v[2+m0] 808 v_movrels_b32 v3, v3 //v3 = v[3+m0] 809 810 s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset 811 s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 812 global_store_addtid_b32 v0, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS 813 global_store_addtid_b32 v1, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:128 814 global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:128*2 815 global_store_addtid_b32 v3, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:128*3 816 817 s_add_u32 m0, m0, 4 //next vgpr index 818 s_add_u32 s_save_mem_offset, s_save_mem_offset, 128*4 //every buffer_store_dword does 128 bytes 819 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 820 s_cbranch_scc1 L_SAVE_VGPR_W32_LOOP //VGPR save is complete? 821 822 s_branch L_SAVE_VGPR_END 823 824L_SAVE_VGPR_WAVE64: 825 // VGPR store using dw burst 826 s_mov_b32 m0, 0x4 //VGPR initial index value =4 827 s_cmp_lt_u32 m0, s_save_alloc_size 828 s_cbranch_scc0 L_SAVE_VGPR_END 829 830L_SAVE_VGPR_W64_LOOP: 831 v_movrels_b32 v0, v0 //v0 = v[0+m0] 832 v_movrels_b32 v1, v1 //v1 = v[1+m0] 833 v_movrels_b32 v2, v2 //v2 = v[2+m0] 834 v_movrels_b32 v3, v3 //v3 = v[3+m0] 835 836 s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset 837 s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 838 global_store_addtid_b32 v0, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS 839 global_store_addtid_b32 v1, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:256 840 global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:256*2 841 global_store_addtid_b32 v3, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:256*3 842 843 s_add_u32 m0, m0, 4 //next vgpr index 844 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 845 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 846 s_cbranch_scc1 L_SAVE_VGPR_W64_LOOP //VGPR save is complete? 847 848L_SAVE_VGPR_END: 849 s_branch L_END_PGM 850 851L_RESTORE: 852 s_mov_b32 s_restore_base_addr_lo, s_restore_spi_init_lo 853 s_and_b32 s_restore_base_addr_hi, s_restore_spi_init_hi, ADDRESS_HI32_MASK 854 855 // Save s_restore_spi_init_hi for later use. 856 s_mov_b32 s_restore_spi_init_hi_save, s_restore_spi_init_hi 857 858 //determine it is wave32 or wave64 859 get_wave_size2(s_restore_size) 860 861 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 862 s_cbranch_scc0 L_RESTORE_VGPR 863 864 /* restore LDS */ 865L_RESTORE_LDS: 866 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 867 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 868 s_and_b32 m0, m0, 1 869 s_cmp_eq_u32 m0, 1 870 s_cbranch_scc1 L_ENABLE_RESTORE_LDS_EXEC_HI 871 s_mov_b32 exec_hi, 0x00000000 872 s_branch L_RESTORE_LDS_NORMAL 873L_ENABLE_RESTORE_LDS_EXEC_HI: 874 s_mov_b32 exec_hi, 0xFFFFFFFF 875L_RESTORE_LDS_NORMAL: 876 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 877 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 878 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 879 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, SQ_WAVE_LDS_ALLOC_GRANULARITY 880 881 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 882 // 883 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 884 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 885 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() 886 887 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 888 s_and_b32 m0, m0, 1 889 s_cmp_eq_u32 m0, 1 890 s_mov_b32 m0, 0x0 891 892 v_mbcnt_lo_u32_b32 v1, -1, 0 893 v_mbcnt_hi_u32_b32 v1, -1, v1 894 v_lshlrev_b32 v1, 2, v1 // 0, 4, 8, ... 124 (W32) or 252 (W64) 895 896 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 897 898L_RESTORE_LDS_LOOP_W32: 899 s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset 900 s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 901 global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS 902 s_wait_idle 903 ds_store_b32 v1, v0 904 v_add_nc_u32 v1, v1, 128 905 s_add_u32 m0, m0, 128 // 128 DW 906 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 //mem offset increased by 128DW 907 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 908 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W32 //LDS restore is complete? 909 s_branch L_RESTORE_VGPR 910 911L_RESTORE_LDS_LOOP_W64: 912 s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset 913 s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 914 global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS 915 s_wait_idle 916 ds_store_b32 v1, v0 917 v_add_nc_u32 v1, v1, 256 918 s_add_u32 m0, m0, 256 // 256 DW 919 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256 //mem offset increased by 256DW 920 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 921 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 //LDS restore is complete? 922 923 /* restore VGPRs */ 924L_RESTORE_VGPR: 925 // VGPR SR memory offset : 0 926 s_mov_b32 s_restore_mem_offset, 0x0 927 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 928 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 929 s_and_b32 m0, m0, 1 930 s_cmp_eq_u32 m0, 1 931 s_cbranch_scc1 L_ENABLE_RESTORE_VGPR_EXEC_HI 932 s_mov_b32 exec_hi, 0x00000000 933 s_branch L_RESTORE_VGPR_NORMAL 934L_ENABLE_RESTORE_VGPR_EXEC_HI: 935 s_mov_b32 exec_hi, 0xFFFFFFFF 936L_RESTORE_VGPR_NORMAL: 937 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_WAVE_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 938 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 939 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 940 //determine it is wave32 or wave64 941 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 942 s_and_b32 m0, m0, 1 943 s_cmp_eq_u32 m0, 1 944 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64 945 946 // VGPR load using dw burst 947 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 948 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 949 s_mov_b32 m0, 4 //VGPR initial index value = 4 950 951L_RESTORE_VGPR_WAVE32_LOOP: 952 s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset 953 s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 954 global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS 955 global_load_addtid_b32 v1, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128 956 global_load_addtid_b32 v2, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128*2 957 global_load_addtid_b32 v3, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128*3 958 s_wait_idle 959 v_movreld_b32 v0, v0 //v[0+m0] = v0 960 v_movreld_b32 v1, v1 961 v_movreld_b32 v2, v2 962 v_movreld_b32 v3, v3 963 s_add_u32 m0, m0, 4 //next vgpr index 964 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 //every buffer_load_dword does 128 bytes 965 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 966 s_cbranch_scc1 L_RESTORE_VGPR_WAVE32_LOOP //VGPR restore (except v0) is complete? 967 968 /* VGPR restore on v0 */ 969 s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset_save 970 s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 971 global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS 972 global_load_addtid_b32 v1, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128 973 global_load_addtid_b32 v2, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128*2 974 global_load_addtid_b32 v3, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128*3 975 s_wait_idle 976 977 s_branch L_RESTORE_SGPR 978 979L_RESTORE_VGPR_WAVE64: 980 // VGPR load using dw burst 981 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v4, v0 will be the last 982 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 983 s_mov_b32 m0, 4 //VGPR initial index value = 4 984 s_cmp_lt_u32 m0, s_restore_alloc_size 985 s_cbranch_scc0 L_RESTORE_V0 986 987L_RESTORE_VGPR_WAVE64_LOOP: 988 s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset 989 s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 990 global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS 991 global_load_addtid_b32 v1, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256 992 global_load_addtid_b32 v2, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256*2 993 global_load_addtid_b32 v3, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256*3 994 s_wait_idle 995 v_movreld_b32 v0, v0 //v[0+m0] = v0 996 v_movreld_b32 v1, v1 997 v_movreld_b32 v2, v2 998 v_movreld_b32 v3, v3 999 s_add_u32 m0, m0, 4 //next vgpr index 1000 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 1001 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 1002 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? 1003 1004 /* VGPR restore on v0 */ 1005L_RESTORE_V0: 1006 s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset_save 1007 s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 1008 global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS 1009 global_load_addtid_b32 v1, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256 1010 global_load_addtid_b32 v2, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256*2 1011 global_load_addtid_b32 v3, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256*3 1012 s_wait_idle 1013 1014 /* restore SGPRs */ 1015 //will be 2+8+16*6 1016 // SGPR SR memory offset : size(VGPR) 1017L_RESTORE_SGPR: 1018 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 1019 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 1020 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 24*4 // s[104:107] 1021 s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset 1022 s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 1023 1024 s_mov_b32 m0, s_sgpr_save_num 1025 1026 s_load_b128 s0, [s_restore_addr_lo, s_restore_addr_hi], 0x0 scope:SCOPE_SYS 1027 s_wait_idle 1028 1029 s_sub_u32 m0, m0, 4 // Restore from S[0] to S[104] 1030 s_nop 0 // hazard SALU M0=> S_MOVREL 1031 1032 s_movreld_b64 s0, s0 //s[0+m0] = s0 1033 s_movreld_b64 s2, s2 1034 1035 s_sub_co_u32 s_restore_addr_lo, s_restore_addr_lo, 8*4 // s[96:103] 1036 s_sub_co_ci_u32 s_restore_addr_hi, s_restore_addr_hi, 0 1037 s_load_b256 s0, [s_restore_addr_lo, s_restore_addr_hi], 0x0 scope:SCOPE_SYS 1038 s_wait_idle 1039 1040 s_sub_u32 m0, m0, 8 // Restore from S[0] to S[96] 1041 s_nop 0 // hazard SALU M0=> S_MOVREL 1042 1043 s_movreld_b64 s0, s0 //s[0+m0] = s0 1044 s_movreld_b64 s2, s2 1045 s_movreld_b64 s4, s4 1046 s_movreld_b64 s6, s6 1047 1048 L_RESTORE_SGPR_LOOP: 1049 s_sub_co_u32 s_restore_addr_lo, s_restore_addr_lo, 16*4 // s[0,16,32,48,64,80] 1050 s_sub_co_ci_u32 s_restore_addr_hi, s_restore_addr_hi, 0 1051 s_load_b512 s0, [s_restore_addr_lo, s_restore_addr_hi], 0x0 scope:SCOPE_SYS 1052 s_wait_idle 1053 1054 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 1055 s_nop 0 // hazard SALU M0=> S_MOVREL 1056 1057 s_movreld_b64 s0, s0 //s[0+m0] = s0 1058 s_movreld_b64 s2, s2 1059 s_movreld_b64 s4, s4 1060 s_movreld_b64 s6, s6 1061 s_movreld_b64 s8, s8 1062 s_movreld_b64 s10, s10 1063 s_movreld_b64 s12, s12 1064 s_movreld_b64 s14, s14 1065 1066 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_sgpr_save_num) ? 1 : 0 1067 s_cbranch_scc0 L_RESTORE_SGPR_LOOP 1068 1069 // s_barrier with STATE_PRIV.TRAP_AFTER_INST=1, STATUS.PRIV=1 incorrectly asserts debug exception. 1070 // Clear DEBUG_EN before and restore MODE after the barrier. 1071 s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE), 0 1072 1073 /* restore HW registers */ 1074L_RESTORE_HWREG: 1075 // HWREG SR memory offset : size(VGPR)+size(SGPR) 1076 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 1077 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 1078 s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset 1079 s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 1080 1081 // Restore s_restore_spi_init_hi before the saved value gets clobbered. 1082 s_mov_b32 s_restore_spi_init_hi, s_restore_spi_init_hi_save 1083 1084 s_load_b32 s_restore_m0, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS 1085 s_load_b32 s_restore_pc_lo, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x4 1086 s_load_b32 s_restore_pc_hi, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x8 1087 s_load_b32 s_restore_exec_lo, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0xC 1088 s_load_b32 s_restore_exec_hi, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x10 1089 s_load_b32 s_restore_state_priv, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x14 1090 s_load_b32 s_restore_excp_flag_priv, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x18 1091 s_load_b32 s_restore_xnack_mask, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x1C 1092 s_load_b32 s_restore_mode, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x20 1093 s_load_b32 s_restore_flat_scratch, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x24 1094 s_wait_idle 1095 1096 s_setreg_b32 hwreg(HW_REG_WAVE_SCRATCH_BASE_LO), s_restore_flat_scratch 1097 1098 s_load_b32 s_restore_flat_scratch, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x28 1099 s_wait_idle 1100 1101 s_setreg_b32 hwreg(HW_REG_WAVE_SCRATCH_BASE_HI), s_restore_flat_scratch 1102 1103 s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x2C 1104 s_wait_idle 1105 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_USER), s_restore_tmp 1106 1107 s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x30 1108 s_wait_idle 1109 s_setreg_b32 hwreg(HW_REG_WAVE_TRAP_CTRL), s_restore_tmp 1110 1111 // Only the first wave needs to restore group barriers. 1112 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 1113 s_cbranch_scc0 L_SKIP_GROUP_BARRIER_RESTORE 1114 1115 // Skip over WAVE_STATUS, since there is no state to restore from it 1116 1117 s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x38 1118 s_wait_idle 1119 1120 // Skip group barriers if wave is not part of a group. 1121 s_bitcmp1_b32 s_restore_tmp, BARRIER_STATE_VALID_OFFSET 1122 s_cbranch_scc0 L_SKIP_GROUP_BARRIER_RESTORE 1123 1124 // Restore workgroup barrier signal count. 1125 restore_barrier_signal_count(-1) 1126 1127#if NUM_NAMED_BARRIERS 1128 s_mov_b32 s_restore_mem_offset, NAMED_BARRIERS_SR_OFFSET_FROM_HWREG 1129 s_mov_b32 m0, 1 1130 1131L_RESTORE_NAMED_BARRIER_LOOP: 1132 s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], s_restore_mem_offset scope:SCOPE_SYS 1133 s_wait_kmcnt 0 1134 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 0x4 1135 1136 // Restore named barrier member count. 1137 s_bfe_u32 exec_lo, s_restore_tmp, (BARRIER_STATE_MEMBER_OFFSET | (BARRIER_STATE_MEMBER_SIZE << 16)) 1138 s_lshl_b32 exec_lo, exec_lo, S_BARRIER_INIT_MEMBERCNT_SHIFT 1139 s_or_b32 m0, m0, exec_lo 1140 s_barrier_init m0 1141 s_andn2_b32 m0, m0, S_BARRIER_INIT_MEMBERCNT_MASK 1142 1143 // Restore named barrier signal count. 1144 restore_barrier_signal_count(m0) 1145 1146 s_add_u32 m0, m0, 1 1147 s_cmp_gt_u32 m0, NUM_NAMED_BARRIERS 1148 s_cbranch_scc0 L_RESTORE_NAMED_BARRIER_LOOP 1149#endif 1150 1151L_SKIP_GROUP_BARRIER_RESTORE: 1152#if HAVE_CLUSTER_BARRIER 1153 s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x3C 1154 s_wait_kmcnt 0 1155 1156 // Skip cluster barrier restore if wave is not part of a cluster. 1157 s_bitcmp1_b32 s_restore_tmp, BARRIER_STATE_VALID_OFFSET 1158 s_cbranch_scc0 L_SKIP_CLUSTER_BARRIER_RESTORE 1159 1160 // Only the first wave in the group signals the trap cluster barrier. 1161 s_bitcmp1_b32 s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT 1162 s_cbranch_scc0 L_SKIP_TRAP_CLUSTER_BARRIER_SIGNAL 1163 1164 // Clear SCC: s_barrier_signal_isfirst -4 writes SCC=>1 but not SCC=>0. 1165 s_cmp_eq_u32 0, 1 1166 s_barrier_signal_isfirst -4 1167L_SKIP_TRAP_CLUSTER_BARRIER_SIGNAL: 1168 s_barrier_wait -4 1169 1170 // Only the first wave in the cluster restores the barrier. 1171 s_cbranch_scc0 L_SKIP_CLUSTER_BARRIER_RESTORE 1172 1173 // Restore cluster barrier signal count. 1174 restore_barrier_signal_count(-3) 1175L_SKIP_CLUSTER_BARRIER_RESTORE: 1176#endif 1177 1178#if ASIC_FAMILY >= CHIP_GC_12_0_3 1179 s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x40 1180 s_wait_kmcnt 0 1181 s_setreg_b32 hwreg(HW_REG_WAVE_SCHED_MODE), s_restore_tmp 1182#endif 1183 1184 s_mov_b32 m0, s_restore_m0 1185 s_mov_b32 exec_lo, s_restore_exec_lo 1186 s_mov_b32 exec_hi, s_restore_exec_hi 1187 1188#if HAVE_XNACK 1189 s_setreg_b32 hwreg(HW_REG_WAVE_XNACK_MASK), s_restore_xnack_mask 1190#endif 1191 1192 // EXCP_FLAG_PRIV.SAVE_CONTEXT and HOST_TRAP may have changed. 1193 // Only restore the other fields to avoid clobbering them. 1194 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, 0, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_1_SIZE), s_restore_excp_flag_priv 1195 s_lshr_b32 s_restore_excp_flag_priv, s_restore_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT 1196 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SIZE), s_restore_excp_flag_priv 1197 s_lshr_b32 s_restore_excp_flag_priv, s_restore_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT - SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT 1198 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SIZE), s_restore_excp_flag_priv 1199 1200 s_setreg_b32 hwreg(HW_REG_WAVE_MODE), s_restore_mode 1201 1202 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 1203 // ttmp SR memory offset : 1204 // - gfx12: size(VGPR)+size(SGPR)+0x40 1205 // - gfx12.5: size(VGPR)+size(SGPR)-0x40 1206 get_vgpr_size_bytes(s_restore_ttmps_lo, s_restore_size) 1207 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, (get_sgpr_size_bytes() + TTMP_SR_OFFSET_FROM_HWREG) 1208 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_base_addr_lo 1209 s_addc_u32 s_restore_ttmps_hi, s_restore_base_addr_hi, 0x0 1210 s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x10 scope:SCOPE_SYS 1211 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x20 scope:SCOPE_SYS 1212 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x34 scope:SCOPE_SYS 1213 s_wait_idle 1214 1215#if HAVE_XNACK 1216 restore_xnack_state_priv(s_restore_tmp) 1217#endif 1218 1219 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, ADDRESS_HI32_MASK //Do it here in order not to affect STATUS 1220 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 1221 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 1222 1223#if RELAXED_SCHEDULING_IN_TRAP 1224 // Assume relaxed scheduling mode after this point. 1225 restore_sched_mode(s_restore_tmp) 1226#endif 1227 1228 s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV), s_restore_state_priv // SCC is included, which is changed by previous salu 1229 1230 // Make barrier and LDS state visible to all waves in the group/cluster. 1231 // STATE_PRIV.*BARRIER_COMPLETE may change after this point. 1232 wait_trap_barriers(s_restore_tmp, 0, 0) 1233 1234#if HAVE_CLUSTER_BARRIER 1235 // SCC is changed by wait_trap_barriers, restore it separately. 1236 s_lshr_b32 s_restore_state_priv, s_restore_state_priv, SQ_WAVE_STATE_PRIV_SCC_SHIFT 1237 s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV, SQ_WAVE_STATE_PRIV_SCC_SHIFT, 1), s_restore_state_priv 1238#endif 1239 1240 s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1241 1242L_END_PGM: 1243 // Make sure that no wave of the group/cluster can exit the trap handler 1244 // before the group/cluster barrier state is saved. 1245 wait_trap_barriers(s_restore_tmp, 0, 0) 1246 1247 s_endpgm_saved 1248end 1249 1250function write_hwreg_to_v2(s) 1251 // Copy into VGPR for later TCP store. 1252 v_writelane_b32 v2, s, m0 1253 s_add_u32 m0, m0, 0x1 1254end 1255 1256 1257function write_16sgpr_to_v2(s) 1258 // Copy into VGPR for later TCP store. 1259 for var sgpr_idx = 0; sgpr_idx < 16; sgpr_idx ++ 1260 v_writelane_b32 v2, s[sgpr_idx], ttmp13 1261 s_add_u32 ttmp13, ttmp13, 0x1 1262 end 1263end 1264 1265function write_12sgpr_to_v2(s) 1266 // Copy into VGPR for later TCP store. 1267 for var sgpr_idx = 0; sgpr_idx < 12; sgpr_idx ++ 1268 v_writelane_b32 v2, s[sgpr_idx], ttmp13 1269 s_add_u32 ttmp13, ttmp13, 0x1 1270 end 1271end 1272 1273function get_vgpr_size_bytes(s_vgpr_size_byte, s_size) 1274 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_WAVE_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 1275 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1276 s_bitcmp1_b32 s_size, S_WAVE_SIZE 1277 s_cbranch_scc1 L_ENABLE_SHIFT_W64 1278 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+7) //Number of VGPRs = (vgpr_size + 1) * 4 * 32 * 4 (non-zero value) 1279 s_branch L_SHIFT_DONE 1280L_ENABLE_SHIFT_W64: 1281 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) 1282L_SHIFT_DONE: 1283end 1284 1285function get_sgpr_size_bytes 1286 return 512 1287end 1288 1289function get_hwreg_size_bytes 1290#if ASIC_FAMILY >= CHIP_GC_12_0_3 1291 return 512 1292#else 1293 return 128 1294#endif 1295end 1296 1297function get_wave_size2(s_reg) 1298 s_getreg_b32 s_reg, hwreg(HW_REG_WAVE_STATUS,SQ_WAVE_STATUS_WAVE64_SHIFT,SQ_WAVE_STATUS_WAVE64_SIZE) 1299 s_lshl_b32 s_reg, s_reg, S_WAVE_SIZE 1300end 1301 1302#if HAVE_XNACK 1303function save_and_clear_xnack_state_priv(s_tmp) 1304 // Preserve and clear XNACK state before issuing further translations. 1305 // Save XNACK_STATE_PRIV.{FIRST_REPLAY, REPLAY_W64H, FXPTR} into ttmp11[22:14]. 1306 s_andn2_b32 ttmp11, ttmp11, (TTMP11_FIRST_REPLAY_MASK | TTMP11_REPLAY_W64H_MASK | TTMP11_FXPTR_MASK) 1307 1308 s_getreg_b32 s_tmp, hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SIZE) 1309 s_lshl_b32 s_tmp, s_tmp, TTMP11_FIRST_REPLAY_SHIFT 1310 s_or_b32 ttmp11, ttmp11, s_tmp 1311 1312 s_getreg_b32 s_tmp, hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SIZE) 1313 s_lshl_b32 s_tmp, s_tmp, TTMP11_REPLAY_W64H_SHIFT 1314 s_or_b32 ttmp11, ttmp11, s_tmp 1315 1316 s_getreg_b32 s_tmp, hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SIZE) 1317 s_lshl_b32 s_tmp, s_tmp, TTMP11_FXPTR_SHIFT 1318 s_or_b32 ttmp11, ttmp11, s_tmp 1319 1320 s_setreg_imm32_b32 hwreg(HW_REG_WAVE_XNACK_STATE_PRIV), 0 1321end 1322 1323function restore_xnack_state_priv(s_tmp) 1324 s_lshr_b32 s_tmp, ttmp11, TTMP11_FIRST_REPLAY_SHIFT 1325 s_setreg_b32 hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SIZE), s_tmp 1326 1327 s_lshr_b32 s_tmp, ttmp11, TTMP11_REPLAY_W64H_SHIFT 1328 s_setreg_b32 hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SIZE), s_tmp 1329 1330 s_lshr_b32 s_tmp, ttmp11, TTMP11_FXPTR_SHIFT 1331 s_setreg_b32 hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SIZE), s_tmp 1332end 1333#endif 1334 1335function wait_trap_barriers(s_tmp1, s_tmp2, serialize_wa) 1336#if HAVE_CLUSTER_BARRIER 1337 // If not in a WG then wave cannot use s_barrier_signal_isfirst. 1338 s_getreg_b32 s_tmp1, hwreg(HW_REG_WAVE_STATUS) 1339 s_bitcmp0_b32 s_tmp1, SQ_WAVE_STATUS_IN_WG_SHIFT 1340 s_cbranch_scc1 L_TRAP_CLUSTER_BARRIER_SIGNAL 1341 1342 s_barrier_signal_isfirst -2 1343 s_barrier_wait -2 1344 1345 // Only the first wave in the group signals the trap cluster barrier. 1346 s_cbranch_scc0 L_SKIP_TRAP_CLUSTER_BARRIER_SIGNAL 1347 1348L_TRAP_CLUSTER_BARRIER_SIGNAL: 1349 s_barrier_signal -4 1350 1351L_SKIP_TRAP_CLUSTER_BARRIER_SIGNAL: 1352 s_barrier_wait -4 1353 1354#if CLUSTER_BARRIER_SERIALIZE_WORKAROUND 1355if serialize_wa 1356 // Trap cluster barrier may complete with a user cluster barrier in-flight. 1357 // This is indicated if user cluster member count and signal count are equal. 1358L_WAIT_USER_CLUSTER_BARRIER_COMPLETE: 1359 s_sendmsg_rtn_b32 s_tmp1, sendmsg(MSG_RTN_GET_CLUSTER_BARRIER_STATE) 1360 s_wait_kmcnt 0 1361 s_bitcmp0_b32 s_tmp1, BARRIER_STATE_VALID_OFFSET 1362 s_cbranch_scc1 L_NOT_IN_CLUSTER 1363 1364 s_bfe_u32 s_tmp2, s_tmp1, (BARRIER_STATE_MEMBER_OFFSET | (BARRIER_STATE_MEMBER_SIZE << 0x10)) 1365 s_bfe_u32 s_tmp1, s_tmp1, (BARRIER_STATE_SIGNAL_OFFSET | (BARRIER_STATE_SIGNAL_SIZE << 0x10)) 1366 s_cmp_eq_u32 s_tmp1, s_tmp2 1367 s_cbranch_scc1 L_WAIT_USER_CLUSTER_BARRIER_COMPLETE 1368end 1369L_NOT_IN_CLUSTER: 1370#endif 1371 1372#else 1373 s_barrier_signal -2 1374 s_barrier_wait -2 1375#endif 1376end 1377 1378#if RELAXED_SCHEDULING_IN_TRAP 1379function restore_sched_mode(s_tmp) 1380 s_bfe_u32 s_tmp, ttmp11, (TTMP11_SCHED_MODE_SHIFT | (TTMP11_SCHED_MODE_SIZE << 0x10)) 1381 s_setreg_b32 hwreg(HW_REG_WAVE_SCHED_MODE), s_tmp 1382end 1383#endif 1384 1385function restore_barrier_signal_count(barrier_id) 1386 // extract the saved signal count from s_restore_tmp 1387 s_lshr_b32 s_restore_tmp, s_restore_tmp, BARRIER_STATE_SIGNAL_OFFSET 1388 1389 // We need to call s_barrier_signal repeatedly to restore the signal count 1390 // of the group/cluster barrier. The member count is already initialized. 1391L_BARRIER_RESTORE_LOOP: 1392 s_and_b32 s_restore_tmp, s_restore_tmp, s_restore_tmp 1393 s_cbranch_scc0 L_BARRIER_RESTORE_DONE 1394 s_barrier_signal barrier_id 1395 s_add_i32 s_restore_tmp, s_restore_tmp, -1 1396 s_branch L_BARRIER_RESTORE_LOOP 1397 1398L_BARRIER_RESTORE_DONE: 1399end 1400 1401#if HAVE_INSTRUCTION_FIXUP 1402function fixup_instruction 1403 // PC read may fault if memory violation has been asserted. 1404 // In this case no further progress is expected so fixup is not needed. 1405 s_bitcmp1_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_SHIFT 1406 s_cbranch_scc1 L_FIXUP_DONE 1407 1408 // ttmp[0:1]: {7b'0} PC[56:0] 1409 // ttmp2, 3, 10, 13, 14, 15: free 1410 s_load_b64 [ttmp14, ttmp15], [ttmp0, ttmp1], 0 scope:SCOPE_CU // Load the 2 instruction DW we are returning to 1411 s_wait_kmcnt 0 1412 s_load_b64 [ttmp2, ttmp3], [ttmp0, ttmp1], 8 scope:SCOPE_CU // Load the next 2 instruction DW, just in case 1413 s_and_b32 ttmp10, ttmp14, 0x80000000 // Check bit 31 in the first DWORD 1414 // SCC set if ttmp10 is != 0, i.e. if bit 31 == 1 1415 s_cbranch_scc1 L_FIXUP_NOT_VOP12C // If bit 31 is 1, we are not VOP1, VOP2, or VOP3C 1416 // Fall through here means bit 31 == 0, meaning we are VOP1, VOP2, or VOPC 1417 // Size of instruction depends on Opcode or SRC0_9 1418 // Check for VOP2 opcode 1419 s_bfe_u32 ttmp10, ttmp14, (25 | (6 << 0x10)) // Check bits 30:25 for VOP2 Opcode 1420 // VOP2 V_FMAMK_F64 of V_FMAAK_F64 has implied 64-bit literature, 3 DW 1421 s_sub_co_i32 ttmp13, ttmp10, 0x23 // V_FMAMK_F64 is 0x23, V_FMAAK_F64 is 0x24 1422 s_cmp_le_u32 ttmp13, 0x1 // 0==0x23, 1==0x24 1423 s_cbranch_scc1 L_FIXUP_THREE_DWORD // If either, this is 3 DWORD inst 1424 // VOP2 V_FMAMK_F32, V_FMAAK_F32, V_FMAMK_F16, V_FMAAK_F16, 2 DW 1425 s_sub_co_i32 ttmp13, ttmp10, 0x2c // V_FMAMK_F32 is 0x2c, V_FMAAK_F32 is 0x2d 1426 s_cmp_le_u32 ttmp13, 0x1 // 0==0x2c, 1==0x2d 1427 s_cbranch_scc1 L_FIXUP_TWO_DWORD // If either, this is 2 DWORD inst 1428 s_sub_co_i32 ttmp13, ttmp10, 0x37 // V_FMAMK_F16 is 0x37, V_FMAAK_F16 is 0x38 1429 s_cmp_le_u32 ttmp13, 0x1 // 0==0x37, 1==0x38 1430 s_cbranch_scc1 L_FIXUP_TWO_DWORD // If either, this is 2 DWORD inst 1431 // Check SRC0_9 for VOP1, VOP2, and VOPC 1432 s_and_b32 ttmp10, ttmp14, 0x1ff // Check bits 8:0 for SRC0_9 1433 // Literal constant 64 is 3 DWORDs 1434 s_cmp_eq_u32 ttmp10, 0xfe // 0xfe == 254 == Literal constant64 1435 s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst 1436 // Literal constant 32, DPP16, DPP8, and DPP8FI are 2 DWORDs 1437 s_cmp_eq_u32 ttmp10, 0xff // 0xff == 255 = Literal constant32 1438 s_cbranch_scc1 L_FIXUP_TWO_DWORD // 2 DWORD inst 1439 s_cmp_eq_u32 ttmp10, 0xfa // 0xfa == 250 = DPP16 1440 s_cbranch_scc1 L_FIXUP_TWO_DWORD // 2 DWORD inst 1441 s_sub_co_i32 ttmp13, ttmp10, 0xe9 // DPP8 is 0xe9, DPP8FI is 0xea 1442 s_cmp_le_u32 ttmp13, 0x1 // 0==0xe9, 1==0xea 1443 s_cbranch_scc1 L_FIXUP_TWO_DWORD // If either, this is 2 DWORD inst 1444 // Instruction is 1 DWORD otherwise 1445 1446L_FIXUP_ONE_DWORD: 1447 // Check if TTMP15 contains the value for S_SET_VGPR_MSB instruction 1448 s_and_b32 ttmp10, ttmp15, 0xffff0000 // Check encoding in upper 16 bits 1449 s_cmp_eq_u32 ttmp10, 0xbf860000 // Check if SOPP (9b'10_1111111) and S_SET_VGPR_MSB (7b'0000110) 1450 s_cbranch_scc0 L_FIXUP_DONE // No problem, no fixup needed 1451 // VALU op followed by a S_SET_VGPR_MSB. Need to pull SIMM[15:8] to fix up MODE.*_VGPR_MSB 1452 s_bfe_u32 ttmp10, ttmp15, (14 | (2 << 0x10)) // Shift SIMM[15:14] over to 1:0, Dst 1453 s_and_b32 ttmp13, ttmp15, 0x3f00 // Mask to get SIMM[13:8] only 1454 s_lshr_b32 ttmp13, ttmp13, 6 // Shift SIMM[13:8] into 7:2, Src2, Src1, Src0 1455 s_or_b32 ttmp10, ttmp10, ttmp13 // Src2, Src1, Src0, Dst --> format in MODE register 1456 s_setreg_b32 hwreg(HW_REG_WAVE_MODE, 12, 8), ttmp10 // Write value into MODE[19:12] 1457 s_branch L_FIXUP_DONE 1458 1459L_FIXUP_NOT_VOP12C: 1460 // ttmp[0:1]: {7b'0} PC[56:0] 1461 // ttmp2: PC+2 value (not waitcnt'ed yet) 1462 // ttmp3: PC+3 value (not waitcnt'ed yet) 1463 // ttmp10, ttmp13: free 1464 // ttmp14: PC+O value 1465 // ttmp15: PC+1 value 1466 // Not VOP1, VOP2, or VOPC. 1467 // Check if we are VOP3 or VOP3SD 1468 s_and_b32 ttmp10, ttmp14, 0xfc000000 // Bits 31:26 1469 s_cmp_eq_u32 ttmp10, 0xd4000000 // If 31:26 = 0x35, this is VOP3 or VOP3SD 1470 s_cbranch_scc1 L_FIXUP_CHECK_VOP3 // If VOP3 or VOP3SD, need to check SRC2_9, SRC1_9, SRC0_9 1471 // Not VOP1, VOP2, VOPC, VOP3, or VOP3SD. 1472 // Check for VOPD 1473 s_cmp_eq_u32 ttmp10, 0xc8000000 // If 31:26 = 0x32, this is VOPD 1474 s_cbranch_scc1 L_FIXUP_CHECK_VOPD // If VOPD, need to check OpX, OpY, SRCX0 and SRCY0 1475 // Not VOP1, VOP2, VOPC, VOP3, VOP3SD, VOPD. 1476 // Check if we are VOPD3 1477 s_and_b32 ttmp10, ttmp14, 0xff000000 // Bits 31:24 1478 s_cmp_eq_u32 ttmp10, 0xcf000000 // If 31:24 = 0xcf, this is VOPD3 1479 s_cbranch_scc1 L_FIXUP_THREE_DWORD // If VOPD3, 3 DWORD inst 1480 // Not VOP1, VOP2, VOPC, VOP3, VOP3SD, VOPD, or VOPD3. 1481 // Check if we are in the middle of VOP3PX. 1482 s_and_b32 ttmp13, ttmp14, 0xffff0000 // Bits 31:16 1483 s_cmp_eq_u32 ttmp13, 0xcc330000 // If 31:16 = 0xcc33, this is 8 bytes past VOP3PX 1484 s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE 1485 s_cmp_eq_u32 ttmp13, 0xcc880000 // If 31:16 = 0xcc88, this is 8 bytes past VOP3PX 1486 s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE 1487 // Might be in VOP3P, but we must ensure we are not VOP3PX2 1488 s_cmp_eq_u32 ttmp13, 0xcc350000 // If 31:16 = 0xcc35, this is VOP3PX2 1489 s_cbranch_scc1 L_FIXUP_DONE // If VOP3PX2, no fixup needed 1490 s_cmp_eq_u32 ttmp13, 0xcc3a0000 // If 31:16 = 0xcc3a, this is VOP3PX2 1491 s_cbranch_scc1 L_FIXUP_DONE // If VOP3PX2, no fixup needed 1492 // Check if we are VOP3P 1493 s_cmp_eq_u32 ttmp10, 0xcc000000 // If 31:24 = 0xcc, this is VOP3P 1494 s_cbranch_scc0 L_FIXUP_DONE // Not in VOP3P, so instruction is not VOP1, VOP2, 1495 // VOPC, VOP3, VOP3SD, VOP3P, VOPD, or VOPD3 1496 // No fixup needed. 1497 // Fall-through if we are in VOP3P to check SRC2_9, SRC1_9, and SRC0_9 1498L_FIXUP_CHECK_VOP3: 1499 // Start with Src0, which is in bits 8:0 of second instruction DW, ttmp15 1500 s_and_b32 ttmp10, ttmp15, 0x1ff // Mask out unused bits 1501 // Src0_9 == Literal constant 32, DPP16, DPP8, and DPP8FI means 3 DWORDs 1502 s_cmp_eq_u32 ttmp10, 0xff // 0xff == 255 = Literal constant32 1503 s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst 1504 s_cmp_eq_u32 ttmp10, 0xfa // 0xfa == 250 = DPP16 1505 s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst 1506 s_sub_co_i32 ttmp10, ttmp10, 0xe9 // DPP8 is 0xe9, DPP8FI is 0xea 1507 s_cmp_le_u32 ttmp10, 0x1 // 0==0xe9, 1==0xea 1508 s_cbranch_scc1 L_FIXUP_THREE_DWORD // If either, this is 3 DWORD inst 1509 s_and_b32 ttmp10, ttmp15, 0x3fe00 // Next is Src1, which is in 17:9 1510 s_cmp_eq_u32 ttmp10, 0x1fe00 // 0xff == 255 = Literal constant32 1511 s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst 1512 s_and_b32 ttmp10, ttmp15, 0x7fc0000 // Next is Src2, which is in 26:18 1513 s_cmp_eq_u32 ttmp10, 0x3fc0000 // 0xff == 255 = Literal constant32 1514 s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst 1515 s_branch L_FIXUP_TWO_DWORD // No special encodings, VOP3* is 2 Dword 1516 1517L_FIXUP_CHECK_VOPD: 1518 // OpX being V_DUAL_FMA*K_F32 means 3 DWORDs 1519 s_bfe_u32 ttmp10, ttmp14, (22 | (4 << 0x10)) // OPX is bits 25:22 1520 s_sub_co_i32 ttmp10, ttmp10, 0x1 // V_DUAL_FMAAK_F32 is 0x1, V_DUAL_FMAMK_F32 is 0x2 1521 s_cmp_le_u32 ttmp10, 0x1 // 0==0x1, 1==0x2 1522 s_cbranch_scc1 L_FIXUP_THREE_DWORD // If either, this is 3 DWORD inst 1523 // OpY being V_DUAL_FMA*K_F32 means 3 DWORDs 1524 s_bfe_u32 ttmp10, ttmp14, (17 | (5 << 0x10)) // OPX is bits 21:17 1525 s_sub_co_i32 ttmp10, ttmp10, 0x1 // V_DUAL_FMAAK_F32 is 0x1, V_DUAL_FMAMK_F32 is 0x2 1526 s_cmp_le_u32 ttmp10, 0x1 // 0==0x1, 1==0x2 1527 s_cbranch_scc1 L_FIXUP_THREE_DWORD // If either, this is 3 DWORD inst 1528 // SRCX0 == Literal constant 32 means 3 DWORDs 1529 s_and_b32 ttmp10, ttmp14, 0x1ff // SRCX0 is in bits 8:0 of 1st DWORD 1530 s_cmp_eq_u32 ttmp10, 0xff // 0xff == 255 = Literal constant32 1531 s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst 1532 // SRCY0 == Literal constant 32 means 3 DWORDs 1533 s_and_b32 ttmp10, ttmp15, 0x1ff // SRCY0 is in bits 8:0 of 2nd DWORD 1534 s_cmp_eq_u32 ttmp10, 0xff // 0xff == 255 = Literal constant32 1535 s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst 1536 // If otherwise, no special encodings. Default VOPD is 2 Dword 1537 // Fall-thru if true, because this is a 2 DWORD inst 1538L_FIXUP_TWO_DWORD: 1539 s_wait_kmcnt 0 // Wait for PC+2 and PC+3 to arrive in ttmp2 and ttmp3 1540 s_mov_b32 ttmp15, ttmp2 // Move possible S_SET_VGPR_MSB into ttmp15 1541 s_branch L_FIXUP_ONE_DWORD // Go to common logic that checks if it is S_SET_VGPR_MSB 1542 1543L_FIXUP_THREE_DWORD: 1544 s_wait_kmcnt 0 // Wait for PC+2 and PC+3 to arrive in ttmp2 and ttmp3 1545 s_mov_b32 ttmp15, ttmp3 // Move possible S_SET_VGPR_MSB into ttmp15 1546 s_branch L_FIXUP_ONE_DWORD // Go to common logic that checks if it is S_SET_VGPR_MSB 1547 1548L_FIXUP_VOP3PX_MIDDLE: 1549 s_sub_co_u32 ttmp0, ttmp0, 8 // Rewind PC 8 bytes to beginning of instruction 1550 s_sub_co_ci_u32 ttmp1, ttmp1, 0 1551 s_branch L_FIXUP_TWO_DWORD // 2 DWORD inst (2nd half of a 4 DWORD inst) 1552 1553L_FIXUP_DONE: 1554 s_wait_kmcnt 0 // Ensure load of ttmp2 and ttmp3 is done 1555end 1556#endif 1557