1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ucode.h" 26 #include "amdgpu_vpe.h" 27 #include "vpe_v2_0.h" 28 #include "soc15_common.h" 29 #include "ivsrcid/vpe/irqsrcs_vpe_6_1.h" 30 #include "vpe/vpe_2_0_0_offset.h" 31 #include "vpe/vpe_2_0_0_sh_mask.h" 32 33 MODULE_FIRMWARE("amdgpu/vpe_2_0_0.bin"); 34 35 #define VPE_THREAD1_UCODE_OFFSET 0x8000 36 37 static uint32_t vpe_v2_0_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset) 38 { 39 uint32_t base; 40 41 base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0]; 42 43 return base + offset; 44 } 45 46 static int vpe_v2_0_irq_init(struct amdgpu_vpe *vpe) 47 { 48 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 49 int ret; 50 51 ret = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VPE, 52 VPE_6_1_SRCID__VPE_TRAP, 53 &adev->vpe.trap_irq); 54 if (ret) 55 return ret; 56 57 return 0; 58 } 59 60 static int vpe_v2_0_load_microcode(struct amdgpu_vpe *vpe) 61 { 62 struct amdgpu_device *adev = vpe->ring.adev; 63 const struct vpe_firmware_header_v1_0 *vpe_hdr; 64 const __le32 *data; 65 uint32_t ucode_offset[2], ucode_size[2], size_dw, ret; 66 uint32_t f32_offset, f32_cntl, reg_data; 67 68 ret = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL)); 69 ret = REG_SET_FIELD(ret, VPEC_CNTL, UMSCH_INT_ENABLE, 0); 70 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), ret); 71 72 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2)); 73 reg_data = REG_SET_FIELD(reg_data, VPEC_CNTL2, IB_FIFO_WATERMARK, 1); 74 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2), reg_data); 75 76 if (amdgpu_vpe_configure_dpm(vpe)) 77 dev_warn(adev->dev, "VPE DPM not enabled.\n"); 78 79 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 80 81 f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL); 82 f32_cntl = RREG32(f32_offset); 83 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); 84 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0); 85 86 adev->vpe.cmdbuf_cpu_addr[0] = f32_offset; 87 adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl; 88 89 return amdgpu_vpe_psp_update_sram(adev); 90 } 91 92 /* Halt and Check F32 cleaness */ 93 f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL); 94 f32_cntl = RREG32(f32_offset); 95 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 1); 96 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 1); 97 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_CHECKSUM_CLR, 1); 98 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH0_CHECKSUM_CLR, 1); 99 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl); 100 101 f32_cntl = RREG32(f32_offset); 102 if (!REG_GET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT)) { 103 dev_err(adev->dev, "VPEC is not halted"); 104 return -EBUSY; 105 } 106 107 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_CHECKSUM_CLR, 0); 108 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH0_CHECKSUM_CLR, 0); 109 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl); 110 111 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE_CHECKSUM)); 112 if (reg_data) { 113 dev_err(adev->dev, "VPE FW checksum 0 not clean"); 114 return -EBUSY; 115 } 116 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE1_CHECKSUM)); 117 if (reg_data) { 118 dev_err(adev->dev, "VPE FW checksum 1 not clean"); 119 return -EBUSY; 120 } 121 122 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS2)); 123 if (REG_GET_FIELD(reg_data, VPEC_STATUS2, TH0F32_INSTR_PTR)) { 124 dev_err(adev->dev, "VPE FW initial status not clean"); 125 return -EBUSY; 126 } 127 128 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS6)); 129 if (REG_GET_FIELD(reg_data, VPEC_STATUS6, TH1F32_INSTR_PTR)) { 130 dev_err(adev->dev, "VPE FW initial status not clean"); 131 return -EBUSY; 132 } 133 /* end of F32 cleaness check */ 134 135 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data; 136 137 /* Thread 0(command thread) ucode offset/size */ 138 ucode_offset[0] = le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes); 139 ucode_size[0] = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes); 140 /* Thread 1(control thread) ucode offset/size */ 141 ucode_offset[1] = le32_to_cpu(vpe_hdr->ctl_ucode_offset); 142 ucode_size[1] = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes); 143 144 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL)); 145 reg_data = REG_SET_FIELD(reg_data, VPEC_PG_CNTL, PG_EN, 0); 146 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data); 147 148 for (int j = 0; j < vpe->num_instances; j++) { 149 for (int i = 0; i < 2; i++) { 150 if (i > 0) 151 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET); 152 else 153 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0); 154 155 data = (const __le32 *)(adev->vpe.fw->data + ucode_offset[i]); 156 size_dw = ucode_size[i] / sizeof(__le32); 157 158 while (size_dw--) { 159 if (amdgpu_emu_mode && size_dw % 500 == 0) 160 msleep(1); 161 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++)); 162 } 163 } 164 } 165 166 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL)); 167 reg_data = REG_SET_FIELD(reg_data, VPEC_PG_CNTL, PG_EN, 1); 168 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data); 169 170 /* Unhalt F32 */ 171 f32_cntl = RREG32(f32_offset); 172 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); 173 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0); 174 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl); 175 176 return 0; 177 } 178 179 static int vpe_v2_0_ring_start(struct amdgpu_vpe *vpe) 180 { 181 struct amdgpu_ring *ring = &vpe->ring; 182 struct amdgpu_device *adev = ring->adev; 183 uint32_t doorbell, doorbell_offset; 184 uint32_t rb_bufsz, rb_cntl; 185 uint32_t ib_cntl, i; 186 int ret; 187 188 for (i = 0; i < vpe->num_instances; i++) { 189 /* Set ring buffer size in dwords */ 190 rb_bufsz = order_base_2(ring->ring_size / 4); 191 rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL)); 192 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 193 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_PRIV, 1); 194 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_VMID, 0); 195 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); 196 197 /* Initialize the ring buffer's read and write pointers */ 198 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR), 0); 199 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_HI), 0); 200 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), 0); 201 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), 0); 202 203 /* set the wb address whether it's enabled or not */ 204 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_LO), 205 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 206 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_HI), 207 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 208 209 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 210 211 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 212 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 213 214 ring->wptr = 0; 215 216 /* before programing wptr to a less value, need set minor_ptr_update first */ 217 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 1); 218 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 219 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 220 /* set minor_ptr_update to 0 after wptr programed */ 221 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 0); 222 223 doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET)); 224 doorbell_offset = REG_SET_FIELD(doorbell_offset, VPEC_QUEUE0_DOORBELL_OFFSET, OFFSET, ring->doorbell_index + i*4); 225 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 226 227 doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL)); 228 doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0); 229 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL), doorbell); 230 231 adev->nbio.funcs->vpe_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index + i*4, 4); 232 233 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 234 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_ENABLE, 1); 235 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); 236 237 ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL)); 238 ib_cntl = REG_SET_FIELD(ib_cntl, VPEC_QUEUE0_IB_CNTL, IB_ENABLE, 1); 239 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL), ib_cntl); 240 } 241 242 ret = amdgpu_ring_test_helper(ring); 243 if (ret) 244 return ret; 245 246 return 0; 247 } 248 249 static int vpe_v2_0_ring_stop(struct amdgpu_vpe *vpe) 250 { 251 struct amdgpu_device *adev = vpe->ring.adev; 252 uint32_t queue_reset, i; 253 int ret; 254 255 for (i = 0; i < vpe->num_instances; i++) { 256 queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ)); 257 258 queue_reset = REG_SET_FIELD(queue_reset, VPEC_QUEUE_RESET_REQ, QUEUE0_RESET, 1); 259 260 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ), queue_reset); 261 /* timeout length is adev->timeout_usec */ 262 ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ, 0, 263 VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK); 264 265 if (ret) 266 dev_err(adev->dev, "VPE queue reset failed\n"); 267 } 268 269 vpe->ring.sched.ready = false; 270 271 return ret; 272 } 273 274 static int vpe_v2_0_set_trap_irq_state(struct amdgpu_device *adev, 275 struct amdgpu_irq_src *source, 276 unsigned int type, 277 enum amdgpu_interrupt_state state) 278 { 279 struct amdgpu_vpe *vpe = &adev->vpe; 280 uint32_t vpe_cntl; 281 282 vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL)); 283 vpe_cntl = REG_SET_FIELD(vpe_cntl, VPEC_CNTL, TRAP_ENABLE, 284 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 285 286 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), vpe_cntl); 287 288 return 0; 289 } 290 291 static int vpe_v2_0_process_trap_irq(struct amdgpu_device *adev, 292 struct amdgpu_irq_src *source, 293 struct amdgpu_iv_entry *entry) 294 { 295 296 DRM_DEBUG("IH: VPE trap\n"); 297 298 switch (entry->client_id) { 299 case SOC21_IH_CLIENTID_VPE: 300 amdgpu_fence_process(&adev->vpe.ring); 301 break; 302 default: 303 break; 304 } 305 306 return 0; 307 } 308 309 static int vpe_v2_0_set_regs(struct amdgpu_vpe *vpe) 310 { 311 vpe->regs.queue0_rb_rptr_lo = regVPEC_QUEUE0_RB_RPTR; 312 vpe->regs.queue0_rb_rptr_hi = regVPEC_QUEUE0_RB_RPTR_HI; 313 vpe->regs.queue0_rb_wptr_lo = regVPEC_QUEUE0_RB_WPTR; 314 vpe->regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI; 315 vpe->regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT; 316 vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2; 317 318 vpe->regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4; 319 vpe->regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3; 320 vpe->regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4; 321 vpe->regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2; 322 vpe->regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3; 323 vpe->regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1; 324 vpe->regs.context_indicator = regVPEC_QUEUE6_DUMMY3; 325 326 return 0; 327 } 328 329 static struct vpe_funcs vpe_v2_0_funcs = { 330 .get_reg_offset = vpe_v2_0_get_reg_offset, 331 .set_regs = vpe_v2_0_set_regs, 332 .irq_init = vpe_v2_0_irq_init, 333 .init_microcode = amdgpu_vpe_init_microcode, 334 .load_microcode = vpe_v2_0_load_microcode, 335 .ring_init = amdgpu_vpe_ring_init, 336 .ring_start = vpe_v2_0_ring_start, 337 .ring_stop = vpe_v2_0_ring_stop, 338 .ring_fini = amdgpu_vpe_ring_fini, 339 }; 340 341 static const struct amdgpu_irq_src_funcs vpe_v2_0_trap_irq_funcs = { 342 .set = vpe_v2_0_set_trap_irq_state, 343 .process = vpe_v2_0_process_trap_irq, 344 }; 345 346 void vpe_v2_0_set_funcs(struct amdgpu_vpe *vpe) 347 { 348 vpe->funcs = &vpe_v2_0_funcs; 349 vpe->trap_irq.funcs = &vpe_v2_0_trap_irq_funcs; 350 } 351