1 /* 2 * Copyright 2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_hw_ip.h" 31 #include "vcn_v2_0.h" 32 #include "vcn_v4_0_3.h" 33 34 #include "vcn/vcn_5_0_0_offset.h" 35 #include "vcn/vcn_5_0_0_sh_mask.h" 36 #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" 37 #include "vcn_v5_0_0.h" 38 #include "vcn_v5_0_1.h" 39 40 #include <drm/drm_drv.h> 41 42 static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev); 43 static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev); 44 static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst, 45 enum amd_powergating_state state); 46 static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring); 47 48 /** 49 * vcn_v5_0_1_early_init - set function pointers and load microcode 50 * 51 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 52 * 53 * Set ring and irq function pointers 54 * Load microcode from filesystem 55 */ 56 static int vcn_v5_0_1_early_init(struct amdgpu_ip_block *ip_block) 57 { 58 struct amdgpu_device *adev = ip_block->adev; 59 int i, r; 60 61 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 62 /* re-use enc ring as unified ring */ 63 adev->vcn.inst[i].num_enc_rings = 1; 64 65 vcn_v5_0_1_set_unified_ring_funcs(adev); 66 vcn_v5_0_1_set_irq_funcs(adev); 67 68 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 69 adev->vcn.inst[i].set_pg_state = vcn_v5_0_1_set_pg_state; 70 71 r = amdgpu_vcn_early_init(adev, i); 72 if (r) 73 return r; 74 } 75 76 return 0; 77 } 78 79 static void vcn_v5_0_1_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 80 { 81 struct amdgpu_vcn5_fw_shared *fw_shared; 82 83 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 84 85 if (fw_shared->sq.is_enabled) 86 return; 87 fw_shared->present_flag_0 = 88 cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 89 fw_shared->sq.is_enabled = 1; 90 91 if (amdgpu_vcnfw_log) 92 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 93 } 94 95 /** 96 * vcn_v5_0_1_sw_init - sw init for VCN block 97 * 98 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 99 * 100 * Load firmware and sw initialization 101 */ 102 static int vcn_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) 103 { 104 struct amdgpu_device *adev = ip_block->adev; 105 struct amdgpu_ring *ring; 106 int i, r, vcn_inst; 107 108 /* VCN UNIFIED TRAP */ 109 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 110 VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 111 if (r) 112 return r; 113 114 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 115 vcn_inst = GET_INST(VCN, i); 116 117 r = amdgpu_vcn_sw_init(adev, i); 118 if (r) 119 return r; 120 121 amdgpu_vcn_setup_ucode(adev, i); 122 123 r = amdgpu_vcn_resume(adev, i); 124 if (r) 125 return r; 126 127 ring = &adev->vcn.inst[i].ring_enc[0]; 128 ring->use_doorbell = true; 129 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * vcn_inst; 130 131 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 132 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 133 134 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 135 AMDGPU_RING_PRIO_DEFAULT, &adev->vcn.inst[i].sched_score); 136 if (r) 137 return r; 138 139 vcn_v5_0_1_fw_shared_init(adev, i); 140 } 141 142 /* TODO: Add queue reset mask when FW fully supports it */ 143 adev->vcn.supported_reset = 144 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 145 146 vcn_v5_0_0_alloc_ip_dump(adev); 147 148 return amdgpu_vcn_sysfs_reset_mask_init(adev); 149 } 150 151 /** 152 * vcn_v5_0_1_sw_fini - sw fini for VCN block 153 * 154 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 155 * 156 * VCN suspend and free up sw allocation 157 */ 158 static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block) 159 { 160 struct amdgpu_device *adev = ip_block->adev; 161 int i, r, idx; 162 163 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 164 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 165 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 166 167 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 168 fw_shared->present_flag_0 = 0; 169 fw_shared->sq.is_enabled = 0; 170 } 171 172 drm_dev_exit(idx); 173 } 174 175 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 176 r = amdgpu_vcn_suspend(adev, i); 177 if (r) 178 return r; 179 } 180 181 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 182 r = amdgpu_vcn_sw_fini(adev, i); 183 if (r) 184 return r; 185 } 186 187 amdgpu_vcn_sysfs_reset_mask_fini(adev); 188 189 kfree(adev->vcn.ip_dump); 190 191 return 0; 192 } 193 194 /** 195 * vcn_v5_0_1_hw_init - start and test VCN block 196 * 197 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 198 * 199 * Initialize the hardware, boot up the VCPU and do some testing 200 */ 201 static int vcn_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block) 202 { 203 struct amdgpu_device *adev = ip_block->adev; 204 struct amdgpu_ring *ring; 205 int i, r, vcn_inst; 206 207 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 208 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 209 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 210 vcn_inst = GET_INST(VCN, i); 211 ring = &adev->vcn.inst[i].ring_enc[0]; 212 213 if (ring->use_doorbell) 214 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 215 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 216 9 * vcn_inst), 217 adev->vcn.inst[i].aid_id); 218 219 /* Re-init fw_shared, if required */ 220 vcn_v5_0_1_fw_shared_init(adev, i); 221 222 r = amdgpu_ring_test_helper(ring); 223 if (r) 224 return r; 225 } 226 227 return 0; 228 } 229 230 /** 231 * vcn_v5_0_1_hw_fini - stop the hardware block 232 * 233 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 234 * 235 * Stop the VCN block, mark ring as not ready any more 236 */ 237 static int vcn_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block) 238 { 239 struct amdgpu_device *adev = ip_block->adev; 240 int i; 241 242 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 243 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 244 245 cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work); 246 if (vinst->cur_state != AMD_PG_STATE_GATE) 247 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 248 } 249 250 return 0; 251 } 252 253 /** 254 * vcn_v5_0_1_suspend - suspend VCN block 255 * 256 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 257 * 258 * HW fini and suspend VCN block 259 */ 260 static int vcn_v5_0_1_suspend(struct amdgpu_ip_block *ip_block) 261 { 262 struct amdgpu_device *adev = ip_block->adev; 263 int r, i; 264 265 r = vcn_v5_0_1_hw_fini(ip_block); 266 if (r) 267 return r; 268 269 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 270 r = amdgpu_vcn_suspend(ip_block->adev, i); 271 if (r) 272 return r; 273 } 274 275 return r; 276 } 277 278 /** 279 * vcn_v5_0_1_resume - resume VCN block 280 * 281 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 282 * 283 * Resume firmware and hw init VCN block 284 */ 285 static int vcn_v5_0_1_resume(struct amdgpu_ip_block *ip_block) 286 { 287 struct amdgpu_device *adev = ip_block->adev; 288 int r, i; 289 290 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 291 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 292 293 if (amdgpu_in_reset(adev)) 294 vinst->cur_state = AMD_PG_STATE_GATE; 295 296 r = amdgpu_vcn_resume(ip_block->adev, i); 297 if (r) 298 return r; 299 } 300 301 r = vcn_v5_0_1_hw_init(ip_block); 302 303 return r; 304 } 305 306 /** 307 * vcn_v5_0_1_mc_resume - memory controller programming 308 * 309 * @vinst: VCN instance 310 * 311 * Let the VCN memory controller know it's offsets 312 */ 313 static void vcn_v5_0_1_mc_resume(struct amdgpu_vcn_inst *vinst) 314 { 315 struct amdgpu_device *adev = vinst->adev; 316 int inst = vinst->inst; 317 uint32_t offset, size, vcn_inst; 318 const struct common_firmware_header *hdr; 319 320 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 321 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 322 323 vcn_inst = GET_INST(VCN, inst); 324 /* cache window 0: fw */ 325 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 326 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 327 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 328 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 329 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 330 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 331 offset = 0; 332 } else { 333 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 334 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 335 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 336 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 337 offset = size; 338 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 339 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 340 } 341 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 342 343 /* cache window 1: stack */ 344 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 345 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 346 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 347 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 348 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 349 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 350 351 /* cache window 2: context */ 352 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 353 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 354 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 355 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 356 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 357 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 358 359 /* non-cache window */ 360 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 361 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 362 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 363 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 364 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 365 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 366 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); 367 } 368 369 /** 370 * vcn_v5_0_1_mc_resume_dpg_mode - memory controller programming for dpg mode 371 * 372 * @vinst: VCN instance 373 * @indirect: indirectly write sram 374 * 375 * Let the VCN memory controller know it's offsets with dpg mode 376 */ 377 static void vcn_v5_0_1_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 378 bool indirect) 379 { 380 struct amdgpu_device *adev = vinst->adev; 381 int inst_idx = vinst->inst; 382 uint32_t offset, size; 383 const struct common_firmware_header *hdr; 384 385 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 386 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 387 388 /* cache window 0: fw */ 389 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 390 if (!indirect) { 391 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 392 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 393 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 394 inst_idx].tmr_mc_addr_lo), 0, indirect); 395 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 396 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 397 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 398 inst_idx].tmr_mc_addr_hi), 0, indirect); 399 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 400 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 401 } else { 402 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 403 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 404 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 405 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 406 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 407 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 408 } 409 offset = 0; 410 } else { 411 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 412 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 413 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 414 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 415 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 416 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 417 offset = size; 418 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 419 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 420 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 421 } 422 423 if (!indirect) 424 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 425 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 426 else 427 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 428 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 429 430 /* cache window 1: stack */ 431 if (!indirect) { 432 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 433 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 434 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 435 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 436 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 437 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 438 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 439 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 440 } else { 441 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 442 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 443 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 444 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 445 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 446 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 447 } 448 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 449 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 450 451 /* cache window 2: context */ 452 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 453 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 454 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 455 AMDGPU_VCN_STACK_SIZE), 0, indirect); 456 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 457 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 458 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 459 AMDGPU_VCN_STACK_SIZE), 0, indirect); 460 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 461 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 462 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 463 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 464 465 /* non-cache window */ 466 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 467 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 468 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 469 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 470 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 471 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 472 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 473 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 474 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 475 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 476 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); 477 478 /* VCN global tiling registers */ 479 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 480 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 481 } 482 483 /** 484 * vcn_v5_0_1_disable_clock_gating - disable VCN clock gating 485 * 486 * @vinst: VCN instance 487 * 488 * Disable clock gating for VCN block 489 */ 490 static void vcn_v5_0_1_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 491 { 492 } 493 494 /** 495 * vcn_v5_0_1_enable_clock_gating - enable VCN clock gating 496 * 497 * @vinst: VCN instance 498 * 499 * Enable clock gating for VCN block 500 */ 501 static void vcn_v5_0_1_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 502 { 503 } 504 505 /** 506 * vcn_v5_0_1_start_dpg_mode - VCN start with dpg mode 507 * 508 * @vinst: VCN instance 509 * @indirect: indirectly write sram 510 * 511 * Start VCN block with dpg mode 512 */ 513 static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 514 bool indirect) 515 { 516 struct amdgpu_device *adev = vinst->adev; 517 int inst_idx = vinst->inst; 518 volatile struct amdgpu_vcn5_fw_shared *fw_shared = 519 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 520 struct amdgpu_ring *ring; 521 int vcn_inst; 522 uint32_t tmp; 523 524 vcn_inst = GET_INST(VCN, inst_idx); 525 526 /* disable register anti-hang mechanism */ 527 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 528 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 529 530 /* enable dynamic power gating mode */ 531 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 532 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 533 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 534 535 if (indirect) { 536 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 537 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 538 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 539 WREG32_SOC24_DPG_MODE(inst_idx, 0xDEADBEEF, 540 adev->vcn.inst[inst_idx].aid_id, 0, true); 541 } 542 543 /* enable VCPU clock */ 544 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 545 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 546 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 547 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 548 549 /* disable master interrupt */ 550 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 551 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 552 553 /* setup regUVD_LMI_CTRL */ 554 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 555 UVD_LMI_CTRL__REQ_MODE_MASK | 556 UVD_LMI_CTRL__CRC_RESET_MASK | 557 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 558 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 559 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 560 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 561 0x00100000L); 562 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 563 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 564 565 vcn_v5_0_1_mc_resume_dpg_mode(vinst, indirect); 566 567 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 568 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 569 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 570 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 571 572 /* enable LMI MC and UMC channels */ 573 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 574 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 575 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 576 577 /* enable master interrupt */ 578 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 579 VCN, 0, regUVD_MASTINT_EN), 580 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 581 582 if (indirect) 583 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 584 585 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 586 587 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); 588 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 589 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / sizeof(uint32_t)); 590 591 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 592 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 593 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 594 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 595 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 596 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 597 598 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); 599 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); 600 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 601 602 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 603 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 604 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 605 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 606 607 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 608 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 609 VCN_RB1_DB_CTRL__EN_MASK); 610 /* Read DB_CTRL to flush the write DB_CTRL command. */ 611 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 612 613 return 0; 614 } 615 616 /** 617 * vcn_v5_0_1_start - VCN start 618 * 619 * @vinst: VCN instance 620 * 621 * Start VCN block 622 */ 623 static int vcn_v5_0_1_start(struct amdgpu_vcn_inst *vinst) 624 { 625 struct amdgpu_device *adev = vinst->adev; 626 int i = vinst->inst; 627 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 628 struct amdgpu_ring *ring; 629 uint32_t tmp; 630 int j, k, r, vcn_inst; 631 632 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 633 634 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 635 return vcn_v5_0_1_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 636 637 vcn_inst = GET_INST(VCN, i); 638 639 /* set VCN status busy */ 640 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 641 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 642 643 /* enable VCPU clock */ 644 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 645 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 646 647 /* disable master interrupt */ 648 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 649 ~UVD_MASTINT_EN__VCPU_EN_MASK); 650 651 /* enable LMI MC and UMC channels */ 652 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 653 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 654 655 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 656 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 657 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 658 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 659 660 /* setup regUVD_LMI_CTRL */ 661 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 662 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp | 663 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 664 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 665 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 666 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 667 668 vcn_v5_0_1_mc_resume(vinst); 669 670 /* VCN global tiling registers */ 671 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 672 adev->gfx.config.gb_addr_config); 673 674 /* unblock VCPU register access */ 675 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 676 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 677 678 /* release VCPU reset to boot */ 679 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 680 ~UVD_VCPU_CNTL__BLK_RST_MASK); 681 682 for (j = 0; j < 10; ++j) { 683 uint32_t status; 684 685 for (k = 0; k < 100; ++k) { 686 status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 687 if (status & 2) 688 break; 689 mdelay(100); 690 if (amdgpu_emu_mode == 1) 691 msleep(20); 692 } 693 694 if (amdgpu_emu_mode == 1) { 695 r = -1; 696 if (status & 2) { 697 r = 0; 698 break; 699 } 700 } else { 701 r = 0; 702 if (status & 2) 703 break; 704 705 dev_err(adev->dev, 706 "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 707 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 708 UVD_VCPU_CNTL__BLK_RST_MASK, 709 ~UVD_VCPU_CNTL__BLK_RST_MASK); 710 mdelay(10); 711 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 712 ~UVD_VCPU_CNTL__BLK_RST_MASK); 713 714 mdelay(10); 715 r = -1; 716 } 717 } 718 719 if (r) { 720 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 721 return r; 722 } 723 724 /* enable master interrupt */ 725 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 726 UVD_MASTINT_EN__VCPU_EN_MASK, 727 ~UVD_MASTINT_EN__VCPU_EN_MASK); 728 729 /* clear the busy bit of VCN_STATUS */ 730 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 731 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 732 733 ring = &adev->vcn.inst[i].ring_enc[0]; 734 735 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 736 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 737 VCN_RB1_DB_CTRL__EN_MASK); 738 739 /* Read DB_CTRL to flush the write DB_CTRL command. */ 740 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 741 742 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr); 743 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 744 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4); 745 746 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 747 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 748 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 749 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 750 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 751 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 752 753 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); 754 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); 755 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 756 757 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 758 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 759 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 760 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 761 762 return 0; 763 } 764 765 /** 766 * vcn_v5_0_1_stop_dpg_mode - VCN stop with dpg mode 767 * 768 * @vinst: VCN instance 769 * 770 * Stop VCN block with dpg mode 771 */ 772 static void vcn_v5_0_1_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 773 { 774 struct amdgpu_device *adev = vinst->adev; 775 int inst_idx = vinst->inst; 776 uint32_t tmp; 777 int vcn_inst; 778 779 vcn_inst = GET_INST(VCN, inst_idx); 780 781 /* Wait for power status to be 1 */ 782 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 783 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 784 785 /* wait for read ptr to be equal to write ptr */ 786 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 787 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 788 789 /* disable dynamic power gating mode */ 790 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 791 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 792 } 793 794 /** 795 * vcn_v5_0_1_stop - VCN stop 796 * 797 * @vinst: VCN instance 798 * 799 * Stop VCN block 800 */ 801 static int vcn_v5_0_1_stop(struct amdgpu_vcn_inst *vinst) 802 { 803 struct amdgpu_device *adev = vinst->adev; 804 int i = vinst->inst; 805 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 806 uint32_t tmp; 807 int r = 0, vcn_inst; 808 809 vcn_inst = GET_INST(VCN, i); 810 811 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 812 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 813 814 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 815 vcn_v5_0_1_stop_dpg_mode(vinst); 816 return 0; 817 } 818 819 /* wait for vcn idle */ 820 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 821 if (r) 822 return r; 823 824 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 825 UVD_LMI_STATUS__READ_CLEAN_MASK | 826 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 827 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 828 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); 829 if (r) 830 return r; 831 832 /* disable LMI UMC channel */ 833 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 834 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 835 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 836 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 837 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 838 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); 839 if (r) 840 return r; 841 842 /* block VCPU register access */ 843 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 844 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 845 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 846 847 /* reset VCPU */ 848 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 849 UVD_VCPU_CNTL__BLK_RST_MASK, 850 ~UVD_VCPU_CNTL__BLK_RST_MASK); 851 852 /* disable VCPU clock */ 853 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 854 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 855 856 /* apply soft reset */ 857 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 858 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 859 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 860 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 861 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 862 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 863 864 /* clear status */ 865 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 866 867 return 0; 868 } 869 870 /** 871 * vcn_v5_0_1_unified_ring_get_rptr - get unified read pointer 872 * 873 * @ring: amdgpu_ring pointer 874 * 875 * Returns the current hardware unified read pointer 876 */ 877 static uint64_t vcn_v5_0_1_unified_ring_get_rptr(struct amdgpu_ring *ring) 878 { 879 struct amdgpu_device *adev = ring->adev; 880 881 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 882 DRM_ERROR("wrong ring id is identified in %s", __func__); 883 884 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 885 } 886 887 /** 888 * vcn_v5_0_1_unified_ring_get_wptr - get unified write pointer 889 * 890 * @ring: amdgpu_ring pointer 891 * 892 * Returns the current hardware unified write pointer 893 */ 894 static uint64_t vcn_v5_0_1_unified_ring_get_wptr(struct amdgpu_ring *ring) 895 { 896 struct amdgpu_device *adev = ring->adev; 897 898 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 899 DRM_ERROR("wrong ring id is identified in %s", __func__); 900 901 if (ring->use_doorbell) 902 return *ring->wptr_cpu_addr; 903 else 904 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR); 905 } 906 907 /** 908 * vcn_v5_0_1_unified_ring_set_wptr - set enc write pointer 909 * 910 * @ring: amdgpu_ring pointer 911 * 912 * Commits the enc write pointer to the hardware 913 */ 914 static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring) 915 { 916 struct amdgpu_device *adev = ring->adev; 917 918 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 919 DRM_ERROR("wrong ring id is identified in %s", __func__); 920 921 if (ring->use_doorbell) { 922 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 923 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 924 } else { 925 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 926 lower_32_bits(ring->wptr)); 927 } 928 } 929 930 static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { 931 .type = AMDGPU_RING_TYPE_VCN_ENC, 932 .align_mask = 0x3f, 933 .nop = VCN_ENC_CMD_NO_OP, 934 .get_rptr = vcn_v5_0_1_unified_ring_get_rptr, 935 .get_wptr = vcn_v5_0_1_unified_ring_get_wptr, 936 .set_wptr = vcn_v5_0_1_unified_ring_set_wptr, 937 .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 938 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 939 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 940 5 + 941 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 942 1, /* vcn_v2_0_enc_ring_insert_end */ 943 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 944 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 945 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 946 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 947 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 948 .test_ring = amdgpu_vcn_enc_ring_test_ring, 949 .test_ib = amdgpu_vcn_unified_ring_test_ib, 950 .insert_nop = amdgpu_ring_insert_nop, 951 .insert_end = vcn_v2_0_enc_ring_insert_end, 952 .pad_ib = amdgpu_ring_generic_pad_ib, 953 .begin_use = amdgpu_vcn_ring_begin_use, 954 .end_use = amdgpu_vcn_ring_end_use, 955 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 956 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 957 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 958 }; 959 960 /** 961 * vcn_v5_0_1_set_unified_ring_funcs - set unified ring functions 962 * 963 * @adev: amdgpu_device pointer 964 * 965 * Set unified ring functions 966 */ 967 static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev) 968 { 969 int i, vcn_inst; 970 971 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 972 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_1_unified_ring_vm_funcs; 973 adev->vcn.inst[i].ring_enc[0].me = i; 974 vcn_inst = GET_INST(VCN, i); 975 adev->vcn.inst[i].aid_id = vcn_inst / adev->vcn.num_inst_per_aid; 976 } 977 } 978 979 /** 980 * vcn_v5_0_1_is_idle - check VCN block is idle 981 * 982 * @ip_block: Pointer to the amdgpu_ip_block structure 983 * 984 * Check whether VCN block is idle 985 */ 986 static bool vcn_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block) 987 { 988 struct amdgpu_device *adev = ip_block->adev; 989 int i, ret = 1; 990 991 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 992 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE); 993 994 return ret; 995 } 996 997 /** 998 * vcn_v5_0_1_wait_for_idle - wait for VCN block idle 999 * 1000 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1001 * 1002 * Wait for VCN block idle 1003 */ 1004 static int vcn_v5_0_1_wait_for_idle(struct amdgpu_ip_block *ip_block) 1005 { 1006 struct amdgpu_device *adev = ip_block->adev; 1007 int i, ret = 0; 1008 1009 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1010 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, 1011 UVD_STATUS__IDLE); 1012 if (ret) 1013 return ret; 1014 } 1015 1016 return ret; 1017 } 1018 1019 /** 1020 * vcn_v5_0_1_set_clockgating_state - set VCN block clockgating state 1021 * 1022 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1023 * @state: clock gating state 1024 * 1025 * Set VCN block clockgating state 1026 */ 1027 static int vcn_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1028 enum amd_clockgating_state state) 1029 { 1030 struct amdgpu_device *adev = ip_block->adev; 1031 bool enable = state == AMD_CG_STATE_GATE; 1032 int i; 1033 1034 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1035 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1036 1037 if (enable) { 1038 if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE) 1039 return -EBUSY; 1040 vcn_v5_0_1_enable_clock_gating(vinst); 1041 } else { 1042 vcn_v5_0_1_disable_clock_gating(vinst); 1043 } 1044 } 1045 1046 return 0; 1047 } 1048 1049 static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst, 1050 enum amd_powergating_state state) 1051 { 1052 int ret = 0; 1053 1054 if (state == vinst->cur_state) 1055 return 0; 1056 1057 if (state == AMD_PG_STATE_GATE) 1058 ret = vcn_v5_0_1_stop(vinst); 1059 else 1060 ret = vcn_v5_0_1_start(vinst); 1061 1062 if (!ret) 1063 vinst->cur_state = state; 1064 1065 return ret; 1066 } 1067 1068 /** 1069 * vcn_v5_0_1_process_interrupt - process VCN block interrupt 1070 * 1071 * @adev: amdgpu_device pointer 1072 * @source: interrupt sources 1073 * @entry: interrupt entry from clients and sources 1074 * 1075 * Process VCN block interrupt 1076 */ 1077 static int vcn_v5_0_1_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1078 struct amdgpu_iv_entry *entry) 1079 { 1080 uint32_t i, inst; 1081 1082 i = node_id_to_phys_map[entry->node_id]; 1083 1084 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1085 1086 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1087 if (adev->vcn.inst[inst].aid_id == i) 1088 break; 1089 if (inst >= adev->vcn.num_vcn_inst) { 1090 dev_WARN_ONCE(adev->dev, 1, 1091 "Interrupt received for unknown VCN instance %d", 1092 entry->node_id); 1093 return 0; 1094 } 1095 1096 switch (entry->src_id) { 1097 case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1098 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1099 break; 1100 default: 1101 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1102 entry->src_id, entry->src_data[0]); 1103 break; 1104 } 1105 1106 return 0; 1107 } 1108 1109 static const struct amdgpu_irq_src_funcs vcn_v5_0_1_irq_funcs = { 1110 .process = vcn_v5_0_1_process_interrupt, 1111 }; 1112 1113 /** 1114 * vcn_v5_0_1_set_irq_funcs - set VCN block interrupt irq functions 1115 * 1116 * @adev: amdgpu_device pointer 1117 * 1118 * Set VCN block interrupt irq functions 1119 */ 1120 static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev) 1121 { 1122 int i; 1123 1124 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 1125 adev->vcn.inst->irq.num_types++; 1126 adev->vcn.inst->irq.funcs = &vcn_v5_0_1_irq_funcs; 1127 } 1128 1129 static const struct amd_ip_funcs vcn_v5_0_1_ip_funcs = { 1130 .name = "vcn_v5_0_1", 1131 .early_init = vcn_v5_0_1_early_init, 1132 .late_init = NULL, 1133 .sw_init = vcn_v5_0_1_sw_init, 1134 .sw_fini = vcn_v5_0_1_sw_fini, 1135 .hw_init = vcn_v5_0_1_hw_init, 1136 .hw_fini = vcn_v5_0_1_hw_fini, 1137 .suspend = vcn_v5_0_1_suspend, 1138 .resume = vcn_v5_0_1_resume, 1139 .is_idle = vcn_v5_0_1_is_idle, 1140 .wait_for_idle = vcn_v5_0_1_wait_for_idle, 1141 .check_soft_reset = NULL, 1142 .pre_soft_reset = NULL, 1143 .soft_reset = NULL, 1144 .post_soft_reset = NULL, 1145 .set_clockgating_state = vcn_v5_0_1_set_clockgating_state, 1146 .set_powergating_state = vcn_set_powergating_state, 1147 .dump_ip_state = vcn_v5_0_0_dump_ip_state, 1148 .print_ip_state = vcn_v5_0_0_print_ip_state, 1149 }; 1150 1151 const struct amdgpu_ip_block_version vcn_v5_0_1_ip_block = { 1152 .type = AMD_IP_BLOCK_TYPE_VCN, 1153 .major = 5, 1154 .minor = 0, 1155 .rev = 1, 1156 .funcs = &vcn_v5_0_1_ip_funcs, 1157 }; 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