1 /* 2 * Copyright 2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_hw_ip.h" 31 #include "vcn_v2_0.h" 32 #include "vcn_v4_0_3.h" 33 #include "mmsch_v5_0.h" 34 35 #include "vcn/vcn_5_0_0_offset.h" 36 #include "vcn/vcn_5_0_0_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" 38 #include "vcn_v5_0_0.h" 39 #include "vcn_v5_0_1.h" 40 41 #include <drm/drm_drv.h> 42 43 static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev); 44 static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev); 45 static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev); 46 static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst, 47 enum amd_powergating_state state); 48 static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring); 49 50 /** 51 * vcn_v5_0_1_early_init - set function pointers and load microcode 52 * 53 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 54 * 55 * Set ring and irq function pointers 56 * Load microcode from filesystem 57 */ 58 static int vcn_v5_0_1_early_init(struct amdgpu_ip_block *ip_block) 59 { 60 struct amdgpu_device *adev = ip_block->adev; 61 int i, r; 62 63 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 64 /* re-use enc ring as unified ring */ 65 adev->vcn.inst[i].num_enc_rings = 1; 66 67 vcn_v5_0_1_set_unified_ring_funcs(adev); 68 vcn_v5_0_1_set_irq_funcs(adev); 69 70 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 71 adev->vcn.inst[i].set_pg_state = vcn_v5_0_1_set_pg_state; 72 73 r = amdgpu_vcn_early_init(adev, i); 74 if (r) 75 return r; 76 } 77 78 return 0; 79 } 80 81 static void vcn_v5_0_1_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 82 { 83 struct amdgpu_vcn5_fw_shared *fw_shared; 84 85 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 86 87 if (fw_shared->sq.is_enabled) 88 return; 89 fw_shared->present_flag_0 = 90 cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 91 fw_shared->sq.is_enabled = 1; 92 93 if (amdgpu_vcnfw_log) 94 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 95 } 96 97 /** 98 * vcn_v5_0_1_sw_init - sw init for VCN block 99 * 100 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 101 * 102 * Load firmware and sw initialization 103 */ 104 static int vcn_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) 105 { 106 struct amdgpu_device *adev = ip_block->adev; 107 struct amdgpu_ring *ring; 108 int i, r, vcn_inst; 109 110 /* VCN UNIFIED TRAP */ 111 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 112 VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 113 if (r) 114 return r; 115 116 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 117 vcn_inst = GET_INST(VCN, i); 118 119 r = amdgpu_vcn_sw_init(adev, i); 120 if (r) 121 return r; 122 123 amdgpu_vcn_setup_ucode(adev, i); 124 125 r = amdgpu_vcn_resume(adev, i); 126 if (r) 127 return r; 128 129 ring = &adev->vcn.inst[i].ring_enc[0]; 130 ring->use_doorbell = true; 131 if (!amdgpu_sriov_vf(adev)) 132 ring->doorbell_index = 133 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 134 11 * vcn_inst; 135 else 136 ring->doorbell_index = 137 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 138 32 * vcn_inst; 139 140 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 141 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 142 143 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 144 AMDGPU_RING_PRIO_DEFAULT, &adev->vcn.inst[i].sched_score); 145 if (r) 146 return r; 147 148 vcn_v5_0_1_fw_shared_init(adev, i); 149 } 150 151 /* TODO: Add queue reset mask when FW fully supports it */ 152 adev->vcn.supported_reset = 153 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 154 155 if (amdgpu_sriov_vf(adev)) { 156 r = amdgpu_virt_alloc_mm_table(adev); 157 if (r) 158 return r; 159 } 160 161 vcn_v5_0_0_alloc_ip_dump(adev); 162 163 return amdgpu_vcn_sysfs_reset_mask_init(adev); 164 } 165 166 /** 167 * vcn_v5_0_1_sw_fini - sw fini for VCN block 168 * 169 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 170 * 171 * VCN suspend and free up sw allocation 172 */ 173 static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block) 174 { 175 struct amdgpu_device *adev = ip_block->adev; 176 int i, r, idx; 177 178 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 179 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 180 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 181 182 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 183 fw_shared->present_flag_0 = 0; 184 fw_shared->sq.is_enabled = 0; 185 } 186 187 drm_dev_exit(idx); 188 } 189 190 if (amdgpu_sriov_vf(adev)) 191 amdgpu_virt_free_mm_table(adev); 192 193 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 194 r = amdgpu_vcn_suspend(adev, i); 195 if (r) 196 return r; 197 } 198 199 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 200 r = amdgpu_vcn_sw_fini(adev, i); 201 if (r) 202 return r; 203 } 204 205 amdgpu_vcn_sysfs_reset_mask_fini(adev); 206 207 kfree(adev->vcn.ip_dump); 208 209 return 0; 210 } 211 212 /** 213 * vcn_v5_0_1_hw_init - start and test VCN block 214 * 215 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 216 * 217 * Initialize the hardware, boot up the VCPU and do some testing 218 */ 219 static int vcn_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block) 220 { 221 struct amdgpu_device *adev = ip_block->adev; 222 struct amdgpu_ring *ring; 223 int i, r, vcn_inst; 224 225 if (amdgpu_sriov_vf(adev)) { 226 r = vcn_v5_0_1_start_sriov(adev); 227 if (r) 228 return r; 229 230 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 231 ring = &adev->vcn.inst[i].ring_enc[0]; 232 ring->wptr = 0; 233 ring->wptr_old = 0; 234 vcn_v5_0_1_unified_ring_set_wptr(ring); 235 ring->sched.ready = true; 236 } 237 } else { 238 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 239 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 240 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 241 vcn_inst = GET_INST(VCN, i); 242 ring = &adev->vcn.inst[i].ring_enc[0]; 243 244 if (ring->use_doorbell) 245 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 246 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 247 11 * vcn_inst), 248 adev->vcn.inst[i].aid_id); 249 250 /* Re-init fw_shared, if required */ 251 vcn_v5_0_1_fw_shared_init(adev, i); 252 253 r = amdgpu_ring_test_helper(ring); 254 if (r) 255 return r; 256 } 257 } 258 259 return 0; 260 } 261 262 /** 263 * vcn_v5_0_1_hw_fini - stop the hardware block 264 * 265 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 266 * 267 * Stop the VCN block, mark ring as not ready any more 268 */ 269 static int vcn_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block) 270 { 271 struct amdgpu_device *adev = ip_block->adev; 272 int i; 273 274 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 275 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 276 277 cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work); 278 if (vinst->cur_state != AMD_PG_STATE_GATE) 279 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 280 } 281 282 return 0; 283 } 284 285 /** 286 * vcn_v5_0_1_suspend - suspend VCN block 287 * 288 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 289 * 290 * HW fini and suspend VCN block 291 */ 292 static int vcn_v5_0_1_suspend(struct amdgpu_ip_block *ip_block) 293 { 294 struct amdgpu_device *adev = ip_block->adev; 295 int r, i; 296 297 r = vcn_v5_0_1_hw_fini(ip_block); 298 if (r) 299 return r; 300 301 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 302 r = amdgpu_vcn_suspend(ip_block->adev, i); 303 if (r) 304 return r; 305 } 306 307 return r; 308 } 309 310 /** 311 * vcn_v5_0_1_resume - resume VCN block 312 * 313 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 314 * 315 * Resume firmware and hw init VCN block 316 */ 317 static int vcn_v5_0_1_resume(struct amdgpu_ip_block *ip_block) 318 { 319 struct amdgpu_device *adev = ip_block->adev; 320 int r, i; 321 322 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 323 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 324 325 if (amdgpu_in_reset(adev)) 326 vinst->cur_state = AMD_PG_STATE_GATE; 327 328 r = amdgpu_vcn_resume(ip_block->adev, i); 329 if (r) 330 return r; 331 } 332 333 r = vcn_v5_0_1_hw_init(ip_block); 334 335 return r; 336 } 337 338 /** 339 * vcn_v5_0_1_mc_resume - memory controller programming 340 * 341 * @vinst: VCN instance 342 * 343 * Let the VCN memory controller know it's offsets 344 */ 345 static void vcn_v5_0_1_mc_resume(struct amdgpu_vcn_inst *vinst) 346 { 347 struct amdgpu_device *adev = vinst->adev; 348 int inst = vinst->inst; 349 uint32_t offset, size, vcn_inst; 350 const struct common_firmware_header *hdr; 351 352 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 353 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 354 355 vcn_inst = GET_INST(VCN, inst); 356 /* cache window 0: fw */ 357 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 358 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 359 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 360 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 361 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 362 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 363 offset = 0; 364 } else { 365 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 366 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 367 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 368 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 369 offset = size; 370 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 371 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 372 } 373 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 374 375 /* cache window 1: stack */ 376 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 377 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 378 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 379 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 380 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 381 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 382 383 /* cache window 2: context */ 384 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 385 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 386 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 387 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 388 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 389 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 390 391 /* non-cache window */ 392 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 393 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 394 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 395 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 396 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 397 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 398 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); 399 } 400 401 /** 402 * vcn_v5_0_1_mc_resume_dpg_mode - memory controller programming for dpg mode 403 * 404 * @vinst: VCN instance 405 * @indirect: indirectly write sram 406 * 407 * Let the VCN memory controller know it's offsets with dpg mode 408 */ 409 static void vcn_v5_0_1_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 410 bool indirect) 411 { 412 struct amdgpu_device *adev = vinst->adev; 413 int inst_idx = vinst->inst; 414 uint32_t offset, size; 415 const struct common_firmware_header *hdr; 416 417 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 418 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 419 420 /* cache window 0: fw */ 421 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 422 if (!indirect) { 423 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 424 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 425 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 426 inst_idx].tmr_mc_addr_lo), 0, indirect); 427 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 428 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 429 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 430 inst_idx].tmr_mc_addr_hi), 0, indirect); 431 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 432 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 433 } else { 434 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 435 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 436 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 437 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 438 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 439 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 440 } 441 offset = 0; 442 } else { 443 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 444 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 445 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 446 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 447 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 448 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 449 offset = size; 450 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 451 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 452 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 453 } 454 455 if (!indirect) 456 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 457 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 458 else 459 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 460 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 461 462 /* cache window 1: stack */ 463 if (!indirect) { 464 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 465 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 466 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 467 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 468 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 469 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 470 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 471 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 472 } else { 473 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 474 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 475 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 476 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 477 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 478 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 479 } 480 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 481 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 482 483 /* cache window 2: context */ 484 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 485 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 486 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 487 AMDGPU_VCN_STACK_SIZE), 0, indirect); 488 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 489 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 490 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 491 AMDGPU_VCN_STACK_SIZE), 0, indirect); 492 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 493 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 494 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 495 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 496 497 /* non-cache window */ 498 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 499 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 500 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 501 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 502 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 503 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 504 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 505 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 506 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 507 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 508 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); 509 510 /* VCN global tiling registers */ 511 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 512 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 513 } 514 515 /** 516 * vcn_v5_0_1_disable_clock_gating - disable VCN clock gating 517 * 518 * @vinst: VCN instance 519 * 520 * Disable clock gating for VCN block 521 */ 522 static void vcn_v5_0_1_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 523 { 524 } 525 526 /** 527 * vcn_v5_0_1_enable_clock_gating - enable VCN clock gating 528 * 529 * @vinst: VCN instance 530 * 531 * Enable clock gating for VCN block 532 */ 533 static void vcn_v5_0_1_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 534 { 535 } 536 537 /** 538 * vcn_v5_0_1_pause_dpg_mode - VCN pause with dpg mode 539 * 540 * @vinst: VCN instance 541 * @new_state: pause state 542 * 543 * Pause dpg mode for VCN block 544 */ 545 static int vcn_v5_0_1_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 546 struct dpg_pause_state *new_state) 547 { 548 struct amdgpu_device *adev = vinst->adev; 549 uint32_t reg_data = 0; 550 int vcn_inst; 551 552 vcn_inst = GET_INST(VCN, vinst->inst); 553 554 /* pause/unpause if state is changed */ 555 if (vinst->pause_state.fw_based != new_state->fw_based) { 556 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d %s\n", 557 vinst->pause_state.fw_based, new_state->fw_based, 558 new_state->fw_based ? "VCN_DPG_STATE__PAUSE" : "VCN_DPG_STATE__UNPAUSE"); 559 reg_data = RREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE) & 560 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 561 562 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 563 /* pause DPG */ 564 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 565 WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); 566 567 /* wait for ACK */ 568 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_DPG_PAUSE, 569 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 570 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 571 } else { 572 /* unpause DPG, no need to wait */ 573 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 574 WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); 575 } 576 vinst->pause_state.fw_based = new_state->fw_based; 577 } 578 579 return 0; 580 } 581 582 583 /** 584 * vcn_v5_0_1_start_dpg_mode - VCN start with dpg mode 585 * 586 * @vinst: VCN instance 587 * @indirect: indirectly write sram 588 * 589 * Start VCN block with dpg mode 590 */ 591 static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 592 bool indirect) 593 { 594 struct amdgpu_device *adev = vinst->adev; 595 int inst_idx = vinst->inst; 596 volatile struct amdgpu_vcn5_fw_shared *fw_shared = 597 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 598 struct amdgpu_ring *ring; 599 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; 600 int vcn_inst; 601 uint32_t tmp; 602 603 vcn_inst = GET_INST(VCN, inst_idx); 604 605 /* disable register anti-hang mechanism */ 606 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 607 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 608 609 /* enable dynamic power gating mode */ 610 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 611 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 612 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 613 614 if (indirect) { 615 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 616 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 617 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 618 WREG32_SOC24_DPG_MODE(inst_idx, 0xDEADBEEF, 619 adev->vcn.inst[inst_idx].aid_id, 0, true); 620 } 621 622 /* enable VCPU clock */ 623 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 624 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 625 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 626 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 627 628 /* disable master interrupt */ 629 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 630 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 631 632 /* setup regUVD_LMI_CTRL */ 633 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 634 UVD_LMI_CTRL__REQ_MODE_MASK | 635 UVD_LMI_CTRL__CRC_RESET_MASK | 636 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 637 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 638 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 639 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 640 0x00100000L); 641 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 642 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 643 644 vcn_v5_0_1_mc_resume_dpg_mode(vinst, indirect); 645 646 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 647 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 648 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 649 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 650 651 /* enable LMI MC and UMC channels */ 652 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 653 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 654 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 655 656 /* enable master interrupt */ 657 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 658 VCN, 0, regUVD_MASTINT_EN), 659 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 660 661 if (indirect) 662 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 663 664 /* Pause dpg */ 665 vcn_v5_0_1_pause_dpg_mode(vinst, &state); 666 667 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 668 669 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); 670 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 671 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / sizeof(uint32_t)); 672 673 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 674 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 675 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 676 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 677 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 678 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 679 680 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); 681 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); 682 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 683 684 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 685 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 686 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 687 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 688 689 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 690 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 691 VCN_RB1_DB_CTRL__EN_MASK); 692 /* Read DB_CTRL to flush the write DB_CTRL command. */ 693 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 694 695 return 0; 696 } 697 698 static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev) 699 { 700 int i, vcn_inst; 701 struct amdgpu_ring *ring_enc; 702 uint64_t cache_addr; 703 uint64_t rb_enc_addr; 704 uint64_t ctx_addr; 705 uint32_t param, resp, expected; 706 uint32_t offset, cache_size; 707 uint32_t tmp, timeout; 708 709 struct amdgpu_mm_table *table = &adev->virt.mm_table; 710 uint32_t *table_loc; 711 uint32_t table_size; 712 uint32_t size, size_dw; 713 uint32_t init_status; 714 uint32_t enabled_vcn; 715 716 struct mmsch_v5_0_cmd_direct_write 717 direct_wt = { {0} }; 718 struct mmsch_v5_0_cmd_direct_read_modify_write 719 direct_rd_mod_wt = { {0} }; 720 struct mmsch_v5_0_cmd_end end = { {0} }; 721 struct mmsch_v5_0_init_header header; 722 723 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 724 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 725 726 direct_wt.cmd_header.command_type = 727 MMSCH_COMMAND__DIRECT_REG_WRITE; 728 direct_rd_mod_wt.cmd_header.command_type = 729 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 730 end.cmd_header.command_type = MMSCH_COMMAND__END; 731 732 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 733 vcn_inst = GET_INST(VCN, i); 734 735 vcn_v5_0_1_fw_shared_init(adev, vcn_inst); 736 737 memset(&header, 0, sizeof(struct mmsch_v5_0_init_header)); 738 header.version = MMSCH_VERSION; 739 header.total_size = sizeof(struct mmsch_v5_0_init_header) >> 2; 740 741 table_loc = (uint32_t *)table->cpu_addr; 742 table_loc += header.total_size; 743 744 table_size = 0; 745 746 MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 747 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 748 749 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 750 751 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 752 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 753 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 754 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 755 756 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 757 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 758 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 759 760 offset = 0; 761 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 762 regUVD_VCPU_CACHE_OFFSET0), 0); 763 } else { 764 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 765 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 766 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 767 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 768 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 769 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 770 offset = cache_size; 771 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 772 regUVD_VCPU_CACHE_OFFSET0), 773 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 774 } 775 776 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 777 regUVD_VCPU_CACHE_SIZE0), 778 cache_size); 779 780 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 781 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 782 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 783 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 784 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 785 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 786 regUVD_VCPU_CACHE_OFFSET1), 0); 787 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 788 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 789 790 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 791 AMDGPU_VCN_STACK_SIZE; 792 793 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 794 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 795 796 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 797 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 798 799 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 800 regUVD_VCPU_CACHE_OFFSET2), 0); 801 802 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 803 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 804 805 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 806 rb_setup = &fw_shared->rb_setup; 807 808 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 809 ring_enc->wptr = 0; 810 rb_enc_addr = ring_enc->gpu_addr; 811 812 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 813 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 814 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 815 rb_setup->rb_size = ring_enc->ring_size / 4; 816 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 817 818 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 819 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 820 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 821 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 822 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 823 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 824 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 825 regUVD_VCPU_NONCACHE_SIZE0), 826 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 827 MMSCH_V5_0_INSERT_END(); 828 829 header.vcn0.init_status = 0; 830 header.vcn0.table_offset = header.total_size; 831 header.vcn0.table_size = table_size; 832 header.total_size += table_size; 833 834 /* Send init table to mmsch */ 835 size = sizeof(struct mmsch_v5_0_init_header); 836 table_loc = (uint32_t *)table->cpu_addr; 837 memcpy((void *)table_loc, &header, size); 838 839 ctx_addr = table->gpu_addr; 840 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 841 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 842 843 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 844 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 845 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 846 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 847 848 size = header.total_size; 849 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 850 851 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 852 853 param = 0x00000001; 854 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 855 tmp = 0; 856 timeout = 1000; 857 resp = 0; 858 expected = MMSCH_VF_MAILBOX_RESP__OK; 859 while (resp != expected) { 860 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 861 if (resp != 0) 862 break; 863 864 udelay(10); 865 tmp = tmp + 10; 866 if (tmp >= timeout) { 867 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 868 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 869 "(expected=0x%08x, readback=0x%08x)\n", 870 tmp, expected, resp); 871 return -EBUSY; 872 } 873 } 874 875 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 876 init_status = ((struct mmsch_v5_0_init_header *)(table_loc))->vcn0.init_status; 877 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 878 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 879 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 880 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 881 } 882 } 883 884 return 0; 885 } 886 887 /** 888 * vcn_v5_0_1_start - VCN start 889 * 890 * @vinst: VCN instance 891 * 892 * Start VCN block 893 */ 894 static int vcn_v5_0_1_start(struct amdgpu_vcn_inst *vinst) 895 { 896 struct amdgpu_device *adev = vinst->adev; 897 int i = vinst->inst; 898 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 899 struct amdgpu_ring *ring; 900 uint32_t tmp; 901 int j, k, r, vcn_inst; 902 903 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 904 905 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 906 return vcn_v5_0_1_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 907 908 vcn_inst = GET_INST(VCN, i); 909 910 /* set VCN status busy */ 911 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 912 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 913 914 /* enable VCPU clock */ 915 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 916 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 917 918 /* disable master interrupt */ 919 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 920 ~UVD_MASTINT_EN__VCPU_EN_MASK); 921 922 /* enable LMI MC and UMC channels */ 923 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 924 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 925 926 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 927 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 928 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 929 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 930 931 /* setup regUVD_LMI_CTRL */ 932 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 933 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp | 934 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 935 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 936 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 937 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 938 939 vcn_v5_0_1_mc_resume(vinst); 940 941 /* VCN global tiling registers */ 942 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 943 adev->gfx.config.gb_addr_config); 944 945 /* unblock VCPU register access */ 946 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 947 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 948 949 /* release VCPU reset to boot */ 950 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 951 ~UVD_VCPU_CNTL__BLK_RST_MASK); 952 953 for (j = 0; j < 10; ++j) { 954 uint32_t status; 955 956 for (k = 0; k < 100; ++k) { 957 status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 958 if (status & 2) 959 break; 960 mdelay(100); 961 if (amdgpu_emu_mode == 1) 962 msleep(20); 963 } 964 965 if (amdgpu_emu_mode == 1) { 966 r = -1; 967 if (status & 2) { 968 r = 0; 969 break; 970 } 971 } else { 972 r = 0; 973 if (status & 2) 974 break; 975 976 dev_err(adev->dev, 977 "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 978 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 979 UVD_VCPU_CNTL__BLK_RST_MASK, 980 ~UVD_VCPU_CNTL__BLK_RST_MASK); 981 mdelay(10); 982 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 983 ~UVD_VCPU_CNTL__BLK_RST_MASK); 984 985 mdelay(10); 986 r = -1; 987 } 988 } 989 990 if (r) { 991 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 992 return r; 993 } 994 995 /* enable master interrupt */ 996 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 997 UVD_MASTINT_EN__VCPU_EN_MASK, 998 ~UVD_MASTINT_EN__VCPU_EN_MASK); 999 1000 /* clear the busy bit of VCN_STATUS */ 1001 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1002 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1003 1004 ring = &adev->vcn.inst[i].ring_enc[0]; 1005 1006 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 1007 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1008 VCN_RB1_DB_CTRL__EN_MASK); 1009 1010 /* Read DB_CTRL to flush the write DB_CTRL command. */ 1011 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 1012 1013 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr); 1014 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1015 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4); 1016 1017 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1018 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1019 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1020 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1021 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1022 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1023 1024 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); 1025 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); 1026 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1027 1028 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1029 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1030 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1031 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1032 1033 return 0; 1034 } 1035 1036 /** 1037 * vcn_v5_0_1_stop_dpg_mode - VCN stop with dpg mode 1038 * 1039 * @vinst: VCN instance 1040 * 1041 * Stop VCN block with dpg mode 1042 */ 1043 static void vcn_v5_0_1_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1044 { 1045 struct amdgpu_device *adev = vinst->adev; 1046 int inst_idx = vinst->inst; 1047 uint32_t tmp; 1048 int vcn_inst; 1049 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1050 1051 vcn_inst = GET_INST(VCN, inst_idx); 1052 1053 /* Unpause dpg */ 1054 vcn_v5_0_1_pause_dpg_mode(vinst, &state); 1055 1056 /* Wait for power status to be 1 */ 1057 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1058 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1059 1060 /* wait for read ptr to be equal to write ptr */ 1061 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1062 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1063 1064 /* disable dynamic power gating mode */ 1065 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1066 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1067 } 1068 1069 /** 1070 * vcn_v5_0_1_stop - VCN stop 1071 * 1072 * @vinst: VCN instance 1073 * 1074 * Stop VCN block 1075 */ 1076 static int vcn_v5_0_1_stop(struct amdgpu_vcn_inst *vinst) 1077 { 1078 struct amdgpu_device *adev = vinst->adev; 1079 int i = vinst->inst; 1080 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 1081 uint32_t tmp; 1082 int r = 0, vcn_inst; 1083 1084 vcn_inst = GET_INST(VCN, i); 1085 1086 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1087 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1088 1089 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1090 vcn_v5_0_1_stop_dpg_mode(vinst); 1091 return 0; 1092 } 1093 1094 /* wait for vcn idle */ 1095 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1096 if (r) 1097 return r; 1098 1099 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1100 UVD_LMI_STATUS__READ_CLEAN_MASK | 1101 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1102 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1103 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); 1104 if (r) 1105 return r; 1106 1107 /* disable LMI UMC channel */ 1108 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1109 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1110 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1111 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1112 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1113 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); 1114 if (r) 1115 return r; 1116 1117 /* block VCPU register access */ 1118 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1119 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1120 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1121 1122 /* reset VCPU */ 1123 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1124 UVD_VCPU_CNTL__BLK_RST_MASK, 1125 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1126 1127 /* disable VCPU clock */ 1128 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1129 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1130 1131 /* apply soft reset */ 1132 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1133 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1134 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1135 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1136 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1137 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1138 1139 /* clear status */ 1140 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1141 1142 return 0; 1143 } 1144 1145 /** 1146 * vcn_v5_0_1_unified_ring_get_rptr - get unified read pointer 1147 * 1148 * @ring: amdgpu_ring pointer 1149 * 1150 * Returns the current hardware unified read pointer 1151 */ 1152 static uint64_t vcn_v5_0_1_unified_ring_get_rptr(struct amdgpu_ring *ring) 1153 { 1154 struct amdgpu_device *adev = ring->adev; 1155 1156 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1157 DRM_ERROR("wrong ring id is identified in %s", __func__); 1158 1159 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1160 } 1161 1162 /** 1163 * vcn_v5_0_1_unified_ring_get_wptr - get unified write pointer 1164 * 1165 * @ring: amdgpu_ring pointer 1166 * 1167 * Returns the current hardware unified write pointer 1168 */ 1169 static uint64_t vcn_v5_0_1_unified_ring_get_wptr(struct amdgpu_ring *ring) 1170 { 1171 struct amdgpu_device *adev = ring->adev; 1172 1173 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1174 DRM_ERROR("wrong ring id is identified in %s", __func__); 1175 1176 if (ring->use_doorbell) 1177 return *ring->wptr_cpu_addr; 1178 else 1179 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR); 1180 } 1181 1182 /** 1183 * vcn_v5_0_1_unified_ring_set_wptr - set enc write pointer 1184 * 1185 * @ring: amdgpu_ring pointer 1186 * 1187 * Commits the enc write pointer to the hardware 1188 */ 1189 static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring) 1190 { 1191 struct amdgpu_device *adev = ring->adev; 1192 1193 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1194 DRM_ERROR("wrong ring id is identified in %s", __func__); 1195 1196 if (ring->use_doorbell) { 1197 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1198 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1199 } else { 1200 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1201 lower_32_bits(ring->wptr)); 1202 } 1203 } 1204 1205 static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { 1206 .type = AMDGPU_RING_TYPE_VCN_ENC, 1207 .align_mask = 0x3f, 1208 .nop = VCN_ENC_CMD_NO_OP, 1209 .get_rptr = vcn_v5_0_1_unified_ring_get_rptr, 1210 .get_wptr = vcn_v5_0_1_unified_ring_get_wptr, 1211 .set_wptr = vcn_v5_0_1_unified_ring_set_wptr, 1212 .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1213 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1214 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1215 5 + 1216 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1217 1, /* vcn_v2_0_enc_ring_insert_end */ 1218 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1219 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1220 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1221 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1222 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1223 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1224 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1225 .insert_nop = amdgpu_ring_insert_nop, 1226 .insert_end = vcn_v2_0_enc_ring_insert_end, 1227 .pad_ib = amdgpu_ring_generic_pad_ib, 1228 .begin_use = amdgpu_vcn_ring_begin_use, 1229 .end_use = amdgpu_vcn_ring_end_use, 1230 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1231 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1232 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1233 }; 1234 1235 /** 1236 * vcn_v5_0_1_set_unified_ring_funcs - set unified ring functions 1237 * 1238 * @adev: amdgpu_device pointer 1239 * 1240 * Set unified ring functions 1241 */ 1242 static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev) 1243 { 1244 int i, vcn_inst; 1245 1246 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1247 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_1_unified_ring_vm_funcs; 1248 adev->vcn.inst[i].ring_enc[0].me = i; 1249 vcn_inst = GET_INST(VCN, i); 1250 adev->vcn.inst[i].aid_id = vcn_inst / adev->vcn.num_inst_per_aid; 1251 } 1252 } 1253 1254 /** 1255 * vcn_v5_0_1_is_idle - check VCN block is idle 1256 * 1257 * @ip_block: Pointer to the amdgpu_ip_block structure 1258 * 1259 * Check whether VCN block is idle 1260 */ 1261 static bool vcn_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block) 1262 { 1263 struct amdgpu_device *adev = ip_block->adev; 1264 int i, ret = 1; 1265 1266 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 1267 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE); 1268 1269 return ret; 1270 } 1271 1272 /** 1273 * vcn_v5_0_1_wait_for_idle - wait for VCN block idle 1274 * 1275 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1276 * 1277 * Wait for VCN block idle 1278 */ 1279 static int vcn_v5_0_1_wait_for_idle(struct amdgpu_ip_block *ip_block) 1280 { 1281 struct amdgpu_device *adev = ip_block->adev; 1282 int i, ret = 0; 1283 1284 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1285 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, 1286 UVD_STATUS__IDLE); 1287 if (ret) 1288 return ret; 1289 } 1290 1291 return ret; 1292 } 1293 1294 /** 1295 * vcn_v5_0_1_set_clockgating_state - set VCN block clockgating state 1296 * 1297 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1298 * @state: clock gating state 1299 * 1300 * Set VCN block clockgating state 1301 */ 1302 static int vcn_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1303 enum amd_clockgating_state state) 1304 { 1305 struct amdgpu_device *adev = ip_block->adev; 1306 bool enable = state == AMD_CG_STATE_GATE; 1307 int i; 1308 1309 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1310 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1311 1312 if (enable) { 1313 if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE) 1314 return -EBUSY; 1315 vcn_v5_0_1_enable_clock_gating(vinst); 1316 } else { 1317 vcn_v5_0_1_disable_clock_gating(vinst); 1318 } 1319 } 1320 1321 return 0; 1322 } 1323 1324 static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst, 1325 enum amd_powergating_state state) 1326 { 1327 struct amdgpu_device *adev = vinst->adev; 1328 int ret = 0; 1329 1330 /* for SRIOV, guest should not control VCN Power-gating 1331 * MMSCH FW should control Power-gating and clock-gating 1332 * guest should avoid touching CGC and PG 1333 */ 1334 if (amdgpu_sriov_vf(adev)) { 1335 vinst->cur_state = AMD_PG_STATE_UNGATE; 1336 return 0; 1337 } 1338 1339 if (state == vinst->cur_state) 1340 return 0; 1341 1342 if (state == AMD_PG_STATE_GATE) 1343 ret = vcn_v5_0_1_stop(vinst); 1344 else 1345 ret = vcn_v5_0_1_start(vinst); 1346 1347 if (!ret) 1348 vinst->cur_state = state; 1349 1350 return ret; 1351 } 1352 1353 /** 1354 * vcn_v5_0_1_process_interrupt - process VCN block interrupt 1355 * 1356 * @adev: amdgpu_device pointer 1357 * @source: interrupt sources 1358 * @entry: interrupt entry from clients and sources 1359 * 1360 * Process VCN block interrupt 1361 */ 1362 static int vcn_v5_0_1_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1363 struct amdgpu_iv_entry *entry) 1364 { 1365 uint32_t i, inst; 1366 1367 i = node_id_to_phys_map[entry->node_id]; 1368 1369 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1370 1371 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1372 if (adev->vcn.inst[inst].aid_id == i) 1373 break; 1374 if (inst >= adev->vcn.num_vcn_inst) { 1375 dev_WARN_ONCE(adev->dev, 1, 1376 "Interrupt received for unknown VCN instance %d", 1377 entry->node_id); 1378 return 0; 1379 } 1380 1381 switch (entry->src_id) { 1382 case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1383 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1384 break; 1385 default: 1386 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1387 entry->src_id, entry->src_data[0]); 1388 break; 1389 } 1390 1391 return 0; 1392 } 1393 1394 static const struct amdgpu_irq_src_funcs vcn_v5_0_1_irq_funcs = { 1395 .process = vcn_v5_0_1_process_interrupt, 1396 }; 1397 1398 /** 1399 * vcn_v5_0_1_set_irq_funcs - set VCN block interrupt irq functions 1400 * 1401 * @adev: amdgpu_device pointer 1402 * 1403 * Set VCN block interrupt irq functions 1404 */ 1405 static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev) 1406 { 1407 int i; 1408 1409 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 1410 adev->vcn.inst->irq.num_types++; 1411 adev->vcn.inst->irq.funcs = &vcn_v5_0_1_irq_funcs; 1412 } 1413 1414 static const struct amd_ip_funcs vcn_v5_0_1_ip_funcs = { 1415 .name = "vcn_v5_0_1", 1416 .early_init = vcn_v5_0_1_early_init, 1417 .late_init = NULL, 1418 .sw_init = vcn_v5_0_1_sw_init, 1419 .sw_fini = vcn_v5_0_1_sw_fini, 1420 .hw_init = vcn_v5_0_1_hw_init, 1421 .hw_fini = vcn_v5_0_1_hw_fini, 1422 .suspend = vcn_v5_0_1_suspend, 1423 .resume = vcn_v5_0_1_resume, 1424 .is_idle = vcn_v5_0_1_is_idle, 1425 .wait_for_idle = vcn_v5_0_1_wait_for_idle, 1426 .check_soft_reset = NULL, 1427 .pre_soft_reset = NULL, 1428 .soft_reset = NULL, 1429 .post_soft_reset = NULL, 1430 .set_clockgating_state = vcn_v5_0_1_set_clockgating_state, 1431 .set_powergating_state = vcn_set_powergating_state, 1432 .dump_ip_state = vcn_v5_0_0_dump_ip_state, 1433 .print_ip_state = vcn_v5_0_0_print_ip_state, 1434 }; 1435 1436 const struct amdgpu_ip_block_version vcn_v5_0_1_ip_block = { 1437 .type = AMD_IP_BLOCK_TYPE_VCN, 1438 .major = 5, 1439 .minor = 0, 1440 .rev = 1, 1441 .funcs = &vcn_v5_0_1_ip_funcs, 1442 }; 1443