1 /* 2 * Copyright 2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_hw_ip.h" 31 #include "vcn_v2_0.h" 32 #include "vcn_v4_0_3.h" 33 #include "mmsch_v5_0.h" 34 35 #include "vcn/vcn_5_0_0_offset.h" 36 #include "vcn/vcn_5_0_0_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" 38 #include "vcn_v5_0_0.h" 39 #include "vcn_v5_0_1.h" 40 41 #include <drm/drm_drv.h> 42 43 static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0_1[] = { 44 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 45 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 46 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 47 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 48 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 75 }; 76 77 static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev); 78 static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev); 79 static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev); 80 static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst, 81 enum amd_powergating_state state); 82 static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring); 83 static void vcn_v5_0_1_set_ras_funcs(struct amdgpu_device *adev); 84 /** 85 * vcn_v5_0_1_early_init - set function pointers and load microcode 86 * 87 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 88 * 89 * Set ring and irq function pointers 90 * Load microcode from filesystem 91 */ 92 static int vcn_v5_0_1_early_init(struct amdgpu_ip_block *ip_block) 93 { 94 struct amdgpu_device *adev = ip_block->adev; 95 int i, r; 96 97 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 98 /* re-use enc ring as unified ring */ 99 adev->vcn.inst[i].num_enc_rings = 1; 100 101 vcn_v5_0_1_set_unified_ring_funcs(adev); 102 vcn_v5_0_1_set_irq_funcs(adev); 103 vcn_v5_0_1_set_ras_funcs(adev); 104 105 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 106 adev->vcn.inst[i].set_pg_state = vcn_v5_0_1_set_pg_state; 107 108 r = amdgpu_vcn_early_init(adev, i); 109 if (r) 110 return r; 111 } 112 113 return 0; 114 } 115 116 static void vcn_v5_0_1_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 117 { 118 struct amdgpu_vcn5_fw_shared *fw_shared; 119 120 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 121 122 if (fw_shared->sq.is_enabled) 123 return; 124 fw_shared->present_flag_0 = 125 cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 126 fw_shared->sq.is_enabled = 1; 127 128 if (amdgpu_vcnfw_log) 129 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 130 } 131 132 /** 133 * vcn_v5_0_1_sw_init - sw init for VCN block 134 * 135 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 136 * 137 * Load firmware and sw initialization 138 */ 139 static int vcn_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) 140 { 141 struct amdgpu_device *adev = ip_block->adev; 142 struct amdgpu_ring *ring; 143 int i, r, vcn_inst; 144 145 /* VCN UNIFIED TRAP */ 146 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 147 VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 148 if (r) 149 return r; 150 151 /* VCN POISON TRAP */ 152 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 153 VCN_5_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq); 154 155 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 156 vcn_inst = GET_INST(VCN, i); 157 158 r = amdgpu_vcn_sw_init(adev, i); 159 if (r) 160 return r; 161 162 amdgpu_vcn_setup_ucode(adev, i); 163 164 r = amdgpu_vcn_resume(adev, i); 165 if (r) 166 return r; 167 168 ring = &adev->vcn.inst[i].ring_enc[0]; 169 ring->use_doorbell = true; 170 if (!amdgpu_sriov_vf(adev)) 171 ring->doorbell_index = 172 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 173 11 * vcn_inst; 174 else 175 ring->doorbell_index = 176 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 177 32 * vcn_inst; 178 179 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 180 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 181 182 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 183 AMDGPU_RING_PRIO_DEFAULT, &adev->vcn.inst[i].sched_score); 184 if (r) 185 return r; 186 187 vcn_v5_0_1_fw_shared_init(adev, i); 188 } 189 190 /* TODO: Add queue reset mask when FW fully supports it */ 191 adev->vcn.supported_reset = 192 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 193 194 if (amdgpu_sriov_vf(adev)) { 195 r = amdgpu_virt_alloc_mm_table(adev); 196 if (r) 197 return r; 198 } 199 200 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 201 r = amdgpu_vcn_ras_sw_init(adev); 202 if (r) { 203 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 204 return r; 205 } 206 } 207 208 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0_1, ARRAY_SIZE(vcn_reg_list_5_0_1)); 209 if (r) 210 return r; 211 212 return amdgpu_vcn_sysfs_reset_mask_init(adev); 213 } 214 215 /** 216 * vcn_v5_0_1_sw_fini - sw fini for VCN block 217 * 218 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 219 * 220 * VCN suspend and free up sw allocation 221 */ 222 static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block) 223 { 224 struct amdgpu_device *adev = ip_block->adev; 225 int i, r, idx; 226 227 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 228 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 229 struct amdgpu_vcn5_fw_shared *fw_shared; 230 231 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 232 fw_shared->present_flag_0 = 0; 233 fw_shared->sq.is_enabled = 0; 234 } 235 236 drm_dev_exit(idx); 237 } 238 239 if (amdgpu_sriov_vf(adev)) 240 amdgpu_virt_free_mm_table(adev); 241 242 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 243 r = amdgpu_vcn_suspend(adev, i); 244 if (r) 245 return r; 246 } 247 248 amdgpu_vcn_sysfs_reset_mask_fini(adev); 249 250 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 251 amdgpu_vcn_sw_fini(adev, i); 252 253 return 0; 254 } 255 256 /** 257 * vcn_v5_0_1_hw_init - start and test VCN block 258 * 259 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 260 * 261 * Initialize the hardware, boot up the VCPU and do some testing 262 */ 263 static int vcn_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block) 264 { 265 struct amdgpu_device *adev = ip_block->adev; 266 struct amdgpu_ring *ring; 267 int i, r, vcn_inst; 268 269 if (amdgpu_sriov_vf(adev)) { 270 r = vcn_v5_0_1_start_sriov(adev); 271 if (r) 272 return r; 273 274 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 275 ring = &adev->vcn.inst[i].ring_enc[0]; 276 ring->wptr = 0; 277 ring->wptr_old = 0; 278 vcn_v5_0_1_unified_ring_set_wptr(ring); 279 ring->sched.ready = true; 280 } 281 } else { 282 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 283 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 284 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 285 vcn_inst = GET_INST(VCN, i); 286 ring = &adev->vcn.inst[i].ring_enc[0]; 287 288 if (ring->use_doorbell) 289 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 290 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 291 11 * vcn_inst), 292 adev->vcn.inst[i].aid_id); 293 294 /* Re-init fw_shared, if required */ 295 vcn_v5_0_1_fw_shared_init(adev, i); 296 297 r = amdgpu_ring_test_helper(ring); 298 if (r) 299 return r; 300 } 301 } 302 303 return 0; 304 } 305 306 /** 307 * vcn_v5_0_1_hw_fini - stop the hardware block 308 * 309 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 310 * 311 * Stop the VCN block, mark ring as not ready any more 312 */ 313 static int vcn_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block) 314 { 315 struct amdgpu_device *adev = ip_block->adev; 316 int i; 317 318 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 319 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 320 321 cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work); 322 if (vinst->cur_state != AMD_PG_STATE_GATE) 323 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 324 } 325 326 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN) && !amdgpu_sriov_vf(adev)) 327 amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0); 328 329 return 0; 330 } 331 332 /** 333 * vcn_v5_0_1_suspend - suspend VCN block 334 * 335 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 336 * 337 * HW fini and suspend VCN block 338 */ 339 static int vcn_v5_0_1_suspend(struct amdgpu_ip_block *ip_block) 340 { 341 struct amdgpu_device *adev = ip_block->adev; 342 int r, i; 343 344 r = vcn_v5_0_1_hw_fini(ip_block); 345 if (r) 346 return r; 347 348 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 349 r = amdgpu_vcn_suspend(ip_block->adev, i); 350 if (r) 351 return r; 352 } 353 354 return r; 355 } 356 357 /** 358 * vcn_v5_0_1_resume - resume VCN block 359 * 360 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 361 * 362 * Resume firmware and hw init VCN block 363 */ 364 static int vcn_v5_0_1_resume(struct amdgpu_ip_block *ip_block) 365 { 366 struct amdgpu_device *adev = ip_block->adev; 367 int r, i; 368 369 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 370 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 371 372 if (amdgpu_in_reset(adev)) 373 vinst->cur_state = AMD_PG_STATE_GATE; 374 375 r = amdgpu_vcn_resume(ip_block->adev, i); 376 if (r) 377 return r; 378 } 379 380 r = vcn_v5_0_1_hw_init(ip_block); 381 382 return r; 383 } 384 385 /** 386 * vcn_v5_0_1_mc_resume - memory controller programming 387 * 388 * @vinst: VCN instance 389 * 390 * Let the VCN memory controller know it's offsets 391 */ 392 static void vcn_v5_0_1_mc_resume(struct amdgpu_vcn_inst *vinst) 393 { 394 struct amdgpu_device *adev = vinst->adev; 395 int inst = vinst->inst; 396 uint32_t offset, size, vcn_inst; 397 const struct common_firmware_header *hdr; 398 399 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 400 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 401 402 vcn_inst = GET_INST(VCN, inst); 403 /* cache window 0: fw */ 404 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 405 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 406 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 407 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 408 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 409 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 410 offset = 0; 411 } else { 412 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 413 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 414 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 415 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 416 offset = size; 417 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 418 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 419 } 420 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 421 422 /* cache window 1: stack */ 423 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 424 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 425 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 426 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 427 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 428 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 429 430 /* cache window 2: context */ 431 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 432 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 433 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 434 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 435 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 436 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 437 438 /* non-cache window */ 439 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 440 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 441 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 442 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 443 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 444 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 445 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); 446 } 447 448 /** 449 * vcn_v5_0_1_mc_resume_dpg_mode - memory controller programming for dpg mode 450 * 451 * @vinst: VCN instance 452 * @indirect: indirectly write sram 453 * 454 * Let the VCN memory controller know it's offsets with dpg mode 455 */ 456 static void vcn_v5_0_1_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 457 bool indirect) 458 { 459 struct amdgpu_device *adev = vinst->adev; 460 int inst_idx = vinst->inst; 461 uint32_t offset, size; 462 const struct common_firmware_header *hdr; 463 464 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 465 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 466 467 /* cache window 0: fw */ 468 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 469 if (!indirect) { 470 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 471 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 472 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 473 inst_idx].tmr_mc_addr_lo), 0, indirect); 474 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 475 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 476 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 477 inst_idx].tmr_mc_addr_hi), 0, indirect); 478 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 479 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 480 } else { 481 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 482 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 483 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 484 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 485 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 486 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 487 } 488 offset = 0; 489 } else { 490 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 491 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 492 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 493 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 494 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 495 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 496 offset = size; 497 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 498 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 499 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 500 } 501 502 if (!indirect) 503 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 504 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 505 else 506 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 507 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 508 509 /* cache window 1: stack */ 510 if (!indirect) { 511 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 512 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 513 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 514 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 515 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 516 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 517 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 518 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 519 } else { 520 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 521 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 522 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 523 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 524 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 525 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 526 } 527 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 528 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 529 530 /* cache window 2: context */ 531 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 532 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 533 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 534 AMDGPU_VCN_STACK_SIZE), 0, indirect); 535 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 536 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 537 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 538 AMDGPU_VCN_STACK_SIZE), 0, indirect); 539 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 540 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 541 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 542 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 543 544 /* non-cache window */ 545 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 546 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 547 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 548 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 549 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 550 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 551 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 552 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 553 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 554 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 555 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); 556 557 /* VCN global tiling registers */ 558 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 559 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 560 } 561 562 /** 563 * vcn_v5_0_1_disable_clock_gating - disable VCN clock gating 564 * 565 * @vinst: VCN instance 566 * 567 * Disable clock gating for VCN block 568 */ 569 static void vcn_v5_0_1_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 570 { 571 } 572 573 /** 574 * vcn_v5_0_1_enable_clock_gating - enable VCN clock gating 575 * 576 * @vinst: VCN instance 577 * 578 * Enable clock gating for VCN block 579 */ 580 static void vcn_v5_0_1_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 581 { 582 } 583 584 /** 585 * vcn_v5_0_1_pause_dpg_mode - VCN pause with dpg mode 586 * 587 * @vinst: VCN instance 588 * @new_state: pause state 589 * 590 * Pause dpg mode for VCN block 591 */ 592 static int vcn_v5_0_1_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 593 struct dpg_pause_state *new_state) 594 { 595 struct amdgpu_device *adev = vinst->adev; 596 uint32_t reg_data = 0; 597 int vcn_inst; 598 599 vcn_inst = GET_INST(VCN, vinst->inst); 600 601 /* pause/unpause if state is changed */ 602 if (vinst->pause_state.fw_based != new_state->fw_based) { 603 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d %s\n", 604 vinst->pause_state.fw_based, new_state->fw_based, 605 new_state->fw_based ? "VCN_DPG_STATE__PAUSE" : "VCN_DPG_STATE__UNPAUSE"); 606 reg_data = RREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE) & 607 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 608 609 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 610 /* pause DPG */ 611 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 612 WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); 613 614 /* wait for ACK */ 615 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_DPG_PAUSE, 616 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 617 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 618 } else { 619 /* unpause DPG, no need to wait */ 620 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 621 WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); 622 } 623 vinst->pause_state.fw_based = new_state->fw_based; 624 } 625 626 return 0; 627 } 628 629 630 /** 631 * vcn_v5_0_1_start_dpg_mode - VCN start with dpg mode 632 * 633 * @vinst: VCN instance 634 * @indirect: indirectly write sram 635 * 636 * Start VCN block with dpg mode 637 */ 638 static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 639 bool indirect) 640 { 641 struct amdgpu_device *adev = vinst->adev; 642 int inst_idx = vinst->inst; 643 struct amdgpu_vcn5_fw_shared *fw_shared = 644 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 645 struct amdgpu_ring *ring; 646 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; 647 int vcn_inst, ret; 648 uint32_t tmp; 649 650 vcn_inst = GET_INST(VCN, inst_idx); 651 652 /* disable register anti-hang mechanism */ 653 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 654 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 655 656 /* enable dynamic power gating mode */ 657 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 658 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 659 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 660 661 if (indirect) { 662 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 663 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 664 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 665 WREG32_SOC24_DPG_MODE(inst_idx, 0xDEADBEEF, 666 adev->vcn.inst[inst_idx].aid_id, 0, true); 667 } 668 669 /* enable VCPU clock */ 670 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 671 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 672 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 673 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 674 675 /* disable master interrupt */ 676 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 677 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 678 679 /* setup regUVD_LMI_CTRL */ 680 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 681 UVD_LMI_CTRL__REQ_MODE_MASK | 682 UVD_LMI_CTRL__CRC_RESET_MASK | 683 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 684 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 685 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 686 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 687 0x00100000L); 688 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 689 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 690 691 vcn_v5_0_1_mc_resume_dpg_mode(vinst, indirect); 692 693 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 694 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 695 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 696 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 697 698 /* enable LMI MC and UMC channels */ 699 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 700 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 701 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 702 703 /* enable master interrupt */ 704 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 705 VCN, 0, regUVD_MASTINT_EN), 706 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 707 708 if (indirect) { 709 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 710 if (ret) { 711 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 712 return ret; 713 } 714 } 715 716 /* resetting ring, fw should not check RB ring */ 717 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 718 719 /* Pause dpg */ 720 vcn_v5_0_1_pause_dpg_mode(vinst, &state); 721 722 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 723 724 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); 725 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 726 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / sizeof(uint32_t)); 727 728 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 729 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 730 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 731 732 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 733 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 734 735 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); 736 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); 737 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 738 739 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 740 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 741 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 742 /* resetting done, fw can check RB ring */ 743 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 744 745 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 746 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 747 VCN_RB1_DB_CTRL__EN_MASK); 748 /* Read DB_CTRL to flush the write DB_CTRL command. */ 749 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 750 751 return 0; 752 } 753 754 static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev) 755 { 756 int i, vcn_inst; 757 struct amdgpu_ring *ring_enc; 758 uint64_t cache_addr; 759 uint64_t rb_enc_addr; 760 uint64_t ctx_addr; 761 uint32_t param, resp, expected; 762 uint32_t offset, cache_size; 763 uint32_t tmp, timeout; 764 765 struct amdgpu_mm_table *table = &adev->virt.mm_table; 766 uint32_t *table_loc; 767 uint32_t table_size; 768 uint32_t size, size_dw; 769 uint32_t init_status; 770 uint32_t enabled_vcn; 771 772 struct mmsch_v5_0_cmd_direct_write 773 direct_wt = { {0} }; 774 struct mmsch_v5_0_cmd_direct_read_modify_write 775 direct_rd_mod_wt = { {0} }; 776 struct mmsch_v5_0_cmd_end end = { {0} }; 777 struct mmsch_v5_0_init_header header; 778 779 struct amdgpu_vcn5_fw_shared *fw_shared; 780 struct amdgpu_fw_shared_rb_setup *rb_setup; 781 782 direct_wt.cmd_header.command_type = 783 MMSCH_COMMAND__DIRECT_REG_WRITE; 784 direct_rd_mod_wt.cmd_header.command_type = 785 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 786 end.cmd_header.command_type = MMSCH_COMMAND__END; 787 788 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 789 vcn_inst = GET_INST(VCN, i); 790 791 vcn_v5_0_1_fw_shared_init(adev, vcn_inst); 792 793 memset(&header, 0, sizeof(struct mmsch_v5_0_init_header)); 794 header.version = MMSCH_VERSION; 795 header.total_size = sizeof(struct mmsch_v5_0_init_header) >> 2; 796 797 table_loc = (uint32_t *)table->cpu_addr; 798 table_loc += header.total_size; 799 800 table_size = 0; 801 802 MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 803 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 804 805 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 806 807 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 808 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 809 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 810 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 811 812 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 813 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 814 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 815 816 offset = 0; 817 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 818 regUVD_VCPU_CACHE_OFFSET0), 0); 819 } else { 820 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 821 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 822 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 823 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 824 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 825 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 826 offset = cache_size; 827 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 828 regUVD_VCPU_CACHE_OFFSET0), 829 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 830 } 831 832 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 833 regUVD_VCPU_CACHE_SIZE0), 834 cache_size); 835 836 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 837 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 838 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 839 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 840 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 841 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 842 regUVD_VCPU_CACHE_OFFSET1), 0); 843 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 844 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 845 846 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 847 AMDGPU_VCN_STACK_SIZE; 848 849 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 850 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 851 852 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 853 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 854 855 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 856 regUVD_VCPU_CACHE_OFFSET2), 0); 857 858 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 859 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 860 861 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 862 rb_setup = &fw_shared->rb_setup; 863 864 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 865 ring_enc->wptr = 0; 866 rb_enc_addr = ring_enc->gpu_addr; 867 868 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 869 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 870 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 871 rb_setup->rb_size = ring_enc->ring_size / 4; 872 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 873 874 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 875 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 876 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 877 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 878 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 879 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 880 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 881 regUVD_VCPU_NONCACHE_SIZE0), 882 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 883 MMSCH_V5_0_INSERT_END(); 884 885 header.vcn0.init_status = 0; 886 header.vcn0.table_offset = header.total_size; 887 header.vcn0.table_size = table_size; 888 header.total_size += table_size; 889 890 /* Send init table to mmsch */ 891 size = sizeof(struct mmsch_v5_0_init_header); 892 table_loc = (uint32_t *)table->cpu_addr; 893 memcpy((void *)table_loc, &header, size); 894 895 ctx_addr = table->gpu_addr; 896 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 897 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 898 899 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 900 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 901 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 902 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 903 904 size = header.total_size; 905 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 906 907 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 908 909 param = 0x00000001; 910 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 911 tmp = 0; 912 timeout = 1000; 913 resp = 0; 914 expected = MMSCH_VF_MAILBOX_RESP__OK; 915 while (resp != expected) { 916 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 917 if (resp != 0) 918 break; 919 920 udelay(10); 921 tmp = tmp + 10; 922 if (tmp >= timeout) { 923 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 924 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 925 "(expected=0x%08x, readback=0x%08x)\n", 926 tmp, expected, resp); 927 return -EBUSY; 928 } 929 } 930 931 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 932 init_status = ((struct mmsch_v5_0_init_header *)(table_loc))->vcn0.init_status; 933 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 934 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 935 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 936 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 937 } 938 } 939 940 return 0; 941 } 942 943 /** 944 * vcn_v5_0_1_start - VCN start 945 * 946 * @vinst: VCN instance 947 * 948 * Start VCN block 949 */ 950 static int vcn_v5_0_1_start(struct amdgpu_vcn_inst *vinst) 951 { 952 struct amdgpu_device *adev = vinst->adev; 953 int i = vinst->inst; 954 struct amdgpu_vcn5_fw_shared *fw_shared; 955 struct amdgpu_ring *ring; 956 uint32_t tmp; 957 int j, k, r, vcn_inst; 958 959 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 960 961 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 962 return vcn_v5_0_1_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 963 964 vcn_inst = GET_INST(VCN, i); 965 966 /* set VCN status busy */ 967 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 968 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 969 970 /* enable VCPU clock */ 971 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 972 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 973 974 /* disable master interrupt */ 975 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 976 ~UVD_MASTINT_EN__VCPU_EN_MASK); 977 978 /* enable LMI MC and UMC channels */ 979 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 980 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 981 982 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 983 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 984 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 985 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 986 987 /* setup regUVD_LMI_CTRL */ 988 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 989 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp | 990 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 991 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 992 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 993 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 994 995 vcn_v5_0_1_mc_resume(vinst); 996 997 /* VCN global tiling registers */ 998 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 999 adev->gfx.config.gb_addr_config); 1000 1001 /* unblock VCPU register access */ 1002 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1003 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1004 1005 /* release VCPU reset to boot */ 1006 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1007 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1008 1009 for (j = 0; j < 10; ++j) { 1010 uint32_t status; 1011 1012 for (k = 0; k < 100; ++k) { 1013 status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1014 if (status & 2) 1015 break; 1016 mdelay(100); 1017 if (amdgpu_emu_mode == 1) 1018 msleep(20); 1019 } 1020 1021 if (amdgpu_emu_mode == 1) { 1022 r = -1; 1023 if (status & 2) { 1024 r = 0; 1025 break; 1026 } 1027 } else { 1028 r = 0; 1029 if (status & 2) 1030 break; 1031 1032 dev_err(adev->dev, 1033 "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 1034 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1035 UVD_VCPU_CNTL__BLK_RST_MASK, 1036 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1037 mdelay(10); 1038 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1039 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1040 1041 mdelay(10); 1042 r = -1; 1043 } 1044 } 1045 1046 if (r) { 1047 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1048 return r; 1049 } 1050 1051 /* enable master interrupt */ 1052 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1053 UVD_MASTINT_EN__VCPU_EN_MASK, 1054 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1055 1056 /* clear the busy bit of VCN_STATUS */ 1057 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1058 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1059 1060 ring = &adev->vcn.inst[i].ring_enc[0]; 1061 1062 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 1063 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1064 VCN_RB1_DB_CTRL__EN_MASK); 1065 1066 /* Read DB_CTRL to flush the write DB_CTRL command. */ 1067 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 1068 1069 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr); 1070 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1071 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4); 1072 1073 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1074 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1075 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1076 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1077 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1078 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1079 1080 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); 1081 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); 1082 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1083 1084 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1085 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1086 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1087 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1088 1089 /* Keeping one read-back to ensure all register writes are done, 1090 * otherwise it may introduce race conditions. 1091 */ 1092 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1093 1094 return 0; 1095 } 1096 1097 /** 1098 * vcn_v5_0_1_stop_dpg_mode - VCN stop with dpg mode 1099 * 1100 * @vinst: VCN instance 1101 * 1102 * Stop VCN block with dpg mode 1103 */ 1104 static void vcn_v5_0_1_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1105 { 1106 struct amdgpu_device *adev = vinst->adev; 1107 int inst_idx = vinst->inst; 1108 uint32_t tmp; 1109 int vcn_inst; 1110 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1111 1112 vcn_inst = GET_INST(VCN, inst_idx); 1113 1114 /* Unpause dpg */ 1115 vcn_v5_0_1_pause_dpg_mode(vinst, &state); 1116 1117 /* Wait for power status to be 1 */ 1118 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1119 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1120 1121 /* wait for read ptr to be equal to write ptr */ 1122 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1123 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1124 1125 /* disable dynamic power gating mode */ 1126 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1127 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1128 1129 /* Keeping one read-back to ensure all register writes are done, 1130 * otherwise it may introduce race conditions. 1131 */ 1132 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1133 } 1134 1135 /** 1136 * vcn_v5_0_1_stop - VCN stop 1137 * 1138 * @vinst: VCN instance 1139 * 1140 * Stop VCN block 1141 */ 1142 static int vcn_v5_0_1_stop(struct amdgpu_vcn_inst *vinst) 1143 { 1144 struct amdgpu_device *adev = vinst->adev; 1145 int i = vinst->inst; 1146 struct amdgpu_vcn5_fw_shared *fw_shared; 1147 uint32_t tmp; 1148 int r = 0, vcn_inst; 1149 1150 vcn_inst = GET_INST(VCN, i); 1151 1152 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1153 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1154 1155 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1156 vcn_v5_0_1_stop_dpg_mode(vinst); 1157 return 0; 1158 } 1159 1160 /* wait for vcn idle */ 1161 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1162 if (r) 1163 return r; 1164 1165 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1166 UVD_LMI_STATUS__READ_CLEAN_MASK | 1167 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1168 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1169 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); 1170 if (r) 1171 return r; 1172 1173 /* disable LMI UMC channel */ 1174 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1175 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1176 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1177 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1178 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1179 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); 1180 if (r) 1181 return r; 1182 1183 /* block VCPU register access */ 1184 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1185 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1186 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1187 1188 /* reset VCPU */ 1189 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1190 UVD_VCPU_CNTL__BLK_RST_MASK, 1191 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1192 1193 /* disable VCPU clock */ 1194 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1195 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1196 1197 /* apply soft reset */ 1198 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1199 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1200 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1201 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1202 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1203 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1204 1205 /* clear status */ 1206 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1207 1208 /* Keeping one read-back to ensure all register writes are done, 1209 * otherwise it may introduce race conditions. 1210 */ 1211 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1212 1213 return 0; 1214 } 1215 1216 /** 1217 * vcn_v5_0_1_unified_ring_get_rptr - get unified read pointer 1218 * 1219 * @ring: amdgpu_ring pointer 1220 * 1221 * Returns the current hardware unified read pointer 1222 */ 1223 static uint64_t vcn_v5_0_1_unified_ring_get_rptr(struct amdgpu_ring *ring) 1224 { 1225 struct amdgpu_device *adev = ring->adev; 1226 1227 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1228 DRM_ERROR("wrong ring id is identified in %s", __func__); 1229 1230 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1231 } 1232 1233 /** 1234 * vcn_v5_0_1_unified_ring_get_wptr - get unified write pointer 1235 * 1236 * @ring: amdgpu_ring pointer 1237 * 1238 * Returns the current hardware unified write pointer 1239 */ 1240 static uint64_t vcn_v5_0_1_unified_ring_get_wptr(struct amdgpu_ring *ring) 1241 { 1242 struct amdgpu_device *adev = ring->adev; 1243 1244 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1245 DRM_ERROR("wrong ring id is identified in %s", __func__); 1246 1247 if (ring->use_doorbell) 1248 return *ring->wptr_cpu_addr; 1249 else 1250 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR); 1251 } 1252 1253 /** 1254 * vcn_v5_0_1_unified_ring_set_wptr - set enc write pointer 1255 * 1256 * @ring: amdgpu_ring pointer 1257 * 1258 * Commits the enc write pointer to the hardware 1259 */ 1260 static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring) 1261 { 1262 struct amdgpu_device *adev = ring->adev; 1263 1264 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1265 DRM_ERROR("wrong ring id is identified in %s", __func__); 1266 1267 if (ring->use_doorbell) { 1268 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1269 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1270 } else { 1271 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1272 lower_32_bits(ring->wptr)); 1273 } 1274 } 1275 1276 static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { 1277 .type = AMDGPU_RING_TYPE_VCN_ENC, 1278 .align_mask = 0x3f, 1279 .nop = VCN_ENC_CMD_NO_OP, 1280 .get_rptr = vcn_v5_0_1_unified_ring_get_rptr, 1281 .get_wptr = vcn_v5_0_1_unified_ring_get_wptr, 1282 .set_wptr = vcn_v5_0_1_unified_ring_set_wptr, 1283 .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1284 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1285 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1286 5 + 1287 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1288 1, /* vcn_v2_0_enc_ring_insert_end */ 1289 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1290 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1291 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1292 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1293 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1294 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1295 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1296 .insert_nop = amdgpu_ring_insert_nop, 1297 .insert_end = vcn_v2_0_enc_ring_insert_end, 1298 .pad_ib = amdgpu_ring_generic_pad_ib, 1299 .begin_use = amdgpu_vcn_ring_begin_use, 1300 .end_use = amdgpu_vcn_ring_end_use, 1301 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1302 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1303 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1304 }; 1305 1306 /** 1307 * vcn_v5_0_1_set_unified_ring_funcs - set unified ring functions 1308 * 1309 * @adev: amdgpu_device pointer 1310 * 1311 * Set unified ring functions 1312 */ 1313 static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev) 1314 { 1315 int i, vcn_inst; 1316 1317 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1318 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_1_unified_ring_vm_funcs; 1319 adev->vcn.inst[i].ring_enc[0].me = i; 1320 vcn_inst = GET_INST(VCN, i); 1321 adev->vcn.inst[i].aid_id = vcn_inst / adev->vcn.num_inst_per_aid; 1322 } 1323 } 1324 1325 /** 1326 * vcn_v5_0_1_is_idle - check VCN block is idle 1327 * 1328 * @ip_block: Pointer to the amdgpu_ip_block structure 1329 * 1330 * Check whether VCN block is idle 1331 */ 1332 static bool vcn_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block) 1333 { 1334 struct amdgpu_device *adev = ip_block->adev; 1335 int i, ret = 1; 1336 1337 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 1338 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE); 1339 1340 return ret; 1341 } 1342 1343 /** 1344 * vcn_v5_0_1_wait_for_idle - wait for VCN block idle 1345 * 1346 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1347 * 1348 * Wait for VCN block idle 1349 */ 1350 static int vcn_v5_0_1_wait_for_idle(struct amdgpu_ip_block *ip_block) 1351 { 1352 struct amdgpu_device *adev = ip_block->adev; 1353 int i, ret = 0; 1354 1355 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1356 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, 1357 UVD_STATUS__IDLE); 1358 if (ret) 1359 return ret; 1360 } 1361 1362 return ret; 1363 } 1364 1365 /** 1366 * vcn_v5_0_1_set_clockgating_state - set VCN block clockgating state 1367 * 1368 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1369 * @state: clock gating state 1370 * 1371 * Set VCN block clockgating state 1372 */ 1373 static int vcn_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1374 enum amd_clockgating_state state) 1375 { 1376 struct amdgpu_device *adev = ip_block->adev; 1377 bool enable = state == AMD_CG_STATE_GATE; 1378 int i; 1379 1380 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1381 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1382 1383 if (enable) { 1384 if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE) 1385 return -EBUSY; 1386 vcn_v5_0_1_enable_clock_gating(vinst); 1387 } else { 1388 vcn_v5_0_1_disable_clock_gating(vinst); 1389 } 1390 } 1391 1392 return 0; 1393 } 1394 1395 static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst, 1396 enum amd_powergating_state state) 1397 { 1398 struct amdgpu_device *adev = vinst->adev; 1399 int ret = 0; 1400 1401 /* for SRIOV, guest should not control VCN Power-gating 1402 * MMSCH FW should control Power-gating and clock-gating 1403 * guest should avoid touching CGC and PG 1404 */ 1405 if (amdgpu_sriov_vf(adev)) { 1406 vinst->cur_state = AMD_PG_STATE_UNGATE; 1407 return 0; 1408 } 1409 1410 if (state == vinst->cur_state) 1411 return 0; 1412 1413 if (state == AMD_PG_STATE_GATE) 1414 ret = vcn_v5_0_1_stop(vinst); 1415 else 1416 ret = vcn_v5_0_1_start(vinst); 1417 1418 if (!ret) 1419 vinst->cur_state = state; 1420 1421 return ret; 1422 } 1423 1424 /** 1425 * vcn_v5_0_1_process_interrupt - process VCN block interrupt 1426 * 1427 * @adev: amdgpu_device pointer 1428 * @source: interrupt sources 1429 * @entry: interrupt entry from clients and sources 1430 * 1431 * Process VCN block interrupt 1432 */ 1433 static int vcn_v5_0_1_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1434 struct amdgpu_iv_entry *entry) 1435 { 1436 uint32_t i, inst; 1437 1438 i = node_id_to_phys_map[entry->node_id]; 1439 1440 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1441 1442 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1443 if (adev->vcn.inst[inst].aid_id == i) 1444 break; 1445 if (inst >= adev->vcn.num_vcn_inst) { 1446 dev_WARN_ONCE(adev->dev, 1, 1447 "Interrupt received for unknown VCN instance %d", 1448 entry->node_id); 1449 return 0; 1450 } 1451 1452 switch (entry->src_id) { 1453 case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1454 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1455 break; 1456 default: 1457 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1458 entry->src_id, entry->src_data[0]); 1459 break; 1460 } 1461 1462 return 0; 1463 } 1464 1465 static int vcn_v5_0_1_set_ras_interrupt_state(struct amdgpu_device *adev, 1466 struct amdgpu_irq_src *source, 1467 unsigned int type, 1468 enum amdgpu_interrupt_state state) 1469 { 1470 return 0; 1471 } 1472 1473 static const struct amdgpu_irq_src_funcs vcn_v5_0_1_irq_funcs = { 1474 .process = vcn_v5_0_1_process_interrupt, 1475 }; 1476 1477 static const struct amdgpu_irq_src_funcs vcn_v5_0_1_ras_irq_funcs = { 1478 .set = vcn_v5_0_1_set_ras_interrupt_state, 1479 .process = amdgpu_vcn_process_poison_irq, 1480 }; 1481 1482 1483 /** 1484 * vcn_v5_0_1_set_irq_funcs - set VCN block interrupt irq functions 1485 * 1486 * @adev: amdgpu_device pointer 1487 * 1488 * Set VCN block interrupt irq functions 1489 */ 1490 static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev) 1491 { 1492 int i; 1493 1494 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 1495 adev->vcn.inst->irq.num_types++; 1496 1497 adev->vcn.inst->irq.funcs = &vcn_v5_0_1_irq_funcs; 1498 1499 adev->vcn.inst->ras_poison_irq.num_types = 1; 1500 adev->vcn.inst->ras_poison_irq.funcs = &vcn_v5_0_1_ras_irq_funcs; 1501 1502 } 1503 1504 static const struct amd_ip_funcs vcn_v5_0_1_ip_funcs = { 1505 .name = "vcn_v5_0_1", 1506 .early_init = vcn_v5_0_1_early_init, 1507 .late_init = NULL, 1508 .sw_init = vcn_v5_0_1_sw_init, 1509 .sw_fini = vcn_v5_0_1_sw_fini, 1510 .hw_init = vcn_v5_0_1_hw_init, 1511 .hw_fini = vcn_v5_0_1_hw_fini, 1512 .suspend = vcn_v5_0_1_suspend, 1513 .resume = vcn_v5_0_1_resume, 1514 .is_idle = vcn_v5_0_1_is_idle, 1515 .wait_for_idle = vcn_v5_0_1_wait_for_idle, 1516 .check_soft_reset = NULL, 1517 .pre_soft_reset = NULL, 1518 .soft_reset = NULL, 1519 .post_soft_reset = NULL, 1520 .set_clockgating_state = vcn_v5_0_1_set_clockgating_state, 1521 .set_powergating_state = vcn_set_powergating_state, 1522 .dump_ip_state = amdgpu_vcn_dump_ip_state, 1523 .print_ip_state = amdgpu_vcn_print_ip_state, 1524 }; 1525 1526 const struct amdgpu_ip_block_version vcn_v5_0_1_ip_block = { 1527 .type = AMD_IP_BLOCK_TYPE_VCN, 1528 .major = 5, 1529 .minor = 0, 1530 .rev = 1, 1531 .funcs = &vcn_v5_0_1_ip_funcs, 1532 }; 1533 1534 static uint32_t vcn_v5_0_1_query_poison_by_instance(struct amdgpu_device *adev, 1535 uint32_t instance, uint32_t sub_block) 1536 { 1537 uint32_t poison_stat = 0, reg_value = 0; 1538 1539 switch (sub_block) { 1540 case AMDGPU_VCN_V5_0_1_VCPU_VCODEC: 1541 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 1542 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 1543 break; 1544 default: 1545 break; 1546 } 1547 1548 if (poison_stat) 1549 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 1550 instance, sub_block); 1551 1552 return poison_stat; 1553 } 1554 1555 static bool vcn_v5_0_1_query_poison_status(struct amdgpu_device *adev) 1556 { 1557 uint32_t inst, sub; 1558 uint32_t poison_stat = 0; 1559 1560 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 1561 for (sub = 0; sub < AMDGPU_VCN_V5_0_1_MAX_SUB_BLOCK; sub++) 1562 poison_stat += 1563 vcn_v5_0_1_query_poison_by_instance(adev, inst, sub); 1564 1565 return !!poison_stat; 1566 } 1567 1568 static const struct amdgpu_ras_block_hw_ops vcn_v5_0_1_ras_hw_ops = { 1569 .query_poison_status = vcn_v5_0_1_query_poison_status, 1570 }; 1571 1572 static int vcn_v5_0_1_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1573 enum aca_smu_type type, void *data) 1574 { 1575 struct aca_bank_info info; 1576 u64 misc0; 1577 int ret; 1578 1579 ret = aca_bank_info_decode(bank, &info); 1580 if (ret) 1581 return ret; 1582 1583 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 1584 switch (type) { 1585 case ACA_SMU_TYPE_UE: 1586 bank->aca_err_type = ACA_ERROR_TYPE_UE; 1587 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 1588 1ULL); 1589 break; 1590 case ACA_SMU_TYPE_CE: 1591 bank->aca_err_type = ACA_ERROR_TYPE_CE; 1592 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1593 ACA_REG__MISC0__ERRCNT(misc0)); 1594 break; 1595 default: 1596 return -EINVAL; 1597 } 1598 1599 return ret; 1600 } 1601 1602 /* reference to smu driver if header file */ 1603 static int vcn_v5_0_1_err_codes[] = { 1604 14, 15, 47, /* VCN [D|V|S] */ 1605 }; 1606 1607 static bool vcn_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 1608 enum aca_smu_type type, void *data) 1609 { 1610 u32 instlo; 1611 1612 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 1613 instlo &= GENMASK(31, 1); 1614 1615 if (instlo != mmSMNAID_AID0_MCA_SMU) 1616 return false; 1617 1618 if (aca_bank_check_error_codes(handle->adev, bank, 1619 vcn_v5_0_1_err_codes, 1620 ARRAY_SIZE(vcn_v5_0_1_err_codes))) 1621 return false; 1622 1623 return true; 1624 } 1625 1626 static const struct aca_bank_ops vcn_v5_0_1_aca_bank_ops = { 1627 .aca_bank_parser = vcn_v5_0_1_aca_bank_parser, 1628 .aca_bank_is_valid = vcn_v5_0_1_aca_bank_is_valid, 1629 }; 1630 1631 static const struct aca_info vcn_v5_0_1_aca_info = { 1632 .hwip = ACA_HWIP_TYPE_SMU, 1633 .mask = ACA_ERROR_UE_MASK, 1634 .bank_ops = &vcn_v5_0_1_aca_bank_ops, 1635 }; 1636 1637 static int vcn_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1638 { 1639 int r; 1640 1641 r = amdgpu_ras_block_late_init(adev, ras_block); 1642 if (r) 1643 return r; 1644 1645 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN, 1646 &vcn_v5_0_1_aca_info, NULL); 1647 if (r) 1648 goto late_fini; 1649 1650 if (amdgpu_ras_is_supported(adev, ras_block->block) && 1651 adev->vcn.inst->ras_poison_irq.funcs) { 1652 r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0); 1653 if (r) 1654 goto late_fini; 1655 } 1656 1657 return 0; 1658 1659 late_fini: 1660 amdgpu_ras_block_late_fini(adev, ras_block); 1661 1662 return r; 1663 } 1664 1665 static struct amdgpu_vcn_ras vcn_v5_0_1_ras = { 1666 .ras_block = { 1667 .hw_ops = &vcn_v5_0_1_ras_hw_ops, 1668 .ras_late_init = vcn_v5_0_1_ras_late_init, 1669 }, 1670 }; 1671 1672 static void vcn_v5_0_1_set_ras_funcs(struct amdgpu_device *adev) 1673 { 1674 adev->vcn.ras = &vcn_v5_0_1_ras; 1675 } 1676