1 /* 2 * Copyright 2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_hw_ip.h" 31 #include "vcn_v2_0.h" 32 #include "vcn_v4_0_3.h" 33 #include "mmsch_v5_0.h" 34 35 #include "vcn/vcn_5_0_0_offset.h" 36 #include "vcn/vcn_5_0_0_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" 38 #include "vcn_v5_0_0.h" 39 #include "vcn_v5_0_1.h" 40 41 #include <drm/drm_drv.h> 42 43 static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0_1[] = { 44 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 45 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 46 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 47 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 48 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 75 }; 76 77 static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev); 78 static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev); 79 static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev); 80 static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst, 81 enum amd_powergating_state state); 82 static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring); 83 static void vcn_v5_0_1_set_ras_funcs(struct amdgpu_device *adev); 84 /** 85 * vcn_v5_0_1_early_init - set function pointers and load microcode 86 * 87 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 88 * 89 * Set ring and irq function pointers 90 * Load microcode from filesystem 91 */ 92 static int vcn_v5_0_1_early_init(struct amdgpu_ip_block *ip_block) 93 { 94 struct amdgpu_device *adev = ip_block->adev; 95 int i, r; 96 97 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 98 /* re-use enc ring as unified ring */ 99 adev->vcn.inst[i].num_enc_rings = 1; 100 101 vcn_v5_0_1_set_unified_ring_funcs(adev); 102 vcn_v5_0_1_set_irq_funcs(adev); 103 vcn_v5_0_1_set_ras_funcs(adev); 104 105 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 106 adev->vcn.inst[i].set_pg_state = vcn_v5_0_1_set_pg_state; 107 108 r = amdgpu_vcn_early_init(adev, i); 109 if (r) 110 return r; 111 } 112 113 return 0; 114 } 115 116 static void vcn_v5_0_1_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 117 { 118 struct amdgpu_vcn5_fw_shared *fw_shared; 119 120 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 121 122 if (fw_shared->sq.is_enabled) 123 return; 124 fw_shared->present_flag_0 = 125 cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 126 fw_shared->sq.is_enabled = 1; 127 128 if (amdgpu_vcnfw_log) 129 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 130 } 131 132 /** 133 * vcn_v5_0_1_sw_init - sw init for VCN block 134 * 135 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 136 * 137 * Load firmware and sw initialization 138 */ 139 static int vcn_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) 140 { 141 struct amdgpu_device *adev = ip_block->adev; 142 struct amdgpu_ring *ring; 143 int i, r, vcn_inst; 144 145 /* VCN UNIFIED TRAP */ 146 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 147 VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 148 if (r) 149 return r; 150 151 /* VCN POISON TRAP */ 152 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 153 VCN_5_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq); 154 155 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 156 vcn_inst = GET_INST(VCN, i); 157 158 r = amdgpu_vcn_sw_init(adev, i); 159 if (r) 160 return r; 161 162 amdgpu_vcn_setup_ucode(adev, i); 163 164 r = amdgpu_vcn_resume(adev, i); 165 if (r) 166 return r; 167 168 ring = &adev->vcn.inst[i].ring_enc[0]; 169 ring->use_doorbell = true; 170 if (!amdgpu_sriov_vf(adev)) 171 ring->doorbell_index = 172 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 173 11 * vcn_inst; 174 else 175 ring->doorbell_index = 176 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 177 32 * vcn_inst; 178 179 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 180 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 181 182 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 183 AMDGPU_RING_PRIO_DEFAULT, &adev->vcn.inst[i].sched_score); 184 if (r) 185 return r; 186 187 vcn_v5_0_1_fw_shared_init(adev, i); 188 } 189 190 /* TODO: Add queue reset mask when FW fully supports it */ 191 adev->vcn.supported_reset = 192 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 193 194 if (amdgpu_sriov_vf(adev)) { 195 r = amdgpu_virt_alloc_mm_table(adev); 196 if (r) 197 return r; 198 } 199 200 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 201 r = amdgpu_vcn_ras_sw_init(adev); 202 if (r) { 203 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 204 return r; 205 } 206 } 207 208 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0_1, ARRAY_SIZE(vcn_reg_list_5_0_1)); 209 if (r) 210 return r; 211 212 return amdgpu_vcn_sysfs_reset_mask_init(adev); 213 } 214 215 /** 216 * vcn_v5_0_1_sw_fini - sw fini for VCN block 217 * 218 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 219 * 220 * VCN suspend and free up sw allocation 221 */ 222 static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block) 223 { 224 struct amdgpu_device *adev = ip_block->adev; 225 int i, r, idx; 226 227 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 228 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 229 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 230 231 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 232 fw_shared->present_flag_0 = 0; 233 fw_shared->sq.is_enabled = 0; 234 } 235 236 drm_dev_exit(idx); 237 } 238 239 if (amdgpu_sriov_vf(adev)) 240 amdgpu_virt_free_mm_table(adev); 241 242 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 243 r = amdgpu_vcn_suspend(adev, i); 244 if (r) 245 return r; 246 } 247 248 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 249 r = amdgpu_vcn_sw_fini(adev, i); 250 if (r) 251 return r; 252 } 253 254 amdgpu_vcn_sysfs_reset_mask_fini(adev); 255 256 return 0; 257 } 258 259 /** 260 * vcn_v5_0_1_hw_init - start and test VCN block 261 * 262 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 263 * 264 * Initialize the hardware, boot up the VCPU and do some testing 265 */ 266 static int vcn_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block) 267 { 268 struct amdgpu_device *adev = ip_block->adev; 269 struct amdgpu_ring *ring; 270 int i, r, vcn_inst; 271 272 if (amdgpu_sriov_vf(adev)) { 273 r = vcn_v5_0_1_start_sriov(adev); 274 if (r) 275 return r; 276 277 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 278 ring = &adev->vcn.inst[i].ring_enc[0]; 279 ring->wptr = 0; 280 ring->wptr_old = 0; 281 vcn_v5_0_1_unified_ring_set_wptr(ring); 282 ring->sched.ready = true; 283 } 284 } else { 285 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 286 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 287 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 288 vcn_inst = GET_INST(VCN, i); 289 ring = &adev->vcn.inst[i].ring_enc[0]; 290 291 if (ring->use_doorbell) 292 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 293 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 294 11 * vcn_inst), 295 adev->vcn.inst[i].aid_id); 296 297 /* Re-init fw_shared, if required */ 298 vcn_v5_0_1_fw_shared_init(adev, i); 299 300 r = amdgpu_ring_test_helper(ring); 301 if (r) 302 return r; 303 } 304 } 305 306 return 0; 307 } 308 309 /** 310 * vcn_v5_0_1_hw_fini - stop the hardware block 311 * 312 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 313 * 314 * Stop the VCN block, mark ring as not ready any more 315 */ 316 static int vcn_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block) 317 { 318 struct amdgpu_device *adev = ip_block->adev; 319 int i; 320 321 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 322 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 323 324 cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work); 325 if (vinst->cur_state != AMD_PG_STATE_GATE) 326 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 327 } 328 329 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 330 amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0); 331 332 return 0; 333 } 334 335 /** 336 * vcn_v5_0_1_suspend - suspend VCN block 337 * 338 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 339 * 340 * HW fini and suspend VCN block 341 */ 342 static int vcn_v5_0_1_suspend(struct amdgpu_ip_block *ip_block) 343 { 344 struct amdgpu_device *adev = ip_block->adev; 345 int r, i; 346 347 r = vcn_v5_0_1_hw_fini(ip_block); 348 if (r) 349 return r; 350 351 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 352 r = amdgpu_vcn_suspend(ip_block->adev, i); 353 if (r) 354 return r; 355 } 356 357 return r; 358 } 359 360 /** 361 * vcn_v5_0_1_resume - resume VCN block 362 * 363 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 364 * 365 * Resume firmware and hw init VCN block 366 */ 367 static int vcn_v5_0_1_resume(struct amdgpu_ip_block *ip_block) 368 { 369 struct amdgpu_device *adev = ip_block->adev; 370 int r, i; 371 372 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 373 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 374 375 if (amdgpu_in_reset(adev)) 376 vinst->cur_state = AMD_PG_STATE_GATE; 377 378 r = amdgpu_vcn_resume(ip_block->adev, i); 379 if (r) 380 return r; 381 } 382 383 r = vcn_v5_0_1_hw_init(ip_block); 384 385 return r; 386 } 387 388 /** 389 * vcn_v5_0_1_mc_resume - memory controller programming 390 * 391 * @vinst: VCN instance 392 * 393 * Let the VCN memory controller know it's offsets 394 */ 395 static void vcn_v5_0_1_mc_resume(struct amdgpu_vcn_inst *vinst) 396 { 397 struct amdgpu_device *adev = vinst->adev; 398 int inst = vinst->inst; 399 uint32_t offset, size, vcn_inst; 400 const struct common_firmware_header *hdr; 401 402 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 403 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 404 405 vcn_inst = GET_INST(VCN, inst); 406 /* cache window 0: fw */ 407 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 408 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 409 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 410 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 411 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 412 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 413 offset = 0; 414 } else { 415 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 416 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 417 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 418 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 419 offset = size; 420 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 421 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 422 } 423 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 424 425 /* cache window 1: stack */ 426 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 427 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 428 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 429 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 430 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 431 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 432 433 /* cache window 2: context */ 434 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 435 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 436 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 437 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 438 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 439 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 440 441 /* non-cache window */ 442 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 443 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 444 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 445 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 446 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 447 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 448 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); 449 } 450 451 /** 452 * vcn_v5_0_1_mc_resume_dpg_mode - memory controller programming for dpg mode 453 * 454 * @vinst: VCN instance 455 * @indirect: indirectly write sram 456 * 457 * Let the VCN memory controller know it's offsets with dpg mode 458 */ 459 static void vcn_v5_0_1_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 460 bool indirect) 461 { 462 struct amdgpu_device *adev = vinst->adev; 463 int inst_idx = vinst->inst; 464 uint32_t offset, size; 465 const struct common_firmware_header *hdr; 466 467 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 468 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 469 470 /* cache window 0: fw */ 471 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 472 if (!indirect) { 473 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 474 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 475 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 476 inst_idx].tmr_mc_addr_lo), 0, indirect); 477 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 478 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 479 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 480 inst_idx].tmr_mc_addr_hi), 0, indirect); 481 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 482 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 483 } else { 484 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 485 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 486 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 487 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 488 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 489 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 490 } 491 offset = 0; 492 } else { 493 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 494 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 495 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 496 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 497 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 498 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 499 offset = size; 500 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 501 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 502 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 503 } 504 505 if (!indirect) 506 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 507 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 508 else 509 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 510 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 511 512 /* cache window 1: stack */ 513 if (!indirect) { 514 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 515 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 516 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 517 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 518 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 519 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 520 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 521 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 522 } else { 523 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 524 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 525 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 526 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 527 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 528 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 529 } 530 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 531 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 532 533 /* cache window 2: context */ 534 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 535 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 536 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 537 AMDGPU_VCN_STACK_SIZE), 0, indirect); 538 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 539 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 540 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 541 AMDGPU_VCN_STACK_SIZE), 0, indirect); 542 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 543 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 544 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 545 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 546 547 /* non-cache window */ 548 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 549 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 550 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 551 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 552 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 553 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 554 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 555 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 556 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 557 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 558 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); 559 560 /* VCN global tiling registers */ 561 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 562 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 563 } 564 565 /** 566 * vcn_v5_0_1_disable_clock_gating - disable VCN clock gating 567 * 568 * @vinst: VCN instance 569 * 570 * Disable clock gating for VCN block 571 */ 572 static void vcn_v5_0_1_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 573 { 574 } 575 576 /** 577 * vcn_v5_0_1_enable_clock_gating - enable VCN clock gating 578 * 579 * @vinst: VCN instance 580 * 581 * Enable clock gating for VCN block 582 */ 583 static void vcn_v5_0_1_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 584 { 585 } 586 587 /** 588 * vcn_v5_0_1_pause_dpg_mode - VCN pause with dpg mode 589 * 590 * @vinst: VCN instance 591 * @new_state: pause state 592 * 593 * Pause dpg mode for VCN block 594 */ 595 static int vcn_v5_0_1_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 596 struct dpg_pause_state *new_state) 597 { 598 struct amdgpu_device *adev = vinst->adev; 599 uint32_t reg_data = 0; 600 int vcn_inst; 601 602 vcn_inst = GET_INST(VCN, vinst->inst); 603 604 /* pause/unpause if state is changed */ 605 if (vinst->pause_state.fw_based != new_state->fw_based) { 606 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d %s\n", 607 vinst->pause_state.fw_based, new_state->fw_based, 608 new_state->fw_based ? "VCN_DPG_STATE__PAUSE" : "VCN_DPG_STATE__UNPAUSE"); 609 reg_data = RREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE) & 610 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 611 612 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 613 /* pause DPG */ 614 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 615 WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); 616 617 /* wait for ACK */ 618 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_DPG_PAUSE, 619 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 620 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 621 } else { 622 /* unpause DPG, no need to wait */ 623 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 624 WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); 625 } 626 vinst->pause_state.fw_based = new_state->fw_based; 627 } 628 629 return 0; 630 } 631 632 633 /** 634 * vcn_v5_0_1_start_dpg_mode - VCN start with dpg mode 635 * 636 * @vinst: VCN instance 637 * @indirect: indirectly write sram 638 * 639 * Start VCN block with dpg mode 640 */ 641 static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 642 bool indirect) 643 { 644 struct amdgpu_device *adev = vinst->adev; 645 int inst_idx = vinst->inst; 646 volatile struct amdgpu_vcn5_fw_shared *fw_shared = 647 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 648 struct amdgpu_ring *ring; 649 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; 650 int vcn_inst, ret; 651 uint32_t tmp; 652 653 vcn_inst = GET_INST(VCN, inst_idx); 654 655 /* disable register anti-hang mechanism */ 656 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 657 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 658 659 /* enable dynamic power gating mode */ 660 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 661 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 662 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 663 664 if (indirect) { 665 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 666 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 667 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 668 WREG32_SOC24_DPG_MODE(inst_idx, 0xDEADBEEF, 669 adev->vcn.inst[inst_idx].aid_id, 0, true); 670 } 671 672 /* enable VCPU clock */ 673 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 674 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 675 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 676 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 677 678 /* disable master interrupt */ 679 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 680 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 681 682 /* setup regUVD_LMI_CTRL */ 683 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 684 UVD_LMI_CTRL__REQ_MODE_MASK | 685 UVD_LMI_CTRL__CRC_RESET_MASK | 686 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 687 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 688 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 689 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 690 0x00100000L); 691 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 692 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 693 694 vcn_v5_0_1_mc_resume_dpg_mode(vinst, indirect); 695 696 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 697 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 698 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 699 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 700 701 /* enable LMI MC and UMC channels */ 702 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 703 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 704 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 705 706 /* enable master interrupt */ 707 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 708 VCN, 0, regUVD_MASTINT_EN), 709 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 710 711 if (indirect) { 712 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 713 if (ret) { 714 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 715 return ret; 716 } 717 } 718 719 /* resetting ring, fw should not check RB ring */ 720 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 721 722 /* Pause dpg */ 723 vcn_v5_0_1_pause_dpg_mode(vinst, &state); 724 725 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 726 727 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); 728 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 729 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / sizeof(uint32_t)); 730 731 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 732 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 733 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 734 735 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 736 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 737 738 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); 739 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); 740 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 741 742 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 743 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 744 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 745 /* resetting done, fw can check RB ring */ 746 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 747 748 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 749 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 750 VCN_RB1_DB_CTRL__EN_MASK); 751 /* Read DB_CTRL to flush the write DB_CTRL command. */ 752 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 753 754 return 0; 755 } 756 757 static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev) 758 { 759 int i, vcn_inst; 760 struct amdgpu_ring *ring_enc; 761 uint64_t cache_addr; 762 uint64_t rb_enc_addr; 763 uint64_t ctx_addr; 764 uint32_t param, resp, expected; 765 uint32_t offset, cache_size; 766 uint32_t tmp, timeout; 767 768 struct amdgpu_mm_table *table = &adev->virt.mm_table; 769 uint32_t *table_loc; 770 uint32_t table_size; 771 uint32_t size, size_dw; 772 uint32_t init_status; 773 uint32_t enabled_vcn; 774 775 struct mmsch_v5_0_cmd_direct_write 776 direct_wt = { {0} }; 777 struct mmsch_v5_0_cmd_direct_read_modify_write 778 direct_rd_mod_wt = { {0} }; 779 struct mmsch_v5_0_cmd_end end = { {0} }; 780 struct mmsch_v5_0_init_header header; 781 782 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 783 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 784 785 direct_wt.cmd_header.command_type = 786 MMSCH_COMMAND__DIRECT_REG_WRITE; 787 direct_rd_mod_wt.cmd_header.command_type = 788 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 789 end.cmd_header.command_type = MMSCH_COMMAND__END; 790 791 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 792 vcn_inst = GET_INST(VCN, i); 793 794 vcn_v5_0_1_fw_shared_init(adev, vcn_inst); 795 796 memset(&header, 0, sizeof(struct mmsch_v5_0_init_header)); 797 header.version = MMSCH_VERSION; 798 header.total_size = sizeof(struct mmsch_v5_0_init_header) >> 2; 799 800 table_loc = (uint32_t *)table->cpu_addr; 801 table_loc += header.total_size; 802 803 table_size = 0; 804 805 MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 806 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 807 808 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 809 810 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 811 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 812 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 813 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 814 815 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 816 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 817 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 818 819 offset = 0; 820 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 821 regUVD_VCPU_CACHE_OFFSET0), 0); 822 } else { 823 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 824 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 825 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 826 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 827 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 828 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 829 offset = cache_size; 830 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 831 regUVD_VCPU_CACHE_OFFSET0), 832 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 833 } 834 835 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 836 regUVD_VCPU_CACHE_SIZE0), 837 cache_size); 838 839 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 840 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 841 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 842 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 843 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 844 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 845 regUVD_VCPU_CACHE_OFFSET1), 0); 846 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 847 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 848 849 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 850 AMDGPU_VCN_STACK_SIZE; 851 852 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 853 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 854 855 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 856 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 857 858 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 859 regUVD_VCPU_CACHE_OFFSET2), 0); 860 861 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 862 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 863 864 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 865 rb_setup = &fw_shared->rb_setup; 866 867 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 868 ring_enc->wptr = 0; 869 rb_enc_addr = ring_enc->gpu_addr; 870 871 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 872 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 873 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 874 rb_setup->rb_size = ring_enc->ring_size / 4; 875 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 876 877 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 878 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 879 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 880 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 881 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 882 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 883 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 884 regUVD_VCPU_NONCACHE_SIZE0), 885 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 886 MMSCH_V5_0_INSERT_END(); 887 888 header.vcn0.init_status = 0; 889 header.vcn0.table_offset = header.total_size; 890 header.vcn0.table_size = table_size; 891 header.total_size += table_size; 892 893 /* Send init table to mmsch */ 894 size = sizeof(struct mmsch_v5_0_init_header); 895 table_loc = (uint32_t *)table->cpu_addr; 896 memcpy((void *)table_loc, &header, size); 897 898 ctx_addr = table->gpu_addr; 899 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 900 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 901 902 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 903 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 904 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 905 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 906 907 size = header.total_size; 908 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 909 910 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 911 912 param = 0x00000001; 913 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 914 tmp = 0; 915 timeout = 1000; 916 resp = 0; 917 expected = MMSCH_VF_MAILBOX_RESP__OK; 918 while (resp != expected) { 919 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 920 if (resp != 0) 921 break; 922 923 udelay(10); 924 tmp = tmp + 10; 925 if (tmp >= timeout) { 926 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 927 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 928 "(expected=0x%08x, readback=0x%08x)\n", 929 tmp, expected, resp); 930 return -EBUSY; 931 } 932 } 933 934 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 935 init_status = ((struct mmsch_v5_0_init_header *)(table_loc))->vcn0.init_status; 936 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 937 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 938 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 939 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 940 } 941 } 942 943 return 0; 944 } 945 946 /** 947 * vcn_v5_0_1_start - VCN start 948 * 949 * @vinst: VCN instance 950 * 951 * Start VCN block 952 */ 953 static int vcn_v5_0_1_start(struct amdgpu_vcn_inst *vinst) 954 { 955 struct amdgpu_device *adev = vinst->adev; 956 int i = vinst->inst; 957 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 958 struct amdgpu_ring *ring; 959 uint32_t tmp; 960 int j, k, r, vcn_inst; 961 962 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 963 964 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 965 return vcn_v5_0_1_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 966 967 vcn_inst = GET_INST(VCN, i); 968 969 /* set VCN status busy */ 970 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 971 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 972 973 /* enable VCPU clock */ 974 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 975 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 976 977 /* disable master interrupt */ 978 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 979 ~UVD_MASTINT_EN__VCPU_EN_MASK); 980 981 /* enable LMI MC and UMC channels */ 982 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 983 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 984 985 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 986 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 987 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 988 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 989 990 /* setup regUVD_LMI_CTRL */ 991 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 992 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp | 993 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 994 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 995 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 996 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 997 998 vcn_v5_0_1_mc_resume(vinst); 999 1000 /* VCN global tiling registers */ 1001 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 1002 adev->gfx.config.gb_addr_config); 1003 1004 /* unblock VCPU register access */ 1005 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1006 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1007 1008 /* release VCPU reset to boot */ 1009 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1010 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1011 1012 for (j = 0; j < 10; ++j) { 1013 uint32_t status; 1014 1015 for (k = 0; k < 100; ++k) { 1016 status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1017 if (status & 2) 1018 break; 1019 mdelay(100); 1020 if (amdgpu_emu_mode == 1) 1021 msleep(20); 1022 } 1023 1024 if (amdgpu_emu_mode == 1) { 1025 r = -1; 1026 if (status & 2) { 1027 r = 0; 1028 break; 1029 } 1030 } else { 1031 r = 0; 1032 if (status & 2) 1033 break; 1034 1035 dev_err(adev->dev, 1036 "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 1037 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1038 UVD_VCPU_CNTL__BLK_RST_MASK, 1039 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1040 mdelay(10); 1041 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1042 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1043 1044 mdelay(10); 1045 r = -1; 1046 } 1047 } 1048 1049 if (r) { 1050 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1051 return r; 1052 } 1053 1054 /* enable master interrupt */ 1055 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1056 UVD_MASTINT_EN__VCPU_EN_MASK, 1057 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1058 1059 /* clear the busy bit of VCN_STATUS */ 1060 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1061 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1062 1063 ring = &adev->vcn.inst[i].ring_enc[0]; 1064 1065 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 1066 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1067 VCN_RB1_DB_CTRL__EN_MASK); 1068 1069 /* Read DB_CTRL to flush the write DB_CTRL command. */ 1070 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 1071 1072 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr); 1073 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1074 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4); 1075 1076 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1077 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1078 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1079 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1080 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1081 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1082 1083 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); 1084 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); 1085 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1086 1087 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1088 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1089 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1090 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1091 1092 /* Keeping one read-back to ensure all register writes are done, 1093 * otherwise it may introduce race conditions. 1094 */ 1095 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1096 1097 return 0; 1098 } 1099 1100 /** 1101 * vcn_v5_0_1_stop_dpg_mode - VCN stop with dpg mode 1102 * 1103 * @vinst: VCN instance 1104 * 1105 * Stop VCN block with dpg mode 1106 */ 1107 static void vcn_v5_0_1_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1108 { 1109 struct amdgpu_device *adev = vinst->adev; 1110 int inst_idx = vinst->inst; 1111 uint32_t tmp; 1112 int vcn_inst; 1113 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1114 1115 vcn_inst = GET_INST(VCN, inst_idx); 1116 1117 /* Unpause dpg */ 1118 vcn_v5_0_1_pause_dpg_mode(vinst, &state); 1119 1120 /* Wait for power status to be 1 */ 1121 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1122 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1123 1124 /* wait for read ptr to be equal to write ptr */ 1125 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1126 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1127 1128 /* disable dynamic power gating mode */ 1129 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1130 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1131 1132 /* Keeping one read-back to ensure all register writes are done, 1133 * otherwise it may introduce race conditions. 1134 */ 1135 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1136 } 1137 1138 /** 1139 * vcn_v5_0_1_stop - VCN stop 1140 * 1141 * @vinst: VCN instance 1142 * 1143 * Stop VCN block 1144 */ 1145 static int vcn_v5_0_1_stop(struct amdgpu_vcn_inst *vinst) 1146 { 1147 struct amdgpu_device *adev = vinst->adev; 1148 int i = vinst->inst; 1149 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 1150 uint32_t tmp; 1151 int r = 0, vcn_inst; 1152 1153 vcn_inst = GET_INST(VCN, i); 1154 1155 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1156 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1157 1158 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1159 vcn_v5_0_1_stop_dpg_mode(vinst); 1160 return 0; 1161 } 1162 1163 /* wait for vcn idle */ 1164 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1165 if (r) 1166 return r; 1167 1168 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1169 UVD_LMI_STATUS__READ_CLEAN_MASK | 1170 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1171 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1172 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); 1173 if (r) 1174 return r; 1175 1176 /* disable LMI UMC channel */ 1177 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1178 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1179 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1180 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1181 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1182 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); 1183 if (r) 1184 return r; 1185 1186 /* block VCPU register access */ 1187 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1188 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1189 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1190 1191 /* reset VCPU */ 1192 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1193 UVD_VCPU_CNTL__BLK_RST_MASK, 1194 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1195 1196 /* disable VCPU clock */ 1197 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1198 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1199 1200 /* apply soft reset */ 1201 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1202 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1203 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1204 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1205 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1206 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1207 1208 /* clear status */ 1209 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1210 1211 /* Keeping one read-back to ensure all register writes are done, 1212 * otherwise it may introduce race conditions. 1213 */ 1214 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1215 1216 return 0; 1217 } 1218 1219 /** 1220 * vcn_v5_0_1_unified_ring_get_rptr - get unified read pointer 1221 * 1222 * @ring: amdgpu_ring pointer 1223 * 1224 * Returns the current hardware unified read pointer 1225 */ 1226 static uint64_t vcn_v5_0_1_unified_ring_get_rptr(struct amdgpu_ring *ring) 1227 { 1228 struct amdgpu_device *adev = ring->adev; 1229 1230 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1231 DRM_ERROR("wrong ring id is identified in %s", __func__); 1232 1233 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1234 } 1235 1236 /** 1237 * vcn_v5_0_1_unified_ring_get_wptr - get unified write pointer 1238 * 1239 * @ring: amdgpu_ring pointer 1240 * 1241 * Returns the current hardware unified write pointer 1242 */ 1243 static uint64_t vcn_v5_0_1_unified_ring_get_wptr(struct amdgpu_ring *ring) 1244 { 1245 struct amdgpu_device *adev = ring->adev; 1246 1247 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1248 DRM_ERROR("wrong ring id is identified in %s", __func__); 1249 1250 if (ring->use_doorbell) 1251 return *ring->wptr_cpu_addr; 1252 else 1253 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR); 1254 } 1255 1256 /** 1257 * vcn_v5_0_1_unified_ring_set_wptr - set enc write pointer 1258 * 1259 * @ring: amdgpu_ring pointer 1260 * 1261 * Commits the enc write pointer to the hardware 1262 */ 1263 static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring) 1264 { 1265 struct amdgpu_device *adev = ring->adev; 1266 1267 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1268 DRM_ERROR("wrong ring id is identified in %s", __func__); 1269 1270 if (ring->use_doorbell) { 1271 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1272 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1273 } else { 1274 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1275 lower_32_bits(ring->wptr)); 1276 } 1277 } 1278 1279 static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { 1280 .type = AMDGPU_RING_TYPE_VCN_ENC, 1281 .align_mask = 0x3f, 1282 .nop = VCN_ENC_CMD_NO_OP, 1283 .get_rptr = vcn_v5_0_1_unified_ring_get_rptr, 1284 .get_wptr = vcn_v5_0_1_unified_ring_get_wptr, 1285 .set_wptr = vcn_v5_0_1_unified_ring_set_wptr, 1286 .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1287 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1288 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1289 5 + 1290 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1291 1, /* vcn_v2_0_enc_ring_insert_end */ 1292 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1293 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1294 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1295 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1296 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1297 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1298 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1299 .insert_nop = amdgpu_ring_insert_nop, 1300 .insert_end = vcn_v2_0_enc_ring_insert_end, 1301 .pad_ib = amdgpu_ring_generic_pad_ib, 1302 .begin_use = amdgpu_vcn_ring_begin_use, 1303 .end_use = amdgpu_vcn_ring_end_use, 1304 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1305 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1306 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1307 }; 1308 1309 /** 1310 * vcn_v5_0_1_set_unified_ring_funcs - set unified ring functions 1311 * 1312 * @adev: amdgpu_device pointer 1313 * 1314 * Set unified ring functions 1315 */ 1316 static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev) 1317 { 1318 int i, vcn_inst; 1319 1320 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1321 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_1_unified_ring_vm_funcs; 1322 adev->vcn.inst[i].ring_enc[0].me = i; 1323 vcn_inst = GET_INST(VCN, i); 1324 adev->vcn.inst[i].aid_id = vcn_inst / adev->vcn.num_inst_per_aid; 1325 } 1326 } 1327 1328 /** 1329 * vcn_v5_0_1_is_idle - check VCN block is idle 1330 * 1331 * @ip_block: Pointer to the amdgpu_ip_block structure 1332 * 1333 * Check whether VCN block is idle 1334 */ 1335 static bool vcn_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block) 1336 { 1337 struct amdgpu_device *adev = ip_block->adev; 1338 int i, ret = 1; 1339 1340 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 1341 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE); 1342 1343 return ret; 1344 } 1345 1346 /** 1347 * vcn_v5_0_1_wait_for_idle - wait for VCN block idle 1348 * 1349 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1350 * 1351 * Wait for VCN block idle 1352 */ 1353 static int vcn_v5_0_1_wait_for_idle(struct amdgpu_ip_block *ip_block) 1354 { 1355 struct amdgpu_device *adev = ip_block->adev; 1356 int i, ret = 0; 1357 1358 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1359 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, 1360 UVD_STATUS__IDLE); 1361 if (ret) 1362 return ret; 1363 } 1364 1365 return ret; 1366 } 1367 1368 /** 1369 * vcn_v5_0_1_set_clockgating_state - set VCN block clockgating state 1370 * 1371 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1372 * @state: clock gating state 1373 * 1374 * Set VCN block clockgating state 1375 */ 1376 static int vcn_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1377 enum amd_clockgating_state state) 1378 { 1379 struct amdgpu_device *adev = ip_block->adev; 1380 bool enable = state == AMD_CG_STATE_GATE; 1381 int i; 1382 1383 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1384 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1385 1386 if (enable) { 1387 if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE) 1388 return -EBUSY; 1389 vcn_v5_0_1_enable_clock_gating(vinst); 1390 } else { 1391 vcn_v5_0_1_disable_clock_gating(vinst); 1392 } 1393 } 1394 1395 return 0; 1396 } 1397 1398 static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst, 1399 enum amd_powergating_state state) 1400 { 1401 struct amdgpu_device *adev = vinst->adev; 1402 int ret = 0; 1403 1404 /* for SRIOV, guest should not control VCN Power-gating 1405 * MMSCH FW should control Power-gating and clock-gating 1406 * guest should avoid touching CGC and PG 1407 */ 1408 if (amdgpu_sriov_vf(adev)) { 1409 vinst->cur_state = AMD_PG_STATE_UNGATE; 1410 return 0; 1411 } 1412 1413 if (state == vinst->cur_state) 1414 return 0; 1415 1416 if (state == AMD_PG_STATE_GATE) 1417 ret = vcn_v5_0_1_stop(vinst); 1418 else 1419 ret = vcn_v5_0_1_start(vinst); 1420 1421 if (!ret) 1422 vinst->cur_state = state; 1423 1424 return ret; 1425 } 1426 1427 /** 1428 * vcn_v5_0_1_process_interrupt - process VCN block interrupt 1429 * 1430 * @adev: amdgpu_device pointer 1431 * @source: interrupt sources 1432 * @entry: interrupt entry from clients and sources 1433 * 1434 * Process VCN block interrupt 1435 */ 1436 static int vcn_v5_0_1_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1437 struct amdgpu_iv_entry *entry) 1438 { 1439 uint32_t i, inst; 1440 1441 i = node_id_to_phys_map[entry->node_id]; 1442 1443 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1444 1445 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1446 if (adev->vcn.inst[inst].aid_id == i) 1447 break; 1448 if (inst >= adev->vcn.num_vcn_inst) { 1449 dev_WARN_ONCE(adev->dev, 1, 1450 "Interrupt received for unknown VCN instance %d", 1451 entry->node_id); 1452 return 0; 1453 } 1454 1455 switch (entry->src_id) { 1456 case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1457 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1458 break; 1459 default: 1460 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1461 entry->src_id, entry->src_data[0]); 1462 break; 1463 } 1464 1465 return 0; 1466 } 1467 1468 static int vcn_v5_0_1_set_ras_interrupt_state(struct amdgpu_device *adev, 1469 struct amdgpu_irq_src *source, 1470 unsigned int type, 1471 enum amdgpu_interrupt_state state) 1472 { 1473 return 0; 1474 } 1475 1476 static const struct amdgpu_irq_src_funcs vcn_v5_0_1_irq_funcs = { 1477 .process = vcn_v5_0_1_process_interrupt, 1478 }; 1479 1480 static const struct amdgpu_irq_src_funcs vcn_v5_0_1_ras_irq_funcs = { 1481 .set = vcn_v5_0_1_set_ras_interrupt_state, 1482 .process = amdgpu_vcn_process_poison_irq, 1483 }; 1484 1485 1486 /** 1487 * vcn_v5_0_1_set_irq_funcs - set VCN block interrupt irq functions 1488 * 1489 * @adev: amdgpu_device pointer 1490 * 1491 * Set VCN block interrupt irq functions 1492 */ 1493 static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev) 1494 { 1495 int i; 1496 1497 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 1498 adev->vcn.inst->irq.num_types++; 1499 1500 adev->vcn.inst->irq.funcs = &vcn_v5_0_1_irq_funcs; 1501 1502 adev->vcn.inst->ras_poison_irq.num_types = 1; 1503 adev->vcn.inst->ras_poison_irq.funcs = &vcn_v5_0_1_ras_irq_funcs; 1504 1505 } 1506 1507 static const struct amd_ip_funcs vcn_v5_0_1_ip_funcs = { 1508 .name = "vcn_v5_0_1", 1509 .early_init = vcn_v5_0_1_early_init, 1510 .late_init = NULL, 1511 .sw_init = vcn_v5_0_1_sw_init, 1512 .sw_fini = vcn_v5_0_1_sw_fini, 1513 .hw_init = vcn_v5_0_1_hw_init, 1514 .hw_fini = vcn_v5_0_1_hw_fini, 1515 .suspend = vcn_v5_0_1_suspend, 1516 .resume = vcn_v5_0_1_resume, 1517 .is_idle = vcn_v5_0_1_is_idle, 1518 .wait_for_idle = vcn_v5_0_1_wait_for_idle, 1519 .check_soft_reset = NULL, 1520 .pre_soft_reset = NULL, 1521 .soft_reset = NULL, 1522 .post_soft_reset = NULL, 1523 .set_clockgating_state = vcn_v5_0_1_set_clockgating_state, 1524 .set_powergating_state = vcn_set_powergating_state, 1525 .dump_ip_state = amdgpu_vcn_dump_ip_state, 1526 .print_ip_state = amdgpu_vcn_print_ip_state, 1527 }; 1528 1529 const struct amdgpu_ip_block_version vcn_v5_0_1_ip_block = { 1530 .type = AMD_IP_BLOCK_TYPE_VCN, 1531 .major = 5, 1532 .minor = 0, 1533 .rev = 1, 1534 .funcs = &vcn_v5_0_1_ip_funcs, 1535 }; 1536 1537 static uint32_t vcn_v5_0_1_query_poison_by_instance(struct amdgpu_device *adev, 1538 uint32_t instance, uint32_t sub_block) 1539 { 1540 uint32_t poison_stat = 0, reg_value = 0; 1541 1542 switch (sub_block) { 1543 case AMDGPU_VCN_V5_0_1_VCPU_VCODEC: 1544 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 1545 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 1546 break; 1547 default: 1548 break; 1549 } 1550 1551 if (poison_stat) 1552 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 1553 instance, sub_block); 1554 1555 return poison_stat; 1556 } 1557 1558 static bool vcn_v5_0_1_query_poison_status(struct amdgpu_device *adev) 1559 { 1560 uint32_t inst, sub; 1561 uint32_t poison_stat = 0; 1562 1563 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 1564 for (sub = 0; sub < AMDGPU_VCN_V5_0_1_MAX_SUB_BLOCK; sub++) 1565 poison_stat += 1566 vcn_v5_0_1_query_poison_by_instance(adev, inst, sub); 1567 1568 return !!poison_stat; 1569 } 1570 1571 static const struct amdgpu_ras_block_hw_ops vcn_v5_0_1_ras_hw_ops = { 1572 .query_poison_status = vcn_v5_0_1_query_poison_status, 1573 }; 1574 1575 static int vcn_v5_0_1_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1576 enum aca_smu_type type, void *data) 1577 { 1578 struct aca_bank_info info; 1579 u64 misc0; 1580 int ret; 1581 1582 ret = aca_bank_info_decode(bank, &info); 1583 if (ret) 1584 return ret; 1585 1586 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 1587 switch (type) { 1588 case ACA_SMU_TYPE_UE: 1589 bank->aca_err_type = ACA_ERROR_TYPE_UE; 1590 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 1591 1ULL); 1592 break; 1593 case ACA_SMU_TYPE_CE: 1594 bank->aca_err_type = ACA_ERROR_TYPE_CE; 1595 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1596 ACA_REG__MISC0__ERRCNT(misc0)); 1597 break; 1598 default: 1599 return -EINVAL; 1600 } 1601 1602 return ret; 1603 } 1604 1605 /* reference to smu driver if header file */ 1606 static int vcn_v5_0_1_err_codes[] = { 1607 14, 15, 47, /* VCN [D|V|S] */ 1608 }; 1609 1610 static bool vcn_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 1611 enum aca_smu_type type, void *data) 1612 { 1613 u32 instlo; 1614 1615 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 1616 instlo &= GENMASK(31, 1); 1617 1618 if (instlo != mmSMNAID_AID0_MCA_SMU) 1619 return false; 1620 1621 if (aca_bank_check_error_codes(handle->adev, bank, 1622 vcn_v5_0_1_err_codes, 1623 ARRAY_SIZE(vcn_v5_0_1_err_codes))) 1624 return false; 1625 1626 return true; 1627 } 1628 1629 static const struct aca_bank_ops vcn_v5_0_1_aca_bank_ops = { 1630 .aca_bank_parser = vcn_v5_0_1_aca_bank_parser, 1631 .aca_bank_is_valid = vcn_v5_0_1_aca_bank_is_valid, 1632 }; 1633 1634 static const struct aca_info vcn_v5_0_1_aca_info = { 1635 .hwip = ACA_HWIP_TYPE_SMU, 1636 .mask = ACA_ERROR_UE_MASK, 1637 .bank_ops = &vcn_v5_0_1_aca_bank_ops, 1638 }; 1639 1640 static int vcn_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1641 { 1642 int r; 1643 1644 r = amdgpu_ras_block_late_init(adev, ras_block); 1645 if (r) 1646 return r; 1647 1648 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN, 1649 &vcn_v5_0_1_aca_info, NULL); 1650 if (r) 1651 goto late_fini; 1652 1653 if (amdgpu_ras_is_supported(adev, ras_block->block) && 1654 adev->vcn.inst->ras_poison_irq.funcs) { 1655 r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0); 1656 if (r) 1657 goto late_fini; 1658 } 1659 1660 return 0; 1661 1662 late_fini: 1663 amdgpu_ras_block_late_fini(adev, ras_block); 1664 1665 return r; 1666 } 1667 1668 static struct amdgpu_vcn_ras vcn_v5_0_1_ras = { 1669 .ras_block = { 1670 .hw_ops = &vcn_v5_0_1_ras_hw_ops, 1671 .ras_late_init = vcn_v5_0_1_ras_late_init, 1672 }, 1673 }; 1674 1675 static void vcn_v5_0_1_set_ras_funcs(struct amdgpu_device *adev) 1676 { 1677 adev->vcn.ras = &vcn_v5_0_1_ras; 1678 } 1679