1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_hw_ip.h" 31 #include "vcn_v2_0.h" 32 33 #include "vcn/vcn_5_0_0_offset.h" 34 #include "vcn/vcn_5_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" 36 #include "vcn_v5_0_0.h" 37 38 #include <drm/drm_drv.h> 39 40 static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0[] = { 41 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 42 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 43 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 44 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 45 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 46 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 47 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 48 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 72 }; 73 74 static int amdgpu_ih_clientid_vcns[] = { 75 SOC15_IH_CLIENTID_VCN, 76 SOC15_IH_CLIENTID_VCN1 77 }; 78 79 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev); 80 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev); 81 static int vcn_v5_0_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 82 enum amd_powergating_state state); 83 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 84 struct dpg_pause_state *new_state); 85 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 86 87 /** 88 * vcn_v5_0_0_early_init - set function pointers and load microcode 89 * 90 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 91 * 92 * Set ring and irq function pointers 93 * Load microcode from filesystem 94 */ 95 static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block) 96 { 97 struct amdgpu_device *adev = ip_block->adev; 98 int i, r; 99 100 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 101 /* re-use enc ring as unified ring */ 102 adev->vcn.inst[i].num_enc_rings = 1; 103 104 vcn_v5_0_0_set_unified_ring_funcs(adev); 105 vcn_v5_0_0_set_irq_funcs(adev); 106 107 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 108 adev->vcn.inst[i].set_pg_state = vcn_v5_0_0_set_pg_state; 109 110 r = amdgpu_vcn_early_init(adev, i); 111 if (r) 112 return r; 113 } 114 115 return 0; 116 } 117 118 /** 119 * vcn_v5_0_0_sw_init - sw init for VCN block 120 * 121 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 122 * 123 * Load firmware and sw initialization 124 */ 125 static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) 126 { 127 struct amdgpu_ring *ring; 128 struct amdgpu_device *adev = ip_block->adev; 129 int i, r; 130 131 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 132 struct amdgpu_vcn5_fw_shared *fw_shared; 133 134 if (adev->vcn.harvest_config & (1 << i)) 135 continue; 136 137 r = amdgpu_vcn_sw_init(adev, i); 138 if (r) 139 return r; 140 141 amdgpu_vcn_setup_ucode(adev, i); 142 143 r = amdgpu_vcn_resume(adev, i); 144 if (r) 145 return r; 146 147 atomic_set(&adev->vcn.inst[i].sched_score, 0); 148 149 /* VCN UNIFIED TRAP */ 150 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 151 VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 152 if (r) 153 return r; 154 155 /* VCN POISON TRAP */ 156 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 157 VCN_5_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 158 if (r) 159 return r; 160 161 ring = &adev->vcn.inst[i].ring_enc[0]; 162 ring->use_doorbell = true; 163 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 164 165 ring->vm_hub = AMDGPU_MMHUB0(0); 166 sprintf(ring->name, "vcn_unified_%d", i); 167 168 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 169 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 170 if (r) 171 return r; 172 173 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 174 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 175 fw_shared->sq.is_enabled = 1; 176 177 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 178 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 179 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 180 181 if (amdgpu_vcnfw_log) 182 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 183 184 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 185 adev->vcn.inst[i].pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode; 186 } 187 188 adev->vcn.supported_reset = 189 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 190 if (!amdgpu_sriov_vf(adev)) 191 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 192 193 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0, ARRAY_SIZE(vcn_reg_list_5_0)); 194 if (r) 195 return r; 196 197 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 198 if (r) 199 return r; 200 201 return 0; 202 } 203 204 /** 205 * vcn_v5_0_0_sw_fini - sw fini for VCN block 206 * 207 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 208 * 209 * VCN suspend and free up sw allocation 210 */ 211 static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block) 212 { 213 struct amdgpu_device *adev = ip_block->adev; 214 int i, r, idx; 215 216 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 217 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 218 struct amdgpu_vcn5_fw_shared *fw_shared; 219 220 if (adev->vcn.harvest_config & (1 << i)) 221 continue; 222 223 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 224 fw_shared->present_flag_0 = 0; 225 fw_shared->sq.is_enabled = 0; 226 } 227 228 drm_dev_exit(idx); 229 } 230 231 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 232 r = amdgpu_vcn_suspend(adev, i); 233 if (r) 234 return r; 235 } 236 237 amdgpu_vcn_sysfs_reset_mask_fini(adev); 238 239 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 240 amdgpu_vcn_sw_fini(adev, i); 241 242 return 0; 243 } 244 245 /** 246 * vcn_v5_0_0_hw_init - start and test VCN block 247 * 248 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 249 * 250 * Initialize the hardware, boot up the VCPU and do some testing 251 */ 252 static int vcn_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block) 253 { 254 struct amdgpu_device *adev = ip_block->adev; 255 struct amdgpu_ring *ring; 256 int i, r; 257 258 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 259 if (adev->vcn.harvest_config & (1 << i)) 260 continue; 261 262 ring = &adev->vcn.inst[i].ring_enc[0]; 263 264 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 265 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 266 267 r = amdgpu_ring_test_helper(ring); 268 if (r) 269 return r; 270 } 271 272 return 0; 273 } 274 275 /** 276 * vcn_v5_0_0_hw_fini - stop the hardware block 277 * 278 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 279 * 280 * Stop the VCN block, mark ring as not ready any more 281 */ 282 static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block) 283 { 284 struct amdgpu_device *adev = ip_block->adev; 285 int i; 286 287 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 288 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 289 290 if (adev->vcn.harvest_config & (1 << i)) 291 continue; 292 293 cancel_delayed_work_sync(&vinst->idle_work); 294 295 if (!amdgpu_sriov_vf(adev)) { 296 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 297 (vinst->cur_state != AMD_PG_STATE_GATE && 298 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 299 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 300 } 301 } 302 } 303 304 return 0; 305 } 306 307 /** 308 * vcn_v5_0_0_suspend - suspend VCN block 309 * 310 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 311 * 312 * HW fini and suspend VCN block 313 */ 314 static int vcn_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) 315 { 316 struct amdgpu_device *adev = ip_block->adev; 317 int r, i; 318 319 r = vcn_v5_0_0_hw_fini(ip_block); 320 if (r) 321 return r; 322 323 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 324 r = amdgpu_vcn_suspend(ip_block->adev, i); 325 if (r) 326 return r; 327 } 328 329 return r; 330 } 331 332 /** 333 * vcn_v5_0_0_resume - resume VCN block 334 * 335 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 336 * 337 * Resume firmware and hw init VCN block 338 */ 339 static int vcn_v5_0_0_resume(struct amdgpu_ip_block *ip_block) 340 { 341 struct amdgpu_device *adev = ip_block->adev; 342 int r, i; 343 344 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 345 r = amdgpu_vcn_resume(ip_block->adev, i); 346 if (r) 347 return r; 348 } 349 350 r = vcn_v5_0_0_hw_init(ip_block); 351 352 return r; 353 } 354 355 /** 356 * vcn_v5_0_0_mc_resume - memory controller programming 357 * 358 * @vinst: VCN instance 359 * 360 * Let the VCN memory controller know it's offsets 361 */ 362 static void vcn_v5_0_0_mc_resume(struct amdgpu_vcn_inst *vinst) 363 { 364 struct amdgpu_device *adev = vinst->adev; 365 int inst = vinst->inst; 366 uint32_t offset, size; 367 const struct common_firmware_header *hdr; 368 369 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 370 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 371 372 /* cache window 0: fw */ 373 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 374 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 375 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 376 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 377 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 378 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 379 offset = 0; 380 } else { 381 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 382 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 383 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 384 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 385 offset = size; 386 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 387 } 388 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 389 390 /* cache window 1: stack */ 391 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 392 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 393 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 394 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 395 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 396 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 397 398 /* cache window 2: context */ 399 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 400 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 401 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 402 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 403 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 404 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 405 406 /* non-cache window */ 407 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 408 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 409 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 410 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 411 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 412 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 413 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); 414 } 415 416 /** 417 * vcn_v5_0_0_mc_resume_dpg_mode - memory controller programming for dpg mode 418 * 419 * @vinst: VCN instance 420 * @indirect: indirectly write sram 421 * 422 * Let the VCN memory controller know it's offsets with dpg mode 423 */ 424 static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 425 bool indirect) 426 { 427 struct amdgpu_device *adev = vinst->adev; 428 int inst_idx = vinst->inst; 429 uint32_t offset, size; 430 const struct common_firmware_header *hdr; 431 432 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 433 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 434 435 /* cache window 0: fw */ 436 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 437 if (!indirect) { 438 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 439 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 440 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 441 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 442 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 443 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 444 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 445 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 446 } else { 447 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 448 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 449 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 450 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 451 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 452 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 453 } 454 offset = 0; 455 } else { 456 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 457 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 458 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 459 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 460 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 461 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 462 offset = size; 463 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 464 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 465 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 466 } 467 468 if (!indirect) 469 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 470 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 471 else 472 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 473 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 474 475 /* cache window 1: stack */ 476 if (!indirect) { 477 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 478 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 479 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 480 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 481 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 482 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 483 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 484 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 485 } else { 486 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 487 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 488 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 489 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 490 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 491 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 492 } 493 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 494 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 495 496 /* cache window 2: context */ 497 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 498 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 499 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 500 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 501 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 502 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 503 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 504 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 505 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 506 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 507 508 /* non-cache window */ 509 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 510 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 511 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 512 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 513 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 514 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 515 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 516 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 517 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 518 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 519 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); 520 521 /* VCN global tiling registers */ 522 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 523 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 524 adev->gfx.config.gb_addr_config, 0, indirect); 525 526 return; 527 } 528 529 /** 530 * vcn_v5_0_0_disable_static_power_gating - disable VCN static power gating 531 * 532 * @vinst: VCN instance 533 * 534 * Disable static power gating for VCN block 535 */ 536 static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 537 { 538 struct amdgpu_device *adev = vinst->adev; 539 int inst = vinst->inst; 540 uint32_t data = 0; 541 542 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 543 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 544 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 545 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 546 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 547 548 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 549 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 550 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 551 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 552 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 553 554 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 555 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 556 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 557 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 558 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 559 560 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 561 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 562 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 563 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 564 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 565 } else { 566 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 567 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 568 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 569 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 570 571 data = 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 572 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 573 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 574 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 575 576 data = 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 577 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 578 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 579 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 580 581 data = 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 582 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 583 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 584 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 585 } 586 587 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 588 data &= ~0x103; 589 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 590 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 591 UVD_POWER_STATUS__UVD_PG_EN_MASK; 592 593 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 594 return; 595 } 596 597 /** 598 * vcn_v5_0_0_enable_static_power_gating - enable VCN static power gating 599 * 600 * @vinst: VCN instance 601 * 602 * Enable static power gating for VCN block 603 */ 604 static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 605 { 606 struct amdgpu_device *adev = vinst->adev; 607 int inst = vinst->inst; 608 uint32_t data; 609 610 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 611 /* Before power off, this indicator has to be turned on */ 612 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 613 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 614 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 615 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 616 617 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 618 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 619 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 620 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 621 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 622 623 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 624 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 625 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 626 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 627 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 628 629 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 630 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 631 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 632 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 633 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 634 635 data = 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 636 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 637 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 638 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 639 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 640 } 641 return; 642 } 643 644 /** 645 * vcn_v5_0_0_disable_clock_gating - disable VCN clock gating 646 * 647 * @vinst: VCN instance 648 * 649 * Disable clock gating for VCN block 650 */ 651 static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 652 { 653 return; 654 } 655 656 #if 0 657 /** 658 * vcn_v5_0_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 659 * 660 * @vinst: VCN instance 661 * @sram_sel: sram select 662 * @indirect: indirectly write sram 663 * 664 * Disable clock gating for VCN block with dpg mode 665 */ 666 static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 667 uint8_t sram_sel, 668 uint8_t indirect) 669 { 670 return; 671 } 672 #endif 673 674 /** 675 * vcn_v5_0_0_enable_clock_gating - enable VCN clock gating 676 * 677 * @vinst: VCN instance 678 * 679 * Enable clock gating for VCN block 680 */ 681 static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 682 { 683 return; 684 } 685 686 /** 687 * vcn_v5_0_0_start_dpg_mode - VCN start with dpg mode 688 * 689 * @vinst: VCN instance 690 * @indirect: indirectly write sram 691 * 692 * Start VCN block with dpg mode 693 */ 694 static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 695 bool indirect) 696 { 697 struct amdgpu_device *adev = vinst->adev; 698 int inst_idx = vinst->inst; 699 struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 700 struct amdgpu_ring *ring; 701 uint32_t tmp; 702 int ret; 703 704 /* disable register anti-hang mechanism */ 705 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 706 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 707 708 /* enable dynamic power gating mode */ 709 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 710 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 711 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 712 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 713 714 if (indirect) 715 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 716 717 /* enable VCPU clock */ 718 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 719 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 720 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 721 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 722 723 /* disable master interrupt */ 724 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 725 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 726 727 /* setup regUVD_LMI_CTRL */ 728 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 729 UVD_LMI_CTRL__REQ_MODE_MASK | 730 UVD_LMI_CTRL__CRC_RESET_MASK | 731 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 732 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 733 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 734 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 735 0x00100000L); 736 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 737 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 738 739 vcn_v5_0_0_mc_resume_dpg_mode(vinst, indirect); 740 741 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 742 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 743 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 744 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 745 746 /* enable LMI MC and UMC channels */ 747 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 748 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 749 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 750 751 /* enable master interrupt */ 752 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 753 VCN, inst_idx, regUVD_MASTINT_EN), 754 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 755 756 if (indirect) { 757 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 758 if (ret) { 759 dev_err(adev->dev, "%s: vcn sram load failed %d\n", __func__, ret); 760 return ret; 761 } 762 } 763 764 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 765 766 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 767 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 768 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 769 770 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 771 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 772 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 773 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 774 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 775 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 776 777 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 778 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 779 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 780 781 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 782 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 783 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 784 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 785 786 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 787 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 788 VCN_RB1_DB_CTRL__EN_MASK); 789 790 /* Keeping one read-back to ensure all register writes are done, 791 * otherwise it may introduce race conditions. 792 */ 793 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); 794 795 return 0; 796 } 797 798 /** 799 * vcn_v5_0_0_set_mmhub_eco_sec_level - set vcn sec lvl reg 800 * 801 * @adev: amdgpu_device pointer 802 * 803 * request psp to set sec lvl 804 */ 805 static int vcn_v5_0_0_set_mmhub_eco_sec_level(struct amdgpu_device *adev) 806 { 807 int r = 0; 808 809 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(5, 3, 0)) { 810 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 811 /* Request to PSP to program VCN secure lvl */ 812 r = psp_set_mmhub_eco_sec_level(adev); 813 } 814 } 815 816 return r; 817 } 818 819 /** 820 * vcn_v5_0_0_start - VCN start 821 * 822 * @vinst: VCN instance 823 * 824 * Start VCN block 825 */ 826 static int vcn_v5_0_0_start(struct amdgpu_vcn_inst *vinst) 827 { 828 struct amdgpu_device *adev = vinst->adev; 829 int i = vinst->inst; 830 struct amdgpu_vcn5_fw_shared *fw_shared; 831 struct amdgpu_ring *ring; 832 uint32_t tmp; 833 int j, k, r; 834 835 if (adev->vcn.harvest_config & (1 << i)) 836 return 0; 837 838 if (adev->pm.dpm_enabled) 839 amdgpu_dpm_enable_vcn(adev, true, i); 840 841 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 842 843 /* program VCN secure lvl register */ 844 r = vcn_v5_0_0_set_mmhub_eco_sec_level(adev); 845 if (r) 846 return r; 847 848 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 849 return vcn_v5_0_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 850 851 /* disable VCN power gating */ 852 vcn_v5_0_0_disable_static_power_gating(vinst); 853 854 /* set VCN status busy */ 855 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 856 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 857 858 /* enable VCPU clock */ 859 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 860 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 861 862 /* disable master interrupt */ 863 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 864 ~UVD_MASTINT_EN__VCPU_EN_MASK); 865 866 /* enable LMI MC and UMC channels */ 867 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 868 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 869 870 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 871 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 872 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 873 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 874 875 /* setup regUVD_LMI_CTRL */ 876 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 877 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 878 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 879 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 880 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 881 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 882 883 vcn_v5_0_0_mc_resume(vinst); 884 885 /* VCN global tiling registers */ 886 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 887 adev->gfx.config.gb_addr_config); 888 889 /* unblock VCPU register access */ 890 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 891 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 892 893 /* release VCPU reset to boot */ 894 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 895 ~UVD_VCPU_CNTL__BLK_RST_MASK); 896 897 for (j = 0; j < 10; ++j) { 898 uint32_t status; 899 900 for (k = 0; k < 100; ++k) { 901 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 902 if (status & 2) 903 break; 904 mdelay(10); 905 if (amdgpu_emu_mode == 1) 906 msleep(1); 907 } 908 909 if (amdgpu_emu_mode == 1) { 910 r = -1; 911 if (status & 2) { 912 r = 0; 913 break; 914 } 915 } else { 916 r = 0; 917 if (status & 2) 918 break; 919 920 dev_err(adev->dev, 921 "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 922 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 923 UVD_VCPU_CNTL__BLK_RST_MASK, 924 ~UVD_VCPU_CNTL__BLK_RST_MASK); 925 mdelay(10); 926 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 927 ~UVD_VCPU_CNTL__BLK_RST_MASK); 928 929 mdelay(10); 930 r = -1; 931 } 932 } 933 934 if (r) { 935 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 936 return r; 937 } 938 939 /* enable master interrupt */ 940 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 941 UVD_MASTINT_EN__VCPU_EN_MASK, 942 ~UVD_MASTINT_EN__VCPU_EN_MASK); 943 944 /* clear the busy bit of VCN_STATUS */ 945 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 946 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 947 948 ring = &adev->vcn.inst[i].ring_enc[0]; 949 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 950 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 951 VCN_RB1_DB_CTRL__EN_MASK); 952 953 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 954 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 955 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 956 957 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 958 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 959 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 960 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 961 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 962 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 963 964 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 965 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 966 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 967 968 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 969 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 970 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 971 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 972 973 /* Keeping one read-back to ensure all register writes are done, 974 * otherwise it may introduce race conditions. 975 */ 976 RREG32_SOC15(VCN, i, regUVD_STATUS); 977 978 return 0; 979 } 980 981 /** 982 * vcn_v5_0_0_stop_dpg_mode - VCN stop with dpg mode 983 * 984 * @vinst: VCN instance 985 * 986 * Stop VCN block with dpg mode 987 */ 988 static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 989 { 990 struct amdgpu_device *adev = vinst->adev; 991 int inst_idx = vinst->inst; 992 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 993 uint32_t tmp; 994 995 vcn_v5_0_0_pause_dpg_mode(vinst, &state); 996 997 /* Wait for power status to be 1 */ 998 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 999 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1000 1001 /* wait for read ptr to be equal to write ptr */ 1002 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1003 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1004 1005 /* disable dynamic power gating mode */ 1006 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1007 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1008 1009 /* Keeping one read-back to ensure all register writes are done, 1010 * otherwise it may introduce race conditions. 1011 */ 1012 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); 1013 1014 return; 1015 } 1016 1017 /** 1018 * vcn_v5_0_0_stop - VCN stop 1019 * 1020 * @vinst: VCN instance 1021 * 1022 * Stop VCN block 1023 */ 1024 static int vcn_v5_0_0_stop(struct amdgpu_vcn_inst *vinst) 1025 { 1026 struct amdgpu_device *adev = vinst->adev; 1027 int i = vinst->inst; 1028 struct amdgpu_vcn5_fw_shared *fw_shared; 1029 uint32_t tmp; 1030 int r = 0; 1031 1032 if (adev->vcn.harvest_config & (1 << i)) 1033 return 0; 1034 1035 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1036 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1037 1038 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1039 vcn_v5_0_0_stop_dpg_mode(vinst); 1040 r = 0; 1041 goto done; 1042 } 1043 1044 /* wait for vcn idle */ 1045 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1046 if (r) 1047 goto done; 1048 1049 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1050 UVD_LMI_STATUS__READ_CLEAN_MASK | 1051 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1052 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1053 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1054 if (r) 1055 goto done; 1056 1057 /* disable LMI UMC channel */ 1058 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1059 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1060 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1061 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1062 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1063 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1064 if (r) 1065 goto done; 1066 1067 /* block VCPU register access */ 1068 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1069 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1070 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1071 1072 /* reset VCPU */ 1073 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1074 UVD_VCPU_CNTL__BLK_RST_MASK, 1075 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1076 1077 /* disable VCPU clock */ 1078 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1079 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1080 1081 /* apply soft reset */ 1082 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1083 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1084 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1085 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1086 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1087 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1088 1089 /* clear status */ 1090 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1091 1092 /* enable VCN power gating */ 1093 vcn_v5_0_0_enable_static_power_gating(vinst); 1094 1095 /* Keeping one read-back to ensure all register writes are done, 1096 * otherwise it may introduce race conditions. 1097 */ 1098 RREG32_SOC15(VCN, i, regUVD_STATUS); 1099 1100 done: 1101 if (adev->pm.dpm_enabled) 1102 amdgpu_dpm_enable_vcn(adev, false, i); 1103 1104 return r; 1105 } 1106 1107 /** 1108 * vcn_v5_0_0_pause_dpg_mode - VCN pause with dpg mode 1109 * 1110 * @vinst: VCN instance 1111 * @new_state: pause state 1112 * 1113 * Pause dpg mode for VCN block 1114 */ 1115 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1116 struct dpg_pause_state *new_state) 1117 { 1118 struct amdgpu_device *adev = vinst->adev; 1119 int inst_idx = vinst->inst; 1120 uint32_t reg_data = 0; 1121 int ret_code; 1122 1123 /* pause/unpause if state is changed */ 1124 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1125 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1126 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1127 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1128 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1129 1130 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1131 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1132 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1133 1134 if (!ret_code) { 1135 /* pause DPG */ 1136 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1137 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1138 1139 /* wait for ACK */ 1140 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1141 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1142 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1143 } 1144 } else { 1145 /* unpause dpg, no need to wait */ 1146 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1147 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1148 } 1149 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1150 } 1151 1152 return 0; 1153 } 1154 1155 /** 1156 * vcn_v5_0_0_unified_ring_get_rptr - get unified read pointer 1157 * 1158 * @ring: amdgpu_ring pointer 1159 * 1160 * Returns the current hardware unified read pointer 1161 */ 1162 static uint64_t vcn_v5_0_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1163 { 1164 struct amdgpu_device *adev = ring->adev; 1165 1166 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1167 DRM_ERROR("wrong ring id is identified in %s", __func__); 1168 1169 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1170 } 1171 1172 /** 1173 * vcn_v5_0_0_unified_ring_get_wptr - get unified write pointer 1174 * 1175 * @ring: amdgpu_ring pointer 1176 * 1177 * Returns the current hardware unified write pointer 1178 */ 1179 static uint64_t vcn_v5_0_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1180 { 1181 struct amdgpu_device *adev = ring->adev; 1182 1183 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1184 DRM_ERROR("wrong ring id is identified in %s", __func__); 1185 1186 if (ring->use_doorbell) 1187 return *ring->wptr_cpu_addr; 1188 else 1189 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1190 } 1191 1192 /** 1193 * vcn_v5_0_0_unified_ring_set_wptr - set enc write pointer 1194 * 1195 * @ring: amdgpu_ring pointer 1196 * 1197 * Commits the enc write pointer to the hardware 1198 */ 1199 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1200 { 1201 struct amdgpu_device *adev = ring->adev; 1202 1203 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1204 DRM_ERROR("wrong ring id is identified in %s", __func__); 1205 1206 if (ring->use_doorbell) { 1207 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1208 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1209 } else { 1210 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1211 } 1212 } 1213 1214 static int vcn_v5_0_0_ring_reset(struct amdgpu_ring *ring, 1215 unsigned int vmid, 1216 struct amdgpu_fence *timedout_fence) 1217 { 1218 struct amdgpu_device *adev = ring->adev; 1219 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1220 int r; 1221 1222 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1223 r = vcn_v5_0_0_stop(vinst); 1224 if (r) 1225 return r; 1226 r = vcn_v5_0_0_start(vinst); 1227 if (r) 1228 return r; 1229 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1230 } 1231 1232 static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { 1233 .type = AMDGPU_RING_TYPE_VCN_ENC, 1234 .align_mask = 0x3f, 1235 .nop = VCN_ENC_CMD_NO_OP, 1236 .no_user_fence = true, 1237 .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, 1238 .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, 1239 .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, 1240 .emit_frame_size = 1241 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1242 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1243 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1244 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1245 1, /* vcn_v2_0_enc_ring_insert_end */ 1246 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1247 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1248 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1249 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1250 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1251 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1252 .insert_nop = amdgpu_ring_insert_nop, 1253 .insert_end = vcn_v2_0_enc_ring_insert_end, 1254 .pad_ib = amdgpu_ring_generic_pad_ib, 1255 .begin_use = amdgpu_vcn_ring_begin_use, 1256 .end_use = amdgpu_vcn_ring_end_use, 1257 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1258 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1259 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1260 .reset = vcn_v5_0_0_ring_reset, 1261 }; 1262 1263 static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs_secure = { 1264 .type = AMDGPU_RING_TYPE_VCN_ENC, 1265 .align_mask = 0x3f, 1266 .nop = VCN_ENC_CMD_NO_OP, 1267 .secure_submission_supported = true, 1268 .no_user_fence = true, 1269 .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, 1270 .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, 1271 .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, 1272 .emit_frame_size = 1273 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1274 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1275 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1276 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1277 1, /* vcn_v2_0_enc_ring_insert_end */ 1278 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1279 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1280 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1281 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1282 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1283 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1284 .insert_nop = amdgpu_ring_insert_nop, 1285 .insert_end = vcn_v2_0_enc_ring_insert_end, 1286 .pad_ib = amdgpu_ring_generic_pad_ib, 1287 .begin_use = amdgpu_vcn_ring_begin_use, 1288 .end_use = amdgpu_vcn_ring_end_use, 1289 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1290 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1291 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1292 .reset = vcn_v5_0_0_ring_reset, 1293 }; 1294 1295 /** 1296 * vcn_v5_0_0_set_unified_ring_funcs - set unified ring functions 1297 * 1298 * @adev: amdgpu_device pointer 1299 * 1300 * Set unified ring functions 1301 */ 1302 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1303 { 1304 int i; 1305 1306 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1307 if (adev->vcn.harvest_config & (1 << i)) 1308 continue; 1309 1310 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(5, 3, 0)) 1311 adev->vcn.inst[i].ring_enc[0].funcs = 1312 &vcn_v5_0_0_unified_ring_vm_funcs_secure; 1313 else 1314 adev->vcn.inst[i].ring_enc[0].funcs = 1315 &vcn_v5_0_0_unified_ring_vm_funcs; 1316 adev->vcn.inst[i].ring_enc[0].me = i; 1317 } 1318 } 1319 1320 /** 1321 * vcn_v5_0_0_is_idle - check VCN block is idle 1322 * 1323 * @ip_block: Pointer to the amdgpu_ip_block structure 1324 * 1325 * Check whether VCN block is idle 1326 */ 1327 static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block) 1328 { 1329 struct amdgpu_device *adev = ip_block->adev; 1330 int i, ret = 1; 1331 1332 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1333 if (adev->vcn.harvest_config & (1 << i)) 1334 continue; 1335 1336 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1337 } 1338 1339 return ret; 1340 } 1341 1342 /** 1343 * vcn_v5_0_0_wait_for_idle - wait for VCN block idle 1344 * 1345 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1346 * 1347 * Wait for VCN block idle 1348 */ 1349 static int vcn_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1350 { 1351 struct amdgpu_device *adev = ip_block->adev; 1352 int i, ret = 0; 1353 1354 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1355 if (adev->vcn.harvest_config & (1 << i)) 1356 continue; 1357 1358 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1359 UVD_STATUS__IDLE); 1360 if (ret) 1361 return ret; 1362 } 1363 1364 return ret; 1365 } 1366 1367 /** 1368 * vcn_v5_0_0_set_clockgating_state - set VCN block clockgating state 1369 * 1370 * @ip_block: amdgpu_ip_block pointer 1371 * @state: clock gating state 1372 * 1373 * Set VCN block clockgating state 1374 */ 1375 static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1376 enum amd_clockgating_state state) 1377 { 1378 struct amdgpu_device *adev = ip_block->adev; 1379 bool enable = state == AMD_CG_STATE_GATE; 1380 int i; 1381 1382 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1383 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1384 1385 if (adev->vcn.harvest_config & (1 << i)) 1386 continue; 1387 1388 if (enable) { 1389 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1390 return -EBUSY; 1391 vcn_v5_0_0_enable_clock_gating(vinst); 1392 } else { 1393 vcn_v5_0_0_disable_clock_gating(vinst); 1394 } 1395 } 1396 1397 return 0; 1398 } 1399 1400 static int vcn_v5_0_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 1401 enum amd_powergating_state state) 1402 { 1403 int ret = 0; 1404 1405 if (state == vinst->cur_state) 1406 return 0; 1407 1408 if (state == AMD_PG_STATE_GATE) 1409 ret = vcn_v5_0_0_stop(vinst); 1410 else 1411 ret = vcn_v5_0_0_start(vinst); 1412 1413 if (!ret) 1414 vinst->cur_state = state; 1415 1416 return ret; 1417 } 1418 1419 /** 1420 * vcn_v5_0_0_process_interrupt - process VCN block interrupt 1421 * 1422 * @adev: amdgpu_device pointer 1423 * @source: interrupt sources 1424 * @entry: interrupt entry from clients and sources 1425 * 1426 * Process VCN block interrupt 1427 */ 1428 static int vcn_v5_0_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1429 struct amdgpu_iv_entry *entry) 1430 { 1431 uint32_t ip_instance; 1432 1433 switch (entry->client_id) { 1434 case SOC15_IH_CLIENTID_VCN: 1435 ip_instance = 0; 1436 break; 1437 case SOC15_IH_CLIENTID_VCN1: 1438 ip_instance = 1; 1439 break; 1440 default: 1441 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1442 return 0; 1443 } 1444 1445 DRM_DEBUG("IH: VCN TRAP\n"); 1446 1447 switch (entry->src_id) { 1448 case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1449 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1450 break; 1451 case VCN_5_0__SRCID_UVD_POISON: 1452 amdgpu_vcn_process_poison_irq(adev, source, entry); 1453 break; 1454 default: 1455 DRM_ERROR("Unhandled interrupt: %d %d\n", 1456 entry->src_id, entry->src_data[0]); 1457 break; 1458 } 1459 1460 return 0; 1461 } 1462 1463 static const struct amdgpu_irq_src_funcs vcn_v5_0_0_irq_funcs = { 1464 .process = vcn_v5_0_0_process_interrupt, 1465 }; 1466 1467 /** 1468 * vcn_v5_0_0_set_irq_funcs - set VCN block interrupt irq functions 1469 * 1470 * @adev: amdgpu_device pointer 1471 * 1472 * Set VCN block interrupt irq functions 1473 */ 1474 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) 1475 { 1476 int i; 1477 1478 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1479 if (adev->vcn.harvest_config & (1 << i)) 1480 continue; 1481 1482 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 1483 adev->vcn.inst[i].irq.funcs = &vcn_v5_0_0_irq_funcs; 1484 } 1485 } 1486 1487 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { 1488 .name = "vcn_v5_0_0", 1489 .early_init = vcn_v5_0_0_early_init, 1490 .sw_init = vcn_v5_0_0_sw_init, 1491 .sw_fini = vcn_v5_0_0_sw_fini, 1492 .hw_init = vcn_v5_0_0_hw_init, 1493 .hw_fini = vcn_v5_0_0_hw_fini, 1494 .suspend = vcn_v5_0_0_suspend, 1495 .resume = vcn_v5_0_0_resume, 1496 .is_idle = vcn_v5_0_0_is_idle, 1497 .wait_for_idle = vcn_v5_0_0_wait_for_idle, 1498 .set_clockgating_state = vcn_v5_0_0_set_clockgating_state, 1499 .set_powergating_state = vcn_set_powergating_state, 1500 .dump_ip_state = amdgpu_vcn_dump_ip_state, 1501 .print_ip_state = amdgpu_vcn_print_ip_state, 1502 }; 1503 1504 const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = { 1505 .type = AMD_IP_BLOCK_TYPE_VCN, 1506 .major = 5, 1507 .minor = 0, 1508 .rev = 0, 1509 .funcs = &vcn_v5_0_0_ip_funcs, 1510 }; 1511