1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_hw_ip.h" 31 #include "vcn_v2_0.h" 32 33 #include "vcn/vcn_5_0_0_offset.h" 34 #include "vcn/vcn_5_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 36 #include "vcn_v5_0_0.h" 37 38 #include <drm/drm_drv.h> 39 40 static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0[] = { 41 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 42 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 43 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 44 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 45 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 46 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 47 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 48 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 72 }; 73 74 static int amdgpu_ih_clientid_vcns[] = { 75 SOC15_IH_CLIENTID_VCN, 76 SOC15_IH_CLIENTID_VCN1 77 }; 78 79 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev); 80 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev); 81 static int vcn_v5_0_0_set_powergating_state(void *handle, 82 enum amd_powergating_state state); 83 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev, 84 int inst_idx, struct dpg_pause_state *new_state); 85 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 86 87 /** 88 * vcn_v5_0_0_early_init - set function pointers and load microcode 89 * 90 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 91 * 92 * Set ring and irq function pointers 93 * Load microcode from filesystem 94 */ 95 static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block) 96 { 97 struct amdgpu_device *adev = ip_block->adev; 98 99 /* re-use enc ring as unified ring */ 100 adev->vcn.num_enc_rings = 1; 101 102 vcn_v5_0_0_set_unified_ring_funcs(adev); 103 vcn_v5_0_0_set_irq_funcs(adev); 104 105 return amdgpu_vcn_early_init(adev); 106 } 107 108 /** 109 * vcn_v5_0_0_sw_init - sw init for VCN block 110 * 111 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 112 * 113 * Load firmware and sw initialization 114 */ 115 static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) 116 { 117 struct amdgpu_ring *ring; 118 struct amdgpu_device *adev = ip_block->adev; 119 int i, r; 120 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); 121 uint32_t *ptr; 122 123 r = amdgpu_vcn_sw_init(adev); 124 if (r) 125 return r; 126 127 amdgpu_vcn_setup_ucode(adev); 128 129 r = amdgpu_vcn_resume(adev); 130 if (r) 131 return r; 132 133 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 134 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 135 136 if (adev->vcn.harvest_config & (1 << i)) 137 continue; 138 139 atomic_set(&adev->vcn.inst[i].sched_score, 0); 140 141 /* VCN UNIFIED TRAP */ 142 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 143 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 144 if (r) 145 return r; 146 147 /* VCN POISON TRAP */ 148 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 149 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 150 if (r) 151 return r; 152 153 ring = &adev->vcn.inst[i].ring_enc[0]; 154 ring->use_doorbell = true; 155 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 156 157 ring->vm_hub = AMDGPU_MMHUB0(0); 158 sprintf(ring->name, "vcn_unified_%d", i); 159 160 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 161 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 162 if (r) 163 return r; 164 165 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 166 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 167 fw_shared->sq.is_enabled = 1; 168 169 if (amdgpu_vcnfw_log) 170 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 171 } 172 173 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 174 adev->vcn.pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode; 175 176 /* Allocate memory for VCN IP Dump buffer */ 177 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 178 if (!ptr) { 179 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 180 adev->vcn.ip_dump = NULL; 181 } else { 182 adev->vcn.ip_dump = ptr; 183 } 184 return 0; 185 } 186 187 /** 188 * vcn_v5_0_0_sw_fini - sw fini for VCN block 189 * 190 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 191 * 192 * VCN suspend and free up sw allocation 193 */ 194 static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block) 195 { 196 struct amdgpu_device *adev = ip_block->adev; 197 int i, r, idx; 198 199 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 200 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 201 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 202 203 if (adev->vcn.harvest_config & (1 << i)) 204 continue; 205 206 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 207 fw_shared->present_flag_0 = 0; 208 fw_shared->sq.is_enabled = 0; 209 } 210 211 drm_dev_exit(idx); 212 } 213 214 r = amdgpu_vcn_suspend(adev); 215 if (r) 216 return r; 217 218 r = amdgpu_vcn_sw_fini(adev); 219 220 kfree(adev->vcn.ip_dump); 221 222 return r; 223 } 224 225 /** 226 * vcn_v5_0_0_hw_init - start and test VCN block 227 * 228 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 229 * 230 * Initialize the hardware, boot up the VCPU and do some testing 231 */ 232 static int vcn_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block) 233 { 234 struct amdgpu_device *adev = ip_block->adev; 235 struct amdgpu_ring *ring; 236 int i, r; 237 238 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 239 if (adev->vcn.harvest_config & (1 << i)) 240 continue; 241 242 ring = &adev->vcn.inst[i].ring_enc[0]; 243 244 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 245 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 246 247 r = amdgpu_ring_test_helper(ring); 248 if (r) 249 return r; 250 } 251 252 return 0; 253 } 254 255 /** 256 * vcn_v5_0_0_hw_fini - stop the hardware block 257 * 258 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 259 * 260 * Stop the VCN block, mark ring as not ready any more 261 */ 262 static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block) 263 { 264 struct amdgpu_device *adev = ip_block->adev; 265 int i; 266 267 cancel_delayed_work_sync(&adev->vcn.idle_work); 268 269 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 270 if (adev->vcn.harvest_config & (1 << i)) 271 continue; 272 if (!amdgpu_sriov_vf(adev)) { 273 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 274 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 275 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 276 vcn_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 277 } 278 } 279 } 280 281 return 0; 282 } 283 284 /** 285 * vcn_v5_0_0_suspend - suspend VCN block 286 * 287 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 288 * 289 * HW fini and suspend VCN block 290 */ 291 static int vcn_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) 292 { 293 int r; 294 295 r = vcn_v5_0_0_hw_fini(ip_block); 296 if (r) 297 return r; 298 299 r = amdgpu_vcn_suspend(ip_block->adev); 300 301 return r; 302 } 303 304 /** 305 * vcn_v5_0_0_resume - resume VCN block 306 * 307 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 308 * 309 * Resume firmware and hw init VCN block 310 */ 311 static int vcn_v5_0_0_resume(struct amdgpu_ip_block *ip_block) 312 { 313 int r; 314 315 r = amdgpu_vcn_resume(ip_block->adev); 316 if (r) 317 return r; 318 319 r = vcn_v5_0_0_hw_init(ip_block); 320 321 return r; 322 } 323 324 /** 325 * vcn_v5_0_0_mc_resume - memory controller programming 326 * 327 * @adev: amdgpu_device pointer 328 * @inst: instance number 329 * 330 * Let the VCN memory controller know it's offsets 331 */ 332 static void vcn_v5_0_0_mc_resume(struct amdgpu_device *adev, int inst) 333 { 334 uint32_t offset, size; 335 const struct common_firmware_header *hdr; 336 337 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data; 338 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 339 340 /* cache window 0: fw */ 341 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 342 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 343 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 344 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 345 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 346 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 347 offset = 0; 348 } else { 349 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 350 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 351 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 352 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 353 offset = size; 354 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 355 } 356 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 357 358 /* cache window 1: stack */ 359 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 360 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 361 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 362 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 363 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 364 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 365 366 /* cache window 2: context */ 367 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 368 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 369 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 370 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 371 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 372 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 373 374 /* non-cache window */ 375 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 376 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 377 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 378 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 379 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 380 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 381 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); 382 } 383 384 /** 385 * vcn_v5_0_0_mc_resume_dpg_mode - memory controller programming for dpg mode 386 * 387 * @adev: amdgpu_device pointer 388 * @inst_idx: instance number index 389 * @indirect: indirectly write sram 390 * 391 * Let the VCN memory controller know it's offsets with dpg mode 392 */ 393 static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 394 { 395 uint32_t offset, size; 396 const struct common_firmware_header *hdr; 397 398 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data; 399 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 400 401 /* cache window 0: fw */ 402 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 403 if (!indirect) { 404 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 405 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 406 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 407 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 408 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 409 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 410 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 411 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 412 } else { 413 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 414 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 415 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 416 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 417 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 418 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 419 } 420 offset = 0; 421 } else { 422 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 423 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 424 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 425 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 426 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 427 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 428 offset = size; 429 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 430 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 431 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 432 } 433 434 if (!indirect) 435 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 436 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 437 else 438 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 439 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 440 441 /* cache window 1: stack */ 442 if (!indirect) { 443 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 444 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 445 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 446 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 447 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 448 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 449 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 450 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 451 } else { 452 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 453 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 454 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 455 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 456 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 457 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 458 } 459 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 460 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 461 462 /* cache window 2: context */ 463 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 464 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 465 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 466 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 467 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 468 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 469 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 470 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 471 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 472 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 473 474 /* non-cache window */ 475 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 476 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 477 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 478 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 479 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 480 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 481 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 482 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 483 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 484 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 485 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); 486 487 /* VCN global tiling registers */ 488 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 489 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 490 491 return; 492 } 493 494 /** 495 * vcn_v5_0_0_disable_static_power_gating - disable VCN static power gating 496 * 497 * @adev: amdgpu_device pointer 498 * @inst: instance number 499 * 500 * Disable static power gating for VCN block 501 */ 502 static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 503 { 504 uint32_t data = 0; 505 506 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 507 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 508 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 509 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 510 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 511 512 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 513 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 514 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 515 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 516 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 517 518 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 519 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 520 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 521 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 522 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 523 524 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 525 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 526 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 527 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 528 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 529 } else { 530 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 531 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 532 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 533 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 534 535 data = 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 536 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 537 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 538 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 539 540 data = 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 541 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 542 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 543 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 544 545 data = 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 546 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 547 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 548 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 549 } 550 551 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 552 data &= ~0x103; 553 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 554 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 555 UVD_POWER_STATUS__UVD_PG_EN_MASK; 556 557 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 558 return; 559 } 560 561 /** 562 * vcn_v5_0_0_enable_static_power_gating - enable VCN static power gating 563 * 564 * @adev: amdgpu_device pointer 565 * @inst: instance number 566 * 567 * Enable static power gating for VCN block 568 */ 569 static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 570 { 571 uint32_t data; 572 573 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 574 /* Before power off, this indicator has to be turned on */ 575 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 576 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 577 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 578 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 579 580 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 581 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 582 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 583 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 584 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 585 586 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 587 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 588 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 589 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 590 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 591 592 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 593 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 594 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 595 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 596 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 597 598 data = 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 599 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 600 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 601 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 602 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 603 } 604 return; 605 } 606 607 /** 608 * vcn_v5_0_0_disable_clock_gating - disable VCN clock gating 609 * 610 * @adev: amdgpu_device pointer 611 * @inst: instance number 612 * 613 * Disable clock gating for VCN block 614 */ 615 static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 616 { 617 return; 618 } 619 620 #if 0 621 /** 622 * vcn_v5_0_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 623 * 624 * @adev: amdgpu_device pointer 625 * @sram_sel: sram select 626 * @inst_idx: instance number index 627 * @indirect: indirectly write sram 628 * 629 * Disable clock gating for VCN block with dpg mode 630 */ 631 static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 632 int inst_idx, uint8_t indirect) 633 { 634 return; 635 } 636 #endif 637 638 /** 639 * vcn_v5_0_0_enable_clock_gating - enable VCN clock gating 640 * 641 * @adev: amdgpu_device pointer 642 * @inst: instance number 643 * 644 * Enable clock gating for VCN block 645 */ 646 static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 647 { 648 return; 649 } 650 651 /** 652 * vcn_v5_0_0_start_dpg_mode - VCN start with dpg mode 653 * 654 * @adev: amdgpu_device pointer 655 * @inst_idx: instance number index 656 * @indirect: indirectly write sram 657 * 658 * Start VCN block with dpg mode 659 */ 660 static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 661 { 662 volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 663 struct amdgpu_ring *ring; 664 uint32_t tmp; 665 666 /* disable register anti-hang mechanism */ 667 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 668 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 669 670 /* enable dynamic power gating mode */ 671 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 672 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 673 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 674 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 675 676 if (indirect) 677 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 678 679 /* enable VCPU clock */ 680 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 681 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 682 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 683 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 684 685 /* disable master interrupt */ 686 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 687 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 688 689 /* setup regUVD_LMI_CTRL */ 690 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 691 UVD_LMI_CTRL__REQ_MODE_MASK | 692 UVD_LMI_CTRL__CRC_RESET_MASK | 693 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 694 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 695 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 696 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 697 0x00100000L); 698 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 699 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 700 701 vcn_v5_0_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 702 703 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 704 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 705 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 706 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 707 708 /* enable LMI MC and UMC channels */ 709 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 710 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 711 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 712 713 /* enable master interrupt */ 714 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 715 VCN, inst_idx, regUVD_MASTINT_EN), 716 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 717 718 if (indirect) 719 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 720 721 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 722 723 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 724 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 725 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 726 727 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 728 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 729 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 730 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 731 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 732 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 733 734 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 735 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 736 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 737 738 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 739 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 740 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 741 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 742 743 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 744 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 745 VCN_RB1_DB_CTRL__EN_MASK); 746 747 return 0; 748 } 749 750 /** 751 * vcn_v5_0_0_start - VCN start 752 * 753 * @adev: amdgpu_device pointer 754 * 755 * Start VCN block 756 */ 757 static int vcn_v5_0_0_start(struct amdgpu_device *adev) 758 { 759 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 760 struct amdgpu_ring *ring; 761 uint32_t tmp; 762 int i, j, k, r; 763 764 if (adev->pm.dpm_enabled) 765 amdgpu_dpm_enable_uvd(adev, true); 766 767 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 768 if (adev->vcn.harvest_config & (1 << i)) 769 continue; 770 771 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 772 773 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 774 r = vcn_v5_0_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 775 continue; 776 } 777 778 /* disable VCN power gating */ 779 vcn_v5_0_0_disable_static_power_gating(adev, i); 780 781 /* set VCN status busy */ 782 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 783 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 784 785 /* enable VCPU clock */ 786 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 787 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 788 789 /* disable master interrupt */ 790 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 791 ~UVD_MASTINT_EN__VCPU_EN_MASK); 792 793 /* enable LMI MC and UMC channels */ 794 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 795 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 796 797 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 798 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 799 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 800 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 801 802 /* setup regUVD_LMI_CTRL */ 803 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 804 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 805 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 806 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 807 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 808 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 809 810 vcn_v5_0_0_mc_resume(adev, i); 811 812 /* VCN global tiling registers */ 813 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 814 adev->gfx.config.gb_addr_config); 815 816 /* unblock VCPU register access */ 817 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 818 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 819 820 /* release VCPU reset to boot */ 821 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 822 ~UVD_VCPU_CNTL__BLK_RST_MASK); 823 824 for (j = 0; j < 10; ++j) { 825 uint32_t status; 826 827 for (k = 0; k < 100; ++k) { 828 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 829 if (status & 2) 830 break; 831 mdelay(10); 832 if (amdgpu_emu_mode == 1) 833 msleep(1); 834 } 835 836 if (amdgpu_emu_mode == 1) { 837 r = -1; 838 if (status & 2) { 839 r = 0; 840 break; 841 } 842 } else { 843 r = 0; 844 if (status & 2) 845 break; 846 847 dev_err(adev->dev, 848 "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 849 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 850 UVD_VCPU_CNTL__BLK_RST_MASK, 851 ~UVD_VCPU_CNTL__BLK_RST_MASK); 852 mdelay(10); 853 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 854 ~UVD_VCPU_CNTL__BLK_RST_MASK); 855 856 mdelay(10); 857 r = -1; 858 } 859 } 860 861 if (r) { 862 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 863 return r; 864 } 865 866 /* enable master interrupt */ 867 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 868 UVD_MASTINT_EN__VCPU_EN_MASK, 869 ~UVD_MASTINT_EN__VCPU_EN_MASK); 870 871 /* clear the busy bit of VCN_STATUS */ 872 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 873 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 874 875 ring = &adev->vcn.inst[i].ring_enc[0]; 876 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 877 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 878 VCN_RB1_DB_CTRL__EN_MASK); 879 880 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 881 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 882 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 883 884 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 885 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 886 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 887 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 888 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 889 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 890 891 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 892 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 893 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 894 895 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 896 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 897 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 898 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 899 } 900 901 return 0; 902 } 903 904 /** 905 * vcn_v5_0_0_stop_dpg_mode - VCN stop with dpg mode 906 * 907 * @adev: amdgpu_device pointer 908 * @inst_idx: instance number index 909 * 910 * Stop VCN block with dpg mode 911 */ 912 static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 913 { 914 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 915 uint32_t tmp; 916 917 vcn_v5_0_0_pause_dpg_mode(adev, inst_idx, &state); 918 919 /* Wait for power status to be 1 */ 920 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 921 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 922 923 /* wait for read ptr to be equal to write ptr */ 924 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 925 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 926 927 /* disable dynamic power gating mode */ 928 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 929 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 930 931 return; 932 } 933 934 /** 935 * vcn_v5_0_0_stop - VCN stop 936 * 937 * @adev: amdgpu_device pointer 938 * 939 * Stop VCN block 940 */ 941 static int vcn_v5_0_0_stop(struct amdgpu_device *adev) 942 { 943 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 944 uint32_t tmp; 945 int i, r = 0; 946 947 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 948 if (adev->vcn.harvest_config & (1 << i)) 949 continue; 950 951 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 952 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 953 954 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 955 vcn_v5_0_0_stop_dpg_mode(adev, i); 956 continue; 957 } 958 959 /* wait for vcn idle */ 960 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 961 if (r) 962 return r; 963 964 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 965 UVD_LMI_STATUS__READ_CLEAN_MASK | 966 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 967 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 968 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 969 if (r) 970 return r; 971 972 /* disable LMI UMC channel */ 973 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 974 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 975 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 976 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 977 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 978 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 979 if (r) 980 return r; 981 982 /* block VCPU register access */ 983 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 984 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 985 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 986 987 /* reset VCPU */ 988 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 989 UVD_VCPU_CNTL__BLK_RST_MASK, 990 ~UVD_VCPU_CNTL__BLK_RST_MASK); 991 992 /* disable VCPU clock */ 993 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 994 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 995 996 /* apply soft reset */ 997 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 998 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 999 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1000 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1001 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1002 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1003 1004 /* clear status */ 1005 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1006 1007 /* enable VCN power gating */ 1008 vcn_v5_0_0_enable_static_power_gating(adev, i); 1009 } 1010 1011 if (adev->pm.dpm_enabled) 1012 amdgpu_dpm_enable_uvd(adev, false); 1013 1014 return 0; 1015 } 1016 1017 /** 1018 * vcn_v5_0_0_pause_dpg_mode - VCN pause with dpg mode 1019 * 1020 * @adev: amdgpu_device pointer 1021 * @inst_idx: instance number index 1022 * @new_state: pause state 1023 * 1024 * Pause dpg mode for VCN block 1025 */ 1026 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1027 struct dpg_pause_state *new_state) 1028 { 1029 uint32_t reg_data = 0; 1030 int ret_code; 1031 1032 /* pause/unpause if state is changed */ 1033 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1034 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1035 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1036 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1037 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1038 1039 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1040 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1041 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1042 1043 if (!ret_code) { 1044 /* pause DPG */ 1045 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1046 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1047 1048 /* wait for ACK */ 1049 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1050 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1051 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1052 } 1053 } else { 1054 /* unpause dpg, no need to wait */ 1055 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1056 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1057 } 1058 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1059 } 1060 1061 return 0; 1062 } 1063 1064 /** 1065 * vcn_v5_0_0_unified_ring_get_rptr - get unified read pointer 1066 * 1067 * @ring: amdgpu_ring pointer 1068 * 1069 * Returns the current hardware unified read pointer 1070 */ 1071 static uint64_t vcn_v5_0_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1072 { 1073 struct amdgpu_device *adev = ring->adev; 1074 1075 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1076 DRM_ERROR("wrong ring id is identified in %s", __func__); 1077 1078 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1079 } 1080 1081 /** 1082 * vcn_v5_0_0_unified_ring_get_wptr - get unified write pointer 1083 * 1084 * @ring: amdgpu_ring pointer 1085 * 1086 * Returns the current hardware unified write pointer 1087 */ 1088 static uint64_t vcn_v5_0_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1089 { 1090 struct amdgpu_device *adev = ring->adev; 1091 1092 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1093 DRM_ERROR("wrong ring id is identified in %s", __func__); 1094 1095 if (ring->use_doorbell) 1096 return *ring->wptr_cpu_addr; 1097 else 1098 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1099 } 1100 1101 /** 1102 * vcn_v5_0_0_unified_ring_set_wptr - set enc write pointer 1103 * 1104 * @ring: amdgpu_ring pointer 1105 * 1106 * Commits the enc write pointer to the hardware 1107 */ 1108 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1109 { 1110 struct amdgpu_device *adev = ring->adev; 1111 1112 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1113 DRM_ERROR("wrong ring id is identified in %s", __func__); 1114 1115 if (ring->use_doorbell) { 1116 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1117 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1118 } else { 1119 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1120 } 1121 } 1122 1123 static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { 1124 .type = AMDGPU_RING_TYPE_VCN_ENC, 1125 .align_mask = 0x3f, 1126 .nop = VCN_ENC_CMD_NO_OP, 1127 .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, 1128 .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, 1129 .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, 1130 .emit_frame_size = 1131 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1132 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1133 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1134 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1135 1, /* vcn_v2_0_enc_ring_insert_end */ 1136 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1137 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1138 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1139 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1140 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1141 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1142 .insert_nop = amdgpu_ring_insert_nop, 1143 .insert_end = vcn_v2_0_enc_ring_insert_end, 1144 .pad_ib = amdgpu_ring_generic_pad_ib, 1145 .begin_use = amdgpu_vcn_ring_begin_use, 1146 .end_use = amdgpu_vcn_ring_end_use, 1147 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1148 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1149 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1150 }; 1151 1152 /** 1153 * vcn_v5_0_0_set_unified_ring_funcs - set unified ring functions 1154 * 1155 * @adev: amdgpu_device pointer 1156 * 1157 * Set unified ring functions 1158 */ 1159 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1160 { 1161 int i; 1162 1163 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1164 if (adev->vcn.harvest_config & (1 << i)) 1165 continue; 1166 1167 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs; 1168 adev->vcn.inst[i].ring_enc[0].me = i; 1169 } 1170 } 1171 1172 /** 1173 * vcn_v5_0_0_is_idle - check VCN block is idle 1174 * 1175 * @handle: amdgpu_device pointer 1176 * 1177 * Check whether VCN block is idle 1178 */ 1179 static bool vcn_v5_0_0_is_idle(void *handle) 1180 { 1181 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1182 int i, ret = 1; 1183 1184 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1185 if (adev->vcn.harvest_config & (1 << i)) 1186 continue; 1187 1188 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1189 } 1190 1191 return ret; 1192 } 1193 1194 /** 1195 * vcn_v5_0_0_wait_for_idle - wait for VCN block idle 1196 * 1197 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1198 * 1199 * Wait for VCN block idle 1200 */ 1201 static int vcn_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1202 { 1203 struct amdgpu_device *adev = ip_block->adev; 1204 int i, ret = 0; 1205 1206 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1207 if (adev->vcn.harvest_config & (1 << i)) 1208 continue; 1209 1210 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1211 UVD_STATUS__IDLE); 1212 if (ret) 1213 return ret; 1214 } 1215 1216 return ret; 1217 } 1218 1219 /** 1220 * vcn_v5_0_0_set_clockgating_state - set VCN block clockgating state 1221 * 1222 * @handle: amdgpu_device pointer 1223 * @state: clock gating state 1224 * 1225 * Set VCN block clockgating state 1226 */ 1227 static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) 1228 { 1229 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1230 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1231 int i; 1232 1233 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1234 if (adev->vcn.harvest_config & (1 << i)) 1235 continue; 1236 1237 if (enable) { 1238 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1239 return -EBUSY; 1240 vcn_v5_0_0_enable_clock_gating(adev, i); 1241 } else { 1242 vcn_v5_0_0_disable_clock_gating(adev, i); 1243 } 1244 } 1245 1246 return 0; 1247 } 1248 1249 /** 1250 * vcn_v5_0_0_set_powergating_state - set VCN block powergating state 1251 * 1252 * @handle: amdgpu_device pointer 1253 * @state: power gating state 1254 * 1255 * Set VCN block powergating state 1256 */ 1257 static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_state state) 1258 { 1259 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1260 int ret; 1261 1262 if (state == adev->vcn.cur_state) 1263 return 0; 1264 1265 if (state == AMD_PG_STATE_GATE) 1266 ret = vcn_v5_0_0_stop(adev); 1267 else 1268 ret = vcn_v5_0_0_start(adev); 1269 1270 if (!ret) 1271 adev->vcn.cur_state = state; 1272 1273 return ret; 1274 } 1275 1276 /** 1277 * vcn_v5_0_0_process_interrupt - process VCN block interrupt 1278 * 1279 * @adev: amdgpu_device pointer 1280 * @source: interrupt sources 1281 * @entry: interrupt entry from clients and sources 1282 * 1283 * Process VCN block interrupt 1284 */ 1285 static int vcn_v5_0_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1286 struct amdgpu_iv_entry *entry) 1287 { 1288 uint32_t ip_instance; 1289 1290 switch (entry->client_id) { 1291 case SOC15_IH_CLIENTID_VCN: 1292 ip_instance = 0; 1293 break; 1294 case SOC15_IH_CLIENTID_VCN1: 1295 ip_instance = 1; 1296 break; 1297 default: 1298 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1299 return 0; 1300 } 1301 1302 DRM_DEBUG("IH: VCN TRAP\n"); 1303 1304 switch (entry->src_id) { 1305 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1306 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1307 break; 1308 case VCN_4_0__SRCID_UVD_POISON: 1309 amdgpu_vcn_process_poison_irq(adev, source, entry); 1310 break; 1311 default: 1312 DRM_ERROR("Unhandled interrupt: %d %d\n", 1313 entry->src_id, entry->src_data[0]); 1314 break; 1315 } 1316 1317 return 0; 1318 } 1319 1320 static const struct amdgpu_irq_src_funcs vcn_v5_0_0_irq_funcs = { 1321 .process = vcn_v5_0_0_process_interrupt, 1322 }; 1323 1324 /** 1325 * vcn_v5_0_0_set_irq_funcs - set VCN block interrupt irq functions 1326 * 1327 * @adev: amdgpu_device pointer 1328 * 1329 * Set VCN block interrupt irq functions 1330 */ 1331 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) 1332 { 1333 int i; 1334 1335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1336 if (adev->vcn.harvest_config & (1 << i)) 1337 continue; 1338 1339 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1340 adev->vcn.inst[i].irq.funcs = &vcn_v5_0_0_irq_funcs; 1341 } 1342 } 1343 1344 static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1345 { 1346 struct amdgpu_device *adev = ip_block->adev; 1347 int i, j; 1348 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); 1349 uint32_t inst_off, is_powered; 1350 1351 if (!adev->vcn.ip_dump) 1352 return; 1353 1354 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1355 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1356 if (adev->vcn.harvest_config & (1 << i)) { 1357 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1358 continue; 1359 } 1360 1361 inst_off = i * reg_count; 1362 is_powered = (adev->vcn.ip_dump[inst_off] & 1363 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1364 1365 if (is_powered) { 1366 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1367 for (j = 0; j < reg_count; j++) 1368 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_5_0[j].reg_name, 1369 adev->vcn.ip_dump[inst_off + j]); 1370 } else { 1371 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1372 } 1373 } 1374 } 1375 1376 static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 1377 { 1378 struct amdgpu_device *adev = ip_block->adev; 1379 int i, j; 1380 bool is_powered; 1381 uint32_t inst_off; 1382 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); 1383 1384 if (!adev->vcn.ip_dump) 1385 return; 1386 1387 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1388 if (adev->vcn.harvest_config & (1 << i)) 1389 continue; 1390 1391 inst_off = i * reg_count; 1392 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1393 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); 1394 is_powered = (adev->vcn.ip_dump[inst_off] & 1395 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1396 1397 if (is_powered) 1398 for (j = 1; j < reg_count; j++) 1399 adev->vcn.ip_dump[inst_off + j] = 1400 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i)); 1401 } 1402 } 1403 1404 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { 1405 .name = "vcn_v5_0_0", 1406 .early_init = vcn_v5_0_0_early_init, 1407 .sw_init = vcn_v5_0_0_sw_init, 1408 .sw_fini = vcn_v5_0_0_sw_fini, 1409 .hw_init = vcn_v5_0_0_hw_init, 1410 .hw_fini = vcn_v5_0_0_hw_fini, 1411 .suspend = vcn_v5_0_0_suspend, 1412 .resume = vcn_v5_0_0_resume, 1413 .is_idle = vcn_v5_0_0_is_idle, 1414 .wait_for_idle = vcn_v5_0_0_wait_for_idle, 1415 .set_clockgating_state = vcn_v5_0_0_set_clockgating_state, 1416 .set_powergating_state = vcn_v5_0_0_set_powergating_state, 1417 .dump_ip_state = vcn_v5_0_dump_ip_state, 1418 .print_ip_state = vcn_v5_0_print_ip_state, 1419 }; 1420 1421 const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = { 1422 .type = AMD_IP_BLOCK_TYPE_VCN, 1423 .major = 5, 1424 .minor = 0, 1425 .rev = 0, 1426 .funcs = &vcn_v5_0_0_ip_funcs, 1427 }; 1428