1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_hw_ip.h" 31 #include "vcn_v2_0.h" 32 33 #include "vcn/vcn_5_0_0_offset.h" 34 #include "vcn/vcn_5_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 36 #include "vcn_v5_0_0.h" 37 38 #include <drm/drm_drv.h> 39 40 static int amdgpu_ih_clientid_vcns[] = { 41 SOC15_IH_CLIENTID_VCN, 42 SOC15_IH_CLIENTID_VCN1 43 }; 44 45 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev); 46 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev); 47 static int vcn_v5_0_0_set_powergating_state(void *handle, 48 enum amd_powergating_state state); 49 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev, 50 int inst_idx, struct dpg_pause_state *new_state); 51 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 52 53 /** 54 * vcn_v5_0_0_early_init - set function pointers and load microcode 55 * 56 * @handle: amdgpu_device pointer 57 * 58 * Set ring and irq function pointers 59 * Load microcode from filesystem 60 */ 61 static int vcn_v5_0_0_early_init(void *handle) 62 { 63 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 64 65 /* re-use enc ring as unified ring */ 66 adev->vcn.num_enc_rings = 1; 67 68 vcn_v5_0_0_set_unified_ring_funcs(adev); 69 vcn_v5_0_0_set_irq_funcs(adev); 70 71 return amdgpu_vcn_early_init(adev); 72 } 73 74 /** 75 * vcn_v5_0_0_sw_init - sw init for VCN block 76 * 77 * @handle: amdgpu_device pointer 78 * 79 * Load firmware and sw initialization 80 */ 81 static int vcn_v5_0_0_sw_init(void *handle) 82 { 83 struct amdgpu_ring *ring; 84 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 85 int i, r; 86 87 r = amdgpu_vcn_sw_init(adev); 88 if (r) 89 return r; 90 91 amdgpu_vcn_setup_ucode(adev); 92 93 r = amdgpu_vcn_resume(adev); 94 if (r) 95 return r; 96 97 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 98 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 99 100 if (adev->vcn.harvest_config & (1 << i)) 101 continue; 102 103 atomic_set(&adev->vcn.inst[i].sched_score, 0); 104 105 /* VCN UNIFIED TRAP */ 106 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 107 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 108 if (r) 109 return r; 110 111 /* VCN POISON TRAP */ 112 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 113 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 114 if (r) 115 return r; 116 117 ring = &adev->vcn.inst[i].ring_enc[0]; 118 ring->use_doorbell = true; 119 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 120 121 ring->vm_hub = AMDGPU_MMHUB0(0); 122 sprintf(ring->name, "vcn_unified_%d", i); 123 124 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 125 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 126 if (r) 127 return r; 128 129 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 130 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 131 fw_shared->sq.is_enabled = 1; 132 133 if (amdgpu_vcnfw_log) 134 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 135 } 136 137 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 138 adev->vcn.pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode; 139 140 return 0; 141 } 142 143 /** 144 * vcn_v5_0_0_sw_fini - sw fini for VCN block 145 * 146 * @handle: amdgpu_device pointer 147 * 148 * VCN suspend and free up sw allocation 149 */ 150 static int vcn_v5_0_0_sw_fini(void *handle) 151 { 152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 153 int i, r, idx; 154 155 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 156 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 157 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 158 159 if (adev->vcn.harvest_config & (1 << i)) 160 continue; 161 162 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 163 fw_shared->present_flag_0 = 0; 164 fw_shared->sq.is_enabled = 0; 165 } 166 167 drm_dev_exit(idx); 168 } 169 170 r = amdgpu_vcn_suspend(adev); 171 if (r) 172 return r; 173 174 r = amdgpu_vcn_sw_fini(adev); 175 176 return r; 177 } 178 179 /** 180 * vcn_v5_0_0_hw_init - start and test VCN block 181 * 182 * @handle: amdgpu_device pointer 183 * 184 * Initialize the hardware, boot up the VCPU and do some testing 185 */ 186 static int vcn_v5_0_0_hw_init(void *handle) 187 { 188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 189 struct amdgpu_ring *ring; 190 int i, r; 191 192 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 193 if (adev->vcn.harvest_config & (1 << i)) 194 continue; 195 196 ring = &adev->vcn.inst[i].ring_enc[0]; 197 198 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 199 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 200 201 r = amdgpu_ring_test_helper(ring); 202 if (r) 203 goto done; 204 } 205 206 return 0; 207 done: 208 if (!r) 209 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 210 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 211 212 return r; 213 } 214 215 /** 216 * vcn_v5_0_0_hw_fini - stop the hardware block 217 * 218 * @handle: amdgpu_device pointer 219 * 220 * Stop the VCN block, mark ring as not ready any more 221 */ 222 static int vcn_v5_0_0_hw_fini(void *handle) 223 { 224 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 225 int i; 226 227 cancel_delayed_work_sync(&adev->vcn.idle_work); 228 229 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 230 if (adev->vcn.harvest_config & (1 << i)) 231 continue; 232 if (!amdgpu_sriov_vf(adev)) { 233 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 234 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 235 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 236 vcn_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 237 } 238 } 239 } 240 241 return 0; 242 } 243 244 /** 245 * vcn_v5_0_0_suspend - suspend VCN block 246 * 247 * @handle: amdgpu_device pointer 248 * 249 * HW fini and suspend VCN block 250 */ 251 static int vcn_v5_0_0_suspend(void *handle) 252 { 253 int r; 254 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 255 256 r = vcn_v5_0_0_hw_fini(adev); 257 if (r) 258 return r; 259 260 r = amdgpu_vcn_suspend(adev); 261 262 return r; 263 } 264 265 /** 266 * vcn_v5_0_0_resume - resume VCN block 267 * 268 * @handle: amdgpu_device pointer 269 * 270 * Resume firmware and hw init VCN block 271 */ 272 static int vcn_v5_0_0_resume(void *handle) 273 { 274 int r; 275 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 276 277 r = amdgpu_vcn_resume(adev); 278 if (r) 279 return r; 280 281 r = vcn_v5_0_0_hw_init(adev); 282 283 return r; 284 } 285 286 /** 287 * vcn_v5_0_0_mc_resume - memory controller programming 288 * 289 * @adev: amdgpu_device pointer 290 * @inst: instance number 291 * 292 * Let the VCN memory controller know it's offsets 293 */ 294 static void vcn_v5_0_0_mc_resume(struct amdgpu_device *adev, int inst) 295 { 296 uint32_t offset, size; 297 const struct common_firmware_header *hdr; 298 299 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data; 300 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 301 302 /* cache window 0: fw */ 303 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 304 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 305 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 306 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 307 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 308 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 309 offset = 0; 310 } else { 311 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 312 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 313 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 314 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 315 offset = size; 316 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 317 } 318 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 319 320 /* cache window 1: stack */ 321 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 322 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 323 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 324 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 325 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 326 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 327 328 /* cache window 2: context */ 329 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 330 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 331 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 332 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 333 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 334 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 335 336 /* non-cache window */ 337 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 338 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 339 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 340 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 341 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 342 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 343 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); 344 } 345 346 /** 347 * vcn_v5_0_0_mc_resume_dpg_mode - memory controller programming for dpg mode 348 * 349 * @adev: amdgpu_device pointer 350 * @inst_idx: instance number index 351 * @indirect: indirectly write sram 352 * 353 * Let the VCN memory controller know it's offsets with dpg mode 354 */ 355 static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 356 { 357 uint32_t offset, size; 358 const struct common_firmware_header *hdr; 359 360 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data; 361 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 362 363 /* cache window 0: fw */ 364 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 365 if (!indirect) { 366 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 367 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 368 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 369 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 370 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 371 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 372 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 373 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 374 } else { 375 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 376 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 377 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 378 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 379 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 380 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 381 } 382 offset = 0; 383 } else { 384 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 385 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 386 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 387 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 388 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 389 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 390 offset = size; 391 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 392 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 393 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 394 } 395 396 if (!indirect) 397 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 398 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 399 else 400 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 401 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 402 403 /* cache window 1: stack */ 404 if (!indirect) { 405 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 406 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 407 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 408 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 409 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 410 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 411 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 412 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 413 } else { 414 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 415 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 416 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 417 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 418 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 419 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 420 } 421 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 422 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 423 424 /* cache window 2: context */ 425 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 426 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 427 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 428 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 429 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 430 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 431 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 432 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 433 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 434 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 435 436 /* non-cache window */ 437 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 438 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 439 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 440 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 441 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 442 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 443 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 444 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 445 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 446 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 447 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); 448 449 /* VCN global tiling registers */ 450 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 451 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 452 453 return; 454 } 455 456 /** 457 * vcn_v5_0_0_disable_static_power_gating - disable VCN static power gating 458 * 459 * @adev: amdgpu_device pointer 460 * @inst: instance number 461 * 462 * Disable static power gating for VCN block 463 */ 464 static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 465 { 466 uint32_t data = 0; 467 468 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 469 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 470 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 471 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 472 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 473 474 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 475 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 476 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 477 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 478 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 479 480 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 481 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 482 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 483 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 484 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 485 486 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 487 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 488 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 489 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 490 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 491 } else { 492 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 493 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 494 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 495 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 496 497 data = 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 498 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 499 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 500 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 501 502 data = 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 503 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 504 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 505 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 506 507 data = 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 508 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 509 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 510 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 511 } 512 513 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 514 data &= ~0x103; 515 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 516 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 517 UVD_POWER_STATUS__UVD_PG_EN_MASK; 518 519 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 520 return; 521 } 522 523 /** 524 * vcn_v5_0_0_enable_static_power_gating - enable VCN static power gating 525 * 526 * @adev: amdgpu_device pointer 527 * @inst: instance number 528 * 529 * Enable static power gating for VCN block 530 */ 531 static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 532 { 533 uint32_t data; 534 535 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 536 /* Before power off, this indicator has to be turned on */ 537 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 538 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 539 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 540 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 541 542 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 543 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 544 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 545 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 546 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 547 548 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 549 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 550 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 551 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 552 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 553 554 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 555 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 556 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 557 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 558 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 559 560 data = 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 561 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 562 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 563 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 564 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 565 } 566 return; 567 } 568 569 /** 570 * vcn_v5_0_0_disable_clock_gating - disable VCN clock gating 571 * 572 * @adev: amdgpu_device pointer 573 * @inst: instance number 574 * 575 * Disable clock gating for VCN block 576 */ 577 static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 578 { 579 return; 580 } 581 582 #if 0 583 /** 584 * vcn_v5_0_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 585 * 586 * @adev: amdgpu_device pointer 587 * @sram_sel: sram select 588 * @inst_idx: instance number index 589 * @indirect: indirectly write sram 590 * 591 * Disable clock gating for VCN block with dpg mode 592 */ 593 static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 594 int inst_idx, uint8_t indirect) 595 { 596 return; 597 } 598 #endif 599 600 /** 601 * vcn_v5_0_0_enable_clock_gating - enable VCN clock gating 602 * 603 * @adev: amdgpu_device pointer 604 * @inst: instance number 605 * 606 * Enable clock gating for VCN block 607 */ 608 static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 609 { 610 return; 611 } 612 613 /** 614 * vcn_v5_0_0_start_dpg_mode - VCN start with dpg mode 615 * 616 * @adev: amdgpu_device pointer 617 * @inst_idx: instance number index 618 * @indirect: indirectly write sram 619 * 620 * Start VCN block with dpg mode 621 */ 622 static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 623 { 624 volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 625 struct amdgpu_ring *ring; 626 uint32_t tmp; 627 628 /* disable register anti-hang mechanism */ 629 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 630 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 631 632 /* enable dynamic power gating mode */ 633 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 634 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 635 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 636 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 637 638 if (indirect) 639 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 640 641 /* enable VCPU clock */ 642 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 643 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 644 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 645 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 646 647 /* disable master interrupt */ 648 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 649 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 650 651 /* setup regUVD_LMI_CTRL */ 652 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 653 UVD_LMI_CTRL__REQ_MODE_MASK | 654 UVD_LMI_CTRL__CRC_RESET_MASK | 655 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 656 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 657 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 658 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 659 0x00100000L); 660 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 661 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 662 663 vcn_v5_0_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 664 665 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 666 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 667 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 668 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 669 670 /* enable LMI MC and UMC channels */ 671 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 672 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 673 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 674 675 /* enable master interrupt */ 676 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 677 VCN, inst_idx, regUVD_MASTINT_EN), 678 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 679 680 if (indirect) 681 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 682 683 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 684 685 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 686 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 687 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 688 689 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 690 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 691 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 692 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 693 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 694 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 695 696 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 697 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 698 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 699 700 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 701 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 702 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 703 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 704 705 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 706 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 707 VCN_RB1_DB_CTRL__EN_MASK); 708 709 return 0; 710 } 711 712 /** 713 * vcn_v5_0_0_start - VCN start 714 * 715 * @adev: amdgpu_device pointer 716 * 717 * Start VCN block 718 */ 719 static int vcn_v5_0_0_start(struct amdgpu_device *adev) 720 { 721 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 722 struct amdgpu_ring *ring; 723 uint32_t tmp; 724 int i, j, k, r; 725 726 if (adev->pm.dpm_enabled) 727 amdgpu_dpm_enable_uvd(adev, true); 728 729 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 730 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 731 732 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 733 r = vcn_v5_0_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 734 continue; 735 } 736 737 /* disable VCN power gating */ 738 vcn_v5_0_0_disable_static_power_gating(adev, i); 739 740 /* set VCN status busy */ 741 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 742 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 743 744 /* enable VCPU clock */ 745 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 746 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 747 748 /* disable master interrupt */ 749 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 750 ~UVD_MASTINT_EN__VCPU_EN_MASK); 751 752 /* enable LMI MC and UMC channels */ 753 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 754 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 755 756 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 757 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 758 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 759 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 760 761 /* setup regUVD_LMI_CTRL */ 762 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 763 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 764 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 765 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 766 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 767 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 768 769 vcn_v5_0_0_mc_resume(adev, i); 770 771 /* VCN global tiling registers */ 772 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 773 adev->gfx.config.gb_addr_config); 774 775 /* unblock VCPU register access */ 776 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 777 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 778 779 /* release VCPU reset to boot */ 780 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 781 ~UVD_VCPU_CNTL__BLK_RST_MASK); 782 783 for (j = 0; j < 10; ++j) { 784 uint32_t status; 785 786 for (k = 0; k < 100; ++k) { 787 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 788 if (status & 2) 789 break; 790 mdelay(10); 791 if (amdgpu_emu_mode == 1) 792 msleep(1); 793 } 794 795 if (amdgpu_emu_mode == 1) { 796 r = -1; 797 if (status & 2) { 798 r = 0; 799 break; 800 } 801 } else { 802 r = 0; 803 if (status & 2) 804 break; 805 806 dev_err(adev->dev, 807 "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 808 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 809 UVD_VCPU_CNTL__BLK_RST_MASK, 810 ~UVD_VCPU_CNTL__BLK_RST_MASK); 811 mdelay(10); 812 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 813 ~UVD_VCPU_CNTL__BLK_RST_MASK); 814 815 mdelay(10); 816 r = -1; 817 } 818 } 819 820 if (r) { 821 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 822 return r; 823 } 824 825 /* enable master interrupt */ 826 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 827 UVD_MASTINT_EN__VCPU_EN_MASK, 828 ~UVD_MASTINT_EN__VCPU_EN_MASK); 829 830 /* clear the busy bit of VCN_STATUS */ 831 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 832 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 833 834 ring = &adev->vcn.inst[i].ring_enc[0]; 835 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 836 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 837 VCN_RB1_DB_CTRL__EN_MASK); 838 839 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 840 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 841 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 842 843 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 844 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 845 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 846 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 847 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 848 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 849 850 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 851 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 852 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 853 854 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 855 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 856 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 857 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 858 } 859 860 return 0; 861 } 862 863 /** 864 * vcn_v5_0_0_stop_dpg_mode - VCN stop with dpg mode 865 * 866 * @adev: amdgpu_device pointer 867 * @inst_idx: instance number index 868 * 869 * Stop VCN block with dpg mode 870 */ 871 static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 872 { 873 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 874 uint32_t tmp; 875 876 vcn_v5_0_0_pause_dpg_mode(adev, inst_idx, &state); 877 878 /* Wait for power status to be 1 */ 879 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 880 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 881 882 /* wait for read ptr to be equal to write ptr */ 883 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 884 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 885 886 /* disable dynamic power gating mode */ 887 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 888 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 889 890 return; 891 } 892 893 /** 894 * vcn_v5_0_0_stop - VCN stop 895 * 896 * @adev: amdgpu_device pointer 897 * 898 * Stop VCN block 899 */ 900 static int vcn_v5_0_0_stop(struct amdgpu_device *adev) 901 { 902 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 903 uint32_t tmp; 904 int i, r = 0; 905 906 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 907 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 908 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 909 910 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 911 vcn_v5_0_0_stop_dpg_mode(adev, i); 912 continue; 913 } 914 915 /* wait for vcn idle */ 916 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 917 if (r) 918 return r; 919 920 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 921 UVD_LMI_STATUS__READ_CLEAN_MASK | 922 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 923 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 924 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 925 if (r) 926 return r; 927 928 /* disable LMI UMC channel */ 929 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 930 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 931 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 932 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 933 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 934 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 935 if (r) 936 return r; 937 938 /* block VCPU register access */ 939 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 940 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 941 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 942 943 /* reset VCPU */ 944 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 945 UVD_VCPU_CNTL__BLK_RST_MASK, 946 ~UVD_VCPU_CNTL__BLK_RST_MASK); 947 948 /* disable VCPU clock */ 949 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 950 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 951 952 /* apply soft reset */ 953 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 954 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 955 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 956 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 957 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 958 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 959 960 /* clear status */ 961 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 962 963 /* enable VCN power gating */ 964 vcn_v5_0_0_enable_static_power_gating(adev, i); 965 } 966 967 if (adev->pm.dpm_enabled) 968 amdgpu_dpm_enable_uvd(adev, false); 969 970 return 0; 971 } 972 973 /** 974 * vcn_v5_0_0_pause_dpg_mode - VCN pause with dpg mode 975 * 976 * @adev: amdgpu_device pointer 977 * @inst_idx: instance number index 978 * @new_state: pause state 979 * 980 * Pause dpg mode for VCN block 981 */ 982 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 983 struct dpg_pause_state *new_state) 984 { 985 uint32_t reg_data = 0; 986 int ret_code; 987 988 /* pause/unpause if state is changed */ 989 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 990 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 991 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 992 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 993 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 994 995 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 996 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 997 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 998 999 if (!ret_code) { 1000 /* pause DPG */ 1001 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1002 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1003 1004 /* wait for ACK */ 1005 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1006 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1007 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1008 } 1009 } else { 1010 /* unpause dpg, no need to wait */ 1011 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1012 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1013 } 1014 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1015 } 1016 1017 return 0; 1018 } 1019 1020 /** 1021 * vcn_v5_0_0_unified_ring_get_rptr - get unified read pointer 1022 * 1023 * @ring: amdgpu_ring pointer 1024 * 1025 * Returns the current hardware unified read pointer 1026 */ 1027 static uint64_t vcn_v5_0_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1028 { 1029 struct amdgpu_device *adev = ring->adev; 1030 1031 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1032 DRM_ERROR("wrong ring id is identified in %s", __func__); 1033 1034 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1035 } 1036 1037 /** 1038 * vcn_v5_0_0_unified_ring_get_wptr - get unified write pointer 1039 * 1040 * @ring: amdgpu_ring pointer 1041 * 1042 * Returns the current hardware unified write pointer 1043 */ 1044 static uint64_t vcn_v5_0_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1045 { 1046 struct amdgpu_device *adev = ring->adev; 1047 1048 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1049 DRM_ERROR("wrong ring id is identified in %s", __func__); 1050 1051 if (ring->use_doorbell) 1052 return *ring->wptr_cpu_addr; 1053 else 1054 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1055 } 1056 1057 /** 1058 * vcn_v5_0_0_unified_ring_set_wptr - set enc write pointer 1059 * 1060 * @ring: amdgpu_ring pointer 1061 * 1062 * Commits the enc write pointer to the hardware 1063 */ 1064 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1065 { 1066 struct amdgpu_device *adev = ring->adev; 1067 1068 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1069 DRM_ERROR("wrong ring id is identified in %s", __func__); 1070 1071 if (ring->use_doorbell) { 1072 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1073 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1074 } else { 1075 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1076 } 1077 } 1078 1079 static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { 1080 .type = AMDGPU_RING_TYPE_VCN_ENC, 1081 .align_mask = 0x3f, 1082 .nop = VCN_ENC_CMD_NO_OP, 1083 .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, 1084 .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, 1085 .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, 1086 .emit_frame_size = 1087 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1088 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1089 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1090 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1091 1, /* vcn_v2_0_enc_ring_insert_end */ 1092 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1093 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1094 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1095 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1096 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1097 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1098 .insert_nop = amdgpu_ring_insert_nop, 1099 .insert_end = vcn_v2_0_enc_ring_insert_end, 1100 .pad_ib = amdgpu_ring_generic_pad_ib, 1101 .begin_use = amdgpu_vcn_ring_begin_use, 1102 .end_use = amdgpu_vcn_ring_end_use, 1103 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1104 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1105 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1106 }; 1107 1108 /** 1109 * vcn_v5_0_0_set_unified_ring_funcs - set unified ring functions 1110 * 1111 * @adev: amdgpu_device pointer 1112 * 1113 * Set unified ring functions 1114 */ 1115 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1116 { 1117 int i; 1118 1119 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1120 if (adev->vcn.harvest_config & (1 << i)) 1121 continue; 1122 1123 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs; 1124 adev->vcn.inst[i].ring_enc[0].me = i; 1125 1126 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); 1127 } 1128 } 1129 1130 /** 1131 * vcn_v5_0_0_is_idle - check VCN block is idle 1132 * 1133 * @handle: amdgpu_device pointer 1134 * 1135 * Check whether VCN block is idle 1136 */ 1137 static bool vcn_v5_0_0_is_idle(void *handle) 1138 { 1139 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1140 int i, ret = 1; 1141 1142 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1143 if (adev->vcn.harvest_config & (1 << i)) 1144 continue; 1145 1146 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1147 } 1148 1149 return ret; 1150 } 1151 1152 /** 1153 * vcn_v5_0_0_wait_for_idle - wait for VCN block idle 1154 * 1155 * @handle: amdgpu_device pointer 1156 * 1157 * Wait for VCN block idle 1158 */ 1159 static int vcn_v5_0_0_wait_for_idle(void *handle) 1160 { 1161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1162 int i, ret = 0; 1163 1164 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1165 if (adev->vcn.harvest_config & (1 << i)) 1166 continue; 1167 1168 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1169 UVD_STATUS__IDLE); 1170 if (ret) 1171 return ret; 1172 } 1173 1174 return ret; 1175 } 1176 1177 /** 1178 * vcn_v5_0_0_set_clockgating_state - set VCN block clockgating state 1179 * 1180 * @handle: amdgpu_device pointer 1181 * @state: clock gating state 1182 * 1183 * Set VCN block clockgating state 1184 */ 1185 static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) 1186 { 1187 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1188 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1189 int i; 1190 1191 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1192 if (adev->vcn.harvest_config & (1 << i)) 1193 continue; 1194 1195 if (enable) { 1196 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1197 return -EBUSY; 1198 vcn_v5_0_0_enable_clock_gating(adev, i); 1199 } else { 1200 vcn_v5_0_0_disable_clock_gating(adev, i); 1201 } 1202 } 1203 1204 return 0; 1205 } 1206 1207 /** 1208 * vcn_v5_0_0_set_powergating_state - set VCN block powergating state 1209 * 1210 * @handle: amdgpu_device pointer 1211 * @state: power gating state 1212 * 1213 * Set VCN block powergating state 1214 */ 1215 static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_state state) 1216 { 1217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1218 int ret; 1219 1220 if (state == adev->vcn.cur_state) 1221 return 0; 1222 1223 if (state == AMD_PG_STATE_GATE) 1224 ret = vcn_v5_0_0_stop(adev); 1225 else 1226 ret = vcn_v5_0_0_start(adev); 1227 1228 if (!ret) 1229 adev->vcn.cur_state = state; 1230 1231 return ret; 1232 } 1233 1234 /** 1235 * vcn_v5_0_0_process_interrupt - process VCN block interrupt 1236 * 1237 * @adev: amdgpu_device pointer 1238 * @source: interrupt sources 1239 * @entry: interrupt entry from clients and sources 1240 * 1241 * Process VCN block interrupt 1242 */ 1243 static int vcn_v5_0_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1244 struct amdgpu_iv_entry *entry) 1245 { 1246 uint32_t ip_instance; 1247 1248 switch (entry->client_id) { 1249 case SOC15_IH_CLIENTID_VCN: 1250 ip_instance = 0; 1251 break; 1252 case SOC15_IH_CLIENTID_VCN1: 1253 ip_instance = 1; 1254 break; 1255 default: 1256 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1257 return 0; 1258 } 1259 1260 DRM_DEBUG("IH: VCN TRAP\n"); 1261 1262 switch (entry->src_id) { 1263 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1264 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1265 break; 1266 case VCN_4_0__SRCID_UVD_POISON: 1267 amdgpu_vcn_process_poison_irq(adev, source, entry); 1268 break; 1269 default: 1270 DRM_ERROR("Unhandled interrupt: %d %d\n", 1271 entry->src_id, entry->src_data[0]); 1272 break; 1273 } 1274 1275 return 0; 1276 } 1277 1278 static const struct amdgpu_irq_src_funcs vcn_v5_0_0_irq_funcs = { 1279 .process = vcn_v5_0_0_process_interrupt, 1280 }; 1281 1282 /** 1283 * vcn_v5_0_0_set_irq_funcs - set VCN block interrupt irq functions 1284 * 1285 * @adev: amdgpu_device pointer 1286 * 1287 * Set VCN block interrupt irq functions 1288 */ 1289 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) 1290 { 1291 int i; 1292 1293 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1294 if (adev->vcn.harvest_config & (1 << i)) 1295 continue; 1296 1297 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1298 adev->vcn.inst[i].irq.funcs = &vcn_v5_0_0_irq_funcs; 1299 } 1300 } 1301 1302 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { 1303 .name = "vcn_v5_0_0", 1304 .early_init = vcn_v5_0_0_early_init, 1305 .late_init = NULL, 1306 .sw_init = vcn_v5_0_0_sw_init, 1307 .sw_fini = vcn_v5_0_0_sw_fini, 1308 .hw_init = vcn_v5_0_0_hw_init, 1309 .hw_fini = vcn_v5_0_0_hw_fini, 1310 .suspend = vcn_v5_0_0_suspend, 1311 .resume = vcn_v5_0_0_resume, 1312 .is_idle = vcn_v5_0_0_is_idle, 1313 .wait_for_idle = vcn_v5_0_0_wait_for_idle, 1314 .check_soft_reset = NULL, 1315 .pre_soft_reset = NULL, 1316 .soft_reset = NULL, 1317 .post_soft_reset = NULL, 1318 .set_clockgating_state = vcn_v5_0_0_set_clockgating_state, 1319 .set_powergating_state = vcn_v5_0_0_set_powergating_state, 1320 .dump_ip_state = NULL, 1321 .print_ip_state = NULL, 1322 }; 1323 1324 const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = { 1325 .type = AMD_IP_BLOCK_TYPE_VCN, 1326 .major = 5, 1327 .minor = 0, 1328 .rev = 0, 1329 .funcs = &vcn_v5_0_0_ip_funcs, 1330 }; 1331