1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_hw_ip.h" 31 #include "vcn_v2_0.h" 32 33 #include "vcn/vcn_5_0_0_offset.h" 34 #include "vcn/vcn_5_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" 36 #include "vcn_v5_0_0.h" 37 38 #include <drm/drm_drv.h> 39 40 static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0[] = { 41 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 42 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 43 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 44 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 45 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 46 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 47 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 48 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 72 }; 73 74 static int amdgpu_ih_clientid_vcns[] = { 75 SOC15_IH_CLIENTID_VCN, 76 SOC15_IH_CLIENTID_VCN1 77 }; 78 79 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev); 80 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev); 81 static int vcn_v5_0_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 82 enum amd_powergating_state state); 83 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 84 struct dpg_pause_state *new_state); 85 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 86 87 /** 88 * vcn_v5_0_0_early_init - set function pointers and load microcode 89 * 90 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 91 * 92 * Set ring and irq function pointers 93 * Load microcode from filesystem 94 */ 95 static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block) 96 { 97 struct amdgpu_device *adev = ip_block->adev; 98 int i, r; 99 100 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 101 /* re-use enc ring as unified ring */ 102 adev->vcn.inst[i].num_enc_rings = 1; 103 104 vcn_v5_0_0_set_unified_ring_funcs(adev); 105 vcn_v5_0_0_set_irq_funcs(adev); 106 107 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 108 adev->vcn.inst[i].set_pg_state = vcn_v5_0_0_set_pg_state; 109 110 r = amdgpu_vcn_early_init(adev, i); 111 if (r) 112 return r; 113 } 114 115 return 0; 116 } 117 118 /** 119 * vcn_v5_0_0_sw_init - sw init for VCN block 120 * 121 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 122 * 123 * Load firmware and sw initialization 124 */ 125 static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) 126 { 127 struct amdgpu_ring *ring; 128 struct amdgpu_device *adev = ip_block->adev; 129 int i, r; 130 131 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 132 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 133 134 if (adev->vcn.harvest_config & (1 << i)) 135 continue; 136 137 r = amdgpu_vcn_sw_init(adev, i); 138 if (r) 139 return r; 140 141 amdgpu_vcn_setup_ucode(adev, i); 142 143 r = amdgpu_vcn_resume(adev, i); 144 if (r) 145 return r; 146 147 atomic_set(&adev->vcn.inst[i].sched_score, 0); 148 149 /* VCN UNIFIED TRAP */ 150 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 151 VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 152 if (r) 153 return r; 154 155 /* VCN POISON TRAP */ 156 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 157 VCN_5_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 158 if (r) 159 return r; 160 161 ring = &adev->vcn.inst[i].ring_enc[0]; 162 ring->use_doorbell = true; 163 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 164 165 ring->vm_hub = AMDGPU_MMHUB0(0); 166 sprintf(ring->name, "vcn_unified_%d", i); 167 168 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 169 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 170 if (r) 171 return r; 172 173 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 174 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 175 fw_shared->sq.is_enabled = 1; 176 177 if (amdgpu_vcnfw_log) 178 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 179 180 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 181 adev->vcn.inst[i].pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode; 182 } 183 184 adev->vcn.supported_reset = 185 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 186 if (!amdgpu_sriov_vf(adev)) 187 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 188 189 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0, ARRAY_SIZE(vcn_reg_list_5_0)); 190 if (r) 191 return r; 192 193 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 194 if (r) 195 return r; 196 197 return 0; 198 } 199 200 /** 201 * vcn_v5_0_0_sw_fini - sw fini for VCN block 202 * 203 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 204 * 205 * VCN suspend and free up sw allocation 206 */ 207 static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block) 208 { 209 struct amdgpu_device *adev = ip_block->adev; 210 int i, r, idx; 211 212 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 213 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 214 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 215 216 if (adev->vcn.harvest_config & (1 << i)) 217 continue; 218 219 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 220 fw_shared->present_flag_0 = 0; 221 fw_shared->sq.is_enabled = 0; 222 } 223 224 drm_dev_exit(idx); 225 } 226 227 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 228 r = amdgpu_vcn_suspend(adev, i); 229 if (r) 230 return r; 231 } 232 233 amdgpu_vcn_sysfs_reset_mask_fini(adev); 234 235 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 236 r = amdgpu_vcn_sw_fini(adev, i); 237 if (r) 238 return r; 239 } 240 241 return 0; 242 } 243 244 /** 245 * vcn_v5_0_0_hw_init - start and test VCN block 246 * 247 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 248 * 249 * Initialize the hardware, boot up the VCPU and do some testing 250 */ 251 static int vcn_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block) 252 { 253 struct amdgpu_device *adev = ip_block->adev; 254 struct amdgpu_ring *ring; 255 int i, r; 256 257 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 258 if (adev->vcn.harvest_config & (1 << i)) 259 continue; 260 261 ring = &adev->vcn.inst[i].ring_enc[0]; 262 263 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 264 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 265 266 r = amdgpu_ring_test_helper(ring); 267 if (r) 268 return r; 269 } 270 271 return 0; 272 } 273 274 /** 275 * vcn_v5_0_0_hw_fini - stop the hardware block 276 * 277 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 278 * 279 * Stop the VCN block, mark ring as not ready any more 280 */ 281 static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block) 282 { 283 struct amdgpu_device *adev = ip_block->adev; 284 int i; 285 286 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 287 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 288 289 if (adev->vcn.harvest_config & (1 << i)) 290 continue; 291 292 cancel_delayed_work_sync(&vinst->idle_work); 293 294 if (!amdgpu_sriov_vf(adev)) { 295 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 296 (vinst->cur_state != AMD_PG_STATE_GATE && 297 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 298 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 299 } 300 } 301 } 302 303 return 0; 304 } 305 306 /** 307 * vcn_v5_0_0_suspend - suspend VCN block 308 * 309 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 310 * 311 * HW fini and suspend VCN block 312 */ 313 static int vcn_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) 314 { 315 struct amdgpu_device *adev = ip_block->adev; 316 int r, i; 317 318 r = vcn_v5_0_0_hw_fini(ip_block); 319 if (r) 320 return r; 321 322 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 323 r = amdgpu_vcn_suspend(ip_block->adev, i); 324 if (r) 325 return r; 326 } 327 328 return r; 329 } 330 331 /** 332 * vcn_v5_0_0_resume - resume VCN block 333 * 334 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 335 * 336 * Resume firmware and hw init VCN block 337 */ 338 static int vcn_v5_0_0_resume(struct amdgpu_ip_block *ip_block) 339 { 340 struct amdgpu_device *adev = ip_block->adev; 341 int r, i; 342 343 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 344 r = amdgpu_vcn_resume(ip_block->adev, i); 345 if (r) 346 return r; 347 } 348 349 r = vcn_v5_0_0_hw_init(ip_block); 350 351 return r; 352 } 353 354 /** 355 * vcn_v5_0_0_mc_resume - memory controller programming 356 * 357 * @vinst: VCN instance 358 * 359 * Let the VCN memory controller know it's offsets 360 */ 361 static void vcn_v5_0_0_mc_resume(struct amdgpu_vcn_inst *vinst) 362 { 363 struct amdgpu_device *adev = vinst->adev; 364 int inst = vinst->inst; 365 uint32_t offset, size; 366 const struct common_firmware_header *hdr; 367 368 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 369 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 370 371 /* cache window 0: fw */ 372 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 373 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 374 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 375 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 376 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 377 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 378 offset = 0; 379 } else { 380 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 381 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 382 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 383 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 384 offset = size; 385 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 386 } 387 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 388 389 /* cache window 1: stack */ 390 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 391 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 392 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 393 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 394 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 395 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 396 397 /* cache window 2: context */ 398 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 399 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 400 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 401 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 402 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 403 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 404 405 /* non-cache window */ 406 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 407 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 408 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 409 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 410 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 411 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 412 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); 413 } 414 415 /** 416 * vcn_v5_0_0_mc_resume_dpg_mode - memory controller programming for dpg mode 417 * 418 * @vinst: VCN instance 419 * @indirect: indirectly write sram 420 * 421 * Let the VCN memory controller know it's offsets with dpg mode 422 */ 423 static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 424 bool indirect) 425 { 426 struct amdgpu_device *adev = vinst->adev; 427 int inst_idx = vinst->inst; 428 uint32_t offset, size; 429 const struct common_firmware_header *hdr; 430 431 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 432 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 433 434 /* cache window 0: fw */ 435 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 436 if (!indirect) { 437 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 438 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 439 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 440 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 441 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 442 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 443 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 444 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 445 } else { 446 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 447 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 448 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 449 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 450 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 451 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 452 } 453 offset = 0; 454 } else { 455 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 456 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 457 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 458 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 459 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 460 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 461 offset = size; 462 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 463 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 464 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 465 } 466 467 if (!indirect) 468 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 469 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 470 else 471 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 472 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 473 474 /* cache window 1: stack */ 475 if (!indirect) { 476 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 477 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 478 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 479 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 480 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 481 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 482 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 483 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 484 } else { 485 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 486 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 487 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 488 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 489 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 490 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 491 } 492 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 493 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 494 495 /* cache window 2: context */ 496 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 497 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 498 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 499 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 500 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 501 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 502 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 503 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 504 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 505 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 506 507 /* non-cache window */ 508 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 509 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 510 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 511 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 512 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 513 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 514 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 515 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 516 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 517 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 518 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); 519 520 /* VCN global tiling registers */ 521 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 522 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 523 adev->gfx.config.gb_addr_config, 0, indirect); 524 525 return; 526 } 527 528 /** 529 * vcn_v5_0_0_disable_static_power_gating - disable VCN static power gating 530 * 531 * @vinst: VCN instance 532 * 533 * Disable static power gating for VCN block 534 */ 535 static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 536 { 537 struct amdgpu_device *adev = vinst->adev; 538 int inst = vinst->inst; 539 uint32_t data = 0; 540 541 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 542 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 543 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 544 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 545 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 546 547 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 548 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 549 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 550 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 551 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 552 553 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 554 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 555 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 556 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 557 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 558 559 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 560 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 561 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 562 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 563 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 564 } else { 565 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 566 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 567 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 568 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 569 570 data = 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 571 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 572 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 573 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 574 575 data = 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 576 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 577 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 578 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 579 580 data = 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 581 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 582 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 583 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 584 } 585 586 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 587 data &= ~0x103; 588 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 589 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 590 UVD_POWER_STATUS__UVD_PG_EN_MASK; 591 592 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 593 return; 594 } 595 596 /** 597 * vcn_v5_0_0_enable_static_power_gating - enable VCN static power gating 598 * 599 * @vinst: VCN instance 600 * 601 * Enable static power gating for VCN block 602 */ 603 static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 604 { 605 struct amdgpu_device *adev = vinst->adev; 606 int inst = vinst->inst; 607 uint32_t data; 608 609 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 610 /* Before power off, this indicator has to be turned on */ 611 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 612 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 613 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 614 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 615 616 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 617 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 618 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 619 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 620 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 621 622 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 623 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 624 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 625 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 626 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 627 628 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 629 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 630 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 631 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 632 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 633 634 data = 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 635 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 636 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 637 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 638 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 639 } 640 return; 641 } 642 643 /** 644 * vcn_v5_0_0_disable_clock_gating - disable VCN clock gating 645 * 646 * @vinst: VCN instance 647 * 648 * Disable clock gating for VCN block 649 */ 650 static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 651 { 652 return; 653 } 654 655 #if 0 656 /** 657 * vcn_v5_0_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 658 * 659 * @vinst: VCN instance 660 * @sram_sel: sram select 661 * @indirect: indirectly write sram 662 * 663 * Disable clock gating for VCN block with dpg mode 664 */ 665 static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 666 uint8_t sram_sel, 667 uint8_t indirect) 668 { 669 return; 670 } 671 #endif 672 673 /** 674 * vcn_v5_0_0_enable_clock_gating - enable VCN clock gating 675 * 676 * @vinst: VCN instance 677 * 678 * Enable clock gating for VCN block 679 */ 680 static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 681 { 682 return; 683 } 684 685 /** 686 * vcn_v5_0_0_start_dpg_mode - VCN start with dpg mode 687 * 688 * @vinst: VCN instance 689 * @indirect: indirectly write sram 690 * 691 * Start VCN block with dpg mode 692 */ 693 static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 694 bool indirect) 695 { 696 struct amdgpu_device *adev = vinst->adev; 697 int inst_idx = vinst->inst; 698 volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 699 struct amdgpu_ring *ring; 700 uint32_t tmp; 701 int ret; 702 703 /* disable register anti-hang mechanism */ 704 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 705 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 706 707 /* enable dynamic power gating mode */ 708 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 709 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 710 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 711 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 712 713 if (indirect) 714 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 715 716 /* enable VCPU clock */ 717 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 718 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 719 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 720 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 721 722 /* disable master interrupt */ 723 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 724 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 725 726 /* setup regUVD_LMI_CTRL */ 727 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 728 UVD_LMI_CTRL__REQ_MODE_MASK | 729 UVD_LMI_CTRL__CRC_RESET_MASK | 730 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 731 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 732 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 733 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 734 0x00100000L); 735 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 736 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 737 738 vcn_v5_0_0_mc_resume_dpg_mode(vinst, indirect); 739 740 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 741 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 742 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 743 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 744 745 /* enable LMI MC and UMC channels */ 746 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 747 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 748 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 749 750 /* enable master interrupt */ 751 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 752 VCN, inst_idx, regUVD_MASTINT_EN), 753 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 754 755 if (indirect) { 756 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 757 if (ret) { 758 dev_err(adev->dev, "%s: vcn sram load failed %d\n", __func__, ret); 759 return ret; 760 } 761 } 762 763 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 764 765 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 766 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 767 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 768 769 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 770 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 771 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 772 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 773 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 774 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 775 776 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 777 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 778 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 779 780 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 781 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 782 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 783 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 784 785 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 786 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 787 VCN_RB1_DB_CTRL__EN_MASK); 788 789 /* Keeping one read-back to ensure all register writes are done, 790 * otherwise it may introduce race conditions. 791 */ 792 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); 793 794 return 0; 795 } 796 797 /** 798 * vcn_v5_0_0_start - VCN start 799 * 800 * @vinst: VCN instance 801 * 802 * Start VCN block 803 */ 804 static int vcn_v5_0_0_start(struct amdgpu_vcn_inst *vinst) 805 { 806 struct amdgpu_device *adev = vinst->adev; 807 int i = vinst->inst; 808 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 809 struct amdgpu_ring *ring; 810 uint32_t tmp; 811 int j, k, r; 812 813 if (adev->vcn.harvest_config & (1 << i)) 814 return 0; 815 816 if (adev->pm.dpm_enabled) 817 amdgpu_dpm_enable_vcn(adev, true, i); 818 819 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 820 821 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 822 return vcn_v5_0_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 823 824 /* disable VCN power gating */ 825 vcn_v5_0_0_disable_static_power_gating(vinst); 826 827 /* set VCN status busy */ 828 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 829 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 830 831 /* enable VCPU clock */ 832 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 833 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 834 835 /* disable master interrupt */ 836 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 837 ~UVD_MASTINT_EN__VCPU_EN_MASK); 838 839 /* enable LMI MC and UMC channels */ 840 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 841 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 842 843 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 844 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 845 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 846 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 847 848 /* setup regUVD_LMI_CTRL */ 849 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 850 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 851 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 852 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 853 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 854 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 855 856 vcn_v5_0_0_mc_resume(vinst); 857 858 /* VCN global tiling registers */ 859 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 860 adev->gfx.config.gb_addr_config); 861 862 /* unblock VCPU register access */ 863 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 864 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 865 866 /* release VCPU reset to boot */ 867 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 868 ~UVD_VCPU_CNTL__BLK_RST_MASK); 869 870 for (j = 0; j < 10; ++j) { 871 uint32_t status; 872 873 for (k = 0; k < 100; ++k) { 874 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 875 if (status & 2) 876 break; 877 mdelay(10); 878 if (amdgpu_emu_mode == 1) 879 msleep(1); 880 } 881 882 if (amdgpu_emu_mode == 1) { 883 r = -1; 884 if (status & 2) { 885 r = 0; 886 break; 887 } 888 } else { 889 r = 0; 890 if (status & 2) 891 break; 892 893 dev_err(adev->dev, 894 "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 895 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 896 UVD_VCPU_CNTL__BLK_RST_MASK, 897 ~UVD_VCPU_CNTL__BLK_RST_MASK); 898 mdelay(10); 899 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 900 ~UVD_VCPU_CNTL__BLK_RST_MASK); 901 902 mdelay(10); 903 r = -1; 904 } 905 } 906 907 if (r) { 908 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 909 return r; 910 } 911 912 /* enable master interrupt */ 913 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 914 UVD_MASTINT_EN__VCPU_EN_MASK, 915 ~UVD_MASTINT_EN__VCPU_EN_MASK); 916 917 /* clear the busy bit of VCN_STATUS */ 918 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 919 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 920 921 ring = &adev->vcn.inst[i].ring_enc[0]; 922 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 923 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 924 VCN_RB1_DB_CTRL__EN_MASK); 925 926 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 927 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 928 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 929 930 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 931 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 932 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 933 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 934 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 935 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 936 937 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 938 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 939 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 940 941 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 942 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 943 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 944 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 945 946 /* Keeping one read-back to ensure all register writes are done, 947 * otherwise it may introduce race conditions. 948 */ 949 RREG32_SOC15(VCN, i, regUVD_STATUS); 950 951 return 0; 952 } 953 954 /** 955 * vcn_v5_0_0_stop_dpg_mode - VCN stop with dpg mode 956 * 957 * @vinst: VCN instance 958 * 959 * Stop VCN block with dpg mode 960 */ 961 static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 962 { 963 struct amdgpu_device *adev = vinst->adev; 964 int inst_idx = vinst->inst; 965 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 966 uint32_t tmp; 967 968 vcn_v5_0_0_pause_dpg_mode(vinst, &state); 969 970 /* Wait for power status to be 1 */ 971 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 972 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 973 974 /* wait for read ptr to be equal to write ptr */ 975 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 976 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 977 978 /* disable dynamic power gating mode */ 979 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 980 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 981 982 /* Keeping one read-back to ensure all register writes are done, 983 * otherwise it may introduce race conditions. 984 */ 985 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); 986 987 return; 988 } 989 990 /** 991 * vcn_v5_0_0_stop - VCN stop 992 * 993 * @vinst: VCN instance 994 * 995 * Stop VCN block 996 */ 997 static int vcn_v5_0_0_stop(struct amdgpu_vcn_inst *vinst) 998 { 999 struct amdgpu_device *adev = vinst->adev; 1000 int i = vinst->inst; 1001 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 1002 uint32_t tmp; 1003 int r = 0; 1004 1005 if (adev->vcn.harvest_config & (1 << i)) 1006 return 0; 1007 1008 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1009 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1010 1011 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1012 vcn_v5_0_0_stop_dpg_mode(vinst); 1013 r = 0; 1014 goto done; 1015 } 1016 1017 /* wait for vcn idle */ 1018 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1019 if (r) 1020 goto done; 1021 1022 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1023 UVD_LMI_STATUS__READ_CLEAN_MASK | 1024 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1025 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1026 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1027 if (r) 1028 goto done; 1029 1030 /* disable LMI UMC channel */ 1031 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1032 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1033 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1034 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1035 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1036 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1037 if (r) 1038 goto done; 1039 1040 /* block VCPU register access */ 1041 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1042 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1043 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1044 1045 /* reset VCPU */ 1046 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1047 UVD_VCPU_CNTL__BLK_RST_MASK, 1048 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1049 1050 /* disable VCPU clock */ 1051 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1052 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1053 1054 /* apply soft reset */ 1055 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1056 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1057 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1058 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1059 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1060 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1061 1062 /* clear status */ 1063 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1064 1065 /* enable VCN power gating */ 1066 vcn_v5_0_0_enable_static_power_gating(vinst); 1067 1068 /* Keeping one read-back to ensure all register writes are done, 1069 * otherwise it may introduce race conditions. 1070 */ 1071 RREG32_SOC15(VCN, i, regUVD_STATUS); 1072 1073 done: 1074 if (adev->pm.dpm_enabled) 1075 amdgpu_dpm_enable_vcn(adev, false, i); 1076 1077 return r; 1078 } 1079 1080 /** 1081 * vcn_v5_0_0_pause_dpg_mode - VCN pause with dpg mode 1082 * 1083 * @vinst: VCN instance 1084 * @new_state: pause state 1085 * 1086 * Pause dpg mode for VCN block 1087 */ 1088 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1089 struct dpg_pause_state *new_state) 1090 { 1091 struct amdgpu_device *adev = vinst->adev; 1092 int inst_idx = vinst->inst; 1093 uint32_t reg_data = 0; 1094 int ret_code; 1095 1096 /* pause/unpause if state is changed */ 1097 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1098 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1099 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1100 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1101 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1102 1103 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1104 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1105 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1106 1107 if (!ret_code) { 1108 /* pause DPG */ 1109 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1110 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1111 1112 /* wait for ACK */ 1113 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1114 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1115 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1116 } 1117 } else { 1118 /* unpause dpg, no need to wait */ 1119 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1120 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1121 } 1122 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1123 } 1124 1125 return 0; 1126 } 1127 1128 /** 1129 * vcn_v5_0_0_unified_ring_get_rptr - get unified read pointer 1130 * 1131 * @ring: amdgpu_ring pointer 1132 * 1133 * Returns the current hardware unified read pointer 1134 */ 1135 static uint64_t vcn_v5_0_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1136 { 1137 struct amdgpu_device *adev = ring->adev; 1138 1139 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1140 DRM_ERROR("wrong ring id is identified in %s", __func__); 1141 1142 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1143 } 1144 1145 /** 1146 * vcn_v5_0_0_unified_ring_get_wptr - get unified write pointer 1147 * 1148 * @ring: amdgpu_ring pointer 1149 * 1150 * Returns the current hardware unified write pointer 1151 */ 1152 static uint64_t vcn_v5_0_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1153 { 1154 struct amdgpu_device *adev = ring->adev; 1155 1156 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1157 DRM_ERROR("wrong ring id is identified in %s", __func__); 1158 1159 if (ring->use_doorbell) 1160 return *ring->wptr_cpu_addr; 1161 else 1162 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1163 } 1164 1165 /** 1166 * vcn_v5_0_0_unified_ring_set_wptr - set enc write pointer 1167 * 1168 * @ring: amdgpu_ring pointer 1169 * 1170 * Commits the enc write pointer to the hardware 1171 */ 1172 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1173 { 1174 struct amdgpu_device *adev = ring->adev; 1175 1176 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1177 DRM_ERROR("wrong ring id is identified in %s", __func__); 1178 1179 if (ring->use_doorbell) { 1180 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1181 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1182 } else { 1183 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1184 } 1185 } 1186 1187 static int vcn_v5_0_0_ring_reset(struct amdgpu_ring *ring, 1188 unsigned int vmid, 1189 struct amdgpu_fence *timedout_fence) 1190 { 1191 struct amdgpu_device *adev = ring->adev; 1192 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1193 int r; 1194 1195 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1196 r = vcn_v5_0_0_stop(vinst); 1197 if (r) 1198 return r; 1199 r = vcn_v5_0_0_start(vinst); 1200 if (r) 1201 return r; 1202 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1203 } 1204 1205 static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { 1206 .type = AMDGPU_RING_TYPE_VCN_ENC, 1207 .align_mask = 0x3f, 1208 .nop = VCN_ENC_CMD_NO_OP, 1209 .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, 1210 .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, 1211 .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, 1212 .emit_frame_size = 1213 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1214 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1215 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1216 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1217 1, /* vcn_v2_0_enc_ring_insert_end */ 1218 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1219 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1220 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1221 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1222 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1223 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1224 .insert_nop = amdgpu_ring_insert_nop, 1225 .insert_end = vcn_v2_0_enc_ring_insert_end, 1226 .pad_ib = amdgpu_ring_generic_pad_ib, 1227 .begin_use = amdgpu_vcn_ring_begin_use, 1228 .end_use = amdgpu_vcn_ring_end_use, 1229 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1230 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1231 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1232 .reset = vcn_v5_0_0_ring_reset, 1233 }; 1234 1235 /** 1236 * vcn_v5_0_0_set_unified_ring_funcs - set unified ring functions 1237 * 1238 * @adev: amdgpu_device pointer 1239 * 1240 * Set unified ring functions 1241 */ 1242 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1243 { 1244 int i; 1245 1246 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1247 if (adev->vcn.harvest_config & (1 << i)) 1248 continue; 1249 1250 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs; 1251 adev->vcn.inst[i].ring_enc[0].me = i; 1252 } 1253 } 1254 1255 /** 1256 * vcn_v5_0_0_is_idle - check VCN block is idle 1257 * 1258 * @ip_block: Pointer to the amdgpu_ip_block structure 1259 * 1260 * Check whether VCN block is idle 1261 */ 1262 static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block) 1263 { 1264 struct amdgpu_device *adev = ip_block->adev; 1265 int i, ret = 1; 1266 1267 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1268 if (adev->vcn.harvest_config & (1 << i)) 1269 continue; 1270 1271 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1272 } 1273 1274 return ret; 1275 } 1276 1277 /** 1278 * vcn_v5_0_0_wait_for_idle - wait for VCN block idle 1279 * 1280 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1281 * 1282 * Wait for VCN block idle 1283 */ 1284 static int vcn_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1285 { 1286 struct amdgpu_device *adev = ip_block->adev; 1287 int i, ret = 0; 1288 1289 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1290 if (adev->vcn.harvest_config & (1 << i)) 1291 continue; 1292 1293 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1294 UVD_STATUS__IDLE); 1295 if (ret) 1296 return ret; 1297 } 1298 1299 return ret; 1300 } 1301 1302 /** 1303 * vcn_v5_0_0_set_clockgating_state - set VCN block clockgating state 1304 * 1305 * @ip_block: amdgpu_ip_block pointer 1306 * @state: clock gating state 1307 * 1308 * Set VCN block clockgating state 1309 */ 1310 static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1311 enum amd_clockgating_state state) 1312 { 1313 struct amdgpu_device *adev = ip_block->adev; 1314 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1315 int i; 1316 1317 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1318 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1319 1320 if (adev->vcn.harvest_config & (1 << i)) 1321 continue; 1322 1323 if (enable) { 1324 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1325 return -EBUSY; 1326 vcn_v5_0_0_enable_clock_gating(vinst); 1327 } else { 1328 vcn_v5_0_0_disable_clock_gating(vinst); 1329 } 1330 } 1331 1332 return 0; 1333 } 1334 1335 static int vcn_v5_0_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 1336 enum amd_powergating_state state) 1337 { 1338 int ret = 0; 1339 1340 if (state == vinst->cur_state) 1341 return 0; 1342 1343 if (state == AMD_PG_STATE_GATE) 1344 ret = vcn_v5_0_0_stop(vinst); 1345 else 1346 ret = vcn_v5_0_0_start(vinst); 1347 1348 if (!ret) 1349 vinst->cur_state = state; 1350 1351 return ret; 1352 } 1353 1354 /** 1355 * vcn_v5_0_0_process_interrupt - process VCN block interrupt 1356 * 1357 * @adev: amdgpu_device pointer 1358 * @source: interrupt sources 1359 * @entry: interrupt entry from clients and sources 1360 * 1361 * Process VCN block interrupt 1362 */ 1363 static int vcn_v5_0_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1364 struct amdgpu_iv_entry *entry) 1365 { 1366 uint32_t ip_instance; 1367 1368 switch (entry->client_id) { 1369 case SOC15_IH_CLIENTID_VCN: 1370 ip_instance = 0; 1371 break; 1372 case SOC15_IH_CLIENTID_VCN1: 1373 ip_instance = 1; 1374 break; 1375 default: 1376 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1377 return 0; 1378 } 1379 1380 DRM_DEBUG("IH: VCN TRAP\n"); 1381 1382 switch (entry->src_id) { 1383 case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1384 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1385 break; 1386 case VCN_5_0__SRCID_UVD_POISON: 1387 amdgpu_vcn_process_poison_irq(adev, source, entry); 1388 break; 1389 default: 1390 DRM_ERROR("Unhandled interrupt: %d %d\n", 1391 entry->src_id, entry->src_data[0]); 1392 break; 1393 } 1394 1395 return 0; 1396 } 1397 1398 static const struct amdgpu_irq_src_funcs vcn_v5_0_0_irq_funcs = { 1399 .process = vcn_v5_0_0_process_interrupt, 1400 }; 1401 1402 /** 1403 * vcn_v5_0_0_set_irq_funcs - set VCN block interrupt irq functions 1404 * 1405 * @adev: amdgpu_device pointer 1406 * 1407 * Set VCN block interrupt irq functions 1408 */ 1409 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) 1410 { 1411 int i; 1412 1413 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1414 if (adev->vcn.harvest_config & (1 << i)) 1415 continue; 1416 1417 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 1418 adev->vcn.inst[i].irq.funcs = &vcn_v5_0_0_irq_funcs; 1419 } 1420 } 1421 1422 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { 1423 .name = "vcn_v5_0_0", 1424 .early_init = vcn_v5_0_0_early_init, 1425 .sw_init = vcn_v5_0_0_sw_init, 1426 .sw_fini = vcn_v5_0_0_sw_fini, 1427 .hw_init = vcn_v5_0_0_hw_init, 1428 .hw_fini = vcn_v5_0_0_hw_fini, 1429 .suspend = vcn_v5_0_0_suspend, 1430 .resume = vcn_v5_0_0_resume, 1431 .is_idle = vcn_v5_0_0_is_idle, 1432 .wait_for_idle = vcn_v5_0_0_wait_for_idle, 1433 .set_clockgating_state = vcn_v5_0_0_set_clockgating_state, 1434 .set_powergating_state = vcn_set_powergating_state, 1435 .dump_ip_state = amdgpu_vcn_dump_ip_state, 1436 .print_ip_state = amdgpu_vcn_print_ip_state, 1437 }; 1438 1439 const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = { 1440 .type = AMD_IP_BLOCK_TYPE_VCN, 1441 .major = 5, 1442 .minor = 0, 1443 .rev = 0, 1444 .funcs = &vcn_v5_0_0_ip_funcs, 1445 }; 1446