1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_hw_ip.h" 31 #include "vcn_v2_0.h" 32 33 #include "vcn/vcn_5_0_0_offset.h" 34 #include "vcn/vcn_5_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" 36 #include "vcn_v5_0_0.h" 37 38 #include <drm/drm_drv.h> 39 40 static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0[] = { 41 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 42 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 43 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 44 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 45 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 46 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 47 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 48 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 72 }; 73 74 static int amdgpu_ih_clientid_vcns[] = { 75 SOC15_IH_CLIENTID_VCN, 76 SOC15_IH_CLIENTID_VCN1 77 }; 78 79 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev); 80 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev); 81 static int vcn_v5_0_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 82 enum amd_powergating_state state); 83 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 84 struct dpg_pause_state *new_state); 85 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 86 87 /** 88 * vcn_v5_0_0_early_init - set function pointers and load microcode 89 * 90 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 91 * 92 * Set ring and irq function pointers 93 * Load microcode from filesystem 94 */ 95 static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block) 96 { 97 struct amdgpu_device *adev = ip_block->adev; 98 int i, r; 99 100 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 101 /* re-use enc ring as unified ring */ 102 adev->vcn.inst[i].num_enc_rings = 1; 103 104 vcn_v5_0_0_set_unified_ring_funcs(adev); 105 vcn_v5_0_0_set_irq_funcs(adev); 106 107 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 108 adev->vcn.inst[i].set_pg_state = vcn_v5_0_0_set_pg_state; 109 110 r = amdgpu_vcn_early_init(adev, i); 111 if (r) 112 return r; 113 } 114 115 return 0; 116 } 117 118 void vcn_v5_0_0_alloc_ip_dump(struct amdgpu_device *adev) 119 { 120 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); 121 uint32_t *ptr; 122 123 /* Allocate memory for VCN IP Dump buffer */ 124 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 125 if (!ptr) { 126 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 127 adev->vcn.ip_dump = NULL; 128 } else { 129 adev->vcn.ip_dump = ptr; 130 } 131 } 132 133 /** 134 * vcn_v5_0_0_sw_init - sw init for VCN block 135 * 136 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 137 * 138 * Load firmware and sw initialization 139 */ 140 static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) 141 { 142 struct amdgpu_ring *ring; 143 struct amdgpu_device *adev = ip_block->adev; 144 int i, r; 145 146 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 147 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 148 149 if (adev->vcn.harvest_config & (1 << i)) 150 continue; 151 152 r = amdgpu_vcn_sw_init(adev, i); 153 if (r) 154 return r; 155 156 amdgpu_vcn_setup_ucode(adev, i); 157 158 r = amdgpu_vcn_resume(adev, i); 159 if (r) 160 return r; 161 162 atomic_set(&adev->vcn.inst[i].sched_score, 0); 163 164 /* VCN UNIFIED TRAP */ 165 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 166 VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 167 if (r) 168 return r; 169 170 /* VCN POISON TRAP */ 171 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 172 VCN_5_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 173 if (r) 174 return r; 175 176 ring = &adev->vcn.inst[i].ring_enc[0]; 177 ring->use_doorbell = true; 178 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 179 180 ring->vm_hub = AMDGPU_MMHUB0(0); 181 sprintf(ring->name, "vcn_unified_%d", i); 182 183 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 184 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 185 if (r) 186 return r; 187 188 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 189 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 190 fw_shared->sq.is_enabled = 1; 191 192 if (amdgpu_vcnfw_log) 193 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 194 195 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 196 adev->vcn.inst[i].pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode; 197 } 198 199 adev->vcn.supported_reset = 200 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 201 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 202 203 vcn_v5_0_0_alloc_ip_dump(adev); 204 205 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 206 if (r) 207 return r; 208 209 return 0; 210 } 211 212 /** 213 * vcn_v5_0_0_sw_fini - sw fini for VCN block 214 * 215 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 216 * 217 * VCN suspend and free up sw allocation 218 */ 219 static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block) 220 { 221 struct amdgpu_device *adev = ip_block->adev; 222 int i, r, idx; 223 224 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 225 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 226 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 227 228 if (adev->vcn.harvest_config & (1 << i)) 229 continue; 230 231 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 232 fw_shared->present_flag_0 = 0; 233 fw_shared->sq.is_enabled = 0; 234 } 235 236 drm_dev_exit(idx); 237 } 238 239 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 240 r = amdgpu_vcn_suspend(adev, i); 241 if (r) 242 return r; 243 } 244 245 amdgpu_vcn_sysfs_reset_mask_fini(adev); 246 247 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 248 r = amdgpu_vcn_sw_fini(adev, i); 249 if (r) 250 return r; 251 } 252 253 kfree(adev->vcn.ip_dump); 254 255 return 0; 256 } 257 258 /** 259 * vcn_v5_0_0_hw_init - start and test VCN block 260 * 261 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 262 * 263 * Initialize the hardware, boot up the VCPU and do some testing 264 */ 265 static int vcn_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block) 266 { 267 struct amdgpu_device *adev = ip_block->adev; 268 struct amdgpu_ring *ring; 269 int i, r; 270 271 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 272 if (adev->vcn.harvest_config & (1 << i)) 273 continue; 274 275 ring = &adev->vcn.inst[i].ring_enc[0]; 276 277 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 278 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 279 280 r = amdgpu_ring_test_helper(ring); 281 if (r) 282 return r; 283 } 284 285 return 0; 286 } 287 288 /** 289 * vcn_v5_0_0_hw_fini - stop the hardware block 290 * 291 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 292 * 293 * Stop the VCN block, mark ring as not ready any more 294 */ 295 static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block) 296 { 297 struct amdgpu_device *adev = ip_block->adev; 298 int i; 299 300 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 301 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 302 303 if (adev->vcn.harvest_config & (1 << i)) 304 continue; 305 306 cancel_delayed_work_sync(&vinst->idle_work); 307 308 if (!amdgpu_sriov_vf(adev)) { 309 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 310 (vinst->cur_state != AMD_PG_STATE_GATE && 311 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 312 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 313 } 314 } 315 } 316 317 return 0; 318 } 319 320 /** 321 * vcn_v5_0_0_suspend - suspend VCN block 322 * 323 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 324 * 325 * HW fini and suspend VCN block 326 */ 327 static int vcn_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) 328 { 329 struct amdgpu_device *adev = ip_block->adev; 330 int r, i; 331 332 r = vcn_v5_0_0_hw_fini(ip_block); 333 if (r) 334 return r; 335 336 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 337 r = amdgpu_vcn_suspend(ip_block->adev, i); 338 if (r) 339 return r; 340 } 341 342 return r; 343 } 344 345 /** 346 * vcn_v5_0_0_resume - resume VCN block 347 * 348 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 349 * 350 * Resume firmware and hw init VCN block 351 */ 352 static int vcn_v5_0_0_resume(struct amdgpu_ip_block *ip_block) 353 { 354 struct amdgpu_device *adev = ip_block->adev; 355 int r, i; 356 357 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 358 r = amdgpu_vcn_resume(ip_block->adev, i); 359 if (r) 360 return r; 361 } 362 363 r = vcn_v5_0_0_hw_init(ip_block); 364 365 return r; 366 } 367 368 /** 369 * vcn_v5_0_0_mc_resume - memory controller programming 370 * 371 * @vinst: VCN instance 372 * 373 * Let the VCN memory controller know it's offsets 374 */ 375 static void vcn_v5_0_0_mc_resume(struct amdgpu_vcn_inst *vinst) 376 { 377 struct amdgpu_device *adev = vinst->adev; 378 int inst = vinst->inst; 379 uint32_t offset, size; 380 const struct common_firmware_header *hdr; 381 382 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 383 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 384 385 /* cache window 0: fw */ 386 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 387 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 388 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 389 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 390 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 391 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 392 offset = 0; 393 } else { 394 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 395 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 396 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 397 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 398 offset = size; 399 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 400 } 401 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 402 403 /* cache window 1: stack */ 404 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 405 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 406 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 407 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 408 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 409 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 410 411 /* cache window 2: context */ 412 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 413 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 414 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 415 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 416 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 417 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 418 419 /* non-cache window */ 420 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 421 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 422 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 423 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 424 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 425 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 426 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); 427 } 428 429 /** 430 * vcn_v5_0_0_mc_resume_dpg_mode - memory controller programming for dpg mode 431 * 432 * @vinst: VCN instance 433 * @indirect: indirectly write sram 434 * 435 * Let the VCN memory controller know it's offsets with dpg mode 436 */ 437 static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 438 bool indirect) 439 { 440 struct amdgpu_device *adev = vinst->adev; 441 int inst_idx = vinst->inst; 442 uint32_t offset, size; 443 const struct common_firmware_header *hdr; 444 445 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 446 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 447 448 /* cache window 0: fw */ 449 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 450 if (!indirect) { 451 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 452 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 453 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 454 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 455 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 456 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 457 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 458 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 459 } else { 460 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 461 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 462 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 463 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 464 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 465 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 466 } 467 offset = 0; 468 } else { 469 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 470 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 471 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 472 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 473 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 474 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 475 offset = size; 476 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 477 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 478 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 479 } 480 481 if (!indirect) 482 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 483 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 484 else 485 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 486 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 487 488 /* cache window 1: stack */ 489 if (!indirect) { 490 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 491 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 492 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 493 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 494 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 495 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 496 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 497 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 498 } else { 499 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 500 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 501 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 502 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 503 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 504 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 505 } 506 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 507 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 508 509 /* cache window 2: context */ 510 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 511 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 512 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 513 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 514 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 515 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 516 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 517 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 518 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 519 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 520 521 /* non-cache window */ 522 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 523 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 524 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 525 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 526 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 527 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 528 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 529 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 530 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 531 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 532 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); 533 534 /* VCN global tiling registers */ 535 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 536 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 537 adev->gfx.config.gb_addr_config, 0, indirect); 538 539 return; 540 } 541 542 /** 543 * vcn_v5_0_0_disable_static_power_gating - disable VCN static power gating 544 * 545 * @vinst: VCN instance 546 * 547 * Disable static power gating for VCN block 548 */ 549 static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 550 { 551 struct amdgpu_device *adev = vinst->adev; 552 int inst = vinst->inst; 553 uint32_t data = 0; 554 555 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 556 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 557 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 558 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 559 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 560 561 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 562 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 563 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 564 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 565 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 566 567 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 568 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 569 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 570 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 571 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 572 573 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 574 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 575 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 576 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 577 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 578 } else { 579 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 580 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 581 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 582 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 583 584 data = 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 585 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 586 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 587 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 588 589 data = 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 590 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 591 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 592 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 593 594 data = 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 595 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 596 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 597 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 598 } 599 600 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 601 data &= ~0x103; 602 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 603 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 604 UVD_POWER_STATUS__UVD_PG_EN_MASK; 605 606 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 607 return; 608 } 609 610 /** 611 * vcn_v5_0_0_enable_static_power_gating - enable VCN static power gating 612 * 613 * @vinst: VCN instance 614 * 615 * Enable static power gating for VCN block 616 */ 617 static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 618 { 619 struct amdgpu_device *adev = vinst->adev; 620 int inst = vinst->inst; 621 uint32_t data; 622 623 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 624 /* Before power off, this indicator has to be turned on */ 625 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 626 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 627 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 628 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 629 630 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 631 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 632 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 633 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 634 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 635 636 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 637 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 638 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 639 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 640 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 641 642 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 643 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 644 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 645 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 646 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 647 648 data = 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 649 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 650 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 651 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 652 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 653 } 654 return; 655 } 656 657 /** 658 * vcn_v5_0_0_disable_clock_gating - disable VCN clock gating 659 * 660 * @vinst: VCN instance 661 * 662 * Disable clock gating for VCN block 663 */ 664 static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 665 { 666 return; 667 } 668 669 #if 0 670 /** 671 * vcn_v5_0_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 672 * 673 * @vinst: VCN instance 674 * @sram_sel: sram select 675 * @indirect: indirectly write sram 676 * 677 * Disable clock gating for VCN block with dpg mode 678 */ 679 static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 680 uint8_t sram_sel, 681 uint8_t indirect) 682 { 683 return; 684 } 685 #endif 686 687 /** 688 * vcn_v5_0_0_enable_clock_gating - enable VCN clock gating 689 * 690 * @vinst: VCN instance 691 * 692 * Enable clock gating for VCN block 693 */ 694 static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 695 { 696 return; 697 } 698 699 /** 700 * vcn_v5_0_0_start_dpg_mode - VCN start with dpg mode 701 * 702 * @vinst: VCN instance 703 * @indirect: indirectly write sram 704 * 705 * Start VCN block with dpg mode 706 */ 707 static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 708 bool indirect) 709 { 710 struct amdgpu_device *adev = vinst->adev; 711 int inst_idx = vinst->inst; 712 volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 713 struct amdgpu_ring *ring; 714 uint32_t tmp; 715 716 /* disable register anti-hang mechanism */ 717 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 718 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 719 720 /* enable dynamic power gating mode */ 721 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 722 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 723 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 724 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 725 726 if (indirect) 727 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 728 729 /* enable VCPU clock */ 730 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 731 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 732 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 733 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 734 735 /* disable master interrupt */ 736 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 737 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 738 739 /* setup regUVD_LMI_CTRL */ 740 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 741 UVD_LMI_CTRL__REQ_MODE_MASK | 742 UVD_LMI_CTRL__CRC_RESET_MASK | 743 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 744 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 745 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 746 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 747 0x00100000L); 748 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 749 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 750 751 vcn_v5_0_0_mc_resume_dpg_mode(vinst, indirect); 752 753 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 754 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 755 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 756 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 757 758 /* enable LMI MC and UMC channels */ 759 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 760 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 761 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 762 763 /* enable master interrupt */ 764 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 765 VCN, inst_idx, regUVD_MASTINT_EN), 766 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 767 768 if (indirect) 769 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 770 771 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 772 773 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 774 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 775 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 776 777 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 778 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 779 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 780 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 781 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 782 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 783 784 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 785 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 786 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 787 788 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 789 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 790 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 791 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 792 793 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 794 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 795 VCN_RB1_DB_CTRL__EN_MASK); 796 797 /* Keeping one read-back to ensure all register writes are done, 798 * otherwise it may introduce race conditions. 799 */ 800 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); 801 802 return 0; 803 } 804 805 /** 806 * vcn_v5_0_0_start - VCN start 807 * 808 * @vinst: VCN instance 809 * 810 * Start VCN block 811 */ 812 static int vcn_v5_0_0_start(struct amdgpu_vcn_inst *vinst) 813 { 814 struct amdgpu_device *adev = vinst->adev; 815 int i = vinst->inst; 816 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 817 struct amdgpu_ring *ring; 818 uint32_t tmp; 819 int j, k, r; 820 821 if (adev->vcn.harvest_config & (1 << i)) 822 return 0; 823 824 if (adev->pm.dpm_enabled) 825 amdgpu_dpm_enable_vcn(adev, true, i); 826 827 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 828 829 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 830 return vcn_v5_0_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 831 832 /* disable VCN power gating */ 833 vcn_v5_0_0_disable_static_power_gating(vinst); 834 835 /* set VCN status busy */ 836 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 837 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 838 839 /* enable VCPU clock */ 840 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 841 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 842 843 /* disable master interrupt */ 844 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 845 ~UVD_MASTINT_EN__VCPU_EN_MASK); 846 847 /* enable LMI MC and UMC channels */ 848 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 849 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 850 851 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 852 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 853 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 854 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 855 856 /* setup regUVD_LMI_CTRL */ 857 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 858 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 859 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 860 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 861 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 862 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 863 864 vcn_v5_0_0_mc_resume(vinst); 865 866 /* VCN global tiling registers */ 867 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 868 adev->gfx.config.gb_addr_config); 869 870 /* unblock VCPU register access */ 871 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 872 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 873 874 /* release VCPU reset to boot */ 875 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 876 ~UVD_VCPU_CNTL__BLK_RST_MASK); 877 878 for (j = 0; j < 10; ++j) { 879 uint32_t status; 880 881 for (k = 0; k < 100; ++k) { 882 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 883 if (status & 2) 884 break; 885 mdelay(10); 886 if (amdgpu_emu_mode == 1) 887 msleep(1); 888 } 889 890 if (amdgpu_emu_mode == 1) { 891 r = -1; 892 if (status & 2) { 893 r = 0; 894 break; 895 } 896 } else { 897 r = 0; 898 if (status & 2) 899 break; 900 901 dev_err(adev->dev, 902 "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 903 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 904 UVD_VCPU_CNTL__BLK_RST_MASK, 905 ~UVD_VCPU_CNTL__BLK_RST_MASK); 906 mdelay(10); 907 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 908 ~UVD_VCPU_CNTL__BLK_RST_MASK); 909 910 mdelay(10); 911 r = -1; 912 } 913 } 914 915 if (r) { 916 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 917 return r; 918 } 919 920 /* enable master interrupt */ 921 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 922 UVD_MASTINT_EN__VCPU_EN_MASK, 923 ~UVD_MASTINT_EN__VCPU_EN_MASK); 924 925 /* clear the busy bit of VCN_STATUS */ 926 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 927 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 928 929 ring = &adev->vcn.inst[i].ring_enc[0]; 930 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 931 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 932 VCN_RB1_DB_CTRL__EN_MASK); 933 934 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 935 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 936 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 937 938 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 939 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 940 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 941 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 942 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 943 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 944 945 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 946 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 947 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 948 949 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 950 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 951 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 952 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 953 954 /* Keeping one read-back to ensure all register writes are done, 955 * otherwise it may introduce race conditions. 956 */ 957 RREG32_SOC15(VCN, i, regUVD_STATUS); 958 959 return 0; 960 } 961 962 /** 963 * vcn_v5_0_0_stop_dpg_mode - VCN stop with dpg mode 964 * 965 * @vinst: VCN instance 966 * 967 * Stop VCN block with dpg mode 968 */ 969 static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 970 { 971 struct amdgpu_device *adev = vinst->adev; 972 int inst_idx = vinst->inst; 973 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 974 uint32_t tmp; 975 976 vcn_v5_0_0_pause_dpg_mode(vinst, &state); 977 978 /* Wait for power status to be 1 */ 979 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 980 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 981 982 /* wait for read ptr to be equal to write ptr */ 983 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 984 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 985 986 /* disable dynamic power gating mode */ 987 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 988 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 989 990 /* Keeping one read-back to ensure all register writes are done, 991 * otherwise it may introduce race conditions. 992 */ 993 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); 994 995 return; 996 } 997 998 /** 999 * vcn_v5_0_0_stop - VCN stop 1000 * 1001 * @vinst: VCN instance 1002 * 1003 * Stop VCN block 1004 */ 1005 static int vcn_v5_0_0_stop(struct amdgpu_vcn_inst *vinst) 1006 { 1007 struct amdgpu_device *adev = vinst->adev; 1008 int i = vinst->inst; 1009 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 1010 uint32_t tmp; 1011 int r = 0; 1012 1013 if (adev->vcn.harvest_config & (1 << i)) 1014 return 0; 1015 1016 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1017 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1018 1019 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1020 vcn_v5_0_0_stop_dpg_mode(vinst); 1021 r = 0; 1022 goto done; 1023 } 1024 1025 /* wait for vcn idle */ 1026 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1027 if (r) 1028 goto done; 1029 1030 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1031 UVD_LMI_STATUS__READ_CLEAN_MASK | 1032 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1033 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1034 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1035 if (r) 1036 goto done; 1037 1038 /* disable LMI UMC channel */ 1039 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1040 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1041 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1042 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1043 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1044 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1045 if (r) 1046 goto done; 1047 1048 /* block VCPU register access */ 1049 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1050 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1051 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1052 1053 /* reset VCPU */ 1054 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1055 UVD_VCPU_CNTL__BLK_RST_MASK, 1056 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1057 1058 /* disable VCPU clock */ 1059 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1060 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1061 1062 /* apply soft reset */ 1063 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1064 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1065 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1066 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1067 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1068 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1069 1070 /* clear status */ 1071 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1072 1073 /* enable VCN power gating */ 1074 vcn_v5_0_0_enable_static_power_gating(vinst); 1075 1076 /* Keeping one read-back to ensure all register writes are done, 1077 * otherwise it may introduce race conditions. 1078 */ 1079 RREG32_SOC15(VCN, i, regUVD_STATUS); 1080 1081 done: 1082 if (adev->pm.dpm_enabled) 1083 amdgpu_dpm_enable_vcn(adev, false, i); 1084 1085 return r; 1086 } 1087 1088 /** 1089 * vcn_v5_0_0_pause_dpg_mode - VCN pause with dpg mode 1090 * 1091 * @vinst: VCN instance 1092 * @new_state: pause state 1093 * 1094 * Pause dpg mode for VCN block 1095 */ 1096 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1097 struct dpg_pause_state *new_state) 1098 { 1099 struct amdgpu_device *adev = vinst->adev; 1100 int inst_idx = vinst->inst; 1101 uint32_t reg_data = 0; 1102 int ret_code; 1103 1104 /* pause/unpause if state is changed */ 1105 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1106 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1107 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1108 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1109 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1110 1111 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1112 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1113 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1114 1115 if (!ret_code) { 1116 /* pause DPG */ 1117 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1118 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1119 1120 /* wait for ACK */ 1121 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1122 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1123 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1124 } 1125 } else { 1126 /* unpause dpg, no need to wait */ 1127 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1128 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1129 } 1130 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1131 } 1132 1133 return 0; 1134 } 1135 1136 /** 1137 * vcn_v5_0_0_unified_ring_get_rptr - get unified read pointer 1138 * 1139 * @ring: amdgpu_ring pointer 1140 * 1141 * Returns the current hardware unified read pointer 1142 */ 1143 static uint64_t vcn_v5_0_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1144 { 1145 struct amdgpu_device *adev = ring->adev; 1146 1147 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1148 DRM_ERROR("wrong ring id is identified in %s", __func__); 1149 1150 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1151 } 1152 1153 /** 1154 * vcn_v5_0_0_unified_ring_get_wptr - get unified write pointer 1155 * 1156 * @ring: amdgpu_ring pointer 1157 * 1158 * Returns the current hardware unified write pointer 1159 */ 1160 static uint64_t vcn_v5_0_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1161 { 1162 struct amdgpu_device *adev = ring->adev; 1163 1164 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1165 DRM_ERROR("wrong ring id is identified in %s", __func__); 1166 1167 if (ring->use_doorbell) 1168 return *ring->wptr_cpu_addr; 1169 else 1170 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1171 } 1172 1173 /** 1174 * vcn_v5_0_0_unified_ring_set_wptr - set enc write pointer 1175 * 1176 * @ring: amdgpu_ring pointer 1177 * 1178 * Commits the enc write pointer to the hardware 1179 */ 1180 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1181 { 1182 struct amdgpu_device *adev = ring->adev; 1183 1184 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1185 DRM_ERROR("wrong ring id is identified in %s", __func__); 1186 1187 if (ring->use_doorbell) { 1188 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1189 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1190 } else { 1191 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1192 } 1193 } 1194 1195 static int vcn_v5_0_0_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) 1196 { 1197 struct amdgpu_device *adev = ring->adev; 1198 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1199 1200 if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) 1201 return -EOPNOTSUPP; 1202 1203 vcn_v5_0_0_stop(vinst); 1204 vcn_v5_0_0_start(vinst); 1205 1206 return amdgpu_ring_test_helper(ring); 1207 } 1208 1209 static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { 1210 .type = AMDGPU_RING_TYPE_VCN_ENC, 1211 .align_mask = 0x3f, 1212 .nop = VCN_ENC_CMD_NO_OP, 1213 .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, 1214 .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, 1215 .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, 1216 .emit_frame_size = 1217 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1218 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1219 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1220 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1221 1, /* vcn_v2_0_enc_ring_insert_end */ 1222 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1223 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1224 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1225 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1226 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1227 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1228 .insert_nop = amdgpu_ring_insert_nop, 1229 .insert_end = vcn_v2_0_enc_ring_insert_end, 1230 .pad_ib = amdgpu_ring_generic_pad_ib, 1231 .begin_use = amdgpu_vcn_ring_begin_use, 1232 .end_use = amdgpu_vcn_ring_end_use, 1233 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1234 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1235 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1236 .reset = vcn_v5_0_0_ring_reset, 1237 }; 1238 1239 /** 1240 * vcn_v5_0_0_set_unified_ring_funcs - set unified ring functions 1241 * 1242 * @adev: amdgpu_device pointer 1243 * 1244 * Set unified ring functions 1245 */ 1246 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1247 { 1248 int i; 1249 1250 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1251 if (adev->vcn.harvest_config & (1 << i)) 1252 continue; 1253 1254 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs; 1255 adev->vcn.inst[i].ring_enc[0].me = i; 1256 } 1257 } 1258 1259 /** 1260 * vcn_v5_0_0_is_idle - check VCN block is idle 1261 * 1262 * @ip_block: Pointer to the amdgpu_ip_block structure 1263 * 1264 * Check whether VCN block is idle 1265 */ 1266 static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block) 1267 { 1268 struct amdgpu_device *adev = ip_block->adev; 1269 int i, ret = 1; 1270 1271 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1272 if (adev->vcn.harvest_config & (1 << i)) 1273 continue; 1274 1275 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1276 } 1277 1278 return ret; 1279 } 1280 1281 /** 1282 * vcn_v5_0_0_wait_for_idle - wait for VCN block idle 1283 * 1284 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1285 * 1286 * Wait for VCN block idle 1287 */ 1288 static int vcn_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1289 { 1290 struct amdgpu_device *adev = ip_block->adev; 1291 int i, ret = 0; 1292 1293 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1294 if (adev->vcn.harvest_config & (1 << i)) 1295 continue; 1296 1297 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1298 UVD_STATUS__IDLE); 1299 if (ret) 1300 return ret; 1301 } 1302 1303 return ret; 1304 } 1305 1306 /** 1307 * vcn_v5_0_0_set_clockgating_state - set VCN block clockgating state 1308 * 1309 * @ip_block: amdgpu_ip_block pointer 1310 * @state: clock gating state 1311 * 1312 * Set VCN block clockgating state 1313 */ 1314 static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1315 enum amd_clockgating_state state) 1316 { 1317 struct amdgpu_device *adev = ip_block->adev; 1318 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1319 int i; 1320 1321 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1322 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1323 1324 if (adev->vcn.harvest_config & (1 << i)) 1325 continue; 1326 1327 if (enable) { 1328 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1329 return -EBUSY; 1330 vcn_v5_0_0_enable_clock_gating(vinst); 1331 } else { 1332 vcn_v5_0_0_disable_clock_gating(vinst); 1333 } 1334 } 1335 1336 return 0; 1337 } 1338 1339 static int vcn_v5_0_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 1340 enum amd_powergating_state state) 1341 { 1342 int ret = 0; 1343 1344 if (state == vinst->cur_state) 1345 return 0; 1346 1347 if (state == AMD_PG_STATE_GATE) 1348 ret = vcn_v5_0_0_stop(vinst); 1349 else 1350 ret = vcn_v5_0_0_start(vinst); 1351 1352 if (!ret) 1353 vinst->cur_state = state; 1354 1355 return ret; 1356 } 1357 1358 /** 1359 * vcn_v5_0_0_process_interrupt - process VCN block interrupt 1360 * 1361 * @adev: amdgpu_device pointer 1362 * @source: interrupt sources 1363 * @entry: interrupt entry from clients and sources 1364 * 1365 * Process VCN block interrupt 1366 */ 1367 static int vcn_v5_0_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1368 struct amdgpu_iv_entry *entry) 1369 { 1370 uint32_t ip_instance; 1371 1372 switch (entry->client_id) { 1373 case SOC15_IH_CLIENTID_VCN: 1374 ip_instance = 0; 1375 break; 1376 case SOC15_IH_CLIENTID_VCN1: 1377 ip_instance = 1; 1378 break; 1379 default: 1380 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1381 return 0; 1382 } 1383 1384 DRM_DEBUG("IH: VCN TRAP\n"); 1385 1386 switch (entry->src_id) { 1387 case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1388 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1389 break; 1390 case VCN_5_0__SRCID_UVD_POISON: 1391 amdgpu_vcn_process_poison_irq(adev, source, entry); 1392 break; 1393 default: 1394 DRM_ERROR("Unhandled interrupt: %d %d\n", 1395 entry->src_id, entry->src_data[0]); 1396 break; 1397 } 1398 1399 return 0; 1400 } 1401 1402 static const struct amdgpu_irq_src_funcs vcn_v5_0_0_irq_funcs = { 1403 .process = vcn_v5_0_0_process_interrupt, 1404 }; 1405 1406 /** 1407 * vcn_v5_0_0_set_irq_funcs - set VCN block interrupt irq functions 1408 * 1409 * @adev: amdgpu_device pointer 1410 * 1411 * Set VCN block interrupt irq functions 1412 */ 1413 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) 1414 { 1415 int i; 1416 1417 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1418 if (adev->vcn.harvest_config & (1 << i)) 1419 continue; 1420 1421 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 1422 adev->vcn.inst[i].irq.funcs = &vcn_v5_0_0_irq_funcs; 1423 } 1424 } 1425 1426 void vcn_v5_0_0_print_ip_state(struct amdgpu_ip_block *ip_block, 1427 struct drm_printer *p) 1428 { 1429 struct amdgpu_device *adev = ip_block->adev; 1430 int i, j; 1431 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); 1432 uint32_t inst_off, is_powered; 1433 1434 if (!adev->vcn.ip_dump) 1435 return; 1436 1437 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1438 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1439 if (adev->vcn.harvest_config & (1 << i)) { 1440 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1441 continue; 1442 } 1443 1444 inst_off = i * reg_count; 1445 is_powered = (adev->vcn.ip_dump[inst_off] & 1446 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1447 1448 if (is_powered) { 1449 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1450 for (j = 0; j < reg_count; j++) 1451 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_5_0[j].reg_name, 1452 adev->vcn.ip_dump[inst_off + j]); 1453 } else { 1454 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1455 } 1456 } 1457 } 1458 1459 void vcn_v5_0_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 1460 { 1461 struct amdgpu_device *adev = ip_block->adev; 1462 int i, j; 1463 bool is_powered; 1464 uint32_t inst_off; 1465 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); 1466 1467 if (!adev->vcn.ip_dump) 1468 return; 1469 1470 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1471 if (adev->vcn.harvest_config & (1 << i)) 1472 continue; 1473 1474 inst_off = i * reg_count; 1475 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1476 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); 1477 is_powered = (adev->vcn.ip_dump[inst_off] & 1478 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1479 1480 if (is_powered) 1481 for (j = 1; j < reg_count; j++) 1482 adev->vcn.ip_dump[inst_off + j] = 1483 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i)); 1484 } 1485 } 1486 1487 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { 1488 .name = "vcn_v5_0_0", 1489 .early_init = vcn_v5_0_0_early_init, 1490 .sw_init = vcn_v5_0_0_sw_init, 1491 .sw_fini = vcn_v5_0_0_sw_fini, 1492 .hw_init = vcn_v5_0_0_hw_init, 1493 .hw_fini = vcn_v5_0_0_hw_fini, 1494 .suspend = vcn_v5_0_0_suspend, 1495 .resume = vcn_v5_0_0_resume, 1496 .is_idle = vcn_v5_0_0_is_idle, 1497 .wait_for_idle = vcn_v5_0_0_wait_for_idle, 1498 .set_clockgating_state = vcn_v5_0_0_set_clockgating_state, 1499 .set_powergating_state = vcn_set_powergating_state, 1500 .dump_ip_state = vcn_v5_0_0_dump_ip_state, 1501 .print_ip_state = vcn_v5_0_0_print_ip_state, 1502 }; 1503 1504 const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = { 1505 .type = AMD_IP_BLOCK_TYPE_VCN, 1506 .major = 5, 1507 .minor = 0, 1508 .rev = 0, 1509 .funcs = &vcn_v5_0_0_ip_funcs, 1510 }; 1511