1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_hw_ip.h" 31 #include "vcn_v2_0.h" 32 33 #include "vcn/vcn_5_0_0_offset.h" 34 #include "vcn/vcn_5_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 36 #include "vcn_v5_0_0.h" 37 38 #include <drm/drm_drv.h> 39 40 static int amdgpu_ih_clientid_vcns[] = { 41 SOC15_IH_CLIENTID_VCN, 42 SOC15_IH_CLIENTID_VCN1 43 }; 44 45 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev); 46 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev); 47 static int vcn_v5_0_0_set_powergating_state(void *handle, 48 enum amd_powergating_state state); 49 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev, 50 int inst_idx, struct dpg_pause_state *new_state); 51 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 52 53 /** 54 * vcn_v5_0_0_early_init - set function pointers and load microcode 55 * 56 * @handle: amdgpu_device pointer 57 * 58 * Set ring and irq function pointers 59 * Load microcode from filesystem 60 */ 61 static int vcn_v5_0_0_early_init(void *handle) 62 { 63 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 64 65 /* re-use enc ring as unified ring */ 66 adev->vcn.num_enc_rings = 1; 67 68 vcn_v5_0_0_set_unified_ring_funcs(adev); 69 vcn_v5_0_0_set_irq_funcs(adev); 70 71 return amdgpu_vcn_early_init(adev); 72 } 73 74 /** 75 * vcn_v5_0_0_sw_init - sw init for VCN block 76 * 77 * @handle: amdgpu_device pointer 78 * 79 * Load firmware and sw initialization 80 */ 81 static int vcn_v5_0_0_sw_init(void *handle) 82 { 83 struct amdgpu_ring *ring; 84 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 85 int i, r; 86 87 r = amdgpu_vcn_sw_init(adev); 88 if (r) 89 return r; 90 91 amdgpu_vcn_setup_ucode(adev); 92 93 r = amdgpu_vcn_resume(adev); 94 if (r) 95 return r; 96 97 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 98 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 99 100 if (adev->vcn.harvest_config & (1 << i)) 101 continue; 102 103 atomic_set(&adev->vcn.inst[i].sched_score, 0); 104 105 /* VCN UNIFIED TRAP */ 106 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 107 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 108 if (r) 109 return r; 110 111 /* VCN POISON TRAP */ 112 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 113 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 114 if (r) 115 return r; 116 117 ring = &adev->vcn.inst[i].ring_enc[0]; 118 ring->use_doorbell = true; 119 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 120 121 ring->vm_hub = AMDGPU_MMHUB0(0); 122 sprintf(ring->name, "vcn_unified_%d", i); 123 124 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 125 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 126 if (r) 127 return r; 128 129 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 130 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 131 fw_shared->sq.is_enabled = 1; 132 133 if (amdgpu_vcnfw_log) 134 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 135 } 136 137 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 138 adev->vcn.pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode; 139 140 return 0; 141 } 142 143 /** 144 * vcn_v5_0_0_sw_fini - sw fini for VCN block 145 * 146 * @handle: amdgpu_device pointer 147 * 148 * VCN suspend and free up sw allocation 149 */ 150 static int vcn_v5_0_0_sw_fini(void *handle) 151 { 152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 153 int i, r, idx; 154 155 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 156 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 157 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 158 159 if (adev->vcn.harvest_config & (1 << i)) 160 continue; 161 162 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 163 fw_shared->present_flag_0 = 0; 164 fw_shared->sq.is_enabled = 0; 165 } 166 167 drm_dev_exit(idx); 168 } 169 170 r = amdgpu_vcn_suspend(adev); 171 if (r) 172 return r; 173 174 r = amdgpu_vcn_sw_fini(adev); 175 176 return r; 177 } 178 179 /** 180 * vcn_v5_0_0_hw_init - start and test VCN block 181 * 182 * @handle: amdgpu_device pointer 183 * 184 * Initialize the hardware, boot up the VCPU and do some testing 185 */ 186 static int vcn_v5_0_0_hw_init(void *handle) 187 { 188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 189 struct amdgpu_ring *ring; 190 int i, r; 191 192 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 193 if (adev->vcn.harvest_config & (1 << i)) 194 continue; 195 196 ring = &adev->vcn.inst[i].ring_enc[0]; 197 198 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 199 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 200 201 r = amdgpu_ring_test_helper(ring); 202 if (r) 203 goto done; 204 } 205 206 return 0; 207 done: 208 if (!r) 209 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 210 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 211 212 return r; 213 } 214 215 /** 216 * vcn_v5_0_0_hw_fini - stop the hardware block 217 * 218 * @handle: amdgpu_device pointer 219 * 220 * Stop the VCN block, mark ring as not ready any more 221 */ 222 static int vcn_v5_0_0_hw_fini(void *handle) 223 { 224 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 225 int i; 226 227 cancel_delayed_work_sync(&adev->vcn.idle_work); 228 229 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 230 if (adev->vcn.harvest_config & (1 << i)) 231 continue; 232 233 amdgpu_irq_put(adev, &adev->vcn.inst[i].irq, 0); 234 } 235 236 return 0; 237 } 238 239 /** 240 * vcn_v5_0_0_suspend - suspend VCN block 241 * 242 * @handle: amdgpu_device pointer 243 * 244 * HW fini and suspend VCN block 245 */ 246 static int vcn_v5_0_0_suspend(void *handle) 247 { 248 int r; 249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 250 251 r = vcn_v5_0_0_hw_fini(adev); 252 if (r) 253 return r; 254 255 r = amdgpu_vcn_suspend(adev); 256 257 return r; 258 } 259 260 /** 261 * vcn_v5_0_0_resume - resume VCN block 262 * 263 * @handle: amdgpu_device pointer 264 * 265 * Resume firmware and hw init VCN block 266 */ 267 static int vcn_v5_0_0_resume(void *handle) 268 { 269 int r; 270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 271 272 r = amdgpu_vcn_resume(adev); 273 if (r) 274 return r; 275 276 r = vcn_v5_0_0_hw_init(adev); 277 278 return r; 279 } 280 281 /** 282 * vcn_v5_0_0_mc_resume - memory controller programming 283 * 284 * @adev: amdgpu_device pointer 285 * @inst: instance number 286 * 287 * Let the VCN memory controller know it's offsets 288 */ 289 static void vcn_v5_0_0_mc_resume(struct amdgpu_device *adev, int inst) 290 { 291 uint32_t offset, size; 292 const struct common_firmware_header *hdr; 293 294 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data; 295 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 296 297 /* cache window 0: fw */ 298 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 299 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 300 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 301 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 302 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 303 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 304 offset = 0; 305 } else { 306 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 307 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 308 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 309 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 310 offset = size; 311 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 312 } 313 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 314 315 /* cache window 1: stack */ 316 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 317 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 318 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 319 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 320 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 321 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 322 323 /* cache window 2: context */ 324 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 325 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 326 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 327 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 328 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 329 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 330 331 /* non-cache window */ 332 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 333 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 334 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 335 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 336 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 337 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 338 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); 339 } 340 341 /** 342 * vcn_v5_0_0_mc_resume_dpg_mode - memory controller programming for dpg mode 343 * 344 * @adev: amdgpu_device pointer 345 * @inst_idx: instance number index 346 * @indirect: indirectly write sram 347 * 348 * Let the VCN memory controller know it's offsets with dpg mode 349 */ 350 static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 351 { 352 uint32_t offset, size; 353 const struct common_firmware_header *hdr; 354 355 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data; 356 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 357 358 /* cache window 0: fw */ 359 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 360 if (!indirect) { 361 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 362 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 363 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 364 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 365 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 366 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 367 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 368 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 369 } else { 370 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 371 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 372 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 373 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 374 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 375 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 376 } 377 offset = 0; 378 } else { 379 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 380 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 381 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 382 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 383 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 384 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 385 offset = size; 386 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 387 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 388 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 389 } 390 391 if (!indirect) 392 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 393 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 394 else 395 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 396 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 397 398 /* cache window 1: stack */ 399 if (!indirect) { 400 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 401 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 402 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 403 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 404 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 405 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 406 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 407 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 408 } else { 409 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 410 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 411 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 412 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 413 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 414 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 415 } 416 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 417 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 418 419 /* cache window 2: context */ 420 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 421 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 422 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 423 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 424 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 425 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 426 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 427 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 428 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 429 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 430 431 /* non-cache window */ 432 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 433 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 434 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 435 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 436 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 437 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 438 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 439 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 440 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 441 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 442 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); 443 444 /* VCN global tiling registers */ 445 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 446 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 447 448 return; 449 } 450 451 /** 452 * vcn_v5_0_0_disable_static_power_gating - disable VCN static power gating 453 * 454 * @adev: amdgpu_device pointer 455 * @inst: instance number 456 * 457 * Disable static power gating for VCN block 458 */ 459 static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 460 { 461 uint32_t data = 0; 462 463 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 464 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 465 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 466 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 467 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 468 469 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 470 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 471 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 472 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 473 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 474 475 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 476 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 477 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 478 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 479 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 480 481 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 482 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 483 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 484 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 485 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 486 } else { 487 data = 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 488 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 489 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 490 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 491 492 data = 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 493 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 494 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 495 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 496 497 data = 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 498 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 499 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 500 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 501 502 data = 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 503 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 504 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 505 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 506 } 507 508 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 509 data &= ~0x103; 510 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 511 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 512 UVD_POWER_STATUS__UVD_PG_EN_MASK; 513 514 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 515 return; 516 } 517 518 /** 519 * vcn_v5_0_0_enable_static_power_gating - enable VCN static power gating 520 * 521 * @adev: amdgpu_device pointer 522 * @inst: instance number 523 * 524 * Enable static power gating for VCN block 525 */ 526 static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 527 { 528 uint32_t data; 529 530 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 531 /* Before power off, this indicator has to be turned on */ 532 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 533 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 534 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 535 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 536 537 data = 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT; 538 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 539 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 540 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 541 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 542 543 data = 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT; 544 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 545 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 546 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 547 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 548 549 data = 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT; 550 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 551 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 552 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 553 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 554 555 data = 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT; 556 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); 557 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 558 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 559 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 560 } 561 return; 562 } 563 564 /** 565 * vcn_v5_0_0_disable_clock_gating - disable VCN clock gating 566 * 567 * @adev: amdgpu_device pointer 568 * @inst: instance number 569 * 570 * Disable clock gating for VCN block 571 */ 572 static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 573 { 574 return; 575 } 576 577 #if 0 578 /** 579 * vcn_v5_0_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 580 * 581 * @adev: amdgpu_device pointer 582 * @sram_sel: sram select 583 * @inst_idx: instance number index 584 * @indirect: indirectly write sram 585 * 586 * Disable clock gating for VCN block with dpg mode 587 */ 588 static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 589 int inst_idx, uint8_t indirect) 590 { 591 return; 592 } 593 #endif 594 595 /** 596 * vcn_v5_0_0_enable_clock_gating - enable VCN clock gating 597 * 598 * @adev: amdgpu_device pointer 599 * @inst: instance number 600 * 601 * Enable clock gating for VCN block 602 */ 603 static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 604 { 605 return; 606 } 607 608 /** 609 * vcn_v5_0_0_start_dpg_mode - VCN start with dpg mode 610 * 611 * @adev: amdgpu_device pointer 612 * @inst_idx: instance number index 613 * @indirect: indirectly write sram 614 * 615 * Start VCN block with dpg mode 616 */ 617 static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 618 { 619 volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 620 struct amdgpu_ring *ring; 621 uint32_t tmp; 622 623 /* disable register anti-hang mechanism */ 624 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 625 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 626 627 /* enable dynamic power gating mode */ 628 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 629 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 630 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 631 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 632 633 if (indirect) 634 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 635 636 /* enable VCPU clock */ 637 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 638 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 639 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 640 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 641 642 /* disable master interrupt */ 643 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 644 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 645 646 /* setup regUVD_LMI_CTRL */ 647 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 648 UVD_LMI_CTRL__REQ_MODE_MASK | 649 UVD_LMI_CTRL__CRC_RESET_MASK | 650 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 651 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 652 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 653 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 654 0x00100000L); 655 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 656 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 657 658 vcn_v5_0_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 659 660 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 661 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 662 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 663 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 664 665 /* enable LMI MC and UMC channels */ 666 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 667 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 668 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 669 670 /* enable master interrupt */ 671 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 672 VCN, inst_idx, regUVD_MASTINT_EN), 673 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 674 675 if (indirect) 676 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 677 678 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 679 680 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 681 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 682 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 683 684 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 685 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 686 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 687 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 688 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 689 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 690 691 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 692 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 693 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 694 695 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 696 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 697 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 698 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 699 700 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 701 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 702 VCN_RB1_DB_CTRL__EN_MASK); 703 704 return 0; 705 } 706 707 /** 708 * vcn_v5_0_0_start - VCN start 709 * 710 * @adev: amdgpu_device pointer 711 * 712 * Start VCN block 713 */ 714 static int vcn_v5_0_0_start(struct amdgpu_device *adev) 715 { 716 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 717 struct amdgpu_ring *ring; 718 uint32_t tmp; 719 int i, j, k, r; 720 721 if (adev->pm.dpm_enabled) 722 amdgpu_dpm_enable_uvd(adev, true); 723 724 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 725 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 726 727 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 728 r = vcn_v5_0_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 729 continue; 730 } 731 732 /* disable VCN power gating */ 733 vcn_v5_0_0_disable_static_power_gating(adev, i); 734 735 /* set VCN status busy */ 736 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 737 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 738 739 /* enable VCPU clock */ 740 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 741 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 742 743 /* disable master interrupt */ 744 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 745 ~UVD_MASTINT_EN__VCPU_EN_MASK); 746 747 /* enable LMI MC and UMC channels */ 748 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 749 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 750 751 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 752 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 753 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 754 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 755 756 /* setup regUVD_LMI_CTRL */ 757 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 758 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 759 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 760 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 761 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 762 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 763 764 vcn_v5_0_0_mc_resume(adev, i); 765 766 /* VCN global tiling registers */ 767 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 768 adev->gfx.config.gb_addr_config); 769 770 /* unblock VCPU register access */ 771 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 772 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 773 774 /* release VCPU reset to boot */ 775 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 776 ~UVD_VCPU_CNTL__BLK_RST_MASK); 777 778 for (j = 0; j < 10; ++j) { 779 uint32_t status; 780 781 for (k = 0; k < 100; ++k) { 782 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 783 if (status & 2) 784 break; 785 mdelay(10); 786 if (amdgpu_emu_mode == 1) 787 msleep(1); 788 } 789 790 if (amdgpu_emu_mode == 1) { 791 r = -1; 792 if (status & 2) { 793 r = 0; 794 break; 795 } 796 } else { 797 r = 0; 798 if (status & 2) 799 break; 800 801 dev_err(adev->dev, 802 "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 803 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 804 UVD_VCPU_CNTL__BLK_RST_MASK, 805 ~UVD_VCPU_CNTL__BLK_RST_MASK); 806 mdelay(10); 807 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 808 ~UVD_VCPU_CNTL__BLK_RST_MASK); 809 810 mdelay(10); 811 r = -1; 812 } 813 } 814 815 if (r) { 816 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 817 return r; 818 } 819 820 /* enable master interrupt */ 821 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 822 UVD_MASTINT_EN__VCPU_EN_MASK, 823 ~UVD_MASTINT_EN__VCPU_EN_MASK); 824 825 /* clear the busy bit of VCN_STATUS */ 826 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 827 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 828 829 ring = &adev->vcn.inst[i].ring_enc[0]; 830 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 831 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 832 VCN_RB1_DB_CTRL__EN_MASK); 833 834 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 835 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 836 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 837 838 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 839 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 840 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 841 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 842 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 843 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 844 845 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 846 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 847 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 848 849 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 850 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 851 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 852 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 853 } 854 855 return 0; 856 } 857 858 /** 859 * vcn_v5_0_0_stop_dpg_mode - VCN stop with dpg mode 860 * 861 * @adev: amdgpu_device pointer 862 * @inst_idx: instance number index 863 * 864 * Stop VCN block with dpg mode 865 */ 866 static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 867 { 868 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 869 uint32_t tmp; 870 871 vcn_v5_0_0_pause_dpg_mode(adev, inst_idx, &state); 872 873 /* Wait for power status to be 1 */ 874 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 875 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 876 877 /* wait for read ptr to be equal to write ptr */ 878 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 879 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 880 881 /* disable dynamic power gating mode */ 882 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 883 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 884 885 return; 886 } 887 888 /** 889 * vcn_v5_0_0_stop - VCN stop 890 * 891 * @adev: amdgpu_device pointer 892 * 893 * Stop VCN block 894 */ 895 static int vcn_v5_0_0_stop(struct amdgpu_device *adev) 896 { 897 volatile struct amdgpu_vcn5_fw_shared *fw_shared; 898 uint32_t tmp; 899 int i, r = 0; 900 901 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 902 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 903 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 904 905 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 906 vcn_v5_0_0_stop_dpg_mode(adev, i); 907 continue; 908 } 909 910 /* wait for vcn idle */ 911 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 912 if (r) 913 return r; 914 915 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 916 UVD_LMI_STATUS__READ_CLEAN_MASK | 917 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 918 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 919 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 920 if (r) 921 return r; 922 923 /* disable LMI UMC channel */ 924 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 925 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 926 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 927 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 928 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 929 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 930 if (r) 931 return r; 932 933 /* block VCPU register access */ 934 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 935 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 936 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 937 938 /* reset VCPU */ 939 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 940 UVD_VCPU_CNTL__BLK_RST_MASK, 941 ~UVD_VCPU_CNTL__BLK_RST_MASK); 942 943 /* disable VCPU clock */ 944 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 945 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 946 947 /* apply soft reset */ 948 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 949 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 950 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 951 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 952 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 953 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 954 955 /* clear status */ 956 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 957 958 /* enable VCN power gating */ 959 vcn_v5_0_0_enable_static_power_gating(adev, i); 960 } 961 962 if (adev->pm.dpm_enabled) 963 amdgpu_dpm_enable_uvd(adev, false); 964 965 return 0; 966 } 967 968 /** 969 * vcn_v5_0_0_pause_dpg_mode - VCN pause with dpg mode 970 * 971 * @adev: amdgpu_device pointer 972 * @inst_idx: instance number index 973 * @new_state: pause state 974 * 975 * Pause dpg mode for VCN block 976 */ 977 static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 978 struct dpg_pause_state *new_state) 979 { 980 uint32_t reg_data = 0; 981 int ret_code; 982 983 /* pause/unpause if state is changed */ 984 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 985 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 986 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 987 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 988 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 989 990 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 991 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 992 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 993 994 if (!ret_code) { 995 /* pause DPG */ 996 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 997 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 998 999 /* wait for ACK */ 1000 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1001 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1002 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1003 } 1004 } else { 1005 /* unpause dpg, no need to wait */ 1006 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1007 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1008 } 1009 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1010 } 1011 1012 return 0; 1013 } 1014 1015 /** 1016 * vcn_v5_0_0_unified_ring_get_rptr - get unified read pointer 1017 * 1018 * @ring: amdgpu_ring pointer 1019 * 1020 * Returns the current hardware unified read pointer 1021 */ 1022 static uint64_t vcn_v5_0_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1023 { 1024 struct amdgpu_device *adev = ring->adev; 1025 1026 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1027 DRM_ERROR("wrong ring id is identified in %s", __func__); 1028 1029 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1030 } 1031 1032 /** 1033 * vcn_v5_0_0_unified_ring_get_wptr - get unified write pointer 1034 * 1035 * @ring: amdgpu_ring pointer 1036 * 1037 * Returns the current hardware unified write pointer 1038 */ 1039 static uint64_t vcn_v5_0_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1040 { 1041 struct amdgpu_device *adev = ring->adev; 1042 1043 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1044 DRM_ERROR("wrong ring id is identified in %s", __func__); 1045 1046 if (ring->use_doorbell) 1047 return *ring->wptr_cpu_addr; 1048 else 1049 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1050 } 1051 1052 /** 1053 * vcn_v5_0_0_unified_ring_set_wptr - set enc write pointer 1054 * 1055 * @ring: amdgpu_ring pointer 1056 * 1057 * Commits the enc write pointer to the hardware 1058 */ 1059 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1060 { 1061 struct amdgpu_device *adev = ring->adev; 1062 1063 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1064 DRM_ERROR("wrong ring id is identified in %s", __func__); 1065 1066 if (ring->use_doorbell) { 1067 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1068 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1069 } else { 1070 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1071 } 1072 } 1073 1074 static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { 1075 .type = AMDGPU_RING_TYPE_VCN_ENC, 1076 .align_mask = 0x3f, 1077 .nop = VCN_ENC_CMD_NO_OP, 1078 .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, 1079 .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, 1080 .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, 1081 .emit_frame_size = 1082 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1083 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1084 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1085 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1086 1, /* vcn_v2_0_enc_ring_insert_end */ 1087 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1088 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1089 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1090 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1091 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1092 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1093 .insert_nop = amdgpu_ring_insert_nop, 1094 .insert_end = vcn_v2_0_enc_ring_insert_end, 1095 .pad_ib = amdgpu_ring_generic_pad_ib, 1096 .begin_use = amdgpu_vcn_ring_begin_use, 1097 .end_use = amdgpu_vcn_ring_end_use, 1098 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1099 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1100 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1101 }; 1102 1103 /** 1104 * vcn_v5_0_0_set_unified_ring_funcs - set unified ring functions 1105 * 1106 * @adev: amdgpu_device pointer 1107 * 1108 * Set unified ring functions 1109 */ 1110 static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1111 { 1112 int i; 1113 1114 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1115 if (adev->vcn.harvest_config & (1 << i)) 1116 continue; 1117 1118 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs; 1119 adev->vcn.inst[i].ring_enc[0].me = i; 1120 1121 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); 1122 } 1123 } 1124 1125 /** 1126 * vcn_v5_0_0_is_idle - check VCN block is idle 1127 * 1128 * @handle: amdgpu_device pointer 1129 * 1130 * Check whether VCN block is idle 1131 */ 1132 static bool vcn_v5_0_0_is_idle(void *handle) 1133 { 1134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135 int i, ret = 1; 1136 1137 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1138 if (adev->vcn.harvest_config & (1 << i)) 1139 continue; 1140 1141 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1142 } 1143 1144 return ret; 1145 } 1146 1147 /** 1148 * vcn_v5_0_0_wait_for_idle - wait for VCN block idle 1149 * 1150 * @handle: amdgpu_device pointer 1151 * 1152 * Wait for VCN block idle 1153 */ 1154 static int vcn_v5_0_0_wait_for_idle(void *handle) 1155 { 1156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1157 int i, ret = 0; 1158 1159 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1160 if (adev->vcn.harvest_config & (1 << i)) 1161 continue; 1162 1163 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1164 UVD_STATUS__IDLE); 1165 if (ret) 1166 return ret; 1167 } 1168 1169 return ret; 1170 } 1171 1172 /** 1173 * vcn_v5_0_0_set_clockgating_state - set VCN block clockgating state 1174 * 1175 * @handle: amdgpu_device pointer 1176 * @state: clock gating state 1177 * 1178 * Set VCN block clockgating state 1179 */ 1180 static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) 1181 { 1182 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1183 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1184 int i; 1185 1186 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1187 if (adev->vcn.harvest_config & (1 << i)) 1188 continue; 1189 1190 if (enable) { 1191 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1192 return -EBUSY; 1193 vcn_v5_0_0_enable_clock_gating(adev, i); 1194 } else { 1195 vcn_v5_0_0_disable_clock_gating(adev, i); 1196 } 1197 } 1198 1199 return 0; 1200 } 1201 1202 /** 1203 * vcn_v5_0_0_set_powergating_state - set VCN block powergating state 1204 * 1205 * @handle: amdgpu_device pointer 1206 * @state: power gating state 1207 * 1208 * Set VCN block powergating state 1209 */ 1210 static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_state state) 1211 { 1212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1213 int ret; 1214 1215 if (state == adev->vcn.cur_state) 1216 return 0; 1217 1218 if (state == AMD_PG_STATE_GATE) 1219 ret = vcn_v5_0_0_stop(adev); 1220 else 1221 ret = vcn_v5_0_0_start(adev); 1222 1223 if (!ret) 1224 adev->vcn.cur_state = state; 1225 1226 return ret; 1227 } 1228 1229 /** 1230 * vcn_v5_0_0_set_interrupt_state - set VCN block interrupt state 1231 * 1232 * @adev: amdgpu_device pointer 1233 * @source: interrupt sources 1234 * @type: interrupt types 1235 * @state: interrupt states 1236 * 1237 * Set VCN block interrupt state 1238 */ 1239 static int vcn_v5_0_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1240 unsigned type, enum amdgpu_interrupt_state state) 1241 { 1242 return 0; 1243 } 1244 1245 /** 1246 * vcn_v5_0_0_process_interrupt - process VCN block interrupt 1247 * 1248 * @adev: amdgpu_device pointer 1249 * @source: interrupt sources 1250 * @entry: interrupt entry from clients and sources 1251 * 1252 * Process VCN block interrupt 1253 */ 1254 static int vcn_v5_0_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1255 struct amdgpu_iv_entry *entry) 1256 { 1257 uint32_t ip_instance; 1258 1259 switch (entry->client_id) { 1260 case SOC15_IH_CLIENTID_VCN: 1261 ip_instance = 0; 1262 break; 1263 case SOC15_IH_CLIENTID_VCN1: 1264 ip_instance = 1; 1265 break; 1266 default: 1267 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1268 return 0; 1269 } 1270 1271 DRM_DEBUG("IH: VCN TRAP\n"); 1272 1273 switch (entry->src_id) { 1274 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1275 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1276 break; 1277 case VCN_4_0__SRCID_UVD_POISON: 1278 amdgpu_vcn_process_poison_irq(adev, source, entry); 1279 break; 1280 default: 1281 DRM_ERROR("Unhandled interrupt: %d %d\n", 1282 entry->src_id, entry->src_data[0]); 1283 break; 1284 } 1285 1286 return 0; 1287 } 1288 1289 static const struct amdgpu_irq_src_funcs vcn_v5_0_0_irq_funcs = { 1290 .set = vcn_v5_0_0_set_interrupt_state, 1291 .process = vcn_v5_0_0_process_interrupt, 1292 }; 1293 1294 /** 1295 * vcn_v5_0_0_set_irq_funcs - set VCN block interrupt irq functions 1296 * 1297 * @adev: amdgpu_device pointer 1298 * 1299 * Set VCN block interrupt irq functions 1300 */ 1301 static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) 1302 { 1303 int i; 1304 1305 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1306 if (adev->vcn.harvest_config & (1 << i)) 1307 continue; 1308 1309 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1310 adev->vcn.inst[i].irq.funcs = &vcn_v5_0_0_irq_funcs; 1311 } 1312 } 1313 1314 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { 1315 .name = "vcn_v5_0_0", 1316 .early_init = vcn_v5_0_0_early_init, 1317 .late_init = NULL, 1318 .sw_init = vcn_v5_0_0_sw_init, 1319 .sw_fini = vcn_v5_0_0_sw_fini, 1320 .hw_init = vcn_v5_0_0_hw_init, 1321 .hw_fini = vcn_v5_0_0_hw_fini, 1322 .suspend = vcn_v5_0_0_suspend, 1323 .resume = vcn_v5_0_0_resume, 1324 .is_idle = vcn_v5_0_0_is_idle, 1325 .wait_for_idle = vcn_v5_0_0_wait_for_idle, 1326 .check_soft_reset = NULL, 1327 .pre_soft_reset = NULL, 1328 .soft_reset = NULL, 1329 .post_soft_reset = NULL, 1330 .set_clockgating_state = vcn_v5_0_0_set_clockgating_state, 1331 .set_powergating_state = vcn_v5_0_0_set_powergating_state, 1332 .dump_ip_state = NULL, 1333 .print_ip_state = NULL, 1334 }; 1335 1336 const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = { 1337 .type = AMD_IP_BLOCK_TYPE_VCN, 1338 .major = 5, 1339 .minor = 0, 1340 .rev = 0, 1341 .funcs = &vcn_v5_0_0_ip_funcs, 1342 }; 1343