1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0_5.h" 35 36 #include "vcn/vcn_4_0_5_offset.h" 37 #include "vcn/vcn_4_0_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 (0x48300 + 0x38000) 49 #define VCN1_AON_SOC_ADDRESS_3_0 (0x48000 + 0x38000) 50 51 #define VCN_HARVEST_MMSCH 0 52 53 #define RDECODE_MSG_CREATE 0x00000000 54 #define RDECODE_MESSAGE_CREATE 0x00000001 55 56 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = { 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 84 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 87 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 89 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 90 }; 91 92 static int amdgpu_ih_clientid_vcns[] = { 93 SOC15_IH_CLIENTID_VCN, 94 SOC15_IH_CLIENTID_VCN1 95 }; 96 97 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev); 99 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 100 enum amd_powergating_state state); 101 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 102 struct dpg_pause_state *new_state); 103 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring); 104 105 /** 106 * vcn_v4_0_5_early_init - set function pointers and load microcode 107 * 108 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 109 * 110 * Set ring and irq function pointers 111 * Load microcode from filesystem 112 */ 113 static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6)) 119 adev->vcn.per_inst_fw = true; 120 121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 122 /* re-use enc ring as unified ring */ 123 adev->vcn.inst[i].num_enc_rings = 1; 124 vcn_v4_0_5_set_unified_ring_funcs(adev); 125 vcn_v4_0_5_set_irq_funcs(adev); 126 127 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 128 adev->vcn.inst[i].set_pg_state = vcn_v4_0_5_set_pg_state; 129 130 r = amdgpu_vcn_early_init(adev, i); 131 if (r) 132 return r; 133 } 134 135 return 0; 136 } 137 138 /** 139 * vcn_v4_0_5_sw_init - sw init for VCN block 140 * 141 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 142 * 143 * Load firmware and sw initialization 144 */ 145 static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) 146 { 147 struct amdgpu_ring *ring; 148 struct amdgpu_device *adev = ip_block->adev; 149 int i, r; 150 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 151 uint32_t *ptr; 152 153 154 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 155 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 156 157 if (adev->vcn.harvest_config & (1 << i)) 158 continue; 159 160 r = amdgpu_vcn_sw_init(adev, i); 161 if (r) 162 return r; 163 164 amdgpu_vcn_setup_ucode(adev, i); 165 166 r = amdgpu_vcn_resume(adev, i); 167 if (r) 168 return r; 169 170 atomic_set(&adev->vcn.inst[i].sched_score, 0); 171 172 /* VCN UNIFIED TRAP */ 173 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 174 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 175 if (r) 176 return r; 177 178 /* VCN POISON TRAP */ 179 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 180 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 181 if (r) 182 return r; 183 184 ring = &adev->vcn.inst[i].ring_enc[0]; 185 ring->use_doorbell = true; 186 if (amdgpu_sriov_vf(adev)) 187 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 188 i * (adev->vcn.inst[i].num_enc_rings + 1) + 1; 189 else 190 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 191 2 + 8 * i; 192 ring->vm_hub = AMDGPU_MMHUB0(0); 193 sprintf(ring->name, "vcn_unified_%d", i); 194 195 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 196 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 197 if (r) 198 return r; 199 200 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 201 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 202 fw_shared->sq.is_enabled = 1; 203 204 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 205 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 206 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 207 208 if (amdgpu_sriov_vf(adev)) 209 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 210 211 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT; 212 fw_shared->drm_key_wa.method = 213 AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING; 214 215 if (amdgpu_vcnfw_log) 216 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 217 218 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 219 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode; 220 } 221 222 adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 223 if (!amdgpu_sriov_vf(adev)) 224 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 225 226 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 227 if (r) 228 return r; 229 230 if (amdgpu_sriov_vf(adev)) { 231 r = amdgpu_virt_alloc_mm_table(adev); 232 if (r) 233 return r; 234 } 235 236 /* Allocate memory for VCN IP Dump buffer */ 237 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 238 if (!ptr) { 239 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 240 adev->vcn.ip_dump = NULL; 241 } else { 242 adev->vcn.ip_dump = ptr; 243 } 244 return 0; 245 } 246 247 /** 248 * vcn_v4_0_5_sw_fini - sw fini for VCN block 249 * 250 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 251 * 252 * VCN suspend and free up sw allocation 253 */ 254 static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) 255 { 256 struct amdgpu_device *adev = ip_block->adev; 257 int i, r, idx; 258 259 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 260 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 261 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 262 263 if (adev->vcn.harvest_config & (1 << i)) 264 continue; 265 266 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 267 fw_shared->present_flag_0 = 0; 268 fw_shared->sq.is_enabled = 0; 269 } 270 271 drm_dev_exit(idx); 272 } 273 274 if (amdgpu_sriov_vf(adev)) 275 amdgpu_virt_free_mm_table(adev); 276 277 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 278 r = amdgpu_vcn_suspend(adev, i); 279 if (r) 280 return r; 281 282 r = amdgpu_vcn_sw_fini(adev, i); 283 if (r) 284 return r; 285 } 286 287 kfree(adev->vcn.ip_dump); 288 289 return 0; 290 } 291 292 /** 293 * vcn_v4_0_5_hw_init - start and test VCN block 294 * 295 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 296 * 297 * Initialize the hardware, boot up the VCPU and do some testing 298 */ 299 static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) 300 { 301 struct amdgpu_device *adev = ip_block->adev; 302 struct amdgpu_ring *ring; 303 int i, r; 304 305 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 306 if (adev->vcn.harvest_config & (1 << i)) 307 continue; 308 309 ring = &adev->vcn.inst[i].ring_enc[0]; 310 311 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 312 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 313 314 r = amdgpu_ring_test_helper(ring); 315 if (r) 316 return r; 317 } 318 319 return 0; 320 } 321 322 /** 323 * vcn_v4_0_5_hw_fini - stop the hardware block 324 * 325 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 326 * 327 * Stop the VCN block, mark ring as not ready any more 328 */ 329 static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block) 330 { 331 struct amdgpu_device *adev = ip_block->adev; 332 int i; 333 334 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 335 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 336 337 if (adev->vcn.harvest_config & (1 << i)) 338 continue; 339 340 cancel_delayed_work_sync(&vinst->idle_work); 341 342 if (!amdgpu_sriov_vf(adev)) { 343 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 344 (vinst->cur_state != AMD_PG_STATE_GATE && 345 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 346 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 347 } 348 } 349 } 350 351 return 0; 352 } 353 354 /** 355 * vcn_v4_0_5_suspend - suspend VCN block 356 * 357 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 358 * 359 * HW fini and suspend VCN block 360 */ 361 static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) 362 { 363 struct amdgpu_device *adev = ip_block->adev; 364 int r, i; 365 366 r = vcn_v4_0_5_hw_fini(ip_block); 367 if (r) 368 return r; 369 370 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 371 r = amdgpu_vcn_suspend(ip_block->adev, i); 372 if (r) 373 return r; 374 } 375 376 return r; 377 } 378 379 /** 380 * vcn_v4_0_5_resume - resume VCN block 381 * 382 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 383 * 384 * Resume firmware and hw init VCN block 385 */ 386 static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block) 387 { 388 struct amdgpu_device *adev = ip_block->adev; 389 int r, i; 390 391 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 392 r = amdgpu_vcn_resume(ip_block->adev, i); 393 if (r) 394 return r; 395 } 396 397 r = vcn_v4_0_5_hw_init(ip_block); 398 399 return r; 400 } 401 402 /** 403 * vcn_v4_0_5_mc_resume - memory controller programming 404 * 405 * @vinst: VCN instance 406 * 407 * Let the VCN memory controller know it's offsets 408 */ 409 static void vcn_v4_0_5_mc_resume(struct amdgpu_vcn_inst *vinst) 410 { 411 struct amdgpu_device *adev = vinst->adev; 412 int inst = vinst->inst; 413 uint32_t offset, size; 414 const struct common_firmware_header *hdr; 415 416 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 417 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 418 419 /* cache window 0: fw */ 420 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 421 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 422 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 423 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 424 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 425 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 426 offset = 0; 427 } else { 428 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 429 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 430 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 431 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 432 offset = size; 433 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 434 } 435 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 436 437 /* cache window 1: stack */ 438 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 439 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 440 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 441 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 442 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 443 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 444 445 /* cache window 2: context */ 446 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 447 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 448 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 449 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 450 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 451 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 452 453 /* non-cache window */ 454 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 455 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 456 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 457 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 458 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 459 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 460 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 461 } 462 463 /** 464 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode 465 * 466 * @vinst: VCN instance 467 * @indirect: indirectly write sram 468 * 469 * Let the VCN memory controller know it's offsets with dpg mode 470 */ 471 static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 472 bool indirect) 473 { 474 struct amdgpu_device *adev = vinst->adev; 475 int inst_idx = vinst->inst; 476 uint32_t offset, size; 477 const struct common_firmware_header *hdr; 478 479 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 480 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 481 482 /* cache window 0: fw */ 483 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 484 if (!indirect) { 485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 486 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 487 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 488 0, indirect); 489 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 490 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 491 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 492 0, indirect); 493 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 494 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 495 } else { 496 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 497 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 498 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 499 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 500 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 501 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 502 } 503 offset = 0; 504 } else { 505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 506 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 507 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 510 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 511 offset = size; 512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 513 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 514 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 515 } 516 517 if (!indirect) 518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 519 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 520 else 521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 522 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 523 524 /* cache window 1: stack */ 525 if (!indirect) { 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 528 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 530 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 531 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 533 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 534 } else { 535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 536 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 537 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 538 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 540 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 541 } 542 543 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 544 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 545 546 /* cache window 2: context */ 547 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 548 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 549 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 550 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 553 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 554 0, indirect); 555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 556 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 557 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 558 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 559 560 /* non-cache window */ 561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 562 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 563 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 564 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 565 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 566 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 567 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 568 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 570 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 571 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 572 573 /* VCN global tiling registers */ 574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 575 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 576 adev->gfx.config.gb_addr_config, 0, indirect); 577 } 578 579 /** 580 * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating 581 * 582 * @vinst: VCN instance 583 * 584 * Disable static power gating for VCN block 585 */ 586 static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 587 { 588 struct amdgpu_device *adev = vinst->adev; 589 int inst = vinst->inst; 590 uint32_t data = 0; 591 592 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 593 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 594 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 595 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 596 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 597 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 598 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 599 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 600 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 601 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 602 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 603 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 604 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 605 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 606 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 607 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 608 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 609 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 610 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 611 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 612 } else { 613 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 614 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 615 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 616 0, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 617 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 618 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 619 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 620 0, UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 621 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 622 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 623 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 624 0, UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 625 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 626 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 627 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 628 0, UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 629 } 630 631 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 632 data &= ~0x103; 633 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 634 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 635 UVD_POWER_STATUS__UVD_PG_EN_MASK; 636 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 637 } 638 639 /** 640 * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating 641 * 642 * @vinst: VCN instance 643 * 644 * Enable static power gating for VCN block 645 */ 646 static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 647 { 648 struct amdgpu_device *adev = vinst->adev; 649 int inst = vinst->inst; 650 uint32_t data; 651 652 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 653 /* Before power off, this indicator has to be turned on */ 654 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 655 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 656 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 657 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 658 659 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 660 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 661 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 662 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 663 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 664 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 665 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 666 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 667 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 668 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 669 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 670 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 671 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 672 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 673 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 674 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 675 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 676 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 677 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 678 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 679 } 680 } 681 682 /** 683 * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating 684 * 685 * @vinst: VCN instance 686 * 687 * Disable clock gating for VCN block 688 */ 689 static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 690 { 691 struct amdgpu_device *adev = vinst->adev; 692 int inst = vinst->inst; 693 uint32_t data; 694 695 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 696 return; 697 698 /* VCN disable CGC */ 699 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 700 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 701 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 702 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 703 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 704 705 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 706 data &= ~(UVD_CGC_GATE__SYS_MASK 707 | UVD_CGC_GATE__UDEC_MASK 708 | UVD_CGC_GATE__MPEG2_MASK 709 | UVD_CGC_GATE__REGS_MASK 710 | UVD_CGC_GATE__RBC_MASK 711 | UVD_CGC_GATE__LMI_MC_MASK 712 | UVD_CGC_GATE__LMI_UMC_MASK 713 | UVD_CGC_GATE__IDCT_MASK 714 | UVD_CGC_GATE__MPRD_MASK 715 | UVD_CGC_GATE__MPC_MASK 716 | UVD_CGC_GATE__LBSI_MASK 717 | UVD_CGC_GATE__LRBBM_MASK 718 | UVD_CGC_GATE__UDEC_RE_MASK 719 | UVD_CGC_GATE__UDEC_CM_MASK 720 | UVD_CGC_GATE__UDEC_IT_MASK 721 | UVD_CGC_GATE__UDEC_DB_MASK 722 | UVD_CGC_GATE__UDEC_MP_MASK 723 | UVD_CGC_GATE__WCB_MASK 724 | UVD_CGC_GATE__VCPU_MASK 725 | UVD_CGC_GATE__MMSCH_MASK); 726 727 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 728 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 729 730 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 731 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 732 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 733 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 734 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 735 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 736 | UVD_CGC_CTRL__SYS_MODE_MASK 737 | UVD_CGC_CTRL__UDEC_MODE_MASK 738 | UVD_CGC_CTRL__MPEG2_MODE_MASK 739 | UVD_CGC_CTRL__REGS_MODE_MASK 740 | UVD_CGC_CTRL__RBC_MODE_MASK 741 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 742 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 743 | UVD_CGC_CTRL__IDCT_MODE_MASK 744 | UVD_CGC_CTRL__MPRD_MODE_MASK 745 | UVD_CGC_CTRL__MPC_MODE_MASK 746 | UVD_CGC_CTRL__LBSI_MODE_MASK 747 | UVD_CGC_CTRL__LRBBM_MODE_MASK 748 | UVD_CGC_CTRL__WCB_MODE_MASK 749 | UVD_CGC_CTRL__VCPU_MODE_MASK 750 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 751 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 752 753 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 754 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 755 | UVD_SUVD_CGC_GATE__SIT_MASK 756 | UVD_SUVD_CGC_GATE__SMP_MASK 757 | UVD_SUVD_CGC_GATE__SCM_MASK 758 | UVD_SUVD_CGC_GATE__SDB_MASK 759 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 760 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 761 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 762 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 763 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 764 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 765 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 766 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 767 | UVD_SUVD_CGC_GATE__SCLR_MASK 768 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 769 | UVD_SUVD_CGC_GATE__ENT_MASK 770 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 771 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 772 | UVD_SUVD_CGC_GATE__SITE_MASK 773 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 774 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 775 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 776 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 777 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 778 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 779 780 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 781 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 782 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 783 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 784 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 785 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 786 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 787 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 788 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 789 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 790 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 791 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 792 } 793 794 /** 795 * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 796 * 797 * @vinst: VCN instance 798 * @sram_sel: sram select 799 * @indirect: indirectly write sram 800 * 801 * Disable clock gating for VCN block with dpg mode 802 */ 803 static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 804 uint8_t sram_sel, 805 uint8_t indirect) 806 { 807 struct amdgpu_device *adev = vinst->adev; 808 int inst_idx = vinst->inst; 809 uint32_t reg_data = 0; 810 811 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 812 return; 813 814 /* enable sw clock gating control */ 815 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 816 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 817 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 818 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 819 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 820 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 821 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 822 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 823 UVD_CGC_CTRL__SYS_MODE_MASK | 824 UVD_CGC_CTRL__UDEC_MODE_MASK | 825 UVD_CGC_CTRL__MPEG2_MODE_MASK | 826 UVD_CGC_CTRL__REGS_MODE_MASK | 827 UVD_CGC_CTRL__RBC_MODE_MASK | 828 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 829 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 830 UVD_CGC_CTRL__IDCT_MODE_MASK | 831 UVD_CGC_CTRL__MPRD_MODE_MASK | 832 UVD_CGC_CTRL__MPC_MODE_MASK | 833 UVD_CGC_CTRL__LBSI_MODE_MASK | 834 UVD_CGC_CTRL__LRBBM_MODE_MASK | 835 UVD_CGC_CTRL__WCB_MODE_MASK | 836 UVD_CGC_CTRL__VCPU_MODE_MASK); 837 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 838 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 839 840 /* turn off clock gating */ 841 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 842 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 843 844 /* turn on SUVD clock gating */ 845 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 846 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 847 848 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 849 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 850 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 851 } 852 853 /** 854 * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating 855 * 856 * @vinst: VCN instance 857 * 858 * Enable clock gating for VCN block 859 */ 860 static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 861 { 862 struct amdgpu_device *adev = vinst->adev; 863 int inst = vinst->inst; 864 uint32_t data; 865 866 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 867 return; 868 869 /* enable VCN CGC */ 870 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 871 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 872 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 873 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 874 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 875 876 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 877 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 878 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 879 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 880 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 881 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 882 | UVD_CGC_CTRL__SYS_MODE_MASK 883 | UVD_CGC_CTRL__UDEC_MODE_MASK 884 | UVD_CGC_CTRL__MPEG2_MODE_MASK 885 | UVD_CGC_CTRL__REGS_MODE_MASK 886 | UVD_CGC_CTRL__RBC_MODE_MASK 887 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 888 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 889 | UVD_CGC_CTRL__IDCT_MODE_MASK 890 | UVD_CGC_CTRL__MPRD_MODE_MASK 891 | UVD_CGC_CTRL__MPC_MODE_MASK 892 | UVD_CGC_CTRL__LBSI_MODE_MASK 893 | UVD_CGC_CTRL__LRBBM_MODE_MASK 894 | UVD_CGC_CTRL__WCB_MODE_MASK 895 | UVD_CGC_CTRL__VCPU_MODE_MASK 896 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 897 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 898 899 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 900 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 901 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 902 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 903 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 904 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 905 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 906 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 907 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 908 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 909 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 910 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 911 } 912 913 /** 914 * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode 915 * 916 * @vinst: VCN instance 917 * @indirect: indirectly write sram 918 * 919 * Start VCN block with dpg mode 920 */ 921 static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 922 bool indirect) 923 { 924 struct amdgpu_device *adev = vinst->adev; 925 int inst_idx = vinst->inst; 926 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 927 struct amdgpu_ring *ring; 928 uint32_t tmp; 929 930 /* disable register anti-hang mechanism */ 931 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 932 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 933 /* enable dynamic power gating mode */ 934 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 935 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 936 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 937 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 938 939 if (indirect) 940 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 941 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 942 943 /* enable clock gating */ 944 vcn_v4_0_5_disable_clock_gating_dpg_mode(vinst, 0, indirect); 945 946 /* enable VCPU clock */ 947 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 948 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 949 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 950 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 951 952 /* disable master interrupt */ 953 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 954 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 955 956 /* setup regUVD_LMI_CTRL */ 957 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 958 UVD_LMI_CTRL__REQ_MODE_MASK | 959 UVD_LMI_CTRL__CRC_RESET_MASK | 960 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 961 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 962 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 963 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 964 0x00100000L); 965 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 966 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 967 968 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 969 VCN, inst_idx, regUVD_MPC_CNTL), 970 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 971 972 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 973 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 974 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 975 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 976 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 977 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 978 979 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 980 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 981 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 982 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 983 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 984 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 985 986 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 987 VCN, inst_idx, regUVD_MPC_SET_MUX), 988 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 989 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 990 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 991 992 vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect); 993 994 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 995 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 996 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 997 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 998 999 /* enable LMI MC and UMC channels */ 1000 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 1001 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1002 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 1003 1004 /* enable master interrupt */ 1005 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1006 VCN, inst_idx, regUVD_MASTINT_EN), 1007 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1008 1009 if (indirect) 1010 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1011 1012 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1013 1014 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 1015 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1016 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1017 1018 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1019 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1020 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1021 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1022 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1023 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1024 1025 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1026 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1027 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1028 1029 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1030 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1031 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1032 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1033 1034 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1035 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1036 VCN_RB1_DB_CTRL__EN_MASK); 1037 1038 /* Keeping one read-back to ensure all register writes are done, otherwise 1039 * it may introduce race conditions */ 1040 RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL); 1041 1042 return 0; 1043 } 1044 1045 1046 /** 1047 * vcn_v4_0_5_start - VCN start 1048 * 1049 * @vinst: VCN instance 1050 * 1051 * Start VCN block 1052 */ 1053 static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst) 1054 { 1055 struct amdgpu_device *adev = vinst->adev; 1056 int i = vinst->inst; 1057 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1058 struct amdgpu_ring *ring; 1059 uint32_t tmp; 1060 int j, k, r; 1061 1062 if (adev->vcn.harvest_config & (1 << i)) 1063 return 0; 1064 1065 if (adev->pm.dpm_enabled) 1066 amdgpu_dpm_enable_vcn(adev, true, i); 1067 1068 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1069 1070 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1071 return vcn_v4_0_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1072 1073 /* disable VCN power gating */ 1074 vcn_v4_0_5_disable_static_power_gating(vinst); 1075 1076 /* set VCN status busy */ 1077 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1078 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1079 1080 /* SW clock gating */ 1081 vcn_v4_0_5_disable_clock_gating(vinst); 1082 1083 /* enable VCPU clock */ 1084 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1085 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1086 1087 /* disable master interrupt */ 1088 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1089 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1090 1091 /* enable LMI MC and UMC channels */ 1092 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1093 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1094 1095 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1096 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1097 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1098 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1099 1100 /* setup regUVD_LMI_CTRL */ 1101 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1102 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1103 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1104 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1105 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1106 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1107 1108 /* setup regUVD_MPC_CNTL */ 1109 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1110 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1111 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1112 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1113 1114 /* setup UVD_MPC_SET_MUXA0 */ 1115 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1116 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1117 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1118 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1119 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1120 1121 /* setup UVD_MPC_SET_MUXB0 */ 1122 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1123 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1124 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1125 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1126 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1127 1128 /* setup UVD_MPC_SET_MUX */ 1129 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1130 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1131 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1132 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1133 1134 vcn_v4_0_5_mc_resume(vinst); 1135 1136 /* VCN global tiling registers */ 1137 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1138 adev->gfx.config.gb_addr_config); 1139 1140 /* unblock VCPU register access */ 1141 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1142 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1143 1144 /* release VCPU reset to boot */ 1145 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1146 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1147 1148 for (j = 0; j < 10; ++j) { 1149 uint32_t status; 1150 1151 for (k = 0; k < 100; ++k) { 1152 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1153 if (status & 2) 1154 break; 1155 mdelay(10); 1156 if (amdgpu_emu_mode == 1) 1157 msleep(1); 1158 } 1159 1160 if (amdgpu_emu_mode == 1) { 1161 r = -1; 1162 if (status & 2) { 1163 r = 0; 1164 break; 1165 } 1166 } else { 1167 r = 0; 1168 if (status & 2) 1169 break; 1170 1171 dev_err(adev->dev, 1172 "VCN[%d] is not responding, trying to reset VCPU!!!\n", i); 1173 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1174 UVD_VCPU_CNTL__BLK_RST_MASK, 1175 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1176 mdelay(10); 1177 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1178 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1179 1180 mdelay(10); 1181 r = -1; 1182 } 1183 } 1184 1185 if (r) { 1186 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1187 return r; 1188 } 1189 1190 /* enable master interrupt */ 1191 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1192 UVD_MASTINT_EN__VCPU_EN_MASK, 1193 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1194 1195 /* clear the busy bit of VCN_STATUS */ 1196 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1197 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1198 1199 ring = &adev->vcn.inst[i].ring_enc[0]; 1200 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1201 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1202 VCN_RB1_DB_CTRL__EN_MASK); 1203 1204 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1205 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1206 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1207 1208 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1209 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1210 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1211 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1212 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1213 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1214 1215 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1216 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1217 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1218 1219 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1220 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1221 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1222 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1223 1224 /* Keeping one read-back to ensure all register writes are done, otherwise 1225 * it may introduce race conditions */ 1226 RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1227 1228 return 0; 1229 } 1230 1231 /** 1232 * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode 1233 * 1234 * @vinst: VCN instance 1235 * 1236 * Stop VCN block with dpg mode 1237 */ 1238 static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1239 { 1240 struct amdgpu_device *adev = vinst->adev; 1241 int inst_idx = vinst->inst; 1242 uint32_t tmp; 1243 1244 /* Wait for power status to be 1 */ 1245 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1246 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1247 1248 /* wait for read ptr to be equal to write ptr */ 1249 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1250 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1251 1252 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1253 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1254 1255 /* disable dynamic power gating mode */ 1256 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1257 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1258 1259 /* Keeping one read-back to ensure all register writes are done, 1260 * otherwise it may introduce race conditions. 1261 */ 1262 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); 1263 } 1264 1265 /** 1266 * vcn_v4_0_5_stop - VCN stop 1267 * 1268 * @vinst: VCN instance 1269 * 1270 * Stop VCN block 1271 */ 1272 static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst) 1273 { 1274 struct amdgpu_device *adev = vinst->adev; 1275 int i = vinst->inst; 1276 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1277 uint32_t tmp; 1278 int r = 0; 1279 1280 if (adev->vcn.harvest_config & (1 << i)) 1281 return 0; 1282 1283 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1284 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1285 1286 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1287 vcn_v4_0_5_stop_dpg_mode(vinst); 1288 r = 0; 1289 goto done; 1290 } 1291 1292 /* wait for vcn idle */ 1293 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1294 if (r) 1295 goto done; 1296 1297 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1298 UVD_LMI_STATUS__READ_CLEAN_MASK | 1299 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1300 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1301 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1302 if (r) 1303 goto done; 1304 1305 /* disable LMI UMC channel */ 1306 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1307 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1308 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1309 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1310 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1311 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1312 if (r) 1313 goto done; 1314 1315 /* block VCPU register access */ 1316 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1317 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1318 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1319 1320 /* reset VCPU */ 1321 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1322 UVD_VCPU_CNTL__BLK_RST_MASK, 1323 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1324 1325 /* disable VCPU clock */ 1326 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1327 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1328 1329 /* apply soft reset */ 1330 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1331 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1332 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1333 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1334 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1335 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1336 1337 /* clear status */ 1338 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1339 1340 /* apply HW clock gating */ 1341 vcn_v4_0_5_enable_clock_gating(vinst); 1342 1343 /* enable VCN power gating */ 1344 vcn_v4_0_5_enable_static_power_gating(vinst); 1345 1346 /* Keeping one read-back to ensure all register writes are done, 1347 * otherwise it may introduce race conditions. 1348 */ 1349 RREG32_SOC15(VCN, i, regUVD_STATUS); 1350 1351 done: 1352 if (adev->pm.dpm_enabled) 1353 amdgpu_dpm_enable_vcn(adev, false, i); 1354 1355 return r; 1356 } 1357 1358 /** 1359 * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode 1360 * 1361 * @vinst: VCN instance 1362 * @new_state: pause state 1363 * 1364 * Pause dpg mode for VCN block 1365 */ 1366 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1367 struct dpg_pause_state *new_state) 1368 { 1369 struct amdgpu_device *adev = vinst->adev; 1370 int inst_idx = vinst->inst; 1371 uint32_t reg_data = 0; 1372 int ret_code; 1373 1374 /* pause/unpause if state is changed */ 1375 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1376 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1377 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1378 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1379 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1380 1381 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1382 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1383 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1384 1385 if (!ret_code) { 1386 /* pause DPG */ 1387 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1388 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1389 1390 /* wait for ACK */ 1391 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1392 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1393 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1394 1395 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1396 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1397 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1398 } 1399 } else { 1400 /* unpause dpg, no need to wait */ 1401 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1402 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1403 } 1404 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1405 } 1406 1407 return 0; 1408 } 1409 1410 /** 1411 * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer 1412 * 1413 * @ring: amdgpu_ring pointer 1414 * 1415 * Returns the current hardware unified read pointer 1416 */ 1417 static uint64_t vcn_v4_0_5_unified_ring_get_rptr(struct amdgpu_ring *ring) 1418 { 1419 struct amdgpu_device *adev = ring->adev; 1420 1421 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1422 DRM_ERROR("wrong ring id is identified in %s", __func__); 1423 1424 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1425 } 1426 1427 /** 1428 * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer 1429 * 1430 * @ring: amdgpu_ring pointer 1431 * 1432 * Returns the current hardware unified write pointer 1433 */ 1434 static uint64_t vcn_v4_0_5_unified_ring_get_wptr(struct amdgpu_ring *ring) 1435 { 1436 struct amdgpu_device *adev = ring->adev; 1437 1438 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1439 DRM_ERROR("wrong ring id is identified in %s", __func__); 1440 1441 if (ring->use_doorbell) 1442 return *ring->wptr_cpu_addr; 1443 else 1444 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1445 } 1446 1447 /** 1448 * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer 1449 * 1450 * @ring: amdgpu_ring pointer 1451 * 1452 * Commits the enc write pointer to the hardware 1453 */ 1454 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring) 1455 { 1456 struct amdgpu_device *adev = ring->adev; 1457 1458 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1459 DRM_ERROR("wrong ring id is identified in %s", __func__); 1460 1461 if (ring->use_doorbell) { 1462 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1463 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1464 } else { 1465 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1466 } 1467 } 1468 1469 static int vcn_v4_0_5_ring_reset(struct amdgpu_ring *ring, 1470 unsigned int vmid, 1471 struct amdgpu_fence *timedout_fence) 1472 { 1473 struct amdgpu_device *adev = ring->adev; 1474 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1475 int r; 1476 1477 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1478 r = vcn_v4_0_5_stop(vinst); 1479 if (r) 1480 return r; 1481 r = vcn_v4_0_5_start(vinst); 1482 if (r) 1483 return r; 1484 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1485 } 1486 1487 static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { 1488 .type = AMDGPU_RING_TYPE_VCN_ENC, 1489 .align_mask = 0x3f, 1490 .nop = VCN_ENC_CMD_NO_OP, 1491 .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, 1492 .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, 1493 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, 1494 .emit_frame_size = 1495 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1496 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1497 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1498 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1499 1, /* vcn_v2_0_enc_ring_insert_end */ 1500 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1501 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1502 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1503 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1504 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1505 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1506 .insert_nop = amdgpu_ring_insert_nop, 1507 .insert_end = vcn_v2_0_enc_ring_insert_end, 1508 .pad_ib = amdgpu_ring_generic_pad_ib, 1509 .begin_use = amdgpu_vcn_ring_begin_use, 1510 .end_use = amdgpu_vcn_ring_end_use, 1511 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1512 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1513 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1514 .reset = vcn_v4_0_5_ring_reset, 1515 }; 1516 1517 /** 1518 * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions 1519 * 1520 * @adev: amdgpu_device pointer 1521 * 1522 * Set unified ring functions 1523 */ 1524 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev) 1525 { 1526 int i; 1527 1528 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1529 if (adev->vcn.harvest_config & (1 << i)) 1530 continue; 1531 1532 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) 1533 vcn_v4_0_5_unified_ring_vm_funcs.secure_submission_supported = true; 1534 1535 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs; 1536 adev->vcn.inst[i].ring_enc[0].me = i; 1537 } 1538 } 1539 1540 /** 1541 * vcn_v4_0_5_is_idle - check VCN block is idle 1542 * 1543 * @ip_block: Pointer to the amdgpu_ip_block structure 1544 * 1545 * Check whether VCN block is idle 1546 */ 1547 static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block) 1548 { 1549 struct amdgpu_device *adev = ip_block->adev; 1550 int i, ret = 1; 1551 1552 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1553 if (adev->vcn.harvest_config & (1 << i)) 1554 continue; 1555 1556 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1557 } 1558 1559 return ret; 1560 } 1561 1562 /** 1563 * vcn_v4_0_5_wait_for_idle - wait for VCN block idle 1564 * 1565 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1566 * 1567 * Wait for VCN block idle 1568 */ 1569 static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 1570 { 1571 struct amdgpu_device *adev = ip_block->adev; 1572 int i, ret = 0; 1573 1574 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1575 if (adev->vcn.harvest_config & (1 << i)) 1576 continue; 1577 1578 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1579 UVD_STATUS__IDLE); 1580 if (ret) 1581 return ret; 1582 } 1583 1584 return ret; 1585 } 1586 1587 /** 1588 * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state 1589 * 1590 * @ip_block: amdgpu_ip_block pointer 1591 * @state: clock gating state 1592 * 1593 * Set VCN block clockgating state 1594 */ 1595 static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1596 enum amd_clockgating_state state) 1597 { 1598 struct amdgpu_device *adev = ip_block->adev; 1599 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1600 int i; 1601 1602 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1603 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1604 1605 if (adev->vcn.harvest_config & (1 << i)) 1606 continue; 1607 1608 if (enable) { 1609 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1610 return -EBUSY; 1611 vcn_v4_0_5_enable_clock_gating(vinst); 1612 } else { 1613 vcn_v4_0_5_disable_clock_gating(vinst); 1614 } 1615 } 1616 1617 return 0; 1618 } 1619 1620 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 1621 enum amd_powergating_state state) 1622 { 1623 int ret = 0; 1624 1625 if (state == vinst->cur_state) 1626 return 0; 1627 1628 if (state == AMD_PG_STATE_GATE) 1629 ret = vcn_v4_0_5_stop(vinst); 1630 else 1631 ret = vcn_v4_0_5_start(vinst); 1632 1633 if (!ret) 1634 vinst->cur_state = state; 1635 1636 return ret; 1637 } 1638 1639 /** 1640 * vcn_v4_0_5_process_interrupt - process VCN block interrupt 1641 * 1642 * @adev: amdgpu_device pointer 1643 * @source: interrupt sources 1644 * @entry: interrupt entry from clients and sources 1645 * 1646 * Process VCN block interrupt 1647 */ 1648 static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1649 struct amdgpu_iv_entry *entry) 1650 { 1651 uint32_t ip_instance; 1652 1653 switch (entry->client_id) { 1654 case SOC15_IH_CLIENTID_VCN: 1655 ip_instance = 0; 1656 break; 1657 case SOC15_IH_CLIENTID_VCN1: 1658 ip_instance = 1; 1659 break; 1660 default: 1661 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1662 return 0; 1663 } 1664 1665 DRM_DEBUG("IH: VCN TRAP\n"); 1666 1667 switch (entry->src_id) { 1668 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1669 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1670 break; 1671 case VCN_4_0__SRCID_UVD_POISON: 1672 amdgpu_vcn_process_poison_irq(adev, source, entry); 1673 break; 1674 default: 1675 DRM_ERROR("Unhandled interrupt: %d %d\n", 1676 entry->src_id, entry->src_data[0]); 1677 break; 1678 } 1679 1680 return 0; 1681 } 1682 1683 static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = { 1684 .process = vcn_v4_0_5_process_interrupt, 1685 }; 1686 1687 /** 1688 * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions 1689 * 1690 * @adev: amdgpu_device pointer 1691 * 1692 * Set VCN block interrupt irq functions 1693 */ 1694 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) 1695 { 1696 int i; 1697 1698 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1699 if (adev->vcn.harvest_config & (1 << i)) 1700 continue; 1701 1702 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 1703 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs; 1704 } 1705 } 1706 1707 static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1708 { 1709 struct amdgpu_device *adev = ip_block->adev; 1710 int i, j; 1711 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 1712 uint32_t inst_off, is_powered; 1713 1714 if (!adev->vcn.ip_dump) 1715 return; 1716 1717 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1718 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1719 if (adev->vcn.harvest_config & (1 << i)) { 1720 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1721 continue; 1722 } 1723 1724 inst_off = i * reg_count; 1725 is_powered = (adev->vcn.ip_dump[inst_off] & 1726 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1727 1728 if (is_powered) { 1729 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1730 for (j = 0; j < reg_count; j++) 1731 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name, 1732 adev->vcn.ip_dump[inst_off + j]); 1733 } else { 1734 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1735 } 1736 } 1737 } 1738 1739 static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block) 1740 { 1741 struct amdgpu_device *adev = ip_block->adev; 1742 int i, j; 1743 bool is_powered; 1744 uint32_t inst_off; 1745 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 1746 1747 if (!adev->vcn.ip_dump) 1748 return; 1749 1750 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1751 if (adev->vcn.harvest_config & (1 << i)) 1752 continue; 1753 1754 inst_off = i * reg_count; 1755 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1756 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); 1757 is_powered = (adev->vcn.ip_dump[inst_off] & 1758 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1759 1760 if (is_powered) 1761 for (j = 1; j < reg_count; j++) 1762 adev->vcn.ip_dump[inst_off + j] = 1763 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j], 1764 i)); 1765 } 1766 } 1767 1768 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { 1769 .name = "vcn_v4_0_5", 1770 .early_init = vcn_v4_0_5_early_init, 1771 .sw_init = vcn_v4_0_5_sw_init, 1772 .sw_fini = vcn_v4_0_5_sw_fini, 1773 .hw_init = vcn_v4_0_5_hw_init, 1774 .hw_fini = vcn_v4_0_5_hw_fini, 1775 .suspend = vcn_v4_0_5_suspend, 1776 .resume = vcn_v4_0_5_resume, 1777 .is_idle = vcn_v4_0_5_is_idle, 1778 .wait_for_idle = vcn_v4_0_5_wait_for_idle, 1779 .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, 1780 .set_powergating_state = vcn_set_powergating_state, 1781 .dump_ip_state = vcn_v4_0_5_dump_ip_state, 1782 .print_ip_state = vcn_v4_0_5_print_ip_state, 1783 }; 1784 1785 const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = { 1786 .type = AMD_IP_BLOCK_TYPE_VCN, 1787 .major = 4, 1788 .minor = 0, 1789 .rev = 5, 1790 .funcs = &vcn_v4_0_5_ip_funcs, 1791 }; 1792