1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0_5.h" 35 36 #include "vcn/vcn_4_0_5_offset.h" 37 #include "vcn/vcn_4_0_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 (0x48300 + 0x38000) 49 #define VCN1_AON_SOC_ADDRESS_3_0 (0x48000 + 0x38000) 50 51 #define VCN_HARVEST_MMSCH 0 52 53 #define RDECODE_MSG_CREATE 0x00000000 54 #define RDECODE_MESSAGE_CREATE 0x00000001 55 56 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = { 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 84 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 87 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 89 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 90 }; 91 92 static int amdgpu_ih_clientid_vcns[] = { 93 SOC15_IH_CLIENTID_VCN, 94 SOC15_IH_CLIENTID_VCN1 95 }; 96 97 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev); 99 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 100 enum amd_powergating_state state); 101 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 102 struct dpg_pause_state *new_state); 103 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring); 104 105 /** 106 * vcn_v4_0_5_early_init - set function pointers and load microcode 107 * 108 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 109 * 110 * Set ring and irq function pointers 111 * Load microcode from filesystem 112 */ 113 static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6)) 119 adev->vcn.per_inst_fw = true; 120 121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 122 /* re-use enc ring as unified ring */ 123 adev->vcn.inst[i].num_enc_rings = 1; 124 vcn_v4_0_5_set_unified_ring_funcs(adev); 125 vcn_v4_0_5_set_irq_funcs(adev); 126 127 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 128 adev->vcn.inst[i].set_pg_state = vcn_v4_0_5_set_pg_state; 129 130 r = amdgpu_vcn_early_init(adev, i); 131 if (r) 132 return r; 133 } 134 135 return 0; 136 } 137 138 /** 139 * vcn_v4_0_5_sw_init - sw init for VCN block 140 * 141 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 142 * 143 * Load firmware and sw initialization 144 */ 145 static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) 146 { 147 struct amdgpu_ring *ring; 148 struct amdgpu_device *adev = ip_block->adev; 149 int i, r; 150 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 151 uint32_t *ptr; 152 153 154 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 155 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 156 157 if (adev->vcn.harvest_config & (1 << i)) 158 continue; 159 160 r = amdgpu_vcn_sw_init(adev, i); 161 if (r) 162 return r; 163 164 amdgpu_vcn_setup_ucode(adev, i); 165 166 r = amdgpu_vcn_resume(adev, i); 167 if (r) 168 return r; 169 170 atomic_set(&adev->vcn.inst[i].sched_score, 0); 171 172 /* VCN UNIFIED TRAP */ 173 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 174 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 175 if (r) 176 return r; 177 178 /* VCN POISON TRAP */ 179 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 180 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 181 if (r) 182 return r; 183 184 ring = &adev->vcn.inst[i].ring_enc[0]; 185 ring->use_doorbell = true; 186 if (amdgpu_sriov_vf(adev)) 187 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 188 i * (adev->vcn.inst[i].num_enc_rings + 1) + 1; 189 else 190 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 191 2 + 8 * i; 192 ring->vm_hub = AMDGPU_MMHUB0(0); 193 sprintf(ring->name, "vcn_unified_%d", i); 194 195 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 196 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 197 if (r) 198 return r; 199 200 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 201 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 202 fw_shared->sq.is_enabled = 1; 203 204 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 205 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 206 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 207 208 if (amdgpu_sriov_vf(adev)) 209 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 210 211 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT; 212 fw_shared->drm_key_wa.method = 213 AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING; 214 215 if (amdgpu_vcnfw_log) 216 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 217 218 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 219 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode; 220 } 221 222 adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 223 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 224 225 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 226 if (r) 227 return r; 228 229 if (amdgpu_sriov_vf(adev)) { 230 r = amdgpu_virt_alloc_mm_table(adev); 231 if (r) 232 return r; 233 } 234 235 /* Allocate memory for VCN IP Dump buffer */ 236 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 237 if (!ptr) { 238 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 239 adev->vcn.ip_dump = NULL; 240 } else { 241 adev->vcn.ip_dump = ptr; 242 } 243 return 0; 244 } 245 246 /** 247 * vcn_v4_0_5_sw_fini - sw fini for VCN block 248 * 249 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 250 * 251 * VCN suspend and free up sw allocation 252 */ 253 static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) 254 { 255 struct amdgpu_device *adev = ip_block->adev; 256 int i, r, idx; 257 258 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 259 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 260 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 261 262 if (adev->vcn.harvest_config & (1 << i)) 263 continue; 264 265 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 266 fw_shared->present_flag_0 = 0; 267 fw_shared->sq.is_enabled = 0; 268 } 269 270 drm_dev_exit(idx); 271 } 272 273 if (amdgpu_sriov_vf(adev)) 274 amdgpu_virt_free_mm_table(adev); 275 276 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 277 r = amdgpu_vcn_suspend(adev, i); 278 if (r) 279 return r; 280 281 r = amdgpu_vcn_sw_fini(adev, i); 282 if (r) 283 return r; 284 } 285 286 kfree(adev->vcn.ip_dump); 287 288 return 0; 289 } 290 291 /** 292 * vcn_v4_0_5_hw_init - start and test VCN block 293 * 294 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 295 * 296 * Initialize the hardware, boot up the VCPU and do some testing 297 */ 298 static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) 299 { 300 struct amdgpu_device *adev = ip_block->adev; 301 struct amdgpu_ring *ring; 302 int i, r; 303 304 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 305 if (adev->vcn.harvest_config & (1 << i)) 306 continue; 307 308 ring = &adev->vcn.inst[i].ring_enc[0]; 309 310 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 311 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 312 313 r = amdgpu_ring_test_helper(ring); 314 if (r) 315 return r; 316 } 317 318 return 0; 319 } 320 321 /** 322 * vcn_v4_0_5_hw_fini - stop the hardware block 323 * 324 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 325 * 326 * Stop the VCN block, mark ring as not ready any more 327 */ 328 static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block) 329 { 330 struct amdgpu_device *adev = ip_block->adev; 331 int i; 332 333 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 334 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 335 336 if (adev->vcn.harvest_config & (1 << i)) 337 continue; 338 339 cancel_delayed_work_sync(&vinst->idle_work); 340 341 if (!amdgpu_sriov_vf(adev)) { 342 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 343 (vinst->cur_state != AMD_PG_STATE_GATE && 344 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 345 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 346 } 347 } 348 } 349 350 return 0; 351 } 352 353 /** 354 * vcn_v4_0_5_suspend - suspend VCN block 355 * 356 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 357 * 358 * HW fini and suspend VCN block 359 */ 360 static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) 361 { 362 struct amdgpu_device *adev = ip_block->adev; 363 int r, i; 364 365 r = vcn_v4_0_5_hw_fini(ip_block); 366 if (r) 367 return r; 368 369 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 370 r = amdgpu_vcn_suspend(ip_block->adev, i); 371 if (r) 372 return r; 373 } 374 375 return r; 376 } 377 378 /** 379 * vcn_v4_0_5_resume - resume VCN block 380 * 381 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 382 * 383 * Resume firmware and hw init VCN block 384 */ 385 static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block) 386 { 387 struct amdgpu_device *adev = ip_block->adev; 388 int r, i; 389 390 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 391 r = amdgpu_vcn_resume(ip_block->adev, i); 392 if (r) 393 return r; 394 } 395 396 r = vcn_v4_0_5_hw_init(ip_block); 397 398 return r; 399 } 400 401 /** 402 * vcn_v4_0_5_mc_resume - memory controller programming 403 * 404 * @vinst: VCN instance 405 * 406 * Let the VCN memory controller know it's offsets 407 */ 408 static void vcn_v4_0_5_mc_resume(struct amdgpu_vcn_inst *vinst) 409 { 410 struct amdgpu_device *adev = vinst->adev; 411 int inst = vinst->inst; 412 uint32_t offset, size; 413 const struct common_firmware_header *hdr; 414 415 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 416 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 417 418 /* cache window 0: fw */ 419 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 420 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 421 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 422 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 423 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 424 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 425 offset = 0; 426 } else { 427 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 428 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 429 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 430 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 431 offset = size; 432 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 433 } 434 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 435 436 /* cache window 1: stack */ 437 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 438 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 439 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 440 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 441 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 442 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 443 444 /* cache window 2: context */ 445 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 446 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 447 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 448 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 449 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 450 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 451 452 /* non-cache window */ 453 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 454 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 455 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 456 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 457 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 458 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 459 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 460 } 461 462 /** 463 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode 464 * 465 * @vinst: VCN instance 466 * @indirect: indirectly write sram 467 * 468 * Let the VCN memory controller know it's offsets with dpg mode 469 */ 470 static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 471 bool indirect) 472 { 473 struct amdgpu_device *adev = vinst->adev; 474 int inst_idx = vinst->inst; 475 uint32_t offset, size; 476 const struct common_firmware_header *hdr; 477 478 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 479 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 480 481 /* cache window 0: fw */ 482 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 483 if (!indirect) { 484 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 485 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 486 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 487 0, indirect); 488 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 489 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 490 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 491 0, indirect); 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 494 } else { 495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 496 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 498 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 501 } 502 offset = 0; 503 } else { 504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 505 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 506 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 507 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 508 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 509 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 510 offset = size; 511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 512 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 513 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 514 } 515 516 if (!indirect) 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 519 else 520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 521 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 522 523 /* cache window 1: stack */ 524 if (!indirect) { 525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 526 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 527 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 529 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 530 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 533 } else { 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 537 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 540 } 541 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 544 545 /* cache window 2: context */ 546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 547 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 548 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 549 0, indirect); 550 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 551 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 552 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 553 0, indirect); 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 558 559 /* non-cache window */ 560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 561 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 562 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 563 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 564 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 565 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 566 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 567 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 568 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 569 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 570 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 571 572 /* VCN global tiling registers */ 573 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 574 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 575 adev->gfx.config.gb_addr_config, 0, indirect); 576 } 577 578 /** 579 * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating 580 * 581 * @vinst: VCN instance 582 * 583 * Disable static power gating for VCN block 584 */ 585 static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 586 { 587 struct amdgpu_device *adev = vinst->adev; 588 int inst = vinst->inst; 589 uint32_t data = 0; 590 591 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 592 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 593 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 594 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 595 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 596 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 597 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 598 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 599 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 600 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 601 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 602 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 603 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 604 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 605 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 606 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 607 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 608 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 609 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 610 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 611 } else { 612 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 613 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 614 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 615 0, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 616 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 617 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 618 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 619 0, UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 620 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 621 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 622 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 623 0, UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 624 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 625 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 626 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 627 0, UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 628 } 629 630 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 631 data &= ~0x103; 632 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 633 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 634 UVD_POWER_STATUS__UVD_PG_EN_MASK; 635 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 636 } 637 638 /** 639 * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating 640 * 641 * @vinst: VCN instance 642 * 643 * Enable static power gating for VCN block 644 */ 645 static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 646 { 647 struct amdgpu_device *adev = vinst->adev; 648 int inst = vinst->inst; 649 uint32_t data; 650 651 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 652 /* Before power off, this indicator has to be turned on */ 653 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 654 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 655 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 656 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 657 658 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 659 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 660 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 661 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 662 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 663 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 664 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 665 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 666 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 667 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 668 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 669 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 670 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 671 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 672 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 673 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 674 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 675 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 676 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 677 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 678 } 679 } 680 681 /** 682 * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating 683 * 684 * @vinst: VCN instance 685 * 686 * Disable clock gating for VCN block 687 */ 688 static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 689 { 690 struct amdgpu_device *adev = vinst->adev; 691 int inst = vinst->inst; 692 uint32_t data; 693 694 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 695 return; 696 697 /* VCN disable CGC */ 698 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 699 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 700 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 701 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 702 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 703 704 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 705 data &= ~(UVD_CGC_GATE__SYS_MASK 706 | UVD_CGC_GATE__UDEC_MASK 707 | UVD_CGC_GATE__MPEG2_MASK 708 | UVD_CGC_GATE__REGS_MASK 709 | UVD_CGC_GATE__RBC_MASK 710 | UVD_CGC_GATE__LMI_MC_MASK 711 | UVD_CGC_GATE__LMI_UMC_MASK 712 | UVD_CGC_GATE__IDCT_MASK 713 | UVD_CGC_GATE__MPRD_MASK 714 | UVD_CGC_GATE__MPC_MASK 715 | UVD_CGC_GATE__LBSI_MASK 716 | UVD_CGC_GATE__LRBBM_MASK 717 | UVD_CGC_GATE__UDEC_RE_MASK 718 | UVD_CGC_GATE__UDEC_CM_MASK 719 | UVD_CGC_GATE__UDEC_IT_MASK 720 | UVD_CGC_GATE__UDEC_DB_MASK 721 | UVD_CGC_GATE__UDEC_MP_MASK 722 | UVD_CGC_GATE__WCB_MASK 723 | UVD_CGC_GATE__VCPU_MASK 724 | UVD_CGC_GATE__MMSCH_MASK); 725 726 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 727 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 728 729 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 730 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 731 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 732 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 733 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 734 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 735 | UVD_CGC_CTRL__SYS_MODE_MASK 736 | UVD_CGC_CTRL__UDEC_MODE_MASK 737 | UVD_CGC_CTRL__MPEG2_MODE_MASK 738 | UVD_CGC_CTRL__REGS_MODE_MASK 739 | UVD_CGC_CTRL__RBC_MODE_MASK 740 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 741 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 742 | UVD_CGC_CTRL__IDCT_MODE_MASK 743 | UVD_CGC_CTRL__MPRD_MODE_MASK 744 | UVD_CGC_CTRL__MPC_MODE_MASK 745 | UVD_CGC_CTRL__LBSI_MODE_MASK 746 | UVD_CGC_CTRL__LRBBM_MODE_MASK 747 | UVD_CGC_CTRL__WCB_MODE_MASK 748 | UVD_CGC_CTRL__VCPU_MODE_MASK 749 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 750 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 751 752 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 753 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 754 | UVD_SUVD_CGC_GATE__SIT_MASK 755 | UVD_SUVD_CGC_GATE__SMP_MASK 756 | UVD_SUVD_CGC_GATE__SCM_MASK 757 | UVD_SUVD_CGC_GATE__SDB_MASK 758 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 759 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 760 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 761 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 762 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 763 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 764 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 765 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 766 | UVD_SUVD_CGC_GATE__SCLR_MASK 767 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 768 | UVD_SUVD_CGC_GATE__ENT_MASK 769 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 770 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 771 | UVD_SUVD_CGC_GATE__SITE_MASK 772 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 773 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 774 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 775 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 776 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 777 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 778 779 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 780 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 781 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 782 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 783 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 784 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 785 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 786 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 787 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 788 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 789 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 790 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 791 } 792 793 /** 794 * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 795 * 796 * @vinst: VCN instance 797 * @sram_sel: sram select 798 * @indirect: indirectly write sram 799 * 800 * Disable clock gating for VCN block with dpg mode 801 */ 802 static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 803 uint8_t sram_sel, 804 uint8_t indirect) 805 { 806 struct amdgpu_device *adev = vinst->adev; 807 int inst_idx = vinst->inst; 808 uint32_t reg_data = 0; 809 810 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 811 return; 812 813 /* enable sw clock gating control */ 814 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 815 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 816 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 817 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 818 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 819 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 820 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 821 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 822 UVD_CGC_CTRL__SYS_MODE_MASK | 823 UVD_CGC_CTRL__UDEC_MODE_MASK | 824 UVD_CGC_CTRL__MPEG2_MODE_MASK | 825 UVD_CGC_CTRL__REGS_MODE_MASK | 826 UVD_CGC_CTRL__RBC_MODE_MASK | 827 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 828 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 829 UVD_CGC_CTRL__IDCT_MODE_MASK | 830 UVD_CGC_CTRL__MPRD_MODE_MASK | 831 UVD_CGC_CTRL__MPC_MODE_MASK | 832 UVD_CGC_CTRL__LBSI_MODE_MASK | 833 UVD_CGC_CTRL__LRBBM_MODE_MASK | 834 UVD_CGC_CTRL__WCB_MODE_MASK | 835 UVD_CGC_CTRL__VCPU_MODE_MASK); 836 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 837 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 838 839 /* turn off clock gating */ 840 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 841 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 842 843 /* turn on SUVD clock gating */ 844 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 845 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 846 847 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 848 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 849 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 850 } 851 852 /** 853 * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating 854 * 855 * @vinst: VCN instance 856 * 857 * Enable clock gating for VCN block 858 */ 859 static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 860 { 861 struct amdgpu_device *adev = vinst->adev; 862 int inst = vinst->inst; 863 uint32_t data; 864 865 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 866 return; 867 868 /* enable VCN CGC */ 869 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 870 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 871 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 872 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 873 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 874 875 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 876 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 877 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 878 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 879 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 880 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 881 | UVD_CGC_CTRL__SYS_MODE_MASK 882 | UVD_CGC_CTRL__UDEC_MODE_MASK 883 | UVD_CGC_CTRL__MPEG2_MODE_MASK 884 | UVD_CGC_CTRL__REGS_MODE_MASK 885 | UVD_CGC_CTRL__RBC_MODE_MASK 886 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 887 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 888 | UVD_CGC_CTRL__IDCT_MODE_MASK 889 | UVD_CGC_CTRL__MPRD_MODE_MASK 890 | UVD_CGC_CTRL__MPC_MODE_MASK 891 | UVD_CGC_CTRL__LBSI_MODE_MASK 892 | UVD_CGC_CTRL__LRBBM_MODE_MASK 893 | UVD_CGC_CTRL__WCB_MODE_MASK 894 | UVD_CGC_CTRL__VCPU_MODE_MASK 895 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 896 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 897 898 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 899 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 900 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 901 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 902 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 903 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 904 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 905 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 906 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 907 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 908 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 909 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 910 } 911 912 /** 913 * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode 914 * 915 * @vinst: VCN instance 916 * @indirect: indirectly write sram 917 * 918 * Start VCN block with dpg mode 919 */ 920 static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 921 bool indirect) 922 { 923 struct amdgpu_device *adev = vinst->adev; 924 int inst_idx = vinst->inst; 925 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 926 struct amdgpu_ring *ring; 927 uint32_t tmp; 928 929 /* disable register anti-hang mechanism */ 930 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 931 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 932 /* enable dynamic power gating mode */ 933 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 934 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 935 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 936 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 937 938 if (indirect) 939 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 940 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 941 942 /* enable clock gating */ 943 vcn_v4_0_5_disable_clock_gating_dpg_mode(vinst, 0, indirect); 944 945 /* enable VCPU clock */ 946 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 947 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 948 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 949 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 950 951 /* disable master interrupt */ 952 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 953 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 954 955 /* setup regUVD_LMI_CTRL */ 956 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 957 UVD_LMI_CTRL__REQ_MODE_MASK | 958 UVD_LMI_CTRL__CRC_RESET_MASK | 959 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 960 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 961 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 962 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 963 0x00100000L); 964 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 965 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 966 967 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 968 VCN, inst_idx, regUVD_MPC_CNTL), 969 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 970 971 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 972 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 973 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 974 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 975 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 976 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 977 978 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 979 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 980 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 981 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 982 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 983 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 984 985 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 986 VCN, inst_idx, regUVD_MPC_SET_MUX), 987 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 988 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 989 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 990 991 vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect); 992 993 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 994 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 995 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 996 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 997 998 /* enable LMI MC and UMC channels */ 999 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 1000 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1001 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 1002 1003 /* enable master interrupt */ 1004 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1005 VCN, inst_idx, regUVD_MASTINT_EN), 1006 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1007 1008 if (indirect) 1009 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1010 1011 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1012 1013 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 1014 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1015 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1016 1017 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1018 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1019 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1020 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1021 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1022 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1023 1024 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1025 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1026 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1027 1028 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1029 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1030 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1031 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1032 1033 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1034 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1035 VCN_RB1_DB_CTRL__EN_MASK); 1036 1037 /* Keeping one read-back to ensure all register writes are done, otherwise 1038 * it may introduce race conditions */ 1039 RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL); 1040 1041 return 0; 1042 } 1043 1044 1045 /** 1046 * vcn_v4_0_5_start - VCN start 1047 * 1048 * @vinst: VCN instance 1049 * 1050 * Start VCN block 1051 */ 1052 static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst) 1053 { 1054 struct amdgpu_device *adev = vinst->adev; 1055 int i = vinst->inst; 1056 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1057 struct amdgpu_ring *ring; 1058 uint32_t tmp; 1059 int j, k, r; 1060 1061 if (adev->vcn.harvest_config & (1 << i)) 1062 return 0; 1063 1064 if (adev->pm.dpm_enabled) 1065 amdgpu_dpm_enable_vcn(adev, true, i); 1066 1067 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1068 1069 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1070 return vcn_v4_0_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1071 1072 /* disable VCN power gating */ 1073 vcn_v4_0_5_disable_static_power_gating(vinst); 1074 1075 /* set VCN status busy */ 1076 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1077 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1078 1079 /* SW clock gating */ 1080 vcn_v4_0_5_disable_clock_gating(vinst); 1081 1082 /* enable VCPU clock */ 1083 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1084 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1085 1086 /* disable master interrupt */ 1087 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1088 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1089 1090 /* enable LMI MC and UMC channels */ 1091 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1092 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1093 1094 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1095 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1096 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1097 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1098 1099 /* setup regUVD_LMI_CTRL */ 1100 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1101 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1102 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1103 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1104 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1105 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1106 1107 /* setup regUVD_MPC_CNTL */ 1108 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1109 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1110 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1111 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1112 1113 /* setup UVD_MPC_SET_MUXA0 */ 1114 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1115 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1116 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1117 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1118 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1119 1120 /* setup UVD_MPC_SET_MUXB0 */ 1121 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1122 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1123 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1124 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1125 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1126 1127 /* setup UVD_MPC_SET_MUX */ 1128 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1129 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1130 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1131 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1132 1133 vcn_v4_0_5_mc_resume(vinst); 1134 1135 /* VCN global tiling registers */ 1136 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1137 adev->gfx.config.gb_addr_config); 1138 1139 /* unblock VCPU register access */ 1140 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1141 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1142 1143 /* release VCPU reset to boot */ 1144 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1145 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1146 1147 for (j = 0; j < 10; ++j) { 1148 uint32_t status; 1149 1150 for (k = 0; k < 100; ++k) { 1151 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1152 if (status & 2) 1153 break; 1154 mdelay(10); 1155 if (amdgpu_emu_mode == 1) 1156 msleep(1); 1157 } 1158 1159 if (amdgpu_emu_mode == 1) { 1160 r = -1; 1161 if (status & 2) { 1162 r = 0; 1163 break; 1164 } 1165 } else { 1166 r = 0; 1167 if (status & 2) 1168 break; 1169 1170 dev_err(adev->dev, 1171 "VCN[%d] is not responding, trying to reset VCPU!!!\n", i); 1172 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1173 UVD_VCPU_CNTL__BLK_RST_MASK, 1174 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1175 mdelay(10); 1176 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1177 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1178 1179 mdelay(10); 1180 r = -1; 1181 } 1182 } 1183 1184 if (r) { 1185 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1186 return r; 1187 } 1188 1189 /* enable master interrupt */ 1190 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1191 UVD_MASTINT_EN__VCPU_EN_MASK, 1192 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1193 1194 /* clear the busy bit of VCN_STATUS */ 1195 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1196 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1197 1198 ring = &adev->vcn.inst[i].ring_enc[0]; 1199 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1200 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1201 VCN_RB1_DB_CTRL__EN_MASK); 1202 1203 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1204 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1205 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1206 1207 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1208 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1209 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1210 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1211 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1212 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1213 1214 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1215 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1216 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1217 1218 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1219 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1220 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1221 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1222 1223 /* Keeping one read-back to ensure all register writes are done, otherwise 1224 * it may introduce race conditions */ 1225 RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1226 1227 return 0; 1228 } 1229 1230 /** 1231 * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode 1232 * 1233 * @vinst: VCN instance 1234 * 1235 * Stop VCN block with dpg mode 1236 */ 1237 static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1238 { 1239 struct amdgpu_device *adev = vinst->adev; 1240 int inst_idx = vinst->inst; 1241 uint32_t tmp; 1242 1243 /* Wait for power status to be 1 */ 1244 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1245 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1246 1247 /* wait for read ptr to be equal to write ptr */ 1248 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1249 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1250 1251 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1252 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1253 1254 /* disable dynamic power gating mode */ 1255 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1256 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1257 } 1258 1259 /** 1260 * vcn_v4_0_5_stop - VCN stop 1261 * 1262 * @vinst: VCN instance 1263 * 1264 * Stop VCN block 1265 */ 1266 static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst) 1267 { 1268 struct amdgpu_device *adev = vinst->adev; 1269 int i = vinst->inst; 1270 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1271 uint32_t tmp; 1272 int r = 0; 1273 1274 if (adev->vcn.harvest_config & (1 << i)) 1275 return 0; 1276 1277 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1278 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1279 1280 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1281 vcn_v4_0_5_stop_dpg_mode(vinst); 1282 r = 0; 1283 goto done; 1284 } 1285 1286 /* wait for vcn idle */ 1287 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1288 if (r) 1289 goto done; 1290 1291 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1292 UVD_LMI_STATUS__READ_CLEAN_MASK | 1293 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1294 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1295 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1296 if (r) 1297 goto done; 1298 1299 /* disable LMI UMC channel */ 1300 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1301 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1302 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1303 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1304 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1305 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1306 if (r) 1307 goto done; 1308 1309 /* block VCPU register access */ 1310 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1311 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1312 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1313 1314 /* reset VCPU */ 1315 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1316 UVD_VCPU_CNTL__BLK_RST_MASK, 1317 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1318 1319 /* disable VCPU clock */ 1320 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1321 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1322 1323 /* apply soft reset */ 1324 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1325 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1326 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1327 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1328 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1329 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1330 1331 /* clear status */ 1332 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1333 1334 /* apply HW clock gating */ 1335 vcn_v4_0_5_enable_clock_gating(vinst); 1336 1337 /* enable VCN power gating */ 1338 vcn_v4_0_5_enable_static_power_gating(vinst); 1339 1340 done: 1341 if (adev->pm.dpm_enabled) 1342 amdgpu_dpm_enable_vcn(adev, false, i); 1343 1344 return r; 1345 } 1346 1347 /** 1348 * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode 1349 * 1350 * @vinst: VCN instance 1351 * @new_state: pause state 1352 * 1353 * Pause dpg mode for VCN block 1354 */ 1355 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1356 struct dpg_pause_state *new_state) 1357 { 1358 struct amdgpu_device *adev = vinst->adev; 1359 int inst_idx = vinst->inst; 1360 uint32_t reg_data = 0; 1361 int ret_code; 1362 1363 /* pause/unpause if state is changed */ 1364 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1365 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1366 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1367 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1368 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1369 1370 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1371 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1372 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1373 1374 if (!ret_code) { 1375 /* pause DPG */ 1376 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1377 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1378 1379 /* wait for ACK */ 1380 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1381 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1382 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1383 1384 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1385 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1386 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1387 } 1388 } else { 1389 /* unpause dpg, no need to wait */ 1390 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1391 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1392 } 1393 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1394 } 1395 1396 return 0; 1397 } 1398 1399 /** 1400 * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer 1401 * 1402 * @ring: amdgpu_ring pointer 1403 * 1404 * Returns the current hardware unified read pointer 1405 */ 1406 static uint64_t vcn_v4_0_5_unified_ring_get_rptr(struct amdgpu_ring *ring) 1407 { 1408 struct amdgpu_device *adev = ring->adev; 1409 1410 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1411 DRM_ERROR("wrong ring id is identified in %s", __func__); 1412 1413 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1414 } 1415 1416 /** 1417 * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer 1418 * 1419 * @ring: amdgpu_ring pointer 1420 * 1421 * Returns the current hardware unified write pointer 1422 */ 1423 static uint64_t vcn_v4_0_5_unified_ring_get_wptr(struct amdgpu_ring *ring) 1424 { 1425 struct amdgpu_device *adev = ring->adev; 1426 1427 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1428 DRM_ERROR("wrong ring id is identified in %s", __func__); 1429 1430 if (ring->use_doorbell) 1431 return *ring->wptr_cpu_addr; 1432 else 1433 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1434 } 1435 1436 /** 1437 * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer 1438 * 1439 * @ring: amdgpu_ring pointer 1440 * 1441 * Commits the enc write pointer to the hardware 1442 */ 1443 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring) 1444 { 1445 struct amdgpu_device *adev = ring->adev; 1446 1447 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1448 DRM_ERROR("wrong ring id is identified in %s", __func__); 1449 1450 if (ring->use_doorbell) { 1451 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1452 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1453 } else { 1454 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1455 } 1456 } 1457 1458 static int vcn_v4_0_5_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) 1459 { 1460 struct amdgpu_device *adev = ring->adev; 1461 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1462 1463 if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) 1464 return -EOPNOTSUPP; 1465 1466 vcn_v4_0_5_stop(vinst); 1467 vcn_v4_0_5_start(vinst); 1468 1469 return amdgpu_ring_test_helper(ring); 1470 } 1471 1472 static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { 1473 .type = AMDGPU_RING_TYPE_VCN_ENC, 1474 .align_mask = 0x3f, 1475 .nop = VCN_ENC_CMD_NO_OP, 1476 .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, 1477 .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, 1478 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, 1479 .emit_frame_size = 1480 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1481 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1482 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1483 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1484 1, /* vcn_v2_0_enc_ring_insert_end */ 1485 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1486 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1487 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1488 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1489 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1490 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1491 .insert_nop = amdgpu_ring_insert_nop, 1492 .insert_end = vcn_v2_0_enc_ring_insert_end, 1493 .pad_ib = amdgpu_ring_generic_pad_ib, 1494 .begin_use = amdgpu_vcn_ring_begin_use, 1495 .end_use = amdgpu_vcn_ring_end_use, 1496 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1497 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1498 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1499 .reset = vcn_v4_0_5_ring_reset, 1500 }; 1501 1502 /** 1503 * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions 1504 * 1505 * @adev: amdgpu_device pointer 1506 * 1507 * Set unified ring functions 1508 */ 1509 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev) 1510 { 1511 int i; 1512 1513 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1514 if (adev->vcn.harvest_config & (1 << i)) 1515 continue; 1516 1517 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) 1518 vcn_v4_0_5_unified_ring_vm_funcs.secure_submission_supported = true; 1519 1520 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs; 1521 adev->vcn.inst[i].ring_enc[0].me = i; 1522 } 1523 } 1524 1525 /** 1526 * vcn_v4_0_5_is_idle - check VCN block is idle 1527 * 1528 * @ip_block: Pointer to the amdgpu_ip_block structure 1529 * 1530 * Check whether VCN block is idle 1531 */ 1532 static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block) 1533 { 1534 struct amdgpu_device *adev = ip_block->adev; 1535 int i, ret = 1; 1536 1537 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1538 if (adev->vcn.harvest_config & (1 << i)) 1539 continue; 1540 1541 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1542 } 1543 1544 return ret; 1545 } 1546 1547 /** 1548 * vcn_v4_0_5_wait_for_idle - wait for VCN block idle 1549 * 1550 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1551 * 1552 * Wait for VCN block idle 1553 */ 1554 static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 1555 { 1556 struct amdgpu_device *adev = ip_block->adev; 1557 int i, ret = 0; 1558 1559 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1560 if (adev->vcn.harvest_config & (1 << i)) 1561 continue; 1562 1563 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1564 UVD_STATUS__IDLE); 1565 if (ret) 1566 return ret; 1567 } 1568 1569 return ret; 1570 } 1571 1572 /** 1573 * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state 1574 * 1575 * @ip_block: amdgpu_ip_block pointer 1576 * @state: clock gating state 1577 * 1578 * Set VCN block clockgating state 1579 */ 1580 static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1581 enum amd_clockgating_state state) 1582 { 1583 struct amdgpu_device *adev = ip_block->adev; 1584 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1585 int i; 1586 1587 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1588 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1589 1590 if (adev->vcn.harvest_config & (1 << i)) 1591 continue; 1592 1593 if (enable) { 1594 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1595 return -EBUSY; 1596 vcn_v4_0_5_enable_clock_gating(vinst); 1597 } else { 1598 vcn_v4_0_5_disable_clock_gating(vinst); 1599 } 1600 } 1601 1602 return 0; 1603 } 1604 1605 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 1606 enum amd_powergating_state state) 1607 { 1608 int ret = 0; 1609 1610 if (state == vinst->cur_state) 1611 return 0; 1612 1613 if (state == AMD_PG_STATE_GATE) 1614 ret = vcn_v4_0_5_stop(vinst); 1615 else 1616 ret = vcn_v4_0_5_start(vinst); 1617 1618 if (!ret) 1619 vinst->cur_state = state; 1620 1621 return ret; 1622 } 1623 1624 /** 1625 * vcn_v4_0_5_process_interrupt - process VCN block interrupt 1626 * 1627 * @adev: amdgpu_device pointer 1628 * @source: interrupt sources 1629 * @entry: interrupt entry from clients and sources 1630 * 1631 * Process VCN block interrupt 1632 */ 1633 static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1634 struct amdgpu_iv_entry *entry) 1635 { 1636 uint32_t ip_instance; 1637 1638 switch (entry->client_id) { 1639 case SOC15_IH_CLIENTID_VCN: 1640 ip_instance = 0; 1641 break; 1642 case SOC15_IH_CLIENTID_VCN1: 1643 ip_instance = 1; 1644 break; 1645 default: 1646 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1647 return 0; 1648 } 1649 1650 DRM_DEBUG("IH: VCN TRAP\n"); 1651 1652 switch (entry->src_id) { 1653 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1654 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1655 break; 1656 case VCN_4_0__SRCID_UVD_POISON: 1657 amdgpu_vcn_process_poison_irq(adev, source, entry); 1658 break; 1659 default: 1660 DRM_ERROR("Unhandled interrupt: %d %d\n", 1661 entry->src_id, entry->src_data[0]); 1662 break; 1663 } 1664 1665 return 0; 1666 } 1667 1668 static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = { 1669 .process = vcn_v4_0_5_process_interrupt, 1670 }; 1671 1672 /** 1673 * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions 1674 * 1675 * @adev: amdgpu_device pointer 1676 * 1677 * Set VCN block interrupt irq functions 1678 */ 1679 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) 1680 { 1681 int i; 1682 1683 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1684 if (adev->vcn.harvest_config & (1 << i)) 1685 continue; 1686 1687 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 1688 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs; 1689 } 1690 } 1691 1692 static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1693 { 1694 struct amdgpu_device *adev = ip_block->adev; 1695 int i, j; 1696 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 1697 uint32_t inst_off, is_powered; 1698 1699 if (!adev->vcn.ip_dump) 1700 return; 1701 1702 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1703 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1704 if (adev->vcn.harvest_config & (1 << i)) { 1705 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1706 continue; 1707 } 1708 1709 inst_off = i * reg_count; 1710 is_powered = (adev->vcn.ip_dump[inst_off] & 1711 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1712 1713 if (is_powered) { 1714 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1715 for (j = 0; j < reg_count; j++) 1716 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name, 1717 adev->vcn.ip_dump[inst_off + j]); 1718 } else { 1719 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1720 } 1721 } 1722 } 1723 1724 static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block) 1725 { 1726 struct amdgpu_device *adev = ip_block->adev; 1727 int i, j; 1728 bool is_powered; 1729 uint32_t inst_off; 1730 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 1731 1732 if (!adev->vcn.ip_dump) 1733 return; 1734 1735 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1736 if (adev->vcn.harvest_config & (1 << i)) 1737 continue; 1738 1739 inst_off = i * reg_count; 1740 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1741 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); 1742 is_powered = (adev->vcn.ip_dump[inst_off] & 1743 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1744 1745 if (is_powered) 1746 for (j = 1; j < reg_count; j++) 1747 adev->vcn.ip_dump[inst_off + j] = 1748 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j], 1749 i)); 1750 } 1751 } 1752 1753 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { 1754 .name = "vcn_v4_0_5", 1755 .early_init = vcn_v4_0_5_early_init, 1756 .sw_init = vcn_v4_0_5_sw_init, 1757 .sw_fini = vcn_v4_0_5_sw_fini, 1758 .hw_init = vcn_v4_0_5_hw_init, 1759 .hw_fini = vcn_v4_0_5_hw_fini, 1760 .suspend = vcn_v4_0_5_suspend, 1761 .resume = vcn_v4_0_5_resume, 1762 .is_idle = vcn_v4_0_5_is_idle, 1763 .wait_for_idle = vcn_v4_0_5_wait_for_idle, 1764 .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, 1765 .set_powergating_state = vcn_set_powergating_state, 1766 .dump_ip_state = vcn_v4_0_5_dump_ip_state, 1767 .print_ip_state = vcn_v4_0_5_print_ip_state, 1768 }; 1769 1770 const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = { 1771 .type = AMD_IP_BLOCK_TYPE_VCN, 1772 .major = 4, 1773 .minor = 0, 1774 .rev = 5, 1775 .funcs = &vcn_v4_0_5_ip_funcs, 1776 }; 1777