1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0_5.h" 35 36 #include "vcn/vcn_4_0_5_offset.h" 37 #include "vcn/vcn_4_0_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 (0x48300 + 0x38000) 49 50 #define VCN_HARVEST_MMSCH 0 51 52 #define RDECODE_MSG_CREATE 0x00000000 53 #define RDECODE_MESSAGE_CREATE 0x00000001 54 55 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = { 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 84 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 87 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 89 }; 90 91 static int amdgpu_ih_clientid_vcns[] = { 92 SOC15_IH_CLIENTID_VCN, 93 SOC15_IH_CLIENTID_VCN1 94 }; 95 96 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev); 97 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev); 98 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 99 enum amd_powergating_state state); 100 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 101 struct dpg_pause_state *new_state); 102 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring); 103 104 /** 105 * vcn_v4_0_5_early_init - set function pointers and load microcode 106 * 107 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 108 * 109 * Set ring and irq function pointers 110 * Load microcode from filesystem 111 */ 112 static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) 113 { 114 struct amdgpu_device *adev = ip_block->adev; 115 int i, r; 116 117 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6)) 118 adev->vcn.per_inst_fw = true; 119 120 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 121 /* re-use enc ring as unified ring */ 122 adev->vcn.inst[i].num_enc_rings = 1; 123 vcn_v4_0_5_set_unified_ring_funcs(adev); 124 vcn_v4_0_5_set_irq_funcs(adev); 125 126 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 127 adev->vcn.inst[i].set_pg_state = vcn_v4_0_5_set_pg_state; 128 129 r = amdgpu_vcn_early_init(adev, i); 130 if (r) 131 return r; 132 } 133 134 return 0; 135 } 136 137 /** 138 * vcn_v4_0_5_sw_init - sw init for VCN block 139 * 140 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 141 * 142 * Load firmware and sw initialization 143 */ 144 static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) 145 { 146 struct amdgpu_ring *ring; 147 struct amdgpu_device *adev = ip_block->adev; 148 int i, r; 149 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 150 uint32_t *ptr; 151 152 153 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 154 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 155 156 if (adev->vcn.harvest_config & (1 << i)) 157 continue; 158 159 r = amdgpu_vcn_sw_init(adev, i); 160 if (r) 161 return r; 162 163 amdgpu_vcn_setup_ucode(adev, i); 164 165 r = amdgpu_vcn_resume(adev, i); 166 if (r) 167 return r; 168 169 atomic_set(&adev->vcn.inst[i].sched_score, 0); 170 171 /* VCN UNIFIED TRAP */ 172 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 173 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 174 if (r) 175 return r; 176 177 /* VCN POISON TRAP */ 178 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 179 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 180 if (r) 181 return r; 182 183 ring = &adev->vcn.inst[i].ring_enc[0]; 184 ring->use_doorbell = true; 185 if (amdgpu_sriov_vf(adev)) 186 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 187 i * (adev->vcn.inst[i].num_enc_rings + 1) + 1; 188 else 189 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 190 2 + 8 * i; 191 ring->vm_hub = AMDGPU_MMHUB0(0); 192 sprintf(ring->name, "vcn_unified_%d", i); 193 194 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 195 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 196 if (r) 197 return r; 198 199 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 200 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 201 fw_shared->sq.is_enabled = 1; 202 203 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 204 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 205 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 206 207 if (amdgpu_sriov_vf(adev)) 208 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 209 210 if (amdgpu_vcnfw_log) 211 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 212 213 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 214 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode; 215 } 216 217 if (amdgpu_sriov_vf(adev)) { 218 r = amdgpu_virt_alloc_mm_table(adev); 219 if (r) 220 return r; 221 } 222 223 /* Allocate memory for VCN IP Dump buffer */ 224 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 225 if (!ptr) { 226 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 227 adev->vcn.ip_dump = NULL; 228 } else { 229 adev->vcn.ip_dump = ptr; 230 } 231 return 0; 232 } 233 234 /** 235 * vcn_v4_0_5_sw_fini - sw fini for VCN block 236 * 237 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 238 * 239 * VCN suspend and free up sw allocation 240 */ 241 static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) 242 { 243 struct amdgpu_device *adev = ip_block->adev; 244 int i, r, idx; 245 246 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 247 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 248 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 249 250 if (adev->vcn.harvest_config & (1 << i)) 251 continue; 252 253 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 254 fw_shared->present_flag_0 = 0; 255 fw_shared->sq.is_enabled = 0; 256 } 257 258 drm_dev_exit(idx); 259 } 260 261 if (amdgpu_sriov_vf(adev)) 262 amdgpu_virt_free_mm_table(adev); 263 264 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 265 r = amdgpu_vcn_suspend(adev, i); 266 if (r) 267 return r; 268 269 r = amdgpu_vcn_sw_fini(adev, i); 270 if (r) 271 return r; 272 } 273 274 kfree(adev->vcn.ip_dump); 275 276 return 0; 277 } 278 279 /** 280 * vcn_v4_0_5_hw_init - start and test VCN block 281 * 282 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 283 * 284 * Initialize the hardware, boot up the VCPU and do some testing 285 */ 286 static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) 287 { 288 struct amdgpu_device *adev = ip_block->adev; 289 struct amdgpu_ring *ring; 290 int i, r; 291 292 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 293 if (adev->vcn.harvest_config & (1 << i)) 294 continue; 295 296 ring = &adev->vcn.inst[i].ring_enc[0]; 297 298 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 299 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 300 301 r = amdgpu_ring_test_helper(ring); 302 if (r) 303 return r; 304 } 305 306 return 0; 307 } 308 309 /** 310 * vcn_v4_0_5_hw_fini - stop the hardware block 311 * 312 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 313 * 314 * Stop the VCN block, mark ring as not ready any more 315 */ 316 static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block) 317 { 318 struct amdgpu_device *adev = ip_block->adev; 319 int i; 320 321 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 322 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 323 324 if (adev->vcn.harvest_config & (1 << i)) 325 continue; 326 327 cancel_delayed_work_sync(&vinst->idle_work); 328 329 if (!amdgpu_sriov_vf(adev)) { 330 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 331 (vinst->cur_state != AMD_PG_STATE_GATE && 332 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 333 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 334 } 335 } 336 } 337 338 return 0; 339 } 340 341 /** 342 * vcn_v4_0_5_suspend - suspend VCN block 343 * 344 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 345 * 346 * HW fini and suspend VCN block 347 */ 348 static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) 349 { 350 struct amdgpu_device *adev = ip_block->adev; 351 int r, i; 352 353 r = vcn_v4_0_5_hw_fini(ip_block); 354 if (r) 355 return r; 356 357 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 358 r = amdgpu_vcn_suspend(ip_block->adev, i); 359 if (r) 360 return r; 361 } 362 363 return r; 364 } 365 366 /** 367 * vcn_v4_0_5_resume - resume VCN block 368 * 369 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 370 * 371 * Resume firmware and hw init VCN block 372 */ 373 static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block) 374 { 375 struct amdgpu_device *adev = ip_block->adev; 376 int r, i; 377 378 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 379 r = amdgpu_vcn_resume(ip_block->adev, i); 380 if (r) 381 return r; 382 } 383 384 r = vcn_v4_0_5_hw_init(ip_block); 385 386 return r; 387 } 388 389 /** 390 * vcn_v4_0_5_mc_resume - memory controller programming 391 * 392 * @vinst: VCN instance 393 * 394 * Let the VCN memory controller know it's offsets 395 */ 396 static void vcn_v4_0_5_mc_resume(struct amdgpu_vcn_inst *vinst) 397 { 398 struct amdgpu_device *adev = vinst->adev; 399 int inst = vinst->inst; 400 uint32_t offset, size; 401 const struct common_firmware_header *hdr; 402 403 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 404 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 405 406 /* cache window 0: fw */ 407 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 408 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 409 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 410 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 411 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 412 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 413 offset = 0; 414 } else { 415 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 416 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 417 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 418 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 419 offset = size; 420 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 421 } 422 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 423 424 /* cache window 1: stack */ 425 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 426 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 427 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 428 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 429 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 430 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 431 432 /* cache window 2: context */ 433 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 434 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 435 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 436 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 437 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 438 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 439 440 /* non-cache window */ 441 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 442 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 443 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 444 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 445 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 446 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 447 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 448 } 449 450 /** 451 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode 452 * 453 * @vinst: VCN instance 454 * @indirect: indirectly write sram 455 * 456 * Let the VCN memory controller know it's offsets with dpg mode 457 */ 458 static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 459 bool indirect) 460 { 461 struct amdgpu_device *adev = vinst->adev; 462 int inst_idx = vinst->inst; 463 uint32_t offset, size; 464 const struct common_firmware_header *hdr; 465 466 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 467 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 468 469 /* cache window 0: fw */ 470 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 471 if (!indirect) { 472 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 473 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 474 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 475 0, indirect); 476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 477 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 478 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 479 0, indirect); 480 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 481 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 482 } else { 483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 484 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 486 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 488 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 489 } 490 offset = 0; 491 } else { 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 494 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 496 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 497 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 498 offset = size; 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 501 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 502 } 503 504 if (!indirect) 505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 506 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 507 else 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 510 511 /* cache window 1: stack */ 512 if (!indirect) { 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 515 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 516 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 517 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 518 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 520 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 521 } else { 522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 523 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 525 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 528 } 529 530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 531 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 532 533 /* cache window 2: context */ 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 536 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 537 0, indirect); 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 540 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 541 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 545 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 546 547 /* non-cache window */ 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 549 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 550 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 553 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 558 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 559 560 /* VCN global tiling registers */ 561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 562 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 563 adev->gfx.config.gb_addr_config, 0, indirect); 564 } 565 566 /** 567 * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating 568 * 569 * @vinst: VCN instance 570 * 571 * Disable static power gating for VCN block 572 */ 573 static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 574 { 575 struct amdgpu_device *adev = vinst->adev; 576 int inst = vinst->inst; 577 uint32_t data = 0; 578 579 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 580 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 581 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 582 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 583 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 584 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 585 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 586 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 587 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 588 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 589 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 590 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 591 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 592 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 593 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 594 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 595 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 596 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 597 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 598 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 599 } else { 600 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 601 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 602 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 603 0, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 604 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 605 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 606 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 607 0, UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 608 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 609 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 610 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 611 0, UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 612 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 613 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 614 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 615 0, UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 616 } 617 618 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 619 data &= ~0x103; 620 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 621 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 622 UVD_POWER_STATUS__UVD_PG_EN_MASK; 623 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 624 } 625 626 /** 627 * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating 628 * 629 * @vinst: VCN instance 630 * 631 * Enable static power gating for VCN block 632 */ 633 static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 634 { 635 struct amdgpu_device *adev = vinst->adev; 636 int inst = vinst->inst; 637 uint32_t data; 638 639 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 640 /* Before power off, this indicator has to be turned on */ 641 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 642 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 643 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 644 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 645 646 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 647 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 648 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 649 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 650 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 651 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 652 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 653 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 654 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 655 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 656 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 657 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 658 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 659 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 660 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 661 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 662 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 663 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 664 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 665 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 666 } 667 } 668 669 /** 670 * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating 671 * 672 * @vinst: VCN instance 673 * 674 * Disable clock gating for VCN block 675 */ 676 static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 677 { 678 struct amdgpu_device *adev = vinst->adev; 679 int inst = vinst->inst; 680 uint32_t data; 681 682 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 683 return; 684 685 /* VCN disable CGC */ 686 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 687 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 688 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 689 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 690 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 691 692 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 693 data &= ~(UVD_CGC_GATE__SYS_MASK 694 | UVD_CGC_GATE__UDEC_MASK 695 | UVD_CGC_GATE__MPEG2_MASK 696 | UVD_CGC_GATE__REGS_MASK 697 | UVD_CGC_GATE__RBC_MASK 698 | UVD_CGC_GATE__LMI_MC_MASK 699 | UVD_CGC_GATE__LMI_UMC_MASK 700 | UVD_CGC_GATE__IDCT_MASK 701 | UVD_CGC_GATE__MPRD_MASK 702 | UVD_CGC_GATE__MPC_MASK 703 | UVD_CGC_GATE__LBSI_MASK 704 | UVD_CGC_GATE__LRBBM_MASK 705 | UVD_CGC_GATE__UDEC_RE_MASK 706 | UVD_CGC_GATE__UDEC_CM_MASK 707 | UVD_CGC_GATE__UDEC_IT_MASK 708 | UVD_CGC_GATE__UDEC_DB_MASK 709 | UVD_CGC_GATE__UDEC_MP_MASK 710 | UVD_CGC_GATE__WCB_MASK 711 | UVD_CGC_GATE__VCPU_MASK 712 | UVD_CGC_GATE__MMSCH_MASK); 713 714 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 715 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 716 717 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 718 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 719 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 720 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 721 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 722 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 723 | UVD_CGC_CTRL__SYS_MODE_MASK 724 | UVD_CGC_CTRL__UDEC_MODE_MASK 725 | UVD_CGC_CTRL__MPEG2_MODE_MASK 726 | UVD_CGC_CTRL__REGS_MODE_MASK 727 | UVD_CGC_CTRL__RBC_MODE_MASK 728 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 729 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 730 | UVD_CGC_CTRL__IDCT_MODE_MASK 731 | UVD_CGC_CTRL__MPRD_MODE_MASK 732 | UVD_CGC_CTRL__MPC_MODE_MASK 733 | UVD_CGC_CTRL__LBSI_MODE_MASK 734 | UVD_CGC_CTRL__LRBBM_MODE_MASK 735 | UVD_CGC_CTRL__WCB_MODE_MASK 736 | UVD_CGC_CTRL__VCPU_MODE_MASK 737 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 738 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 739 740 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 741 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 742 | UVD_SUVD_CGC_GATE__SIT_MASK 743 | UVD_SUVD_CGC_GATE__SMP_MASK 744 | UVD_SUVD_CGC_GATE__SCM_MASK 745 | UVD_SUVD_CGC_GATE__SDB_MASK 746 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 747 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 748 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 749 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 750 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 751 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 752 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 753 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 754 | UVD_SUVD_CGC_GATE__SCLR_MASK 755 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 756 | UVD_SUVD_CGC_GATE__ENT_MASK 757 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 758 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 759 | UVD_SUVD_CGC_GATE__SITE_MASK 760 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 761 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 762 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 763 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 764 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 765 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 766 767 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 768 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 769 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 770 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 771 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 772 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 773 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 774 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 775 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 776 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 777 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 778 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 779 } 780 781 /** 782 * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 783 * 784 * @vinst: VCN instance 785 * @sram_sel: sram select 786 * @indirect: indirectly write sram 787 * 788 * Disable clock gating for VCN block with dpg mode 789 */ 790 static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 791 uint8_t sram_sel, 792 uint8_t indirect) 793 { 794 struct amdgpu_device *adev = vinst->adev; 795 int inst_idx = vinst->inst; 796 uint32_t reg_data = 0; 797 798 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 799 return; 800 801 /* enable sw clock gating control */ 802 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 803 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 804 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 805 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 806 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 807 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 808 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 809 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 810 UVD_CGC_CTRL__SYS_MODE_MASK | 811 UVD_CGC_CTRL__UDEC_MODE_MASK | 812 UVD_CGC_CTRL__MPEG2_MODE_MASK | 813 UVD_CGC_CTRL__REGS_MODE_MASK | 814 UVD_CGC_CTRL__RBC_MODE_MASK | 815 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 816 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 817 UVD_CGC_CTRL__IDCT_MODE_MASK | 818 UVD_CGC_CTRL__MPRD_MODE_MASK | 819 UVD_CGC_CTRL__MPC_MODE_MASK | 820 UVD_CGC_CTRL__LBSI_MODE_MASK | 821 UVD_CGC_CTRL__LRBBM_MODE_MASK | 822 UVD_CGC_CTRL__WCB_MODE_MASK | 823 UVD_CGC_CTRL__VCPU_MODE_MASK); 824 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 825 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 826 827 /* turn off clock gating */ 828 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 829 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 830 831 /* turn on SUVD clock gating */ 832 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 833 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 834 835 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 836 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 837 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 838 } 839 840 /** 841 * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating 842 * 843 * @vinst: VCN instance 844 * 845 * Enable clock gating for VCN block 846 */ 847 static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 848 { 849 struct amdgpu_device *adev = vinst->adev; 850 int inst = vinst->inst; 851 uint32_t data; 852 853 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 854 return; 855 856 /* enable VCN CGC */ 857 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 858 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 859 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 860 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 861 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 862 863 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 864 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 865 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 866 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 867 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 868 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 869 | UVD_CGC_CTRL__SYS_MODE_MASK 870 | UVD_CGC_CTRL__UDEC_MODE_MASK 871 | UVD_CGC_CTRL__MPEG2_MODE_MASK 872 | UVD_CGC_CTRL__REGS_MODE_MASK 873 | UVD_CGC_CTRL__RBC_MODE_MASK 874 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 875 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 876 | UVD_CGC_CTRL__IDCT_MODE_MASK 877 | UVD_CGC_CTRL__MPRD_MODE_MASK 878 | UVD_CGC_CTRL__MPC_MODE_MASK 879 | UVD_CGC_CTRL__LBSI_MODE_MASK 880 | UVD_CGC_CTRL__LRBBM_MODE_MASK 881 | UVD_CGC_CTRL__WCB_MODE_MASK 882 | UVD_CGC_CTRL__VCPU_MODE_MASK 883 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 884 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 885 886 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 887 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 888 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 889 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 890 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 891 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 892 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 893 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 894 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 895 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 896 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 897 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 898 } 899 900 /** 901 * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode 902 * 903 * @vinst: VCN instance 904 * @indirect: indirectly write sram 905 * 906 * Start VCN block with dpg mode 907 */ 908 static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 909 bool indirect) 910 { 911 struct amdgpu_device *adev = vinst->adev; 912 int inst_idx = vinst->inst; 913 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 914 struct amdgpu_ring *ring; 915 uint32_t tmp; 916 917 /* disable register anti-hang mechanism */ 918 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 919 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 920 /* enable dynamic power gating mode */ 921 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 922 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 923 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 924 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 925 926 if (indirect) 927 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 928 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 929 930 /* enable clock gating */ 931 vcn_v4_0_5_disable_clock_gating_dpg_mode(vinst, 0, indirect); 932 933 /* enable VCPU clock */ 934 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 935 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 936 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 937 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 938 939 /* disable master interrupt */ 940 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 941 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 942 943 /* setup regUVD_LMI_CTRL */ 944 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 945 UVD_LMI_CTRL__REQ_MODE_MASK | 946 UVD_LMI_CTRL__CRC_RESET_MASK | 947 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 948 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 949 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 950 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 951 0x00100000L); 952 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 953 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 954 955 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 956 VCN, inst_idx, regUVD_MPC_CNTL), 957 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 958 959 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 960 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 961 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 962 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 963 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 964 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 965 966 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 967 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 968 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 969 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 970 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 971 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 972 973 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 974 VCN, inst_idx, regUVD_MPC_SET_MUX), 975 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 976 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 977 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 978 979 vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect); 980 981 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 982 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 983 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 984 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 985 986 /* enable LMI MC and UMC channels */ 987 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 988 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 989 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 990 991 /* enable master interrupt */ 992 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 993 VCN, inst_idx, regUVD_MASTINT_EN), 994 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 995 996 if (indirect) 997 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 998 999 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1000 1001 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 1002 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1003 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1004 1005 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1006 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1007 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1008 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1009 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1010 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1011 1012 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1013 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1014 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1015 1016 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1017 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1018 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1019 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1020 1021 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1022 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1023 VCN_RB1_DB_CTRL__EN_MASK); 1024 1025 return 0; 1026 } 1027 1028 1029 /** 1030 * vcn_v4_0_5_start - VCN start 1031 * 1032 * @vinst: VCN instance 1033 * 1034 * Start VCN block 1035 */ 1036 static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst) 1037 { 1038 struct amdgpu_device *adev = vinst->adev; 1039 int i = vinst->inst; 1040 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1041 struct amdgpu_ring *ring; 1042 uint32_t tmp; 1043 int j, k, r; 1044 1045 if (adev->vcn.harvest_config & (1 << i)) 1046 return 0; 1047 1048 if (adev->pm.dpm_enabled) 1049 amdgpu_dpm_enable_vcn(adev, true, i); 1050 1051 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1052 1053 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1054 return vcn_v4_0_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1055 1056 /* disable VCN power gating */ 1057 vcn_v4_0_5_disable_static_power_gating(vinst); 1058 1059 /* set VCN status busy */ 1060 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1061 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1062 1063 /* SW clock gating */ 1064 vcn_v4_0_5_disable_clock_gating(vinst); 1065 1066 /* enable VCPU clock */ 1067 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1068 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1069 1070 /* disable master interrupt */ 1071 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1072 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1073 1074 /* enable LMI MC and UMC channels */ 1075 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1076 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1077 1078 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1079 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1080 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1081 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1082 1083 /* setup regUVD_LMI_CTRL */ 1084 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1085 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1086 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1087 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1088 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1089 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1090 1091 /* setup regUVD_MPC_CNTL */ 1092 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1093 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1094 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1095 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1096 1097 /* setup UVD_MPC_SET_MUXA0 */ 1098 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1099 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1100 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1101 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1102 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1103 1104 /* setup UVD_MPC_SET_MUXB0 */ 1105 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1106 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1107 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1108 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1109 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1110 1111 /* setup UVD_MPC_SET_MUX */ 1112 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1113 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1114 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1115 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1116 1117 vcn_v4_0_5_mc_resume(vinst); 1118 1119 /* VCN global tiling registers */ 1120 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1121 adev->gfx.config.gb_addr_config); 1122 1123 /* unblock VCPU register access */ 1124 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1125 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1126 1127 /* release VCPU reset to boot */ 1128 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1129 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1130 1131 for (j = 0; j < 10; ++j) { 1132 uint32_t status; 1133 1134 for (k = 0; k < 100; ++k) { 1135 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1136 if (status & 2) 1137 break; 1138 mdelay(10); 1139 if (amdgpu_emu_mode == 1) 1140 msleep(1); 1141 } 1142 1143 if (amdgpu_emu_mode == 1) { 1144 r = -1; 1145 if (status & 2) { 1146 r = 0; 1147 break; 1148 } 1149 } else { 1150 r = 0; 1151 if (status & 2) 1152 break; 1153 1154 dev_err(adev->dev, 1155 "VCN[%d] is not responding, trying to reset VCPU!!!\n", i); 1156 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1157 UVD_VCPU_CNTL__BLK_RST_MASK, 1158 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1159 mdelay(10); 1160 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1161 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1162 1163 mdelay(10); 1164 r = -1; 1165 } 1166 } 1167 1168 if (r) { 1169 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1170 return r; 1171 } 1172 1173 /* enable master interrupt */ 1174 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1175 UVD_MASTINT_EN__VCPU_EN_MASK, 1176 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1177 1178 /* clear the busy bit of VCN_STATUS */ 1179 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1180 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1181 1182 ring = &adev->vcn.inst[i].ring_enc[0]; 1183 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1184 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1185 VCN_RB1_DB_CTRL__EN_MASK); 1186 1187 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1188 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1189 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1190 1191 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1192 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1193 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1194 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1195 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1196 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1197 1198 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1199 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1200 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1201 1202 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1203 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1204 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1205 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1206 1207 return 0; 1208 } 1209 1210 /** 1211 * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode 1212 * 1213 * @vinst: VCN instance 1214 * 1215 * Stop VCN block with dpg mode 1216 */ 1217 static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1218 { 1219 struct amdgpu_device *adev = vinst->adev; 1220 int inst_idx = vinst->inst; 1221 uint32_t tmp; 1222 1223 /* Wait for power status to be 1 */ 1224 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1225 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1226 1227 /* wait for read ptr to be equal to write ptr */ 1228 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1229 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1230 1231 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1232 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1233 1234 /* disable dynamic power gating mode */ 1235 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1236 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1237 } 1238 1239 /** 1240 * vcn_v4_0_5_stop - VCN stop 1241 * 1242 * @vinst: VCN instance 1243 * 1244 * Stop VCN block 1245 */ 1246 static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst) 1247 { 1248 struct amdgpu_device *adev = vinst->adev; 1249 int i = vinst->inst; 1250 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1251 uint32_t tmp; 1252 int r = 0; 1253 1254 if (adev->vcn.harvest_config & (1 << i)) 1255 return 0; 1256 1257 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1258 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1259 1260 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1261 vcn_v4_0_5_stop_dpg_mode(vinst); 1262 r = 0; 1263 goto done; 1264 } 1265 1266 /* wait for vcn idle */ 1267 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1268 if (r) 1269 goto done; 1270 1271 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1272 UVD_LMI_STATUS__READ_CLEAN_MASK | 1273 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1274 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1275 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1276 if (r) 1277 goto done; 1278 1279 /* disable LMI UMC channel */ 1280 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1281 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1282 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1283 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1284 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1285 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1286 if (r) 1287 goto done; 1288 1289 /* block VCPU register access */ 1290 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1291 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1292 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1293 1294 /* reset VCPU */ 1295 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1296 UVD_VCPU_CNTL__BLK_RST_MASK, 1297 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1298 1299 /* disable VCPU clock */ 1300 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1301 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1302 1303 /* apply soft reset */ 1304 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1305 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1306 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1307 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1308 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1309 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1310 1311 /* clear status */ 1312 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1313 1314 /* apply HW clock gating */ 1315 vcn_v4_0_5_enable_clock_gating(vinst); 1316 1317 /* enable VCN power gating */ 1318 vcn_v4_0_5_enable_static_power_gating(vinst); 1319 1320 done: 1321 if (adev->pm.dpm_enabled) 1322 amdgpu_dpm_enable_vcn(adev, false, i); 1323 1324 return r; 1325 } 1326 1327 /** 1328 * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode 1329 * 1330 * @vinst: VCN instance 1331 * @new_state: pause state 1332 * 1333 * Pause dpg mode for VCN block 1334 */ 1335 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1336 struct dpg_pause_state *new_state) 1337 { 1338 struct amdgpu_device *adev = vinst->adev; 1339 int inst_idx = vinst->inst; 1340 uint32_t reg_data = 0; 1341 int ret_code; 1342 1343 /* pause/unpause if state is changed */ 1344 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1345 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1346 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1347 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1348 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1349 1350 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1351 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1352 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1353 1354 if (!ret_code) { 1355 /* pause DPG */ 1356 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1357 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1358 1359 /* wait for ACK */ 1360 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1361 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1362 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1363 1364 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1365 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1366 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1367 } 1368 } else { 1369 /* unpause dpg, no need to wait */ 1370 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1371 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1372 } 1373 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1374 } 1375 1376 return 0; 1377 } 1378 1379 /** 1380 * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer 1381 * 1382 * @ring: amdgpu_ring pointer 1383 * 1384 * Returns the current hardware unified read pointer 1385 */ 1386 static uint64_t vcn_v4_0_5_unified_ring_get_rptr(struct amdgpu_ring *ring) 1387 { 1388 struct amdgpu_device *adev = ring->adev; 1389 1390 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1391 DRM_ERROR("wrong ring id is identified in %s", __func__); 1392 1393 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1394 } 1395 1396 /** 1397 * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer 1398 * 1399 * @ring: amdgpu_ring pointer 1400 * 1401 * Returns the current hardware unified write pointer 1402 */ 1403 static uint64_t vcn_v4_0_5_unified_ring_get_wptr(struct amdgpu_ring *ring) 1404 { 1405 struct amdgpu_device *adev = ring->adev; 1406 1407 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1408 DRM_ERROR("wrong ring id is identified in %s", __func__); 1409 1410 if (ring->use_doorbell) 1411 return *ring->wptr_cpu_addr; 1412 else 1413 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1414 } 1415 1416 /** 1417 * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer 1418 * 1419 * @ring: amdgpu_ring pointer 1420 * 1421 * Commits the enc write pointer to the hardware 1422 */ 1423 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring) 1424 { 1425 struct amdgpu_device *adev = ring->adev; 1426 1427 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1428 DRM_ERROR("wrong ring id is identified in %s", __func__); 1429 1430 if (ring->use_doorbell) { 1431 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1432 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1433 } else { 1434 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1435 } 1436 } 1437 1438 static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { 1439 .type = AMDGPU_RING_TYPE_VCN_ENC, 1440 .align_mask = 0x3f, 1441 .nop = VCN_ENC_CMD_NO_OP, 1442 .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, 1443 .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, 1444 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, 1445 .emit_frame_size = 1446 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1447 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1448 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1449 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1450 1, /* vcn_v2_0_enc_ring_insert_end */ 1451 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1452 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1453 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1454 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1455 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1456 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1457 .insert_nop = amdgpu_ring_insert_nop, 1458 .insert_end = vcn_v2_0_enc_ring_insert_end, 1459 .pad_ib = amdgpu_ring_generic_pad_ib, 1460 .begin_use = amdgpu_vcn_ring_begin_use, 1461 .end_use = amdgpu_vcn_ring_end_use, 1462 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1463 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1464 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1465 }; 1466 1467 /** 1468 * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions 1469 * 1470 * @adev: amdgpu_device pointer 1471 * 1472 * Set unified ring functions 1473 */ 1474 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev) 1475 { 1476 int i; 1477 1478 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1479 if (adev->vcn.harvest_config & (1 << i)) 1480 continue; 1481 1482 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) 1483 vcn_v4_0_5_unified_ring_vm_funcs.secure_submission_supported = true; 1484 1485 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs; 1486 adev->vcn.inst[i].ring_enc[0].me = i; 1487 } 1488 } 1489 1490 /** 1491 * vcn_v4_0_5_is_idle - check VCN block is idle 1492 * 1493 * @ip_block: Pointer to the amdgpu_ip_block structure 1494 * 1495 * Check whether VCN block is idle 1496 */ 1497 static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block) 1498 { 1499 struct amdgpu_device *adev = ip_block->adev; 1500 int i, ret = 1; 1501 1502 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1503 if (adev->vcn.harvest_config & (1 << i)) 1504 continue; 1505 1506 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1507 } 1508 1509 return ret; 1510 } 1511 1512 /** 1513 * vcn_v4_0_5_wait_for_idle - wait for VCN block idle 1514 * 1515 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1516 * 1517 * Wait for VCN block idle 1518 */ 1519 static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 1520 { 1521 struct amdgpu_device *adev = ip_block->adev; 1522 int i, ret = 0; 1523 1524 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1525 if (adev->vcn.harvest_config & (1 << i)) 1526 continue; 1527 1528 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1529 UVD_STATUS__IDLE); 1530 if (ret) 1531 return ret; 1532 } 1533 1534 return ret; 1535 } 1536 1537 /** 1538 * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state 1539 * 1540 * @ip_block: amdgpu_ip_block pointer 1541 * @state: clock gating state 1542 * 1543 * Set VCN block clockgating state 1544 */ 1545 static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1546 enum amd_clockgating_state state) 1547 { 1548 struct amdgpu_device *adev = ip_block->adev; 1549 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1550 int i; 1551 1552 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1553 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1554 1555 if (adev->vcn.harvest_config & (1 << i)) 1556 continue; 1557 1558 if (enable) { 1559 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1560 return -EBUSY; 1561 vcn_v4_0_5_enable_clock_gating(vinst); 1562 } else { 1563 vcn_v4_0_5_disable_clock_gating(vinst); 1564 } 1565 } 1566 1567 return 0; 1568 } 1569 1570 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 1571 enum amd_powergating_state state) 1572 { 1573 int ret = 0; 1574 1575 if (state == vinst->cur_state) 1576 return 0; 1577 1578 if (state == AMD_PG_STATE_GATE) 1579 ret = vcn_v4_0_5_stop(vinst); 1580 else 1581 ret = vcn_v4_0_5_start(vinst); 1582 1583 if (!ret) 1584 vinst->cur_state = state; 1585 1586 return ret; 1587 } 1588 1589 /** 1590 * vcn_v4_0_5_process_interrupt - process VCN block interrupt 1591 * 1592 * @adev: amdgpu_device pointer 1593 * @source: interrupt sources 1594 * @entry: interrupt entry from clients and sources 1595 * 1596 * Process VCN block interrupt 1597 */ 1598 static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1599 struct amdgpu_iv_entry *entry) 1600 { 1601 uint32_t ip_instance; 1602 1603 switch (entry->client_id) { 1604 case SOC15_IH_CLIENTID_VCN: 1605 ip_instance = 0; 1606 break; 1607 case SOC15_IH_CLIENTID_VCN1: 1608 ip_instance = 1; 1609 break; 1610 default: 1611 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1612 return 0; 1613 } 1614 1615 DRM_DEBUG("IH: VCN TRAP\n"); 1616 1617 switch (entry->src_id) { 1618 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1619 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1620 break; 1621 case VCN_4_0__SRCID_UVD_POISON: 1622 amdgpu_vcn_process_poison_irq(adev, source, entry); 1623 break; 1624 default: 1625 DRM_ERROR("Unhandled interrupt: %d %d\n", 1626 entry->src_id, entry->src_data[0]); 1627 break; 1628 } 1629 1630 return 0; 1631 } 1632 1633 static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = { 1634 .process = vcn_v4_0_5_process_interrupt, 1635 }; 1636 1637 /** 1638 * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions 1639 * 1640 * @adev: amdgpu_device pointer 1641 * 1642 * Set VCN block interrupt irq functions 1643 */ 1644 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) 1645 { 1646 int i; 1647 1648 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1649 if (adev->vcn.harvest_config & (1 << i)) 1650 continue; 1651 1652 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 1653 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs; 1654 } 1655 } 1656 1657 static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1658 { 1659 struct amdgpu_device *adev = ip_block->adev; 1660 int i, j; 1661 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 1662 uint32_t inst_off, is_powered; 1663 1664 if (!adev->vcn.ip_dump) 1665 return; 1666 1667 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1668 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1669 if (adev->vcn.harvest_config & (1 << i)) { 1670 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1671 continue; 1672 } 1673 1674 inst_off = i * reg_count; 1675 is_powered = (adev->vcn.ip_dump[inst_off] & 1676 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1677 1678 if (is_powered) { 1679 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1680 for (j = 0; j < reg_count; j++) 1681 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name, 1682 adev->vcn.ip_dump[inst_off + j]); 1683 } else { 1684 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1685 } 1686 } 1687 } 1688 1689 static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block) 1690 { 1691 struct amdgpu_device *adev = ip_block->adev; 1692 int i, j; 1693 bool is_powered; 1694 uint32_t inst_off; 1695 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 1696 1697 if (!adev->vcn.ip_dump) 1698 return; 1699 1700 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1701 if (adev->vcn.harvest_config & (1 << i)) 1702 continue; 1703 1704 inst_off = i * reg_count; 1705 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1706 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); 1707 is_powered = (adev->vcn.ip_dump[inst_off] & 1708 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1709 1710 if (is_powered) 1711 for (j = 1; j < reg_count; j++) 1712 adev->vcn.ip_dump[inst_off + j] = 1713 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j], 1714 i)); 1715 } 1716 } 1717 1718 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { 1719 .name = "vcn_v4_0_5", 1720 .early_init = vcn_v4_0_5_early_init, 1721 .sw_init = vcn_v4_0_5_sw_init, 1722 .sw_fini = vcn_v4_0_5_sw_fini, 1723 .hw_init = vcn_v4_0_5_hw_init, 1724 .hw_fini = vcn_v4_0_5_hw_fini, 1725 .suspend = vcn_v4_0_5_suspend, 1726 .resume = vcn_v4_0_5_resume, 1727 .is_idle = vcn_v4_0_5_is_idle, 1728 .wait_for_idle = vcn_v4_0_5_wait_for_idle, 1729 .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, 1730 .set_powergating_state = vcn_set_powergating_state, 1731 .dump_ip_state = vcn_v4_0_5_dump_ip_state, 1732 .print_ip_state = vcn_v4_0_5_print_ip_state, 1733 }; 1734 1735 const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = { 1736 .type = AMD_IP_BLOCK_TYPE_VCN, 1737 .major = 4, 1738 .minor = 0, 1739 .rev = 5, 1740 .funcs = &vcn_v4_0_5_ip_funcs, 1741 }; 1742