1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0_5.h" 35 36 #include "vcn/vcn_4_0_5_offset.h" 37 #include "vcn/vcn_4_0_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 (0x48300 + 0x38000) 49 #define VCN1_AON_SOC_ADDRESS_3_0 (0x48000 + 0x38000) 50 51 #define VCN_HARVEST_MMSCH 0 52 53 #define RDECODE_MSG_CREATE 0x00000000 54 #define RDECODE_MESSAGE_CREATE 0x00000001 55 56 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = { 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 84 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 87 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 89 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 90 }; 91 92 static int amdgpu_ih_clientid_vcns[] = { 93 SOC15_IH_CLIENTID_VCN, 94 SOC15_IH_CLIENTID_VCN1 95 }; 96 97 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev); 99 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 100 enum amd_powergating_state state); 101 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 102 struct dpg_pause_state *new_state); 103 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring); 104 105 /** 106 * vcn_v4_0_5_early_init - set function pointers and load microcode 107 * 108 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 109 * 110 * Set ring and irq function pointers 111 * Load microcode from filesystem 112 */ 113 static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6)) 119 adev->vcn.per_inst_fw = true; 120 121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 122 /* re-use enc ring as unified ring */ 123 adev->vcn.inst[i].num_enc_rings = 1; 124 vcn_v4_0_5_set_unified_ring_funcs(adev); 125 vcn_v4_0_5_set_irq_funcs(adev); 126 127 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 128 adev->vcn.inst[i].set_pg_state = vcn_v4_0_5_set_pg_state; 129 130 r = amdgpu_vcn_early_init(adev, i); 131 if (r) 132 return r; 133 } 134 135 return 0; 136 } 137 138 /** 139 * vcn_v4_0_5_sw_init - sw init for VCN block 140 * 141 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 142 * 143 * Load firmware and sw initialization 144 */ 145 static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) 146 { 147 struct amdgpu_ring *ring; 148 struct amdgpu_device *adev = ip_block->adev; 149 int i, r; 150 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 151 uint32_t *ptr; 152 153 154 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 155 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 156 157 if (adev->vcn.harvest_config & (1 << i)) 158 continue; 159 160 r = amdgpu_vcn_sw_init(adev, i); 161 if (r) 162 return r; 163 164 amdgpu_vcn_setup_ucode(adev, i); 165 166 r = amdgpu_vcn_resume(adev, i); 167 if (r) 168 return r; 169 170 atomic_set(&adev->vcn.inst[i].sched_score, 0); 171 172 /* VCN UNIFIED TRAP */ 173 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 174 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 175 if (r) 176 return r; 177 178 /* VCN POISON TRAP */ 179 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 180 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 181 if (r) 182 return r; 183 184 ring = &adev->vcn.inst[i].ring_enc[0]; 185 ring->use_doorbell = true; 186 if (amdgpu_sriov_vf(adev)) 187 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 188 i * (adev->vcn.inst[i].num_enc_rings + 1) + 1; 189 else 190 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 191 2 + 8 * i; 192 ring->vm_hub = AMDGPU_MMHUB0(0); 193 sprintf(ring->name, "vcn_unified_%d", i); 194 195 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 196 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 197 if (r) 198 return r; 199 200 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 201 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 202 fw_shared->sq.is_enabled = 1; 203 204 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 205 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 206 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 207 208 if (amdgpu_sriov_vf(adev)) 209 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 210 211 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT; 212 fw_shared->drm_key_wa.method = 213 AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING; 214 215 if (amdgpu_vcnfw_log) 216 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 217 218 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 219 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode; 220 } 221 222 adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 223 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 224 225 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 226 if (r) 227 return r; 228 229 if (amdgpu_sriov_vf(adev)) { 230 r = amdgpu_virt_alloc_mm_table(adev); 231 if (r) 232 return r; 233 } 234 235 /* Allocate memory for VCN IP Dump buffer */ 236 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 237 if (!ptr) { 238 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 239 adev->vcn.ip_dump = NULL; 240 } else { 241 adev->vcn.ip_dump = ptr; 242 } 243 return 0; 244 } 245 246 /** 247 * vcn_v4_0_5_sw_fini - sw fini for VCN block 248 * 249 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 250 * 251 * VCN suspend and free up sw allocation 252 */ 253 static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) 254 { 255 struct amdgpu_device *adev = ip_block->adev; 256 int i, r, idx; 257 258 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 259 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 260 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 261 262 if (adev->vcn.harvest_config & (1 << i)) 263 continue; 264 265 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 266 fw_shared->present_flag_0 = 0; 267 fw_shared->sq.is_enabled = 0; 268 } 269 270 drm_dev_exit(idx); 271 } 272 273 if (amdgpu_sriov_vf(adev)) 274 amdgpu_virt_free_mm_table(adev); 275 276 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 277 r = amdgpu_vcn_suspend(adev, i); 278 if (r) 279 return r; 280 281 r = amdgpu_vcn_sw_fini(adev, i); 282 if (r) 283 return r; 284 } 285 286 kfree(adev->vcn.ip_dump); 287 288 return 0; 289 } 290 291 /** 292 * vcn_v4_0_5_hw_init - start and test VCN block 293 * 294 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 295 * 296 * Initialize the hardware, boot up the VCPU and do some testing 297 */ 298 static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) 299 { 300 struct amdgpu_device *adev = ip_block->adev; 301 struct amdgpu_ring *ring; 302 int i, r; 303 304 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 305 if (adev->vcn.harvest_config & (1 << i)) 306 continue; 307 308 ring = &adev->vcn.inst[i].ring_enc[0]; 309 310 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 311 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 312 313 r = amdgpu_ring_test_helper(ring); 314 if (r) 315 return r; 316 } 317 318 return 0; 319 } 320 321 /** 322 * vcn_v4_0_5_hw_fini - stop the hardware block 323 * 324 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 325 * 326 * Stop the VCN block, mark ring as not ready any more 327 */ 328 static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block) 329 { 330 struct amdgpu_device *adev = ip_block->adev; 331 int i; 332 333 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 334 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 335 336 if (adev->vcn.harvest_config & (1 << i)) 337 continue; 338 339 cancel_delayed_work_sync(&vinst->idle_work); 340 341 if (!amdgpu_sriov_vf(adev)) { 342 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 343 (vinst->cur_state != AMD_PG_STATE_GATE && 344 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 345 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 346 } 347 } 348 } 349 350 return 0; 351 } 352 353 /** 354 * vcn_v4_0_5_suspend - suspend VCN block 355 * 356 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 357 * 358 * HW fini and suspend VCN block 359 */ 360 static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) 361 { 362 struct amdgpu_device *adev = ip_block->adev; 363 int r, i; 364 365 r = vcn_v4_0_5_hw_fini(ip_block); 366 if (r) 367 return r; 368 369 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 370 r = amdgpu_vcn_suspend(ip_block->adev, i); 371 if (r) 372 return r; 373 } 374 375 return r; 376 } 377 378 /** 379 * vcn_v4_0_5_resume - resume VCN block 380 * 381 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 382 * 383 * Resume firmware and hw init VCN block 384 */ 385 static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block) 386 { 387 struct amdgpu_device *adev = ip_block->adev; 388 int r, i; 389 390 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 391 r = amdgpu_vcn_resume(ip_block->adev, i); 392 if (r) 393 return r; 394 } 395 396 r = vcn_v4_0_5_hw_init(ip_block); 397 398 return r; 399 } 400 401 /** 402 * vcn_v4_0_5_mc_resume - memory controller programming 403 * 404 * @vinst: VCN instance 405 * 406 * Let the VCN memory controller know it's offsets 407 */ 408 static void vcn_v4_0_5_mc_resume(struct amdgpu_vcn_inst *vinst) 409 { 410 struct amdgpu_device *adev = vinst->adev; 411 int inst = vinst->inst; 412 uint32_t offset, size; 413 const struct common_firmware_header *hdr; 414 415 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 416 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 417 418 /* cache window 0: fw */ 419 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 420 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 421 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 422 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 423 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 424 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 425 offset = 0; 426 } else { 427 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 428 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 429 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 430 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 431 offset = size; 432 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 433 } 434 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 435 436 /* cache window 1: stack */ 437 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 438 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 439 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 440 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 441 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 442 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 443 444 /* cache window 2: context */ 445 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 446 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 447 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 448 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 449 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 450 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 451 452 /* non-cache window */ 453 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 454 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 455 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 456 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 457 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 458 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 459 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 460 } 461 462 /** 463 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode 464 * 465 * @vinst: VCN instance 466 * @indirect: indirectly write sram 467 * 468 * Let the VCN memory controller know it's offsets with dpg mode 469 */ 470 static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 471 bool indirect) 472 { 473 struct amdgpu_device *adev = vinst->adev; 474 int inst_idx = vinst->inst; 475 uint32_t offset, size; 476 const struct common_firmware_header *hdr; 477 478 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 479 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 480 481 /* cache window 0: fw */ 482 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 483 if (!indirect) { 484 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 485 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 486 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 487 0, indirect); 488 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 489 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 490 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 491 0, indirect); 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 494 } else { 495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 496 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 498 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 501 } 502 offset = 0; 503 } else { 504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 505 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 506 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 507 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 508 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 509 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 510 offset = size; 511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 512 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 513 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 514 } 515 516 if (!indirect) 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 519 else 520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 521 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 522 523 /* cache window 1: stack */ 524 if (!indirect) { 525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 526 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 527 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 529 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 530 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 533 } else { 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 537 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 540 } 541 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 544 545 /* cache window 2: context */ 546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 547 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 548 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 549 0, indirect); 550 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 551 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 552 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 553 0, indirect); 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 558 559 /* non-cache window */ 560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 561 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 562 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 563 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 564 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 565 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 566 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 567 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 568 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 569 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 570 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 571 572 /* VCN global tiling registers */ 573 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 574 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 575 adev->gfx.config.gb_addr_config, 0, indirect); 576 } 577 578 /** 579 * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating 580 * 581 * @vinst: VCN instance 582 * 583 * Disable static power gating for VCN block 584 */ 585 static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 586 { 587 struct amdgpu_device *adev = vinst->adev; 588 int inst = vinst->inst; 589 uint32_t data = 0; 590 591 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 592 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 593 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 594 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 595 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 596 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 597 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 598 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 599 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 600 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 601 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 602 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 603 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 604 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 605 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 606 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 607 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 608 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 609 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 610 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 611 } else { 612 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 613 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 614 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 615 0, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 616 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 617 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 618 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 619 0, UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 620 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 621 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 622 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 623 0, UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 624 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 625 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 626 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 627 0, UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 628 } 629 630 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 631 data &= ~0x103; 632 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 633 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 634 UVD_POWER_STATUS__UVD_PG_EN_MASK; 635 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 636 } 637 638 /** 639 * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating 640 * 641 * @vinst: VCN instance 642 * 643 * Enable static power gating for VCN block 644 */ 645 static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 646 { 647 struct amdgpu_device *adev = vinst->adev; 648 int inst = vinst->inst; 649 uint32_t data; 650 651 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 652 /* Before power off, this indicator has to be turned on */ 653 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 654 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 655 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 656 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 657 658 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 659 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 660 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 661 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 662 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 663 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 664 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 665 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 666 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 667 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 668 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 669 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 670 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 671 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 672 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 673 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 674 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 675 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 676 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 677 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 678 } 679 } 680 681 /** 682 * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating 683 * 684 * @vinst: VCN instance 685 * 686 * Disable clock gating for VCN block 687 */ 688 static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 689 { 690 struct amdgpu_device *adev = vinst->adev; 691 int inst = vinst->inst; 692 uint32_t data; 693 694 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 695 return; 696 697 /* VCN disable CGC */ 698 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 699 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 700 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 701 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 702 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 703 704 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 705 data &= ~(UVD_CGC_GATE__SYS_MASK 706 | UVD_CGC_GATE__UDEC_MASK 707 | UVD_CGC_GATE__MPEG2_MASK 708 | UVD_CGC_GATE__REGS_MASK 709 | UVD_CGC_GATE__RBC_MASK 710 | UVD_CGC_GATE__LMI_MC_MASK 711 | UVD_CGC_GATE__LMI_UMC_MASK 712 | UVD_CGC_GATE__IDCT_MASK 713 | UVD_CGC_GATE__MPRD_MASK 714 | UVD_CGC_GATE__MPC_MASK 715 | UVD_CGC_GATE__LBSI_MASK 716 | UVD_CGC_GATE__LRBBM_MASK 717 | UVD_CGC_GATE__UDEC_RE_MASK 718 | UVD_CGC_GATE__UDEC_CM_MASK 719 | UVD_CGC_GATE__UDEC_IT_MASK 720 | UVD_CGC_GATE__UDEC_DB_MASK 721 | UVD_CGC_GATE__UDEC_MP_MASK 722 | UVD_CGC_GATE__WCB_MASK 723 | UVD_CGC_GATE__VCPU_MASK 724 | UVD_CGC_GATE__MMSCH_MASK); 725 726 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 727 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 728 729 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 730 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 731 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 732 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 733 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 734 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 735 | UVD_CGC_CTRL__SYS_MODE_MASK 736 | UVD_CGC_CTRL__UDEC_MODE_MASK 737 | UVD_CGC_CTRL__MPEG2_MODE_MASK 738 | UVD_CGC_CTRL__REGS_MODE_MASK 739 | UVD_CGC_CTRL__RBC_MODE_MASK 740 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 741 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 742 | UVD_CGC_CTRL__IDCT_MODE_MASK 743 | UVD_CGC_CTRL__MPRD_MODE_MASK 744 | UVD_CGC_CTRL__MPC_MODE_MASK 745 | UVD_CGC_CTRL__LBSI_MODE_MASK 746 | UVD_CGC_CTRL__LRBBM_MODE_MASK 747 | UVD_CGC_CTRL__WCB_MODE_MASK 748 | UVD_CGC_CTRL__VCPU_MODE_MASK 749 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 750 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 751 752 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 753 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 754 | UVD_SUVD_CGC_GATE__SIT_MASK 755 | UVD_SUVD_CGC_GATE__SMP_MASK 756 | UVD_SUVD_CGC_GATE__SCM_MASK 757 | UVD_SUVD_CGC_GATE__SDB_MASK 758 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 759 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 760 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 761 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 762 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 763 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 764 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 765 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 766 | UVD_SUVD_CGC_GATE__SCLR_MASK 767 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 768 | UVD_SUVD_CGC_GATE__ENT_MASK 769 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 770 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 771 | UVD_SUVD_CGC_GATE__SITE_MASK 772 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 773 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 774 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 775 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 776 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 777 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 778 779 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 780 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 781 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 782 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 783 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 784 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 785 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 786 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 787 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 788 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 789 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 790 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 791 } 792 793 /** 794 * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 795 * 796 * @vinst: VCN instance 797 * @sram_sel: sram select 798 * @indirect: indirectly write sram 799 * 800 * Disable clock gating for VCN block with dpg mode 801 */ 802 static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 803 uint8_t sram_sel, 804 uint8_t indirect) 805 { 806 struct amdgpu_device *adev = vinst->adev; 807 int inst_idx = vinst->inst; 808 uint32_t reg_data = 0; 809 810 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 811 return; 812 813 /* enable sw clock gating control */ 814 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 815 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 816 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 817 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 818 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 819 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 820 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 821 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 822 UVD_CGC_CTRL__SYS_MODE_MASK | 823 UVD_CGC_CTRL__UDEC_MODE_MASK | 824 UVD_CGC_CTRL__MPEG2_MODE_MASK | 825 UVD_CGC_CTRL__REGS_MODE_MASK | 826 UVD_CGC_CTRL__RBC_MODE_MASK | 827 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 828 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 829 UVD_CGC_CTRL__IDCT_MODE_MASK | 830 UVD_CGC_CTRL__MPRD_MODE_MASK | 831 UVD_CGC_CTRL__MPC_MODE_MASK | 832 UVD_CGC_CTRL__LBSI_MODE_MASK | 833 UVD_CGC_CTRL__LRBBM_MODE_MASK | 834 UVD_CGC_CTRL__WCB_MODE_MASK | 835 UVD_CGC_CTRL__VCPU_MODE_MASK); 836 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 837 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 838 839 /* turn off clock gating */ 840 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 841 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 842 843 /* turn on SUVD clock gating */ 844 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 845 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 846 847 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 848 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 849 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 850 } 851 852 /** 853 * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating 854 * 855 * @vinst: VCN instance 856 * 857 * Enable clock gating for VCN block 858 */ 859 static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 860 { 861 struct amdgpu_device *adev = vinst->adev; 862 int inst = vinst->inst; 863 uint32_t data; 864 865 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 866 return; 867 868 /* enable VCN CGC */ 869 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 870 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 871 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 872 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 873 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 874 875 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 876 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 877 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 878 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 879 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 880 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 881 | UVD_CGC_CTRL__SYS_MODE_MASK 882 | UVD_CGC_CTRL__UDEC_MODE_MASK 883 | UVD_CGC_CTRL__MPEG2_MODE_MASK 884 | UVD_CGC_CTRL__REGS_MODE_MASK 885 | UVD_CGC_CTRL__RBC_MODE_MASK 886 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 887 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 888 | UVD_CGC_CTRL__IDCT_MODE_MASK 889 | UVD_CGC_CTRL__MPRD_MODE_MASK 890 | UVD_CGC_CTRL__MPC_MODE_MASK 891 | UVD_CGC_CTRL__LBSI_MODE_MASK 892 | UVD_CGC_CTRL__LRBBM_MODE_MASK 893 | UVD_CGC_CTRL__WCB_MODE_MASK 894 | UVD_CGC_CTRL__VCPU_MODE_MASK 895 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 896 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 897 898 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 899 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 900 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 901 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 902 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 903 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 904 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 905 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 906 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 907 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 908 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 909 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 910 } 911 912 /** 913 * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode 914 * 915 * @vinst: VCN instance 916 * @indirect: indirectly write sram 917 * 918 * Start VCN block with dpg mode 919 */ 920 static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 921 bool indirect) 922 { 923 struct amdgpu_device *adev = vinst->adev; 924 int inst_idx = vinst->inst; 925 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 926 struct amdgpu_ring *ring; 927 uint32_t tmp; 928 929 /* disable register anti-hang mechanism */ 930 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 931 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 932 /* enable dynamic power gating mode */ 933 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 934 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 935 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 936 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 937 938 if (indirect) 939 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 940 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 941 942 /* enable clock gating */ 943 vcn_v4_0_5_disable_clock_gating_dpg_mode(vinst, 0, indirect); 944 945 /* enable VCPU clock */ 946 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 947 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 948 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 949 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 950 951 /* disable master interrupt */ 952 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 953 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 954 955 /* setup regUVD_LMI_CTRL */ 956 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 957 UVD_LMI_CTRL__REQ_MODE_MASK | 958 UVD_LMI_CTRL__CRC_RESET_MASK | 959 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 960 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 961 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 962 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 963 0x00100000L); 964 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 965 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 966 967 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 968 VCN, inst_idx, regUVD_MPC_CNTL), 969 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 970 971 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 972 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 973 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 974 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 975 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 976 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 977 978 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 979 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 980 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 981 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 982 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 983 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 984 985 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 986 VCN, inst_idx, regUVD_MPC_SET_MUX), 987 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 988 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 989 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 990 991 vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect); 992 993 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 994 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 995 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 996 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 997 998 /* enable LMI MC and UMC channels */ 999 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 1000 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1001 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 1002 1003 /* enable master interrupt */ 1004 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1005 VCN, inst_idx, regUVD_MASTINT_EN), 1006 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1007 1008 if (indirect) 1009 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1010 1011 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1012 1013 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 1014 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1015 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1016 1017 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1018 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1019 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1020 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1021 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1022 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1023 1024 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1025 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1026 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1027 1028 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1029 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1030 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1031 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1032 1033 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1034 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1035 VCN_RB1_DB_CTRL__EN_MASK); 1036 1037 return 0; 1038 } 1039 1040 1041 /** 1042 * vcn_v4_0_5_start - VCN start 1043 * 1044 * @vinst: VCN instance 1045 * 1046 * Start VCN block 1047 */ 1048 static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst) 1049 { 1050 struct amdgpu_device *adev = vinst->adev; 1051 int i = vinst->inst; 1052 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1053 struct amdgpu_ring *ring; 1054 uint32_t tmp; 1055 int j, k, r; 1056 1057 if (adev->vcn.harvest_config & (1 << i)) 1058 return 0; 1059 1060 if (adev->pm.dpm_enabled) 1061 amdgpu_dpm_enable_vcn(adev, true, i); 1062 1063 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1064 1065 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1066 return vcn_v4_0_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1067 1068 /* disable VCN power gating */ 1069 vcn_v4_0_5_disable_static_power_gating(vinst); 1070 1071 /* set VCN status busy */ 1072 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1073 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1074 1075 /* SW clock gating */ 1076 vcn_v4_0_5_disable_clock_gating(vinst); 1077 1078 /* enable VCPU clock */ 1079 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1080 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1081 1082 /* disable master interrupt */ 1083 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1084 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1085 1086 /* enable LMI MC and UMC channels */ 1087 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1088 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1089 1090 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1091 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1092 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1093 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1094 1095 /* setup regUVD_LMI_CTRL */ 1096 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1097 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1098 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1099 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1100 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1101 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1102 1103 /* setup regUVD_MPC_CNTL */ 1104 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1105 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1106 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1107 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1108 1109 /* setup UVD_MPC_SET_MUXA0 */ 1110 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1111 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1112 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1113 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1114 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1115 1116 /* setup UVD_MPC_SET_MUXB0 */ 1117 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1118 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1119 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1120 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1121 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1122 1123 /* setup UVD_MPC_SET_MUX */ 1124 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1125 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1126 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1127 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1128 1129 vcn_v4_0_5_mc_resume(vinst); 1130 1131 /* VCN global tiling registers */ 1132 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1133 adev->gfx.config.gb_addr_config); 1134 1135 /* unblock VCPU register access */ 1136 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1137 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1138 1139 /* release VCPU reset to boot */ 1140 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1141 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1142 1143 for (j = 0; j < 10; ++j) { 1144 uint32_t status; 1145 1146 for (k = 0; k < 100; ++k) { 1147 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1148 if (status & 2) 1149 break; 1150 mdelay(10); 1151 if (amdgpu_emu_mode == 1) 1152 msleep(1); 1153 } 1154 1155 if (amdgpu_emu_mode == 1) { 1156 r = -1; 1157 if (status & 2) { 1158 r = 0; 1159 break; 1160 } 1161 } else { 1162 r = 0; 1163 if (status & 2) 1164 break; 1165 1166 dev_err(adev->dev, 1167 "VCN[%d] is not responding, trying to reset VCPU!!!\n", i); 1168 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1169 UVD_VCPU_CNTL__BLK_RST_MASK, 1170 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1171 mdelay(10); 1172 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1173 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1174 1175 mdelay(10); 1176 r = -1; 1177 } 1178 } 1179 1180 if (r) { 1181 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1182 return r; 1183 } 1184 1185 /* enable master interrupt */ 1186 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1187 UVD_MASTINT_EN__VCPU_EN_MASK, 1188 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1189 1190 /* clear the busy bit of VCN_STATUS */ 1191 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1192 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1193 1194 ring = &adev->vcn.inst[i].ring_enc[0]; 1195 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1196 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1197 VCN_RB1_DB_CTRL__EN_MASK); 1198 1199 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1200 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1201 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1202 1203 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1204 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1205 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1206 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1207 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1208 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1209 1210 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1211 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1212 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1213 1214 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1215 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1216 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1217 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1218 1219 return 0; 1220 } 1221 1222 /** 1223 * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode 1224 * 1225 * @vinst: VCN instance 1226 * 1227 * Stop VCN block with dpg mode 1228 */ 1229 static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1230 { 1231 struct amdgpu_device *adev = vinst->adev; 1232 int inst_idx = vinst->inst; 1233 uint32_t tmp; 1234 1235 /* Wait for power status to be 1 */ 1236 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1237 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1238 1239 /* wait for read ptr to be equal to write ptr */ 1240 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1241 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1242 1243 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1244 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1245 1246 /* disable dynamic power gating mode */ 1247 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1248 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1249 } 1250 1251 /** 1252 * vcn_v4_0_5_stop - VCN stop 1253 * 1254 * @vinst: VCN instance 1255 * 1256 * Stop VCN block 1257 */ 1258 static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst) 1259 { 1260 struct amdgpu_device *adev = vinst->adev; 1261 int i = vinst->inst; 1262 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1263 uint32_t tmp; 1264 int r = 0; 1265 1266 if (adev->vcn.harvest_config & (1 << i)) 1267 return 0; 1268 1269 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1270 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1271 1272 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1273 vcn_v4_0_5_stop_dpg_mode(vinst); 1274 r = 0; 1275 goto done; 1276 } 1277 1278 /* wait for vcn idle */ 1279 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1280 if (r) 1281 goto done; 1282 1283 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1284 UVD_LMI_STATUS__READ_CLEAN_MASK | 1285 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1286 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1287 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1288 if (r) 1289 goto done; 1290 1291 /* disable LMI UMC channel */ 1292 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1293 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1294 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1295 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1296 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1297 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1298 if (r) 1299 goto done; 1300 1301 /* block VCPU register access */ 1302 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1303 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1304 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1305 1306 /* reset VCPU */ 1307 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1308 UVD_VCPU_CNTL__BLK_RST_MASK, 1309 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1310 1311 /* disable VCPU clock */ 1312 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1313 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1314 1315 /* apply soft reset */ 1316 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1317 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1318 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1319 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1320 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1321 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1322 1323 /* clear status */ 1324 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1325 1326 /* apply HW clock gating */ 1327 vcn_v4_0_5_enable_clock_gating(vinst); 1328 1329 /* enable VCN power gating */ 1330 vcn_v4_0_5_enable_static_power_gating(vinst); 1331 1332 done: 1333 if (adev->pm.dpm_enabled) 1334 amdgpu_dpm_enable_vcn(adev, false, i); 1335 1336 return r; 1337 } 1338 1339 /** 1340 * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode 1341 * 1342 * @vinst: VCN instance 1343 * @new_state: pause state 1344 * 1345 * Pause dpg mode for VCN block 1346 */ 1347 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1348 struct dpg_pause_state *new_state) 1349 { 1350 struct amdgpu_device *adev = vinst->adev; 1351 int inst_idx = vinst->inst; 1352 uint32_t reg_data = 0; 1353 int ret_code; 1354 1355 /* pause/unpause if state is changed */ 1356 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1357 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1358 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1359 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1360 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1361 1362 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1363 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1364 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1365 1366 if (!ret_code) { 1367 /* pause DPG */ 1368 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1369 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1370 1371 /* wait for ACK */ 1372 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1373 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1374 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1375 1376 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1377 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1378 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1379 } 1380 } else { 1381 /* unpause dpg, no need to wait */ 1382 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1383 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1384 } 1385 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1386 } 1387 1388 return 0; 1389 } 1390 1391 /** 1392 * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer 1393 * 1394 * @ring: amdgpu_ring pointer 1395 * 1396 * Returns the current hardware unified read pointer 1397 */ 1398 static uint64_t vcn_v4_0_5_unified_ring_get_rptr(struct amdgpu_ring *ring) 1399 { 1400 struct amdgpu_device *adev = ring->adev; 1401 1402 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1403 DRM_ERROR("wrong ring id is identified in %s", __func__); 1404 1405 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1406 } 1407 1408 /** 1409 * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer 1410 * 1411 * @ring: amdgpu_ring pointer 1412 * 1413 * Returns the current hardware unified write pointer 1414 */ 1415 static uint64_t vcn_v4_0_5_unified_ring_get_wptr(struct amdgpu_ring *ring) 1416 { 1417 struct amdgpu_device *adev = ring->adev; 1418 1419 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1420 DRM_ERROR("wrong ring id is identified in %s", __func__); 1421 1422 if (ring->use_doorbell) 1423 return *ring->wptr_cpu_addr; 1424 else 1425 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1426 } 1427 1428 /** 1429 * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer 1430 * 1431 * @ring: amdgpu_ring pointer 1432 * 1433 * Commits the enc write pointer to the hardware 1434 */ 1435 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring) 1436 { 1437 struct amdgpu_device *adev = ring->adev; 1438 1439 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1440 DRM_ERROR("wrong ring id is identified in %s", __func__); 1441 1442 if (ring->use_doorbell) { 1443 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1444 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1445 } else { 1446 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1447 } 1448 } 1449 1450 static int vcn_v4_0_5_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) 1451 { 1452 struct amdgpu_device *adev = ring->adev; 1453 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1454 1455 if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) 1456 return -EOPNOTSUPP; 1457 1458 vcn_v4_0_5_stop(vinst); 1459 vcn_v4_0_5_start(vinst); 1460 1461 return amdgpu_ring_test_helper(ring); 1462 } 1463 1464 static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { 1465 .type = AMDGPU_RING_TYPE_VCN_ENC, 1466 .align_mask = 0x3f, 1467 .nop = VCN_ENC_CMD_NO_OP, 1468 .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, 1469 .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, 1470 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, 1471 .emit_frame_size = 1472 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1473 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1474 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1475 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1476 1, /* vcn_v2_0_enc_ring_insert_end */ 1477 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1478 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1479 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1480 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1481 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1482 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1483 .insert_nop = amdgpu_ring_insert_nop, 1484 .insert_end = vcn_v2_0_enc_ring_insert_end, 1485 .pad_ib = amdgpu_ring_generic_pad_ib, 1486 .begin_use = amdgpu_vcn_ring_begin_use, 1487 .end_use = amdgpu_vcn_ring_end_use, 1488 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1489 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1490 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1491 .reset = vcn_v4_0_5_ring_reset, 1492 }; 1493 1494 /** 1495 * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions 1496 * 1497 * @adev: amdgpu_device pointer 1498 * 1499 * Set unified ring functions 1500 */ 1501 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev) 1502 { 1503 int i; 1504 1505 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1506 if (adev->vcn.harvest_config & (1 << i)) 1507 continue; 1508 1509 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) 1510 vcn_v4_0_5_unified_ring_vm_funcs.secure_submission_supported = true; 1511 1512 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs; 1513 adev->vcn.inst[i].ring_enc[0].me = i; 1514 } 1515 } 1516 1517 /** 1518 * vcn_v4_0_5_is_idle - check VCN block is idle 1519 * 1520 * @ip_block: Pointer to the amdgpu_ip_block structure 1521 * 1522 * Check whether VCN block is idle 1523 */ 1524 static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block) 1525 { 1526 struct amdgpu_device *adev = ip_block->adev; 1527 int i, ret = 1; 1528 1529 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1530 if (adev->vcn.harvest_config & (1 << i)) 1531 continue; 1532 1533 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1534 } 1535 1536 return ret; 1537 } 1538 1539 /** 1540 * vcn_v4_0_5_wait_for_idle - wait for VCN block idle 1541 * 1542 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1543 * 1544 * Wait for VCN block idle 1545 */ 1546 static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 1547 { 1548 struct amdgpu_device *adev = ip_block->adev; 1549 int i, ret = 0; 1550 1551 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1552 if (adev->vcn.harvest_config & (1 << i)) 1553 continue; 1554 1555 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1556 UVD_STATUS__IDLE); 1557 if (ret) 1558 return ret; 1559 } 1560 1561 return ret; 1562 } 1563 1564 /** 1565 * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state 1566 * 1567 * @ip_block: amdgpu_ip_block pointer 1568 * @state: clock gating state 1569 * 1570 * Set VCN block clockgating state 1571 */ 1572 static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1573 enum amd_clockgating_state state) 1574 { 1575 struct amdgpu_device *adev = ip_block->adev; 1576 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1577 int i; 1578 1579 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1580 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1581 1582 if (adev->vcn.harvest_config & (1 << i)) 1583 continue; 1584 1585 if (enable) { 1586 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1587 return -EBUSY; 1588 vcn_v4_0_5_enable_clock_gating(vinst); 1589 } else { 1590 vcn_v4_0_5_disable_clock_gating(vinst); 1591 } 1592 } 1593 1594 return 0; 1595 } 1596 1597 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 1598 enum amd_powergating_state state) 1599 { 1600 int ret = 0; 1601 1602 if (state == vinst->cur_state) 1603 return 0; 1604 1605 if (state == AMD_PG_STATE_GATE) 1606 ret = vcn_v4_0_5_stop(vinst); 1607 else 1608 ret = vcn_v4_0_5_start(vinst); 1609 1610 if (!ret) 1611 vinst->cur_state = state; 1612 1613 return ret; 1614 } 1615 1616 /** 1617 * vcn_v4_0_5_process_interrupt - process VCN block interrupt 1618 * 1619 * @adev: amdgpu_device pointer 1620 * @source: interrupt sources 1621 * @entry: interrupt entry from clients and sources 1622 * 1623 * Process VCN block interrupt 1624 */ 1625 static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1626 struct amdgpu_iv_entry *entry) 1627 { 1628 uint32_t ip_instance; 1629 1630 switch (entry->client_id) { 1631 case SOC15_IH_CLIENTID_VCN: 1632 ip_instance = 0; 1633 break; 1634 case SOC15_IH_CLIENTID_VCN1: 1635 ip_instance = 1; 1636 break; 1637 default: 1638 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1639 return 0; 1640 } 1641 1642 DRM_DEBUG("IH: VCN TRAP\n"); 1643 1644 switch (entry->src_id) { 1645 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1646 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1647 break; 1648 case VCN_4_0__SRCID_UVD_POISON: 1649 amdgpu_vcn_process_poison_irq(adev, source, entry); 1650 break; 1651 default: 1652 DRM_ERROR("Unhandled interrupt: %d %d\n", 1653 entry->src_id, entry->src_data[0]); 1654 break; 1655 } 1656 1657 return 0; 1658 } 1659 1660 static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = { 1661 .process = vcn_v4_0_5_process_interrupt, 1662 }; 1663 1664 /** 1665 * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions 1666 * 1667 * @adev: amdgpu_device pointer 1668 * 1669 * Set VCN block interrupt irq functions 1670 */ 1671 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) 1672 { 1673 int i; 1674 1675 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1676 if (adev->vcn.harvest_config & (1 << i)) 1677 continue; 1678 1679 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 1680 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs; 1681 } 1682 } 1683 1684 static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1685 { 1686 struct amdgpu_device *adev = ip_block->adev; 1687 int i, j; 1688 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 1689 uint32_t inst_off, is_powered; 1690 1691 if (!adev->vcn.ip_dump) 1692 return; 1693 1694 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1695 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1696 if (adev->vcn.harvest_config & (1 << i)) { 1697 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1698 continue; 1699 } 1700 1701 inst_off = i * reg_count; 1702 is_powered = (adev->vcn.ip_dump[inst_off] & 1703 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1704 1705 if (is_powered) { 1706 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1707 for (j = 0; j < reg_count; j++) 1708 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name, 1709 adev->vcn.ip_dump[inst_off + j]); 1710 } else { 1711 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1712 } 1713 } 1714 } 1715 1716 static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block) 1717 { 1718 struct amdgpu_device *adev = ip_block->adev; 1719 int i, j; 1720 bool is_powered; 1721 uint32_t inst_off; 1722 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); 1723 1724 if (!adev->vcn.ip_dump) 1725 return; 1726 1727 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1728 if (adev->vcn.harvest_config & (1 << i)) 1729 continue; 1730 1731 inst_off = i * reg_count; 1732 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1733 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); 1734 is_powered = (adev->vcn.ip_dump[inst_off] & 1735 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1736 1737 if (is_powered) 1738 for (j = 1; j < reg_count; j++) 1739 adev->vcn.ip_dump[inst_off + j] = 1740 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j], 1741 i)); 1742 } 1743 } 1744 1745 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { 1746 .name = "vcn_v4_0_5", 1747 .early_init = vcn_v4_0_5_early_init, 1748 .sw_init = vcn_v4_0_5_sw_init, 1749 .sw_fini = vcn_v4_0_5_sw_fini, 1750 .hw_init = vcn_v4_0_5_hw_init, 1751 .hw_fini = vcn_v4_0_5_hw_fini, 1752 .suspend = vcn_v4_0_5_suspend, 1753 .resume = vcn_v4_0_5_resume, 1754 .is_idle = vcn_v4_0_5_is_idle, 1755 .wait_for_idle = vcn_v4_0_5_wait_for_idle, 1756 .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, 1757 .set_powergating_state = vcn_set_powergating_state, 1758 .dump_ip_state = vcn_v4_0_5_dump_ip_state, 1759 .print_ip_state = vcn_v4_0_5_print_ip_state, 1760 }; 1761 1762 const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = { 1763 .type = AMD_IP_BLOCK_TYPE_VCN, 1764 .major = 4, 1765 .minor = 0, 1766 .rev = 5, 1767 .funcs = &vcn_v4_0_5_ip_funcs, 1768 }; 1769