1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0_5.h" 35 36 #include "vcn/vcn_4_0_5_offset.h" 37 #include "vcn/vcn_4_0_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 49 50 #define VCN_HARVEST_MMSCH 0 51 52 #define RDECODE_MSG_CREATE 0x00000000 53 #define RDECODE_MESSAGE_CREATE 0x00000001 54 55 static int amdgpu_ih_clientid_vcns[] = { 56 SOC15_IH_CLIENTID_VCN, 57 SOC15_IH_CLIENTID_VCN1 58 }; 59 60 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev); 61 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev); 62 static int vcn_v4_0_5_set_powergating_state(void *handle, 63 enum amd_powergating_state state); 64 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev, 65 int inst_idx, struct dpg_pause_state *new_state); 66 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring); 67 68 /** 69 * vcn_v4_0_5_early_init - set function pointers and load microcode 70 * 71 * @handle: amdgpu_device pointer 72 * 73 * Set ring and irq function pointers 74 * Load microcode from filesystem 75 */ 76 static int vcn_v4_0_5_early_init(void *handle) 77 { 78 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 79 80 /* re-use enc ring as unified ring */ 81 adev->vcn.num_enc_rings = 1; 82 vcn_v4_0_5_set_unified_ring_funcs(adev); 83 vcn_v4_0_5_set_irq_funcs(adev); 84 85 return amdgpu_vcn_early_init(adev); 86 } 87 88 /** 89 * vcn_v4_0_5_sw_init - sw init for VCN block 90 * 91 * @handle: amdgpu_device pointer 92 * 93 * Load firmware and sw initialization 94 */ 95 static int vcn_v4_0_5_sw_init(void *handle) 96 { 97 struct amdgpu_ring *ring; 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99 int i, r; 100 101 r = amdgpu_vcn_sw_init(adev); 102 if (r) 103 return r; 104 105 amdgpu_vcn_setup_ucode(adev); 106 107 r = amdgpu_vcn_resume(adev); 108 if (r) 109 return r; 110 111 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 112 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 113 114 if (adev->vcn.harvest_config & (1 << i)) 115 continue; 116 117 atomic_set(&adev->vcn.inst[i].sched_score, 0); 118 119 /* VCN UNIFIED TRAP */ 120 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 121 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 122 if (r) 123 return r; 124 125 /* VCN POISON TRAP */ 126 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 127 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 128 if (r) 129 return r; 130 131 ring = &adev->vcn.inst[i].ring_enc[0]; 132 ring->use_doorbell = true; 133 if (amdgpu_sriov_vf(adev)) 134 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 135 i * (adev->vcn.num_enc_rings + 1) + 1; 136 else 137 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 138 2 + 8 * i; 139 ring->vm_hub = AMDGPU_MMHUB0(0); 140 sprintf(ring->name, "vcn_unified_%d", i); 141 142 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 143 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 144 if (r) 145 return r; 146 147 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 148 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 149 fw_shared->sq.is_enabled = 1; 150 151 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 152 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 153 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 154 155 if (amdgpu_sriov_vf(adev)) 156 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 157 158 if (amdgpu_vcnfw_log) 159 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 160 } 161 162 if (amdgpu_sriov_vf(adev)) { 163 r = amdgpu_virt_alloc_mm_table(adev); 164 if (r) 165 return r; 166 } 167 168 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 169 adev->vcn.pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode; 170 171 return 0; 172 } 173 174 /** 175 * vcn_v4_0_5_sw_fini - sw fini for VCN block 176 * 177 * @handle: amdgpu_device pointer 178 * 179 * VCN suspend and free up sw allocation 180 */ 181 static int vcn_v4_0_5_sw_fini(void *handle) 182 { 183 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 184 int i, r, idx; 185 186 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 187 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 188 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 189 190 if (adev->vcn.harvest_config & (1 << i)) 191 continue; 192 193 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 194 fw_shared->present_flag_0 = 0; 195 fw_shared->sq.is_enabled = 0; 196 } 197 198 drm_dev_exit(idx); 199 } 200 201 if (amdgpu_sriov_vf(adev)) 202 amdgpu_virt_free_mm_table(adev); 203 204 r = amdgpu_vcn_suspend(adev); 205 if (r) 206 return r; 207 208 r = amdgpu_vcn_sw_fini(adev); 209 210 return r; 211 } 212 213 /** 214 * vcn_v4_0_5_hw_init - start and test VCN block 215 * 216 * @handle: amdgpu_device pointer 217 * 218 * Initialize the hardware, boot up the VCPU and do some testing 219 */ 220 static int vcn_v4_0_5_hw_init(void *handle) 221 { 222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 223 struct amdgpu_ring *ring; 224 int i, r; 225 226 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 227 if (adev->vcn.harvest_config & (1 << i)) 228 continue; 229 230 ring = &adev->vcn.inst[i].ring_enc[0]; 231 232 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 233 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 234 235 r = amdgpu_ring_test_helper(ring); 236 if (r) 237 goto done; 238 } 239 240 done: 241 if (!r) 242 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 243 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 244 245 return r; 246 } 247 248 /** 249 * vcn_v4_0_5_hw_fini - stop the hardware block 250 * 251 * @handle: amdgpu_device pointer 252 * 253 * Stop the VCN block, mark ring as not ready any more 254 */ 255 static int vcn_v4_0_5_hw_fini(void *handle) 256 { 257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 258 int i; 259 260 cancel_delayed_work_sync(&adev->vcn.idle_work); 261 262 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 263 if (adev->vcn.harvest_config & (1 << i)) 264 continue; 265 if (!amdgpu_sriov_vf(adev)) { 266 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 267 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 268 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 269 vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 270 } 271 } 272 273 amdgpu_irq_put(adev, &adev->vcn.inst[i].irq, 0); 274 } 275 276 return 0; 277 } 278 279 /** 280 * vcn_v4_0_5_suspend - suspend VCN block 281 * 282 * @handle: amdgpu_device pointer 283 * 284 * HW fini and suspend VCN block 285 */ 286 static int vcn_v4_0_5_suspend(void *handle) 287 { 288 int r; 289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 290 291 r = vcn_v4_0_5_hw_fini(adev); 292 if (r) 293 return r; 294 295 r = amdgpu_vcn_suspend(adev); 296 297 return r; 298 } 299 300 /** 301 * vcn_v4_0_5_resume - resume VCN block 302 * 303 * @handle: amdgpu_device pointer 304 * 305 * Resume firmware and hw init VCN block 306 */ 307 static int vcn_v4_0_5_resume(void *handle) 308 { 309 int r; 310 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 311 312 r = amdgpu_vcn_resume(adev); 313 if (r) 314 return r; 315 316 r = vcn_v4_0_5_hw_init(adev); 317 318 return r; 319 } 320 321 /** 322 * vcn_v4_0_5_mc_resume - memory controller programming 323 * 324 * @adev: amdgpu_device pointer 325 * @inst: instance number 326 * 327 * Let the VCN memory controller know it's offsets 328 */ 329 static void vcn_v4_0_5_mc_resume(struct amdgpu_device *adev, int inst) 330 { 331 uint32_t offset, size; 332 const struct common_firmware_header *hdr; 333 334 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 335 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 336 337 /* cache window 0: fw */ 338 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 339 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 340 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 341 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 342 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 343 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 344 offset = 0; 345 } else { 346 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 347 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 348 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 349 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 350 offset = size; 351 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 352 } 353 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 354 355 /* cache window 1: stack */ 356 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 357 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 358 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 359 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 360 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 361 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 362 363 /* cache window 2: context */ 364 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 365 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 366 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 367 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 368 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 369 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 370 371 /* non-cache window */ 372 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 373 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 374 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 375 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 376 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 377 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 378 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 379 } 380 381 /** 382 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode 383 * 384 * @adev: amdgpu_device pointer 385 * @inst_idx: instance number index 386 * @indirect: indirectly write sram 387 * 388 * Let the VCN memory controller know it's offsets with dpg mode 389 */ 390 static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 391 { 392 uint32_t offset, size; 393 const struct common_firmware_header *hdr; 394 395 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 396 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 397 398 /* cache window 0: fw */ 399 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 400 if (!indirect) { 401 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 402 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 403 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 404 0, indirect); 405 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 406 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 407 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 408 0, indirect); 409 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 410 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 411 } else { 412 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 413 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 414 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 415 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 416 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 417 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 418 } 419 offset = 0; 420 } else { 421 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 422 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 423 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 424 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 425 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 426 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 427 offset = size; 428 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 429 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 430 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 431 } 432 433 if (!indirect) 434 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 435 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 436 else 437 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 438 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 439 440 /* cache window 1: stack */ 441 if (!indirect) { 442 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 443 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 444 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 445 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 446 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 447 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 448 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 449 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 450 } else { 451 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 452 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 453 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 454 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 455 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 456 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 457 } 458 459 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 460 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 461 462 /* cache window 2: context */ 463 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 464 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 465 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 466 0, indirect); 467 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 468 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 469 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 470 0, indirect); 471 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 472 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 473 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 474 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 475 476 /* non-cache window */ 477 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 478 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 479 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 480 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 481 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 482 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 484 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 486 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 487 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 488 489 /* VCN global tiling registers */ 490 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 491 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 492 } 493 494 /** 495 * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating 496 * 497 * @adev: amdgpu_device pointer 498 * @inst: instance number 499 * 500 * Disable static power gating for VCN block 501 */ 502 static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, int inst) 503 { 504 uint32_t data = 0; 505 506 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 507 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 508 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 509 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 510 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 511 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 512 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 513 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 514 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 515 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 516 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 517 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 518 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 519 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 520 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 521 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 522 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 523 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 524 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 525 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 526 } else { 527 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 528 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 529 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 530 0, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 531 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 532 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 533 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 534 0, UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 535 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 536 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 537 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 538 0, UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 539 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 540 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 541 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 542 0, UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 543 } 544 545 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 546 data &= ~0x103; 547 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 548 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 549 UVD_POWER_STATUS__UVD_PG_EN_MASK; 550 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 551 } 552 553 /** 554 * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating 555 * 556 * @adev: amdgpu_device pointer 557 * @inst: instance number 558 * 559 * Enable static power gating for VCN block 560 */ 561 static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, int inst) 562 { 563 uint32_t data; 564 565 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 566 /* Before power off, this indicator has to be turned on */ 567 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 568 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 569 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 570 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 571 572 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 573 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 574 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 575 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 576 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 577 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 578 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 579 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 580 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 581 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 582 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 583 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 584 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 585 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 586 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 587 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 588 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 589 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 590 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 591 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 592 } 593 } 594 595 /** 596 * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating 597 * 598 * @adev: amdgpu_device pointer 599 * @inst: instance number 600 * 601 * Disable clock gating for VCN block 602 */ 603 static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst) 604 { 605 uint32_t data; 606 607 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 608 return; 609 610 /* VCN disable CGC */ 611 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 612 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 613 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 614 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 615 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 616 617 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 618 data &= ~(UVD_CGC_GATE__SYS_MASK 619 | UVD_CGC_GATE__UDEC_MASK 620 | UVD_CGC_GATE__MPEG2_MASK 621 | UVD_CGC_GATE__REGS_MASK 622 | UVD_CGC_GATE__RBC_MASK 623 | UVD_CGC_GATE__LMI_MC_MASK 624 | UVD_CGC_GATE__LMI_UMC_MASK 625 | UVD_CGC_GATE__IDCT_MASK 626 | UVD_CGC_GATE__MPRD_MASK 627 | UVD_CGC_GATE__MPC_MASK 628 | UVD_CGC_GATE__LBSI_MASK 629 | UVD_CGC_GATE__LRBBM_MASK 630 | UVD_CGC_GATE__UDEC_RE_MASK 631 | UVD_CGC_GATE__UDEC_CM_MASK 632 | UVD_CGC_GATE__UDEC_IT_MASK 633 | UVD_CGC_GATE__UDEC_DB_MASK 634 | UVD_CGC_GATE__UDEC_MP_MASK 635 | UVD_CGC_GATE__WCB_MASK 636 | UVD_CGC_GATE__VCPU_MASK 637 | UVD_CGC_GATE__MMSCH_MASK); 638 639 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 640 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 641 642 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 643 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 644 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 645 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 646 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 647 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 648 | UVD_CGC_CTRL__SYS_MODE_MASK 649 | UVD_CGC_CTRL__UDEC_MODE_MASK 650 | UVD_CGC_CTRL__MPEG2_MODE_MASK 651 | UVD_CGC_CTRL__REGS_MODE_MASK 652 | UVD_CGC_CTRL__RBC_MODE_MASK 653 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 654 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 655 | UVD_CGC_CTRL__IDCT_MODE_MASK 656 | UVD_CGC_CTRL__MPRD_MODE_MASK 657 | UVD_CGC_CTRL__MPC_MODE_MASK 658 | UVD_CGC_CTRL__LBSI_MODE_MASK 659 | UVD_CGC_CTRL__LRBBM_MODE_MASK 660 | UVD_CGC_CTRL__WCB_MODE_MASK 661 | UVD_CGC_CTRL__VCPU_MODE_MASK 662 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 663 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 664 665 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 666 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 667 | UVD_SUVD_CGC_GATE__SIT_MASK 668 | UVD_SUVD_CGC_GATE__SMP_MASK 669 | UVD_SUVD_CGC_GATE__SCM_MASK 670 | UVD_SUVD_CGC_GATE__SDB_MASK 671 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 672 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 673 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 674 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 675 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 676 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 677 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 678 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 679 | UVD_SUVD_CGC_GATE__SCLR_MASK 680 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 681 | UVD_SUVD_CGC_GATE__ENT_MASK 682 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 683 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 684 | UVD_SUVD_CGC_GATE__SITE_MASK 685 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 686 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 687 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 688 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 689 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 690 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 691 692 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 693 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 694 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 695 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 696 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 697 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 698 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 699 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 700 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 701 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 702 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 703 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 704 } 705 706 /** 707 * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 708 * 709 * @adev: amdgpu_device pointer 710 * @sram_sel: sram select 711 * @inst_idx: instance number index 712 * @indirect: indirectly write sram 713 * 714 * Disable clock gating for VCN block with dpg mode 715 */ 716 static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 717 int inst_idx, uint8_t indirect) 718 { 719 uint32_t reg_data = 0; 720 721 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 722 return; 723 724 /* enable sw clock gating control */ 725 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 726 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 727 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 728 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 729 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 730 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 731 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 732 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 733 UVD_CGC_CTRL__SYS_MODE_MASK | 734 UVD_CGC_CTRL__UDEC_MODE_MASK | 735 UVD_CGC_CTRL__MPEG2_MODE_MASK | 736 UVD_CGC_CTRL__REGS_MODE_MASK | 737 UVD_CGC_CTRL__RBC_MODE_MASK | 738 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 739 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 740 UVD_CGC_CTRL__IDCT_MODE_MASK | 741 UVD_CGC_CTRL__MPRD_MODE_MASK | 742 UVD_CGC_CTRL__MPC_MODE_MASK | 743 UVD_CGC_CTRL__LBSI_MODE_MASK | 744 UVD_CGC_CTRL__LRBBM_MODE_MASK | 745 UVD_CGC_CTRL__WCB_MODE_MASK | 746 UVD_CGC_CTRL__VCPU_MODE_MASK); 747 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 748 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 749 750 /* turn off clock gating */ 751 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 752 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 753 754 /* turn on SUVD clock gating */ 755 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 756 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 757 758 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 759 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 760 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 761 } 762 763 /** 764 * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating 765 * 766 * @adev: amdgpu_device pointer 767 * @inst: instance number 768 * 769 * Enable clock gating for VCN block 770 */ 771 static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst) 772 { 773 uint32_t data; 774 775 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 776 return; 777 778 /* enable VCN CGC */ 779 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 780 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 781 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 782 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 783 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 784 785 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 786 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 787 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 788 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 789 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 790 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 791 | UVD_CGC_CTRL__SYS_MODE_MASK 792 | UVD_CGC_CTRL__UDEC_MODE_MASK 793 | UVD_CGC_CTRL__MPEG2_MODE_MASK 794 | UVD_CGC_CTRL__REGS_MODE_MASK 795 | UVD_CGC_CTRL__RBC_MODE_MASK 796 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 797 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 798 | UVD_CGC_CTRL__IDCT_MODE_MASK 799 | UVD_CGC_CTRL__MPRD_MODE_MASK 800 | UVD_CGC_CTRL__MPC_MODE_MASK 801 | UVD_CGC_CTRL__LBSI_MODE_MASK 802 | UVD_CGC_CTRL__LRBBM_MODE_MASK 803 | UVD_CGC_CTRL__WCB_MODE_MASK 804 | UVD_CGC_CTRL__VCPU_MODE_MASK 805 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 806 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 807 808 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 809 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 810 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 811 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 812 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 813 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 816 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 817 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 818 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 819 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 820 } 821 822 /** 823 * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode 824 * 825 * @adev: amdgpu_device pointer 826 * @inst_idx: instance number index 827 * @indirect: indirectly write sram 828 * 829 * Start VCN block with dpg mode 830 */ 831 static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 832 { 833 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 834 struct amdgpu_ring *ring; 835 uint32_t tmp; 836 837 /* disable register anti-hang mechanism */ 838 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 839 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 840 /* enable dynamic power gating mode */ 841 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 842 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 843 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 844 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 845 846 if (indirect) 847 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 848 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 849 850 /* enable clock gating */ 851 vcn_v4_0_5_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 852 853 /* enable VCPU clock */ 854 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 855 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 856 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 857 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 858 859 /* disable master interrupt */ 860 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 861 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 862 863 /* setup regUVD_LMI_CTRL */ 864 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 865 UVD_LMI_CTRL__REQ_MODE_MASK | 866 UVD_LMI_CTRL__CRC_RESET_MASK | 867 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 868 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 869 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 870 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 871 0x00100000L); 872 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 873 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 874 875 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 876 VCN, inst_idx, regUVD_MPC_CNTL), 877 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 878 879 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 880 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 881 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 882 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 883 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 884 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 885 886 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 887 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 888 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 889 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 890 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 891 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 892 893 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 894 VCN, inst_idx, regUVD_MPC_SET_MUX), 895 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 896 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 897 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 898 899 vcn_v4_0_5_mc_resume_dpg_mode(adev, inst_idx, indirect); 900 901 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 902 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 903 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 904 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 905 906 /* enable LMI MC and UMC channels */ 907 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 908 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 909 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 910 911 /* enable master interrupt */ 912 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 913 VCN, inst_idx, regUVD_MASTINT_EN), 914 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 915 916 917 if (indirect) 918 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 919 920 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 921 922 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 923 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 924 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 925 926 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 927 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 928 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 929 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 930 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 931 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 932 933 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 934 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 935 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 936 937 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 938 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 939 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 940 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 941 942 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 943 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 944 VCN_RB1_DB_CTRL__EN_MASK); 945 946 return 0; 947 } 948 949 950 /** 951 * vcn_v4_0_5_start - VCN start 952 * 953 * @adev: amdgpu_device pointer 954 * 955 * Start VCN block 956 */ 957 static int vcn_v4_0_5_start(struct amdgpu_device *adev) 958 { 959 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 960 struct amdgpu_ring *ring; 961 uint32_t tmp; 962 int i, j, k, r; 963 964 if (adev->pm.dpm_enabled) 965 amdgpu_dpm_enable_uvd(adev, true); 966 967 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 968 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 969 970 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 971 r = vcn_v4_0_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 972 continue; 973 } 974 975 /* disable VCN power gating */ 976 vcn_v4_0_5_disable_static_power_gating(adev, i); 977 978 /* set VCN status busy */ 979 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 980 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 981 982 /*SW clock gating */ 983 vcn_v4_0_5_disable_clock_gating(adev, i); 984 985 /* enable VCPU clock */ 986 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 987 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 988 989 /* disable master interrupt */ 990 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 991 ~UVD_MASTINT_EN__VCPU_EN_MASK); 992 993 /* enable LMI MC and UMC channels */ 994 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 995 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 996 997 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 998 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 999 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1000 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1001 1002 /* setup regUVD_LMI_CTRL */ 1003 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1004 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1005 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1006 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1007 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1008 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1009 1010 /* setup regUVD_MPC_CNTL */ 1011 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1012 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1013 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1014 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1015 1016 /* setup UVD_MPC_SET_MUXA0 */ 1017 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1018 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1019 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1020 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1021 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1022 1023 /* setup UVD_MPC_SET_MUXB0 */ 1024 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1025 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1026 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1027 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1028 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1029 1030 /* setup UVD_MPC_SET_MUX */ 1031 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1032 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1033 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1034 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1035 1036 vcn_v4_0_5_mc_resume(adev, i); 1037 1038 /* VCN global tiling registers */ 1039 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1040 adev->gfx.config.gb_addr_config); 1041 1042 /* unblock VCPU register access */ 1043 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1044 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1045 1046 /* release VCPU reset to boot */ 1047 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1048 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1049 1050 for (j = 0; j < 10; ++j) { 1051 uint32_t status; 1052 1053 for (k = 0; k < 100; ++k) { 1054 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1055 if (status & 2) 1056 break; 1057 mdelay(10); 1058 if (amdgpu_emu_mode == 1) 1059 msleep(1); 1060 } 1061 1062 if (amdgpu_emu_mode == 1) { 1063 r = -1; 1064 if (status & 2) { 1065 r = 0; 1066 break; 1067 } 1068 } else { 1069 r = 0; 1070 if (status & 2) 1071 break; 1072 1073 dev_err(adev->dev, 1074 "VCN[%d] is not responding, trying to reset VCPU!!!\n", i); 1075 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1076 UVD_VCPU_CNTL__BLK_RST_MASK, 1077 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1078 mdelay(10); 1079 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1080 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1081 1082 mdelay(10); 1083 r = -1; 1084 } 1085 } 1086 1087 if (r) { 1088 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1089 return r; 1090 } 1091 1092 /* enable master interrupt */ 1093 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1094 UVD_MASTINT_EN__VCPU_EN_MASK, 1095 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1096 1097 /* clear the busy bit of VCN_STATUS */ 1098 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1099 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1100 1101 ring = &adev->vcn.inst[i].ring_enc[0]; 1102 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1103 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1104 VCN_RB1_DB_CTRL__EN_MASK); 1105 1106 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1107 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1108 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1109 1110 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1111 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1112 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1113 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1114 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1115 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1116 1117 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1118 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1119 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1120 1121 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1122 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1123 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1124 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1125 } 1126 1127 return 0; 1128 } 1129 1130 /** 1131 * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode 1132 * 1133 * @adev: amdgpu_device pointer 1134 * @inst_idx: instance number index 1135 * 1136 * Stop VCN block with dpg mode 1137 */ 1138 static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1139 { 1140 uint32_t tmp; 1141 1142 /* Wait for power status to be 1 */ 1143 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1144 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1145 1146 /* wait for read ptr to be equal to write ptr */ 1147 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1148 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1149 1150 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1151 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1152 1153 /* disable dynamic power gating mode */ 1154 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1155 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1156 } 1157 1158 /** 1159 * vcn_v4_0_5_stop - VCN stop 1160 * 1161 * @adev: amdgpu_device pointer 1162 * 1163 * Stop VCN block 1164 */ 1165 static int vcn_v4_0_5_stop(struct amdgpu_device *adev) 1166 { 1167 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1168 uint32_t tmp; 1169 int i, r = 0; 1170 1171 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1172 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1173 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1174 1175 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1176 vcn_v4_0_5_stop_dpg_mode(adev, i); 1177 continue; 1178 } 1179 1180 /* wait for vcn idle */ 1181 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1182 if (r) 1183 return r; 1184 1185 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1186 UVD_LMI_STATUS__READ_CLEAN_MASK | 1187 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1188 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1189 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1190 if (r) 1191 return r; 1192 1193 /* disable LMI UMC channel */ 1194 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1195 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1196 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1197 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1198 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1199 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1200 if (r) 1201 return r; 1202 1203 /* block VCPU register access */ 1204 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1205 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1206 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1207 1208 /* reset VCPU */ 1209 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1210 UVD_VCPU_CNTL__BLK_RST_MASK, 1211 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1212 1213 /* disable VCPU clock */ 1214 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1215 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1216 1217 /* apply soft reset */ 1218 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1219 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1220 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1221 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1222 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1223 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1224 1225 /* clear status */ 1226 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1227 1228 /* apply HW clock gating */ 1229 vcn_v4_0_5_enable_clock_gating(adev, i); 1230 1231 /* enable VCN power gating */ 1232 vcn_v4_0_5_enable_static_power_gating(adev, i); 1233 } 1234 1235 if (adev->pm.dpm_enabled) 1236 amdgpu_dpm_enable_uvd(adev, false); 1237 1238 return 0; 1239 } 1240 1241 /** 1242 * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode 1243 * 1244 * @adev: amdgpu_device pointer 1245 * @inst_idx: instance number index 1246 * @new_state: pause state 1247 * 1248 * Pause dpg mode for VCN block 1249 */ 1250 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1251 struct dpg_pause_state *new_state) 1252 { 1253 uint32_t reg_data = 0; 1254 int ret_code; 1255 1256 /* pause/unpause if state is changed */ 1257 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1258 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1259 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1260 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1261 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1262 1263 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1264 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1265 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1266 1267 if (!ret_code) { 1268 /* pause DPG */ 1269 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1270 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1271 1272 /* wait for ACK */ 1273 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1274 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1275 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1276 1277 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1278 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1279 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1280 } 1281 } else { 1282 /* unpause dpg, no need to wait */ 1283 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1284 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1285 } 1286 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1287 } 1288 1289 return 0; 1290 } 1291 1292 /** 1293 * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer 1294 * 1295 * @ring: amdgpu_ring pointer 1296 * 1297 * Returns the current hardware unified read pointer 1298 */ 1299 static uint64_t vcn_v4_0_5_unified_ring_get_rptr(struct amdgpu_ring *ring) 1300 { 1301 struct amdgpu_device *adev = ring->adev; 1302 1303 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1304 DRM_ERROR("wrong ring id is identified in %s", __func__); 1305 1306 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1307 } 1308 1309 /** 1310 * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer 1311 * 1312 * @ring: amdgpu_ring pointer 1313 * 1314 * Returns the current hardware unified write pointer 1315 */ 1316 static uint64_t vcn_v4_0_5_unified_ring_get_wptr(struct amdgpu_ring *ring) 1317 { 1318 struct amdgpu_device *adev = ring->adev; 1319 1320 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1321 DRM_ERROR("wrong ring id is identified in %s", __func__); 1322 1323 if (ring->use_doorbell) 1324 return *ring->wptr_cpu_addr; 1325 else 1326 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1327 } 1328 1329 /** 1330 * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer 1331 * 1332 * @ring: amdgpu_ring pointer 1333 * 1334 * Commits the enc write pointer to the hardware 1335 */ 1336 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring) 1337 { 1338 struct amdgpu_device *adev = ring->adev; 1339 1340 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1341 DRM_ERROR("wrong ring id is identified in %s", __func__); 1342 1343 if (ring->use_doorbell) { 1344 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1345 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1346 } else { 1347 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1348 } 1349 } 1350 1351 static int vcn_v4_0_5_limit_sched(struct amdgpu_cs_parser *p, 1352 struct amdgpu_job *job) 1353 { 1354 struct drm_gpu_scheduler **scheds; 1355 1356 /* The create msg must be in the first IB submitted */ 1357 if (atomic_read(&job->base.entity->fence_seq)) 1358 return -EINVAL; 1359 1360 /* if VCN0 is harvested, we can't support AV1 */ 1361 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1362 return -EINVAL; 1363 1364 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 1365 [AMDGPU_RING_PRIO_0].sched; 1366 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1367 return 0; 1368 } 1369 1370 static int vcn_v4_0_5_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1371 uint64_t addr) 1372 { 1373 struct ttm_operation_ctx ctx = { false, false }; 1374 struct amdgpu_bo_va_mapping *map; 1375 uint32_t *msg, num_buffers; 1376 struct amdgpu_bo *bo; 1377 uint64_t start, end; 1378 unsigned int i; 1379 void *ptr; 1380 int r; 1381 1382 addr &= AMDGPU_GMC_HOLE_MASK; 1383 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1384 if (r) { 1385 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 1386 return r; 1387 } 1388 1389 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1390 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1391 if (addr & 0x7) { 1392 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1393 return -EINVAL; 1394 } 1395 1396 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1397 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1398 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1399 if (r) { 1400 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1401 return r; 1402 } 1403 1404 r = amdgpu_bo_kmap(bo, &ptr); 1405 if (r) { 1406 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1407 return r; 1408 } 1409 1410 msg = ptr + addr - start; 1411 1412 /* Check length */ 1413 if (msg[1] > end - addr) { 1414 r = -EINVAL; 1415 goto out; 1416 } 1417 1418 if (msg[3] != RDECODE_MSG_CREATE) 1419 goto out; 1420 1421 num_buffers = msg[2]; 1422 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1423 uint32_t offset, size, *create; 1424 1425 if (msg[0] != RDECODE_MESSAGE_CREATE) 1426 continue; 1427 1428 offset = msg[1]; 1429 size = msg[2]; 1430 1431 if (offset + size > end) { 1432 r = -EINVAL; 1433 goto out; 1434 } 1435 1436 create = ptr + addr + offset - start; 1437 1438 /* H264, HEVC and VP9 can run on any instance */ 1439 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1440 continue; 1441 1442 r = vcn_v4_0_5_limit_sched(p, job); 1443 if (r) 1444 goto out; 1445 } 1446 1447 out: 1448 amdgpu_bo_kunmap(bo); 1449 return r; 1450 } 1451 1452 #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) 1453 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 1454 1455 #define RADEON_VCN_ENGINE_INFO (0x30000001) 1456 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16 1457 1458 #define RENCODE_ENCODE_STANDARD_AV1 2 1459 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 1460 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64 1461 1462 /* return the offset in ib if id is found, -1 otherwise 1463 * to speed up the searching we only search upto max_offset 1464 */ 1465 static int vcn_v4_0_5_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) 1466 { 1467 int i; 1468 1469 for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) { 1470 if (ib->ptr[i + 1] == id) 1471 return i; 1472 } 1473 return -1; 1474 } 1475 1476 static int vcn_v4_0_5_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1477 struct amdgpu_job *job, 1478 struct amdgpu_ib *ib) 1479 { 1480 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1481 struct amdgpu_vcn_decode_buffer *decode_buffer; 1482 uint64_t addr; 1483 uint32_t val; 1484 int idx; 1485 1486 /* The first instance can decode anything */ 1487 if (!ring->me) 1488 return 0; 1489 1490 /* RADEON_VCN_ENGINE_INFO is at the top of ib block */ 1491 idx = vcn_v4_0_5_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, 1492 RADEON_VCN_ENGINE_INFO_MAX_OFFSET); 1493 if (idx < 0) /* engine info is missing */ 1494 return 0; 1495 1496 val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ 1497 if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1498 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; 1499 1500 if (!(decode_buffer->valid_buf_flag & 0x1)) 1501 return 0; 1502 1503 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1504 decode_buffer->msg_buffer_address_lo; 1505 return vcn_v4_0_5_dec_msg(p, job, addr); 1506 } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { 1507 idx = vcn_v4_0_5_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, 1508 RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET); 1509 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1) 1510 return vcn_v4_0_5_limit_sched(p, job); 1511 } 1512 return 0; 1513 } 1514 1515 static const struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { 1516 .type = AMDGPU_RING_TYPE_VCN_ENC, 1517 .align_mask = 0x3f, 1518 .nop = VCN_ENC_CMD_NO_OP, 1519 .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, 1520 .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, 1521 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, 1522 .patch_cs_in_place = vcn_v4_0_5_ring_patch_cs_in_place, 1523 .emit_frame_size = 1524 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1525 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1526 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1527 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1528 1, /* vcn_v2_0_enc_ring_insert_end */ 1529 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1530 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1531 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1532 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1533 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1534 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1535 .insert_nop = amdgpu_ring_insert_nop, 1536 .insert_end = vcn_v2_0_enc_ring_insert_end, 1537 .pad_ib = amdgpu_ring_generic_pad_ib, 1538 .begin_use = amdgpu_vcn_ring_begin_use, 1539 .end_use = amdgpu_vcn_ring_end_use, 1540 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1541 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1542 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1543 }; 1544 1545 /** 1546 * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions 1547 * 1548 * @adev: amdgpu_device pointer 1549 * 1550 * Set unified ring functions 1551 */ 1552 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev) 1553 { 1554 int i; 1555 1556 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1557 if (adev->vcn.harvest_config & (1 << i)) 1558 continue; 1559 1560 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs; 1561 adev->vcn.inst[i].ring_enc[0].me = i; 1562 1563 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); 1564 } 1565 } 1566 1567 /** 1568 * vcn_v4_0_5_is_idle - check VCN block is idle 1569 * 1570 * @handle: amdgpu_device pointer 1571 * 1572 * Check whether VCN block is idle 1573 */ 1574 static bool vcn_v4_0_5_is_idle(void *handle) 1575 { 1576 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1577 int i, ret = 1; 1578 1579 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1580 if (adev->vcn.harvest_config & (1 << i)) 1581 continue; 1582 1583 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1584 } 1585 1586 return ret; 1587 } 1588 1589 /** 1590 * vcn_v4_0_5_wait_for_idle - wait for VCN block idle 1591 * 1592 * @handle: amdgpu_device pointer 1593 * 1594 * Wait for VCN block idle 1595 */ 1596 static int vcn_v4_0_5_wait_for_idle(void *handle) 1597 { 1598 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1599 int i, ret = 0; 1600 1601 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1602 if (adev->vcn.harvest_config & (1 << i)) 1603 continue; 1604 1605 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1606 UVD_STATUS__IDLE); 1607 if (ret) 1608 return ret; 1609 } 1610 1611 return ret; 1612 } 1613 1614 /** 1615 * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state 1616 * 1617 * @handle: amdgpu_device pointer 1618 * @state: clock gating state 1619 * 1620 * Set VCN block clockgating state 1621 */ 1622 static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_state state) 1623 { 1624 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1625 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1626 int i; 1627 1628 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1629 if (adev->vcn.harvest_config & (1 << i)) 1630 continue; 1631 1632 if (enable) { 1633 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1634 return -EBUSY; 1635 vcn_v4_0_5_enable_clock_gating(adev, i); 1636 } else { 1637 vcn_v4_0_5_disable_clock_gating(adev, i); 1638 } 1639 } 1640 1641 return 0; 1642 } 1643 1644 /** 1645 * vcn_v4_0_5_set_powergating_state - set VCN block powergating state 1646 * 1647 * @handle: amdgpu_device pointer 1648 * @state: power gating state 1649 * 1650 * Set VCN block powergating state 1651 */ 1652 static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_state state) 1653 { 1654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1655 int ret; 1656 1657 if (state == adev->vcn.cur_state) 1658 return 0; 1659 1660 if (state == AMD_PG_STATE_GATE) 1661 ret = vcn_v4_0_5_stop(adev); 1662 else 1663 ret = vcn_v4_0_5_start(adev); 1664 1665 if (!ret) 1666 adev->vcn.cur_state = state; 1667 1668 return ret; 1669 } 1670 1671 /** 1672 * vcn_v4_0_5_set_interrupt_state - set VCN block interrupt state 1673 * 1674 * @adev: amdgpu_device pointer 1675 * @source: interrupt sources 1676 * @type: interrupt types 1677 * @state: interrupt states 1678 * 1679 * Set VCN block interrupt state 1680 */ 1681 static int vcn_v4_0_5_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1682 unsigned type, enum amdgpu_interrupt_state state) 1683 { 1684 return 0; 1685 } 1686 1687 /** 1688 * vcn_v4_0_5_process_interrupt - process VCN block interrupt 1689 * 1690 * @adev: amdgpu_device pointer 1691 * @source: interrupt sources 1692 * @entry: interrupt entry from clients and sources 1693 * 1694 * Process VCN block interrupt 1695 */ 1696 static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1697 struct amdgpu_iv_entry *entry) 1698 { 1699 uint32_t ip_instance; 1700 1701 switch (entry->client_id) { 1702 case SOC15_IH_CLIENTID_VCN: 1703 ip_instance = 0; 1704 break; 1705 default: 1706 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1707 return 0; 1708 } 1709 1710 DRM_DEBUG("IH: VCN TRAP\n"); 1711 1712 switch (entry->src_id) { 1713 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1714 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1715 break; 1716 case VCN_4_0__SRCID_UVD_POISON: 1717 amdgpu_vcn_process_poison_irq(adev, source, entry); 1718 break; 1719 default: 1720 DRM_ERROR("Unhandled interrupt: %d %d\n", 1721 entry->src_id, entry->src_data[0]); 1722 break; 1723 } 1724 1725 return 0; 1726 } 1727 1728 static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = { 1729 .set = vcn_v4_0_5_set_interrupt_state, 1730 .process = vcn_v4_0_5_process_interrupt, 1731 }; 1732 1733 /** 1734 * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions 1735 * 1736 * @adev: amdgpu_device pointer 1737 * 1738 * Set VCN block interrupt irq functions 1739 */ 1740 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) 1741 { 1742 int i; 1743 1744 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1745 if (adev->vcn.harvest_config & (1 << i)) 1746 continue; 1747 1748 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1749 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs; 1750 } 1751 } 1752 1753 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { 1754 .name = "vcn_v4_0_5", 1755 .early_init = vcn_v4_0_5_early_init, 1756 .late_init = NULL, 1757 .sw_init = vcn_v4_0_5_sw_init, 1758 .sw_fini = vcn_v4_0_5_sw_fini, 1759 .hw_init = vcn_v4_0_5_hw_init, 1760 .hw_fini = vcn_v4_0_5_hw_fini, 1761 .suspend = vcn_v4_0_5_suspend, 1762 .resume = vcn_v4_0_5_resume, 1763 .is_idle = vcn_v4_0_5_is_idle, 1764 .wait_for_idle = vcn_v4_0_5_wait_for_idle, 1765 .check_soft_reset = NULL, 1766 .pre_soft_reset = NULL, 1767 .soft_reset = NULL, 1768 .post_soft_reset = NULL, 1769 .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, 1770 .set_powergating_state = vcn_v4_0_5_set_powergating_state, 1771 }; 1772 1773 const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = { 1774 .type = AMD_IP_BLOCK_TYPE_VCN, 1775 .major = 4, 1776 .minor = 0, 1777 .rev = 5, 1778 .funcs = &vcn_v4_0_5_ip_funcs, 1779 }; 1780