1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0_5.h" 35 36 #include "vcn/vcn_4_0_5_offset.h" 37 #include "vcn/vcn_4_0_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 (0x48300 + 0x38000) 49 #define VCN1_AON_SOC_ADDRESS_3_0 (0x48000 + 0x38000) 50 51 #define VCN_HARVEST_MMSCH 0 52 53 #define RDECODE_MSG_CREATE 0x00000000 54 #define RDECODE_MESSAGE_CREATE 0x00000001 55 56 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = { 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 84 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 87 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 89 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 90 }; 91 92 static int amdgpu_ih_clientid_vcns[] = { 93 SOC15_IH_CLIENTID_VCN, 94 SOC15_IH_CLIENTID_VCN1 95 }; 96 97 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev); 99 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 100 enum amd_powergating_state state); 101 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 102 struct dpg_pause_state *new_state); 103 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring); 104 105 /** 106 * vcn_v4_0_5_early_init - set function pointers and load microcode 107 * 108 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 109 * 110 * Set ring and irq function pointers 111 * Load microcode from filesystem 112 */ 113 static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6)) 119 adev->vcn.per_inst_fw = true; 120 121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 122 /* re-use enc ring as unified ring */ 123 adev->vcn.inst[i].num_enc_rings = 1; 124 vcn_v4_0_5_set_unified_ring_funcs(adev); 125 vcn_v4_0_5_set_irq_funcs(adev); 126 127 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 128 adev->vcn.inst[i].set_pg_state = vcn_v4_0_5_set_pg_state; 129 130 r = amdgpu_vcn_early_init(adev, i); 131 if (r) 132 return r; 133 } 134 135 return 0; 136 } 137 138 /** 139 * vcn_v4_0_5_sw_init - sw init for VCN block 140 * 141 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 142 * 143 * Load firmware and sw initialization 144 */ 145 static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) 146 { 147 struct amdgpu_ring *ring; 148 struct amdgpu_device *adev = ip_block->adev; 149 int i, r; 150 151 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 152 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 153 154 if (adev->vcn.harvest_config & (1 << i)) 155 continue; 156 157 r = amdgpu_vcn_sw_init(adev, i); 158 if (r) 159 return r; 160 161 amdgpu_vcn_setup_ucode(adev, i); 162 163 r = amdgpu_vcn_resume(adev, i); 164 if (r) 165 return r; 166 167 atomic_set(&adev->vcn.inst[i].sched_score, 0); 168 169 /* VCN UNIFIED TRAP */ 170 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 171 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 172 if (r) 173 return r; 174 175 /* VCN POISON TRAP */ 176 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 177 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 178 if (r) 179 return r; 180 181 ring = &adev->vcn.inst[i].ring_enc[0]; 182 ring->use_doorbell = true; 183 if (amdgpu_sriov_vf(adev)) 184 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 185 i * (adev->vcn.inst[i].num_enc_rings + 1) + 1; 186 else 187 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 188 2 + 8 * i; 189 ring->vm_hub = AMDGPU_MMHUB0(0); 190 sprintf(ring->name, "vcn_unified_%d", i); 191 192 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 193 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 194 if (r) 195 return r; 196 197 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 198 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 199 fw_shared->sq.is_enabled = 1; 200 201 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 202 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 203 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 204 205 if (amdgpu_sriov_vf(adev)) 206 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 207 208 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT; 209 fw_shared->drm_key_wa.method = 210 AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING; 211 212 if (amdgpu_vcnfw_log) 213 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 214 215 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 216 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode; 217 } 218 219 adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 220 if (!amdgpu_sriov_vf(adev)) 221 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 222 223 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 224 if (r) 225 return r; 226 227 if (amdgpu_sriov_vf(adev)) { 228 r = amdgpu_virt_alloc_mm_table(adev); 229 if (r) 230 return r; 231 } 232 233 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_5, ARRAY_SIZE(vcn_reg_list_4_0_5)); 234 235 return r; 236 } 237 238 /** 239 * vcn_v4_0_5_sw_fini - sw fini for VCN block 240 * 241 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 242 * 243 * VCN suspend and free up sw allocation 244 */ 245 static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) 246 { 247 struct amdgpu_device *adev = ip_block->adev; 248 int i, r, idx; 249 250 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 251 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 252 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 253 254 if (adev->vcn.harvest_config & (1 << i)) 255 continue; 256 257 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 258 fw_shared->present_flag_0 = 0; 259 fw_shared->sq.is_enabled = 0; 260 } 261 262 drm_dev_exit(idx); 263 } 264 265 if (amdgpu_sriov_vf(adev)) 266 amdgpu_virt_free_mm_table(adev); 267 268 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 269 r = amdgpu_vcn_suspend(adev, i); 270 if (r) 271 return r; 272 273 r = amdgpu_vcn_sw_fini(adev, i); 274 if (r) 275 return r; 276 } 277 278 kfree(adev->vcn.ip_dump); 279 280 return 0; 281 } 282 283 /** 284 * vcn_v4_0_5_hw_init - start and test VCN block 285 * 286 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 287 * 288 * Initialize the hardware, boot up the VCPU and do some testing 289 */ 290 static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) 291 { 292 struct amdgpu_device *adev = ip_block->adev; 293 struct amdgpu_ring *ring; 294 int i, r; 295 296 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 297 if (adev->vcn.harvest_config & (1 << i)) 298 continue; 299 300 ring = &adev->vcn.inst[i].ring_enc[0]; 301 302 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 303 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 304 305 r = amdgpu_ring_test_helper(ring); 306 if (r) 307 return r; 308 } 309 310 return 0; 311 } 312 313 /** 314 * vcn_v4_0_5_hw_fini - stop the hardware block 315 * 316 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 317 * 318 * Stop the VCN block, mark ring as not ready any more 319 */ 320 static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block) 321 { 322 struct amdgpu_device *adev = ip_block->adev; 323 int i; 324 325 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 326 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 327 328 if (adev->vcn.harvest_config & (1 << i)) 329 continue; 330 331 cancel_delayed_work_sync(&vinst->idle_work); 332 333 if (!amdgpu_sriov_vf(adev)) { 334 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 335 (vinst->cur_state != AMD_PG_STATE_GATE && 336 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 337 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 338 } 339 } 340 } 341 342 return 0; 343 } 344 345 /** 346 * vcn_v4_0_5_suspend - suspend VCN block 347 * 348 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 349 * 350 * HW fini and suspend VCN block 351 */ 352 static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) 353 { 354 struct amdgpu_device *adev = ip_block->adev; 355 int r, i; 356 357 r = vcn_v4_0_5_hw_fini(ip_block); 358 if (r) 359 return r; 360 361 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 362 r = amdgpu_vcn_suspend(ip_block->adev, i); 363 if (r) 364 return r; 365 } 366 367 return r; 368 } 369 370 /** 371 * vcn_v4_0_5_resume - resume VCN block 372 * 373 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 374 * 375 * Resume firmware and hw init VCN block 376 */ 377 static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block) 378 { 379 struct amdgpu_device *adev = ip_block->adev; 380 int r, i; 381 382 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 383 r = amdgpu_vcn_resume(ip_block->adev, i); 384 if (r) 385 return r; 386 } 387 388 r = vcn_v4_0_5_hw_init(ip_block); 389 390 return r; 391 } 392 393 /** 394 * vcn_v4_0_5_mc_resume - memory controller programming 395 * 396 * @vinst: VCN instance 397 * 398 * Let the VCN memory controller know it's offsets 399 */ 400 static void vcn_v4_0_5_mc_resume(struct amdgpu_vcn_inst *vinst) 401 { 402 struct amdgpu_device *adev = vinst->adev; 403 int inst = vinst->inst; 404 uint32_t offset, size; 405 const struct common_firmware_header *hdr; 406 407 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 408 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 409 410 /* cache window 0: fw */ 411 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 412 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 413 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 414 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 415 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 416 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 417 offset = 0; 418 } else { 419 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 420 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 421 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 422 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 423 offset = size; 424 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 425 } 426 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 427 428 /* cache window 1: stack */ 429 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 430 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 431 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 432 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 433 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 434 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 435 436 /* cache window 2: context */ 437 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 438 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 439 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 440 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 441 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 442 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 443 444 /* non-cache window */ 445 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 446 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 447 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 448 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 449 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 450 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 451 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 452 } 453 454 /** 455 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode 456 * 457 * @vinst: VCN instance 458 * @indirect: indirectly write sram 459 * 460 * Let the VCN memory controller know it's offsets with dpg mode 461 */ 462 static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 463 bool indirect) 464 { 465 struct amdgpu_device *adev = vinst->adev; 466 int inst_idx = vinst->inst; 467 uint32_t offset, size; 468 const struct common_firmware_header *hdr; 469 470 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 471 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 472 473 /* cache window 0: fw */ 474 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 475 if (!indirect) { 476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 477 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 478 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 479 0, indirect); 480 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 481 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 482 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 483 0, indirect); 484 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 485 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 486 } else { 487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 488 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 489 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 490 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 491 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 492 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 493 } 494 offset = 0; 495 } else { 496 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 497 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 498 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 501 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 502 offset = size; 503 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 504 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 505 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 506 } 507 508 if (!indirect) 509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 510 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 511 else 512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 513 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 514 515 /* cache window 1: stack */ 516 if (!indirect) { 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 519 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 521 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 522 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 524 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 525 } else { 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 529 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 531 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 532 } 533 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 536 537 /* cache window 2: context */ 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 540 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 541 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 544 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 545 0, indirect); 546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 547 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 549 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 550 551 /* non-cache window */ 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 553 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 554 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 556 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 557 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 559 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 561 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 562 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 563 564 /* VCN global tiling registers */ 565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 566 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 567 adev->gfx.config.gb_addr_config, 0, indirect); 568 } 569 570 /** 571 * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating 572 * 573 * @vinst: VCN instance 574 * 575 * Disable static power gating for VCN block 576 */ 577 static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 578 { 579 struct amdgpu_device *adev = vinst->adev; 580 int inst = vinst->inst; 581 uint32_t data = 0; 582 583 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 584 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 585 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 586 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 587 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 588 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 589 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 590 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 591 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 592 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 593 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 594 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 595 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 596 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 597 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 598 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 599 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 600 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 601 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 602 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 603 } else { 604 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 605 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 606 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 607 0, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 608 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 609 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 610 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 611 0, UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 612 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 613 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 614 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 615 0, UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 616 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 617 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 618 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 619 0, UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 620 } 621 622 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 623 data &= ~0x103; 624 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 625 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 626 UVD_POWER_STATUS__UVD_PG_EN_MASK; 627 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 628 } 629 630 /** 631 * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating 632 * 633 * @vinst: VCN instance 634 * 635 * Enable static power gating for VCN block 636 */ 637 static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 638 { 639 struct amdgpu_device *adev = vinst->adev; 640 int inst = vinst->inst; 641 uint32_t data; 642 643 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 644 /* Before power off, this indicator has to be turned on */ 645 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 646 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 647 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 648 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 649 650 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 651 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 652 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 653 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 654 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 655 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 656 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 657 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 658 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 659 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 660 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 661 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 662 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 663 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 664 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 665 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 666 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 667 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 668 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 669 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 670 } 671 } 672 673 /** 674 * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating 675 * 676 * @vinst: VCN instance 677 * 678 * Disable clock gating for VCN block 679 */ 680 static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 681 { 682 struct amdgpu_device *adev = vinst->adev; 683 int inst = vinst->inst; 684 uint32_t data; 685 686 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 687 return; 688 689 /* VCN disable CGC */ 690 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 691 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 692 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 693 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 694 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 695 696 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 697 data &= ~(UVD_CGC_GATE__SYS_MASK 698 | UVD_CGC_GATE__UDEC_MASK 699 | UVD_CGC_GATE__MPEG2_MASK 700 | UVD_CGC_GATE__REGS_MASK 701 | UVD_CGC_GATE__RBC_MASK 702 | UVD_CGC_GATE__LMI_MC_MASK 703 | UVD_CGC_GATE__LMI_UMC_MASK 704 | UVD_CGC_GATE__IDCT_MASK 705 | UVD_CGC_GATE__MPRD_MASK 706 | UVD_CGC_GATE__MPC_MASK 707 | UVD_CGC_GATE__LBSI_MASK 708 | UVD_CGC_GATE__LRBBM_MASK 709 | UVD_CGC_GATE__UDEC_RE_MASK 710 | UVD_CGC_GATE__UDEC_CM_MASK 711 | UVD_CGC_GATE__UDEC_IT_MASK 712 | UVD_CGC_GATE__UDEC_DB_MASK 713 | UVD_CGC_GATE__UDEC_MP_MASK 714 | UVD_CGC_GATE__WCB_MASK 715 | UVD_CGC_GATE__VCPU_MASK 716 | UVD_CGC_GATE__MMSCH_MASK); 717 718 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 719 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 720 721 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 722 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 723 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 724 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 725 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 726 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 727 | UVD_CGC_CTRL__SYS_MODE_MASK 728 | UVD_CGC_CTRL__UDEC_MODE_MASK 729 | UVD_CGC_CTRL__MPEG2_MODE_MASK 730 | UVD_CGC_CTRL__REGS_MODE_MASK 731 | UVD_CGC_CTRL__RBC_MODE_MASK 732 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 733 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 734 | UVD_CGC_CTRL__IDCT_MODE_MASK 735 | UVD_CGC_CTRL__MPRD_MODE_MASK 736 | UVD_CGC_CTRL__MPC_MODE_MASK 737 | UVD_CGC_CTRL__LBSI_MODE_MASK 738 | UVD_CGC_CTRL__LRBBM_MODE_MASK 739 | UVD_CGC_CTRL__WCB_MODE_MASK 740 | UVD_CGC_CTRL__VCPU_MODE_MASK 741 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 742 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 743 744 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 745 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 746 | UVD_SUVD_CGC_GATE__SIT_MASK 747 | UVD_SUVD_CGC_GATE__SMP_MASK 748 | UVD_SUVD_CGC_GATE__SCM_MASK 749 | UVD_SUVD_CGC_GATE__SDB_MASK 750 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 751 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 752 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 753 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 754 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 755 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 756 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 757 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 758 | UVD_SUVD_CGC_GATE__SCLR_MASK 759 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 760 | UVD_SUVD_CGC_GATE__ENT_MASK 761 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 762 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 763 | UVD_SUVD_CGC_GATE__SITE_MASK 764 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 765 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 766 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 767 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 768 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 769 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 770 771 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 772 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 773 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 774 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 775 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 776 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 777 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 778 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 779 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 780 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 781 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 782 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 783 } 784 785 /** 786 * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 787 * 788 * @vinst: VCN instance 789 * @sram_sel: sram select 790 * @indirect: indirectly write sram 791 * 792 * Disable clock gating for VCN block with dpg mode 793 */ 794 static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 795 uint8_t sram_sel, 796 uint8_t indirect) 797 { 798 struct amdgpu_device *adev = vinst->adev; 799 int inst_idx = vinst->inst; 800 uint32_t reg_data = 0; 801 802 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 803 return; 804 805 /* enable sw clock gating control */ 806 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 807 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 808 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 809 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 810 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 811 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 812 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 813 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 814 UVD_CGC_CTRL__SYS_MODE_MASK | 815 UVD_CGC_CTRL__UDEC_MODE_MASK | 816 UVD_CGC_CTRL__MPEG2_MODE_MASK | 817 UVD_CGC_CTRL__REGS_MODE_MASK | 818 UVD_CGC_CTRL__RBC_MODE_MASK | 819 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 820 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 821 UVD_CGC_CTRL__IDCT_MODE_MASK | 822 UVD_CGC_CTRL__MPRD_MODE_MASK | 823 UVD_CGC_CTRL__MPC_MODE_MASK | 824 UVD_CGC_CTRL__LBSI_MODE_MASK | 825 UVD_CGC_CTRL__LRBBM_MODE_MASK | 826 UVD_CGC_CTRL__WCB_MODE_MASK | 827 UVD_CGC_CTRL__VCPU_MODE_MASK); 828 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 829 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 830 831 /* turn off clock gating */ 832 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 833 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 834 835 /* turn on SUVD clock gating */ 836 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 837 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 838 839 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 840 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 841 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 842 } 843 844 /** 845 * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating 846 * 847 * @vinst: VCN instance 848 * 849 * Enable clock gating for VCN block 850 */ 851 static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 852 { 853 struct amdgpu_device *adev = vinst->adev; 854 int inst = vinst->inst; 855 uint32_t data; 856 857 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 858 return; 859 860 /* enable VCN CGC */ 861 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 862 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 863 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 864 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 865 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 866 867 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 868 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 869 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 870 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 871 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 872 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 873 | UVD_CGC_CTRL__SYS_MODE_MASK 874 | UVD_CGC_CTRL__UDEC_MODE_MASK 875 | UVD_CGC_CTRL__MPEG2_MODE_MASK 876 | UVD_CGC_CTRL__REGS_MODE_MASK 877 | UVD_CGC_CTRL__RBC_MODE_MASK 878 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 879 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 880 | UVD_CGC_CTRL__IDCT_MODE_MASK 881 | UVD_CGC_CTRL__MPRD_MODE_MASK 882 | UVD_CGC_CTRL__MPC_MODE_MASK 883 | UVD_CGC_CTRL__LBSI_MODE_MASK 884 | UVD_CGC_CTRL__LRBBM_MODE_MASK 885 | UVD_CGC_CTRL__WCB_MODE_MASK 886 | UVD_CGC_CTRL__VCPU_MODE_MASK 887 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 888 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 889 890 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 891 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 892 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 893 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 894 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 895 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 896 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 897 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 898 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 899 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 900 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 901 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 902 } 903 904 /** 905 * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode 906 * 907 * @vinst: VCN instance 908 * @indirect: indirectly write sram 909 * 910 * Start VCN block with dpg mode 911 */ 912 static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 913 bool indirect) 914 { 915 struct amdgpu_device *adev = vinst->adev; 916 int inst_idx = vinst->inst; 917 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 918 struct amdgpu_ring *ring; 919 uint32_t tmp; 920 int ret; 921 922 /* disable register anti-hang mechanism */ 923 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 924 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 925 /* enable dynamic power gating mode */ 926 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 927 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 928 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 929 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 930 931 if (indirect) 932 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 933 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 934 935 /* enable clock gating */ 936 vcn_v4_0_5_disable_clock_gating_dpg_mode(vinst, 0, indirect); 937 938 /* enable VCPU clock */ 939 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 940 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 941 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 942 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 943 944 /* disable master interrupt */ 945 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 946 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 947 948 /* setup regUVD_LMI_CTRL */ 949 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 950 UVD_LMI_CTRL__REQ_MODE_MASK | 951 UVD_LMI_CTRL__CRC_RESET_MASK | 952 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 953 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 954 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 955 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 956 0x00100000L); 957 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 958 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 959 960 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 961 VCN, inst_idx, regUVD_MPC_CNTL), 962 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 963 964 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 965 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 966 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 967 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 968 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 969 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 970 971 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 972 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 973 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 974 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 975 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 976 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 977 978 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 979 VCN, inst_idx, regUVD_MPC_SET_MUX), 980 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 981 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 982 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 983 984 vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect); 985 986 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 987 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 988 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 989 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 990 991 /* enable LMI MC and UMC channels */ 992 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 993 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 994 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 995 996 /* enable master interrupt */ 997 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 998 VCN, inst_idx, regUVD_MASTINT_EN), 999 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1000 1001 if (indirect) { 1002 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1003 if (ret) { 1004 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 1005 return ret; 1006 } 1007 } 1008 1009 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1010 1011 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 1012 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1013 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1014 1015 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1016 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1017 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1018 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1019 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1020 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1021 1022 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1023 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1024 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1025 1026 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1027 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1028 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1029 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1030 1031 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1032 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1033 VCN_RB1_DB_CTRL__EN_MASK); 1034 1035 /* Keeping one read-back to ensure all register writes are done, otherwise 1036 * it may introduce race conditions */ 1037 RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL); 1038 1039 return 0; 1040 } 1041 1042 1043 /** 1044 * vcn_v4_0_5_start - VCN start 1045 * 1046 * @vinst: VCN instance 1047 * 1048 * Start VCN block 1049 */ 1050 static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst) 1051 { 1052 struct amdgpu_device *adev = vinst->adev; 1053 int i = vinst->inst; 1054 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1055 struct amdgpu_ring *ring; 1056 uint32_t tmp; 1057 int j, k, r; 1058 1059 if (adev->vcn.harvest_config & (1 << i)) 1060 return 0; 1061 1062 if (adev->pm.dpm_enabled) 1063 amdgpu_dpm_enable_vcn(adev, true, i); 1064 1065 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1066 1067 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1068 return vcn_v4_0_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1069 1070 /* disable VCN power gating */ 1071 vcn_v4_0_5_disable_static_power_gating(vinst); 1072 1073 /* set VCN status busy */ 1074 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1075 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1076 1077 /* SW clock gating */ 1078 vcn_v4_0_5_disable_clock_gating(vinst); 1079 1080 /* enable VCPU clock */ 1081 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1082 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1083 1084 /* disable master interrupt */ 1085 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1086 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1087 1088 /* enable LMI MC and UMC channels */ 1089 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1090 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1091 1092 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1093 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1094 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1095 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1096 1097 /* setup regUVD_LMI_CTRL */ 1098 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1099 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1100 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1101 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1102 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1103 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1104 1105 /* setup regUVD_MPC_CNTL */ 1106 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1107 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1108 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1109 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1110 1111 /* setup UVD_MPC_SET_MUXA0 */ 1112 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1113 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1114 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1115 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1116 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1117 1118 /* setup UVD_MPC_SET_MUXB0 */ 1119 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1120 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1121 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1122 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1123 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1124 1125 /* setup UVD_MPC_SET_MUX */ 1126 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1127 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1128 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1129 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1130 1131 vcn_v4_0_5_mc_resume(vinst); 1132 1133 /* VCN global tiling registers */ 1134 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1135 adev->gfx.config.gb_addr_config); 1136 1137 /* unblock VCPU register access */ 1138 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1139 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1140 1141 /* release VCPU reset to boot */ 1142 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1143 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1144 1145 for (j = 0; j < 10; ++j) { 1146 uint32_t status; 1147 1148 for (k = 0; k < 100; ++k) { 1149 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1150 if (status & 2) 1151 break; 1152 mdelay(10); 1153 if (amdgpu_emu_mode == 1) 1154 msleep(1); 1155 } 1156 1157 if (amdgpu_emu_mode == 1) { 1158 r = -1; 1159 if (status & 2) { 1160 r = 0; 1161 break; 1162 } 1163 } else { 1164 r = 0; 1165 if (status & 2) 1166 break; 1167 1168 dev_err(adev->dev, 1169 "VCN[%d] is not responding, trying to reset VCPU!!!\n", i); 1170 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1171 UVD_VCPU_CNTL__BLK_RST_MASK, 1172 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1173 mdelay(10); 1174 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1175 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1176 1177 mdelay(10); 1178 r = -1; 1179 } 1180 } 1181 1182 if (r) { 1183 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1184 return r; 1185 } 1186 1187 /* enable master interrupt */ 1188 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1189 UVD_MASTINT_EN__VCPU_EN_MASK, 1190 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1191 1192 /* clear the busy bit of VCN_STATUS */ 1193 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1194 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1195 1196 ring = &adev->vcn.inst[i].ring_enc[0]; 1197 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1198 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1199 VCN_RB1_DB_CTRL__EN_MASK); 1200 1201 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1202 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1203 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1204 1205 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1206 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1207 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1208 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1209 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1210 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1211 1212 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1213 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1214 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1215 1216 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1217 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1218 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1219 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1220 1221 /* Keeping one read-back to ensure all register writes are done, otherwise 1222 * it may introduce race conditions */ 1223 RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1224 1225 return 0; 1226 } 1227 1228 /** 1229 * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode 1230 * 1231 * @vinst: VCN instance 1232 * 1233 * Stop VCN block with dpg mode 1234 */ 1235 static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1236 { 1237 struct amdgpu_device *adev = vinst->adev; 1238 int inst_idx = vinst->inst; 1239 uint32_t tmp; 1240 1241 /* Wait for power status to be 1 */ 1242 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1243 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1244 1245 /* wait for read ptr to be equal to write ptr */ 1246 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1247 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1248 1249 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1250 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1251 1252 /* disable dynamic power gating mode */ 1253 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1254 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1255 1256 /* Keeping one read-back to ensure all register writes are done, 1257 * otherwise it may introduce race conditions. 1258 */ 1259 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); 1260 } 1261 1262 /** 1263 * vcn_v4_0_5_stop - VCN stop 1264 * 1265 * @vinst: VCN instance 1266 * 1267 * Stop VCN block 1268 */ 1269 static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst) 1270 { 1271 struct amdgpu_device *adev = vinst->adev; 1272 int i = vinst->inst; 1273 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1274 uint32_t tmp; 1275 int r = 0; 1276 1277 if (adev->vcn.harvest_config & (1 << i)) 1278 return 0; 1279 1280 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1281 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1282 1283 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1284 vcn_v4_0_5_stop_dpg_mode(vinst); 1285 r = 0; 1286 goto done; 1287 } 1288 1289 /* wait for vcn idle */ 1290 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1291 if (r) 1292 goto done; 1293 1294 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1295 UVD_LMI_STATUS__READ_CLEAN_MASK | 1296 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1297 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1298 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1299 if (r) 1300 goto done; 1301 1302 /* disable LMI UMC channel */ 1303 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1304 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1305 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1306 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1307 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1308 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1309 if (r) 1310 goto done; 1311 1312 /* block VCPU register access */ 1313 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1314 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1315 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1316 1317 /* reset VCPU */ 1318 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1319 UVD_VCPU_CNTL__BLK_RST_MASK, 1320 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1321 1322 /* disable VCPU clock */ 1323 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1324 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1325 1326 /* apply soft reset */ 1327 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1328 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1329 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1330 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1331 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1332 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1333 1334 /* clear status */ 1335 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1336 1337 /* apply HW clock gating */ 1338 vcn_v4_0_5_enable_clock_gating(vinst); 1339 1340 /* enable VCN power gating */ 1341 vcn_v4_0_5_enable_static_power_gating(vinst); 1342 1343 /* Keeping one read-back to ensure all register writes are done, 1344 * otherwise it may introduce race conditions. 1345 */ 1346 RREG32_SOC15(VCN, i, regUVD_STATUS); 1347 1348 done: 1349 if (adev->pm.dpm_enabled) 1350 amdgpu_dpm_enable_vcn(adev, false, i); 1351 1352 return r; 1353 } 1354 1355 /** 1356 * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode 1357 * 1358 * @vinst: VCN instance 1359 * @new_state: pause state 1360 * 1361 * Pause dpg mode for VCN block 1362 */ 1363 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1364 struct dpg_pause_state *new_state) 1365 { 1366 struct amdgpu_device *adev = vinst->adev; 1367 int inst_idx = vinst->inst; 1368 uint32_t reg_data = 0; 1369 int ret_code; 1370 1371 /* pause/unpause if state is changed */ 1372 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1373 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1374 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1375 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1376 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1377 1378 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1379 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1380 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1381 1382 if (!ret_code) { 1383 /* pause DPG */ 1384 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1385 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1386 1387 /* wait for ACK */ 1388 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1389 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1390 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1391 1392 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1393 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1394 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1395 } 1396 } else { 1397 /* unpause dpg, no need to wait */ 1398 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1399 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1400 } 1401 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1402 } 1403 1404 return 0; 1405 } 1406 1407 /** 1408 * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer 1409 * 1410 * @ring: amdgpu_ring pointer 1411 * 1412 * Returns the current hardware unified read pointer 1413 */ 1414 static uint64_t vcn_v4_0_5_unified_ring_get_rptr(struct amdgpu_ring *ring) 1415 { 1416 struct amdgpu_device *adev = ring->adev; 1417 1418 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1419 DRM_ERROR("wrong ring id is identified in %s", __func__); 1420 1421 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1422 } 1423 1424 /** 1425 * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer 1426 * 1427 * @ring: amdgpu_ring pointer 1428 * 1429 * Returns the current hardware unified write pointer 1430 */ 1431 static uint64_t vcn_v4_0_5_unified_ring_get_wptr(struct amdgpu_ring *ring) 1432 { 1433 struct amdgpu_device *adev = ring->adev; 1434 1435 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1436 DRM_ERROR("wrong ring id is identified in %s", __func__); 1437 1438 if (ring->use_doorbell) 1439 return *ring->wptr_cpu_addr; 1440 else 1441 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1442 } 1443 1444 /** 1445 * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer 1446 * 1447 * @ring: amdgpu_ring pointer 1448 * 1449 * Commits the enc write pointer to the hardware 1450 */ 1451 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring) 1452 { 1453 struct amdgpu_device *adev = ring->adev; 1454 1455 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1456 DRM_ERROR("wrong ring id is identified in %s", __func__); 1457 1458 if (ring->use_doorbell) { 1459 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1460 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1461 } else { 1462 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1463 } 1464 } 1465 1466 static int vcn_v4_0_5_ring_reset(struct amdgpu_ring *ring, 1467 unsigned int vmid, 1468 struct amdgpu_fence *timedout_fence) 1469 { 1470 struct amdgpu_device *adev = ring->adev; 1471 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1472 int r; 1473 1474 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1475 r = vcn_v4_0_5_stop(vinst); 1476 if (r) 1477 return r; 1478 r = vcn_v4_0_5_start(vinst); 1479 if (r) 1480 return r; 1481 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1482 } 1483 1484 static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { 1485 .type = AMDGPU_RING_TYPE_VCN_ENC, 1486 .align_mask = 0x3f, 1487 .nop = VCN_ENC_CMD_NO_OP, 1488 .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, 1489 .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, 1490 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, 1491 .emit_frame_size = 1492 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1493 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1494 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1495 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1496 1, /* vcn_v2_0_enc_ring_insert_end */ 1497 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1498 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1499 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1500 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1501 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1502 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1503 .insert_nop = amdgpu_ring_insert_nop, 1504 .insert_end = vcn_v2_0_enc_ring_insert_end, 1505 .pad_ib = amdgpu_ring_generic_pad_ib, 1506 .begin_use = amdgpu_vcn_ring_begin_use, 1507 .end_use = amdgpu_vcn_ring_end_use, 1508 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1509 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1510 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1511 .reset = vcn_v4_0_5_ring_reset, 1512 }; 1513 1514 /** 1515 * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions 1516 * 1517 * @adev: amdgpu_device pointer 1518 * 1519 * Set unified ring functions 1520 */ 1521 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev) 1522 { 1523 int i; 1524 1525 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1526 if (adev->vcn.harvest_config & (1 << i)) 1527 continue; 1528 1529 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) 1530 vcn_v4_0_5_unified_ring_vm_funcs.secure_submission_supported = true; 1531 1532 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs; 1533 adev->vcn.inst[i].ring_enc[0].me = i; 1534 } 1535 } 1536 1537 /** 1538 * vcn_v4_0_5_is_idle - check VCN block is idle 1539 * 1540 * @ip_block: Pointer to the amdgpu_ip_block structure 1541 * 1542 * Check whether VCN block is idle 1543 */ 1544 static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block) 1545 { 1546 struct amdgpu_device *adev = ip_block->adev; 1547 int i, ret = 1; 1548 1549 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1550 if (adev->vcn.harvest_config & (1 << i)) 1551 continue; 1552 1553 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1554 } 1555 1556 return ret; 1557 } 1558 1559 /** 1560 * vcn_v4_0_5_wait_for_idle - wait for VCN block idle 1561 * 1562 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1563 * 1564 * Wait for VCN block idle 1565 */ 1566 static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 1567 { 1568 struct amdgpu_device *adev = ip_block->adev; 1569 int i, ret = 0; 1570 1571 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1572 if (adev->vcn.harvest_config & (1 << i)) 1573 continue; 1574 1575 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1576 UVD_STATUS__IDLE); 1577 if (ret) 1578 return ret; 1579 } 1580 1581 return ret; 1582 } 1583 1584 /** 1585 * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state 1586 * 1587 * @ip_block: amdgpu_ip_block pointer 1588 * @state: clock gating state 1589 * 1590 * Set VCN block clockgating state 1591 */ 1592 static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1593 enum amd_clockgating_state state) 1594 { 1595 struct amdgpu_device *adev = ip_block->adev; 1596 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1597 int i; 1598 1599 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1600 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1601 1602 if (adev->vcn.harvest_config & (1 << i)) 1603 continue; 1604 1605 if (enable) { 1606 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1607 return -EBUSY; 1608 vcn_v4_0_5_enable_clock_gating(vinst); 1609 } else { 1610 vcn_v4_0_5_disable_clock_gating(vinst); 1611 } 1612 } 1613 1614 return 0; 1615 } 1616 1617 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 1618 enum amd_powergating_state state) 1619 { 1620 int ret = 0; 1621 1622 if (state == vinst->cur_state) 1623 return 0; 1624 1625 if (state == AMD_PG_STATE_GATE) 1626 ret = vcn_v4_0_5_stop(vinst); 1627 else 1628 ret = vcn_v4_0_5_start(vinst); 1629 1630 if (!ret) 1631 vinst->cur_state = state; 1632 1633 return ret; 1634 } 1635 1636 /** 1637 * vcn_v4_0_5_process_interrupt - process VCN block interrupt 1638 * 1639 * @adev: amdgpu_device pointer 1640 * @source: interrupt sources 1641 * @entry: interrupt entry from clients and sources 1642 * 1643 * Process VCN block interrupt 1644 */ 1645 static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1646 struct amdgpu_iv_entry *entry) 1647 { 1648 uint32_t ip_instance; 1649 1650 switch (entry->client_id) { 1651 case SOC15_IH_CLIENTID_VCN: 1652 ip_instance = 0; 1653 break; 1654 case SOC15_IH_CLIENTID_VCN1: 1655 ip_instance = 1; 1656 break; 1657 default: 1658 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1659 return 0; 1660 } 1661 1662 DRM_DEBUG("IH: VCN TRAP\n"); 1663 1664 switch (entry->src_id) { 1665 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1666 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1667 break; 1668 case VCN_4_0__SRCID_UVD_POISON: 1669 amdgpu_vcn_process_poison_irq(adev, source, entry); 1670 break; 1671 default: 1672 DRM_ERROR("Unhandled interrupt: %d %d\n", 1673 entry->src_id, entry->src_data[0]); 1674 break; 1675 } 1676 1677 return 0; 1678 } 1679 1680 static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = { 1681 .process = vcn_v4_0_5_process_interrupt, 1682 }; 1683 1684 /** 1685 * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions 1686 * 1687 * @adev: amdgpu_device pointer 1688 * 1689 * Set VCN block interrupt irq functions 1690 */ 1691 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) 1692 { 1693 int i; 1694 1695 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1696 if (adev->vcn.harvest_config & (1 << i)) 1697 continue; 1698 1699 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 1700 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs; 1701 } 1702 } 1703 1704 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { 1705 .name = "vcn_v4_0_5", 1706 .early_init = vcn_v4_0_5_early_init, 1707 .sw_init = vcn_v4_0_5_sw_init, 1708 .sw_fini = vcn_v4_0_5_sw_fini, 1709 .hw_init = vcn_v4_0_5_hw_init, 1710 .hw_fini = vcn_v4_0_5_hw_fini, 1711 .suspend = vcn_v4_0_5_suspend, 1712 .resume = vcn_v4_0_5_resume, 1713 .is_idle = vcn_v4_0_5_is_idle, 1714 .wait_for_idle = vcn_v4_0_5_wait_for_idle, 1715 .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, 1716 .set_powergating_state = vcn_set_powergating_state, 1717 .dump_ip_state = amdgpu_vcn_dump_ip_state, 1718 .print_ip_state = amdgpu_vcn_print_ip_state, 1719 }; 1720 1721 const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = { 1722 .type = AMD_IP_BLOCK_TYPE_VCN, 1723 .major = 4, 1724 .minor = 0, 1725 .rev = 5, 1726 .funcs = &vcn_v4_0_5_ip_funcs, 1727 }; 1728