1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0_5.h" 35 36 #include "vcn/vcn_4_0_5_offset.h" 37 #include "vcn/vcn_4_0_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 (0x48300 + 0x38000) 49 #define VCN1_AON_SOC_ADDRESS_3_0 (0x48000 + 0x38000) 50 51 #define VCN_HARVEST_MMSCH 0 52 53 #define RDECODE_MSG_CREATE 0x00000000 54 #define RDECODE_MESSAGE_CREATE 0x00000001 55 56 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = { 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 84 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 87 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 89 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 90 }; 91 92 static int amdgpu_ih_clientid_vcns[] = { 93 SOC15_IH_CLIENTID_VCN, 94 SOC15_IH_CLIENTID_VCN1 95 }; 96 97 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev); 99 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 100 enum amd_powergating_state state); 101 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 102 struct dpg_pause_state *new_state); 103 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring); 104 105 /** 106 * vcn_v4_0_5_early_init - set function pointers and load microcode 107 * 108 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 109 * 110 * Set ring and irq function pointers 111 * Load microcode from filesystem 112 */ 113 static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6)) 119 adev->vcn.per_inst_fw = true; 120 121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 122 /* re-use enc ring as unified ring */ 123 adev->vcn.inst[i].num_enc_rings = 1; 124 vcn_v4_0_5_set_unified_ring_funcs(adev); 125 vcn_v4_0_5_set_irq_funcs(adev); 126 127 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 128 adev->vcn.inst[i].set_pg_state = vcn_v4_0_5_set_pg_state; 129 130 r = amdgpu_vcn_early_init(adev, i); 131 if (r) 132 return r; 133 } 134 135 return 0; 136 } 137 138 /** 139 * vcn_v4_0_5_sw_init - sw init for VCN block 140 * 141 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 142 * 143 * Load firmware and sw initialization 144 */ 145 static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) 146 { 147 struct amdgpu_ring *ring; 148 struct amdgpu_device *adev = ip_block->adev; 149 int i, r; 150 151 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 152 struct amdgpu_vcn4_fw_shared *fw_shared; 153 154 if (adev->vcn.harvest_config & (1 << i)) 155 continue; 156 157 r = amdgpu_vcn_sw_init(adev, i); 158 if (r) 159 return r; 160 161 amdgpu_vcn_setup_ucode(adev, i); 162 163 r = amdgpu_vcn_resume(adev, i); 164 if (r) 165 return r; 166 167 atomic_set(&adev->vcn.inst[i].sched_score, 0); 168 169 /* VCN UNIFIED TRAP */ 170 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 171 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 172 if (r) 173 return r; 174 175 /* VCN POISON TRAP */ 176 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 177 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 178 if (r) 179 return r; 180 181 ring = &adev->vcn.inst[i].ring_enc[0]; 182 ring->use_doorbell = true; 183 if (amdgpu_sriov_vf(adev)) 184 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 185 i * (adev->vcn.inst[i].num_enc_rings + 1) + 1; 186 else 187 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 188 2 + 8 * i; 189 ring->vm_hub = AMDGPU_MMHUB0(0); 190 sprintf(ring->name, "vcn_unified_%d", i); 191 192 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 193 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 194 if (r) 195 return r; 196 197 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 198 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 199 fw_shared->sq.is_enabled = 1; 200 201 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 202 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 203 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 204 205 if (amdgpu_sriov_vf(adev)) 206 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 207 208 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT; 209 fw_shared->drm_key_wa.method = 210 AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING; 211 212 if (amdgpu_vcnfw_log) 213 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 214 215 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 216 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode; 217 } 218 219 adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 220 if (!amdgpu_sriov_vf(adev)) 221 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 222 223 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 224 if (r) 225 return r; 226 227 if (amdgpu_sriov_vf(adev)) { 228 r = amdgpu_virt_alloc_mm_table(adev); 229 if (r) 230 return r; 231 } 232 233 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_5, ARRAY_SIZE(vcn_reg_list_4_0_5)); 234 235 return r; 236 } 237 238 /** 239 * vcn_v4_0_5_sw_fini - sw fini for VCN block 240 * 241 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 242 * 243 * VCN suspend and free up sw allocation 244 */ 245 static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) 246 { 247 struct amdgpu_device *adev = ip_block->adev; 248 int i, r, idx; 249 250 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 251 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 252 struct amdgpu_vcn4_fw_shared *fw_shared; 253 254 if (adev->vcn.harvest_config & (1 << i)) 255 continue; 256 257 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 258 fw_shared->present_flag_0 = 0; 259 fw_shared->sq.is_enabled = 0; 260 } 261 262 drm_dev_exit(idx); 263 } 264 265 if (amdgpu_sriov_vf(adev)) 266 amdgpu_virt_free_mm_table(adev); 267 268 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 269 r = amdgpu_vcn_suspend(adev, i); 270 if (r) 271 return r; 272 273 amdgpu_vcn_sw_fini(adev, i); 274 } 275 276 return 0; 277 } 278 279 /** 280 * vcn_v4_0_5_hw_init - start and test VCN block 281 * 282 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 283 * 284 * Initialize the hardware, boot up the VCPU and do some testing 285 */ 286 static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) 287 { 288 struct amdgpu_device *adev = ip_block->adev; 289 struct amdgpu_ring *ring; 290 int i, r; 291 292 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 293 if (adev->vcn.harvest_config & (1 << i)) 294 continue; 295 296 ring = &adev->vcn.inst[i].ring_enc[0]; 297 298 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 299 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 300 301 r = amdgpu_ring_test_helper(ring); 302 if (r) 303 return r; 304 } 305 306 return 0; 307 } 308 309 /** 310 * vcn_v4_0_5_hw_fini - stop the hardware block 311 * 312 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 313 * 314 * Stop the VCN block, mark ring as not ready any more 315 */ 316 static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block) 317 { 318 struct amdgpu_device *adev = ip_block->adev; 319 int i; 320 321 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 322 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 323 324 if (adev->vcn.harvest_config & (1 << i)) 325 continue; 326 327 cancel_delayed_work_sync(&vinst->idle_work); 328 329 if (!amdgpu_sriov_vf(adev)) { 330 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 331 (vinst->cur_state != AMD_PG_STATE_GATE && 332 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 333 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 334 } 335 } 336 } 337 338 return 0; 339 } 340 341 /** 342 * vcn_v4_0_5_suspend - suspend VCN block 343 * 344 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 345 * 346 * HW fini and suspend VCN block 347 */ 348 static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) 349 { 350 struct amdgpu_device *adev = ip_block->adev; 351 int r, i; 352 353 r = vcn_v4_0_5_hw_fini(ip_block); 354 if (r) 355 return r; 356 357 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 358 r = amdgpu_vcn_suspend(ip_block->adev, i); 359 if (r) 360 return r; 361 } 362 363 return r; 364 } 365 366 /** 367 * vcn_v4_0_5_resume - resume VCN block 368 * 369 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 370 * 371 * Resume firmware and hw init VCN block 372 */ 373 static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block) 374 { 375 struct amdgpu_device *adev = ip_block->adev; 376 int r, i; 377 378 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 379 r = amdgpu_vcn_resume(ip_block->adev, i); 380 if (r) 381 return r; 382 } 383 384 r = vcn_v4_0_5_hw_init(ip_block); 385 386 return r; 387 } 388 389 /** 390 * vcn_v4_0_5_mc_resume - memory controller programming 391 * 392 * @vinst: VCN instance 393 * 394 * Let the VCN memory controller know it's offsets 395 */ 396 static void vcn_v4_0_5_mc_resume(struct amdgpu_vcn_inst *vinst) 397 { 398 struct amdgpu_device *adev = vinst->adev; 399 int inst = vinst->inst; 400 uint32_t offset, size; 401 const struct common_firmware_header *hdr; 402 403 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 404 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 405 406 /* cache window 0: fw */ 407 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 408 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 409 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 410 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 411 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 412 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 413 offset = 0; 414 } else { 415 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 416 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 417 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 418 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 419 offset = size; 420 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 421 } 422 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 423 424 /* cache window 1: stack */ 425 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 426 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 427 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 428 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 429 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 430 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 431 432 /* cache window 2: context */ 433 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 434 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 435 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 436 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 437 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 438 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 439 440 /* non-cache window */ 441 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 442 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 443 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 444 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 445 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 446 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 447 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 448 } 449 450 /** 451 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode 452 * 453 * @vinst: VCN instance 454 * @indirect: indirectly write sram 455 * 456 * Let the VCN memory controller know it's offsets with dpg mode 457 */ 458 static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 459 bool indirect) 460 { 461 struct amdgpu_device *adev = vinst->adev; 462 int inst_idx = vinst->inst; 463 uint32_t offset, size; 464 const struct common_firmware_header *hdr; 465 466 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 467 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 468 469 /* cache window 0: fw */ 470 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 471 if (!indirect) { 472 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 473 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 474 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 475 0, indirect); 476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 477 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 478 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 479 0, indirect); 480 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 481 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 482 } else { 483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 484 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 486 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 488 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 489 } 490 offset = 0; 491 } else { 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 494 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 496 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 497 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 498 offset = size; 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 501 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 502 } 503 504 if (!indirect) 505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 506 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 507 else 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 510 511 /* cache window 1: stack */ 512 if (!indirect) { 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 515 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 516 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 517 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 518 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 520 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 521 } else { 522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 523 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 525 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 528 } 529 530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 531 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 532 533 /* cache window 2: context */ 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 536 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 537 0, indirect); 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 540 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 541 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 545 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 546 547 /* non-cache window */ 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 549 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 550 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 553 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 558 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 559 560 /* VCN global tiling registers */ 561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 562 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 563 adev->gfx.config.gb_addr_config, 0, indirect); 564 } 565 566 /** 567 * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating 568 * 569 * @vinst: VCN instance 570 * 571 * Disable static power gating for VCN block 572 */ 573 static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 574 { 575 struct amdgpu_device *adev = vinst->adev; 576 int inst = vinst->inst; 577 uint32_t data = 0; 578 579 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 580 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 581 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 582 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, 583 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 584 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 585 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 586 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 587 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 588 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 589 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 590 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 591 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 592 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 593 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 594 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 595 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 596 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 597 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 598 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 599 } else { 600 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 601 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 602 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 603 0, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 604 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 605 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 606 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 607 0, UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 608 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 609 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 610 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 611 0, UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 612 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 613 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 614 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 615 0, UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 616 } 617 618 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 619 data &= ~0x103; 620 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 621 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 622 UVD_POWER_STATUS__UVD_PG_EN_MASK; 623 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 624 } 625 626 /** 627 * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating 628 * 629 * @vinst: VCN instance 630 * 631 * Enable static power gating for VCN block 632 */ 633 static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 634 { 635 struct amdgpu_device *adev = vinst->adev; 636 int inst = vinst->inst; 637 uint32_t data; 638 639 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 640 /* Before power off, this indicator has to be turned on */ 641 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 642 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 643 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 644 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 645 646 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 647 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT); 648 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 649 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT, 650 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK); 651 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 652 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT); 653 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 654 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT, 655 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK); 656 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 657 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT); 658 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 659 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT, 660 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK); 661 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, 662 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT); 663 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 664 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT, 665 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK); 666 } 667 } 668 669 /** 670 * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating 671 * 672 * @vinst: VCN instance 673 * 674 * Disable clock gating for VCN block 675 */ 676 static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 677 { 678 struct amdgpu_device *adev = vinst->adev; 679 int inst = vinst->inst; 680 uint32_t data; 681 682 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 683 return; 684 685 /* VCN disable CGC */ 686 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 687 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 688 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 689 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 690 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 691 692 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 693 data &= ~(UVD_CGC_GATE__SYS_MASK 694 | UVD_CGC_GATE__UDEC_MASK 695 | UVD_CGC_GATE__MPEG2_MASK 696 | UVD_CGC_GATE__REGS_MASK 697 | UVD_CGC_GATE__RBC_MASK 698 | UVD_CGC_GATE__LMI_MC_MASK 699 | UVD_CGC_GATE__LMI_UMC_MASK 700 | UVD_CGC_GATE__IDCT_MASK 701 | UVD_CGC_GATE__MPRD_MASK 702 | UVD_CGC_GATE__MPC_MASK 703 | UVD_CGC_GATE__LBSI_MASK 704 | UVD_CGC_GATE__LRBBM_MASK 705 | UVD_CGC_GATE__UDEC_RE_MASK 706 | UVD_CGC_GATE__UDEC_CM_MASK 707 | UVD_CGC_GATE__UDEC_IT_MASK 708 | UVD_CGC_GATE__UDEC_DB_MASK 709 | UVD_CGC_GATE__UDEC_MP_MASK 710 | UVD_CGC_GATE__WCB_MASK 711 | UVD_CGC_GATE__VCPU_MASK 712 | UVD_CGC_GATE__MMSCH_MASK); 713 714 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 715 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 716 717 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 718 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 719 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 720 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 721 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 722 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 723 | UVD_CGC_CTRL__SYS_MODE_MASK 724 | UVD_CGC_CTRL__UDEC_MODE_MASK 725 | UVD_CGC_CTRL__MPEG2_MODE_MASK 726 | UVD_CGC_CTRL__REGS_MODE_MASK 727 | UVD_CGC_CTRL__RBC_MODE_MASK 728 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 729 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 730 | UVD_CGC_CTRL__IDCT_MODE_MASK 731 | UVD_CGC_CTRL__MPRD_MODE_MASK 732 | UVD_CGC_CTRL__MPC_MODE_MASK 733 | UVD_CGC_CTRL__LBSI_MODE_MASK 734 | UVD_CGC_CTRL__LRBBM_MODE_MASK 735 | UVD_CGC_CTRL__WCB_MODE_MASK 736 | UVD_CGC_CTRL__VCPU_MODE_MASK 737 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 738 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 739 740 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 741 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 742 | UVD_SUVD_CGC_GATE__SIT_MASK 743 | UVD_SUVD_CGC_GATE__SMP_MASK 744 | UVD_SUVD_CGC_GATE__SCM_MASK 745 | UVD_SUVD_CGC_GATE__SDB_MASK 746 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 747 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 748 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 749 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 750 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 751 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 752 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 753 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 754 | UVD_SUVD_CGC_GATE__SCLR_MASK 755 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 756 | UVD_SUVD_CGC_GATE__ENT_MASK 757 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 758 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 759 | UVD_SUVD_CGC_GATE__SITE_MASK 760 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 761 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 762 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 763 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 764 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 765 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 766 767 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 768 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 769 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 770 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 771 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 772 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 773 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 774 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 775 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 776 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 777 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 778 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 779 } 780 781 /** 782 * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 783 * 784 * @vinst: VCN instance 785 * @sram_sel: sram select 786 * @indirect: indirectly write sram 787 * 788 * Disable clock gating for VCN block with dpg mode 789 */ 790 static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 791 uint8_t sram_sel, 792 uint8_t indirect) 793 { 794 struct amdgpu_device *adev = vinst->adev; 795 int inst_idx = vinst->inst; 796 uint32_t reg_data = 0; 797 798 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 799 return; 800 801 /* enable sw clock gating control */ 802 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 803 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 804 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 805 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 806 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 807 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 808 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 809 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 810 UVD_CGC_CTRL__SYS_MODE_MASK | 811 UVD_CGC_CTRL__UDEC_MODE_MASK | 812 UVD_CGC_CTRL__MPEG2_MODE_MASK | 813 UVD_CGC_CTRL__REGS_MODE_MASK | 814 UVD_CGC_CTRL__RBC_MODE_MASK | 815 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 816 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 817 UVD_CGC_CTRL__IDCT_MODE_MASK | 818 UVD_CGC_CTRL__MPRD_MODE_MASK | 819 UVD_CGC_CTRL__MPC_MODE_MASK | 820 UVD_CGC_CTRL__LBSI_MODE_MASK | 821 UVD_CGC_CTRL__LRBBM_MODE_MASK | 822 UVD_CGC_CTRL__WCB_MODE_MASK | 823 UVD_CGC_CTRL__VCPU_MODE_MASK); 824 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 825 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 826 827 /* turn off clock gating */ 828 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 829 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 830 831 /* turn on SUVD clock gating */ 832 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 833 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 834 835 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 836 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 837 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 838 } 839 840 /** 841 * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating 842 * 843 * @vinst: VCN instance 844 * 845 * Enable clock gating for VCN block 846 */ 847 static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 848 { 849 struct amdgpu_device *adev = vinst->adev; 850 int inst = vinst->inst; 851 uint32_t data; 852 853 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 854 return; 855 856 /* enable VCN CGC */ 857 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 858 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 859 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 860 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 861 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 862 863 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 864 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 865 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 866 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 867 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 868 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 869 | UVD_CGC_CTRL__SYS_MODE_MASK 870 | UVD_CGC_CTRL__UDEC_MODE_MASK 871 | UVD_CGC_CTRL__MPEG2_MODE_MASK 872 | UVD_CGC_CTRL__REGS_MODE_MASK 873 | UVD_CGC_CTRL__RBC_MODE_MASK 874 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 875 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 876 | UVD_CGC_CTRL__IDCT_MODE_MASK 877 | UVD_CGC_CTRL__MPRD_MODE_MASK 878 | UVD_CGC_CTRL__MPC_MODE_MASK 879 | UVD_CGC_CTRL__LBSI_MODE_MASK 880 | UVD_CGC_CTRL__LRBBM_MODE_MASK 881 | UVD_CGC_CTRL__WCB_MODE_MASK 882 | UVD_CGC_CTRL__VCPU_MODE_MASK 883 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 884 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 885 886 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 887 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 888 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 889 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 890 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 891 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 892 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 893 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 894 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 895 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 896 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 897 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 898 } 899 900 /** 901 * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode 902 * 903 * @vinst: VCN instance 904 * @indirect: indirectly write sram 905 * 906 * Start VCN block with dpg mode 907 */ 908 static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 909 bool indirect) 910 { 911 struct amdgpu_device *adev = vinst->adev; 912 int inst_idx = vinst->inst; 913 struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 914 struct amdgpu_ring *ring; 915 uint32_t tmp; 916 int ret; 917 918 /* disable register anti-hang mechanism */ 919 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 920 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 921 /* enable dynamic power gating mode */ 922 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 923 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 924 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 925 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 926 927 if (indirect) 928 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 929 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 930 931 /* enable clock gating */ 932 vcn_v4_0_5_disable_clock_gating_dpg_mode(vinst, 0, indirect); 933 934 /* enable VCPU clock */ 935 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 936 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 937 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 938 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 939 940 /* disable master interrupt */ 941 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 942 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 943 944 /* setup regUVD_LMI_CTRL */ 945 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 946 UVD_LMI_CTRL__REQ_MODE_MASK | 947 UVD_LMI_CTRL__CRC_RESET_MASK | 948 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 949 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 950 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 951 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 952 0x00100000L); 953 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 954 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 955 956 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 957 VCN, inst_idx, regUVD_MPC_CNTL), 958 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 959 960 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 961 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 962 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 963 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 964 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 965 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 966 967 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 968 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 969 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 970 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 971 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 972 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 973 974 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 975 VCN, inst_idx, regUVD_MPC_SET_MUX), 976 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 977 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 978 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 979 980 vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect); 981 982 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 983 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 984 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 985 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 986 987 /* enable LMI MC and UMC channels */ 988 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 989 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 990 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 991 992 /* enable master interrupt */ 993 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 994 VCN, inst_idx, regUVD_MASTINT_EN), 995 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 996 997 if (indirect) { 998 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 999 if (ret) { 1000 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 1001 return ret; 1002 } 1003 } 1004 1005 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1006 1007 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 1008 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1009 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1010 1011 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1012 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1013 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1014 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1015 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1016 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1017 1018 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1019 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1020 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1021 1022 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1023 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1024 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1025 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1026 1027 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1028 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1029 VCN_RB1_DB_CTRL__EN_MASK); 1030 1031 /* Keeping one read-back to ensure all register writes are done, otherwise 1032 * it may introduce race conditions */ 1033 RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL); 1034 1035 return 0; 1036 } 1037 1038 1039 /** 1040 * vcn_v4_0_5_start - VCN start 1041 * 1042 * @vinst: VCN instance 1043 * 1044 * Start VCN block 1045 */ 1046 static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst) 1047 { 1048 struct amdgpu_device *adev = vinst->adev; 1049 int i = vinst->inst; 1050 struct amdgpu_vcn4_fw_shared *fw_shared; 1051 struct amdgpu_ring *ring; 1052 uint32_t tmp; 1053 int j, k, r; 1054 1055 if (adev->vcn.harvest_config & (1 << i)) 1056 return 0; 1057 1058 if (adev->pm.dpm_enabled) 1059 amdgpu_dpm_enable_vcn(adev, true, i); 1060 1061 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1062 1063 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1064 return vcn_v4_0_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1065 1066 /* disable VCN power gating */ 1067 vcn_v4_0_5_disable_static_power_gating(vinst); 1068 1069 /* set VCN status busy */ 1070 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1071 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1072 1073 /* SW clock gating */ 1074 vcn_v4_0_5_disable_clock_gating(vinst); 1075 1076 /* enable VCPU clock */ 1077 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1078 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1079 1080 /* disable master interrupt */ 1081 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1082 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1083 1084 /* enable LMI MC and UMC channels */ 1085 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1086 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1087 1088 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1089 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1090 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1091 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1092 1093 /* setup regUVD_LMI_CTRL */ 1094 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1095 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1096 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1097 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1098 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1099 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1100 1101 /* setup regUVD_MPC_CNTL */ 1102 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1103 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1104 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1105 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1106 1107 /* setup UVD_MPC_SET_MUXA0 */ 1108 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1109 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1110 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1111 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1112 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1113 1114 /* setup UVD_MPC_SET_MUXB0 */ 1115 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1116 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1117 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1118 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1119 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1120 1121 /* setup UVD_MPC_SET_MUX */ 1122 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1123 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1124 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1125 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1126 1127 vcn_v4_0_5_mc_resume(vinst); 1128 1129 /* VCN global tiling registers */ 1130 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1131 adev->gfx.config.gb_addr_config); 1132 1133 /* unblock VCPU register access */ 1134 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1135 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1136 1137 /* release VCPU reset to boot */ 1138 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1139 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1140 1141 for (j = 0; j < 10; ++j) { 1142 uint32_t status; 1143 1144 for (k = 0; k < 100; ++k) { 1145 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1146 if (status & 2) 1147 break; 1148 mdelay(10); 1149 if (amdgpu_emu_mode == 1) 1150 msleep(1); 1151 } 1152 1153 if (amdgpu_emu_mode == 1) { 1154 r = -1; 1155 if (status & 2) { 1156 r = 0; 1157 break; 1158 } 1159 } else { 1160 r = 0; 1161 if (status & 2) 1162 break; 1163 1164 dev_err(adev->dev, 1165 "VCN[%d] is not responding, trying to reset VCPU!!!\n", i); 1166 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1167 UVD_VCPU_CNTL__BLK_RST_MASK, 1168 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1169 mdelay(10); 1170 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1171 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1172 1173 mdelay(10); 1174 r = -1; 1175 } 1176 } 1177 1178 if (r) { 1179 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1180 return r; 1181 } 1182 1183 /* enable master interrupt */ 1184 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1185 UVD_MASTINT_EN__VCPU_EN_MASK, 1186 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1187 1188 /* clear the busy bit of VCN_STATUS */ 1189 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1190 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1191 1192 ring = &adev->vcn.inst[i].ring_enc[0]; 1193 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1194 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1195 VCN_RB1_DB_CTRL__EN_MASK); 1196 1197 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1198 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1199 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1200 1201 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1202 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1203 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1204 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1205 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1206 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1207 1208 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1209 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1210 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1211 1212 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1213 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1214 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1215 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1216 1217 /* Keeping one read-back to ensure all register writes are done, otherwise 1218 * it may introduce race conditions */ 1219 RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1220 1221 return 0; 1222 } 1223 1224 /** 1225 * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode 1226 * 1227 * @vinst: VCN instance 1228 * 1229 * Stop VCN block with dpg mode 1230 */ 1231 static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1232 { 1233 struct amdgpu_device *adev = vinst->adev; 1234 int inst_idx = vinst->inst; 1235 uint32_t tmp; 1236 1237 /* Wait for power status to be 1 */ 1238 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1239 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1240 1241 /* wait for read ptr to be equal to write ptr */ 1242 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1243 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1244 1245 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1246 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1247 1248 /* disable dynamic power gating mode */ 1249 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1250 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1251 1252 /* Keeping one read-back to ensure all register writes are done, 1253 * otherwise it may introduce race conditions. 1254 */ 1255 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); 1256 } 1257 1258 /** 1259 * vcn_v4_0_5_stop - VCN stop 1260 * 1261 * @vinst: VCN instance 1262 * 1263 * Stop VCN block 1264 */ 1265 static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst) 1266 { 1267 struct amdgpu_device *adev = vinst->adev; 1268 int i = vinst->inst; 1269 struct amdgpu_vcn4_fw_shared *fw_shared; 1270 uint32_t tmp; 1271 int r = 0; 1272 1273 if (adev->vcn.harvest_config & (1 << i)) 1274 return 0; 1275 1276 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1277 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1278 1279 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1280 vcn_v4_0_5_stop_dpg_mode(vinst); 1281 r = 0; 1282 goto done; 1283 } 1284 1285 /* wait for vcn idle */ 1286 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1287 if (r) 1288 goto done; 1289 1290 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1291 UVD_LMI_STATUS__READ_CLEAN_MASK | 1292 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1293 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1294 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1295 if (r) 1296 goto done; 1297 1298 /* disable LMI UMC channel */ 1299 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1300 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1301 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1302 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1303 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1304 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1305 if (r) 1306 goto done; 1307 1308 /* block VCPU register access */ 1309 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1310 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1311 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1312 1313 /* reset VCPU */ 1314 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1315 UVD_VCPU_CNTL__BLK_RST_MASK, 1316 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1317 1318 /* disable VCPU clock */ 1319 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1320 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1321 1322 /* apply soft reset */ 1323 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1324 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1325 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1326 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1327 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1328 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1329 1330 /* clear status */ 1331 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1332 1333 /* apply HW clock gating */ 1334 vcn_v4_0_5_enable_clock_gating(vinst); 1335 1336 /* enable VCN power gating */ 1337 vcn_v4_0_5_enable_static_power_gating(vinst); 1338 1339 /* Keeping one read-back to ensure all register writes are done, 1340 * otherwise it may introduce race conditions. 1341 */ 1342 RREG32_SOC15(VCN, i, regUVD_STATUS); 1343 1344 done: 1345 if (adev->pm.dpm_enabled) 1346 amdgpu_dpm_enable_vcn(adev, false, i); 1347 1348 return r; 1349 } 1350 1351 /** 1352 * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode 1353 * 1354 * @vinst: VCN instance 1355 * @new_state: pause state 1356 * 1357 * Pause dpg mode for VCN block 1358 */ 1359 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1360 struct dpg_pause_state *new_state) 1361 { 1362 struct amdgpu_device *adev = vinst->adev; 1363 int inst_idx = vinst->inst; 1364 uint32_t reg_data = 0; 1365 int ret_code; 1366 1367 /* pause/unpause if state is changed */ 1368 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1369 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1370 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1371 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1372 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1373 1374 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1375 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1376 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1377 1378 if (!ret_code) { 1379 /* pause DPG */ 1380 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1381 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1382 1383 /* wait for ACK */ 1384 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1385 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1386 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1387 1388 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1389 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1390 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1391 } 1392 } else { 1393 /* unpause dpg, no need to wait */ 1394 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1395 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1396 } 1397 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1398 } 1399 1400 return 0; 1401 } 1402 1403 /** 1404 * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer 1405 * 1406 * @ring: amdgpu_ring pointer 1407 * 1408 * Returns the current hardware unified read pointer 1409 */ 1410 static uint64_t vcn_v4_0_5_unified_ring_get_rptr(struct amdgpu_ring *ring) 1411 { 1412 struct amdgpu_device *adev = ring->adev; 1413 1414 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1415 DRM_ERROR("wrong ring id is identified in %s", __func__); 1416 1417 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1418 } 1419 1420 /** 1421 * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer 1422 * 1423 * @ring: amdgpu_ring pointer 1424 * 1425 * Returns the current hardware unified write pointer 1426 */ 1427 static uint64_t vcn_v4_0_5_unified_ring_get_wptr(struct amdgpu_ring *ring) 1428 { 1429 struct amdgpu_device *adev = ring->adev; 1430 1431 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1432 DRM_ERROR("wrong ring id is identified in %s", __func__); 1433 1434 if (ring->use_doorbell) 1435 return *ring->wptr_cpu_addr; 1436 else 1437 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1438 } 1439 1440 /** 1441 * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer 1442 * 1443 * @ring: amdgpu_ring pointer 1444 * 1445 * Commits the enc write pointer to the hardware 1446 */ 1447 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring) 1448 { 1449 struct amdgpu_device *adev = ring->adev; 1450 1451 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1452 DRM_ERROR("wrong ring id is identified in %s", __func__); 1453 1454 if (ring->use_doorbell) { 1455 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1456 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1457 } else { 1458 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1459 } 1460 } 1461 1462 static int vcn_v4_0_5_ring_reset(struct amdgpu_ring *ring, 1463 unsigned int vmid, 1464 struct amdgpu_fence *timedout_fence) 1465 { 1466 struct amdgpu_device *adev = ring->adev; 1467 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1468 int r; 1469 1470 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1471 r = vcn_v4_0_5_stop(vinst); 1472 if (r) 1473 return r; 1474 r = vcn_v4_0_5_start(vinst); 1475 if (r) 1476 return r; 1477 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1478 } 1479 1480 static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { 1481 .type = AMDGPU_RING_TYPE_VCN_ENC, 1482 .align_mask = 0x3f, 1483 .nop = VCN_ENC_CMD_NO_OP, 1484 .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, 1485 .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, 1486 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, 1487 .emit_frame_size = 1488 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1489 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1490 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1491 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1492 1, /* vcn_v2_0_enc_ring_insert_end */ 1493 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1494 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1495 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1496 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1497 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1498 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1499 .insert_nop = amdgpu_ring_insert_nop, 1500 .insert_end = vcn_v2_0_enc_ring_insert_end, 1501 .pad_ib = amdgpu_ring_generic_pad_ib, 1502 .begin_use = amdgpu_vcn_ring_begin_use, 1503 .end_use = amdgpu_vcn_ring_end_use, 1504 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1505 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1506 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1507 .reset = vcn_v4_0_5_ring_reset, 1508 }; 1509 1510 /** 1511 * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions 1512 * 1513 * @adev: amdgpu_device pointer 1514 * 1515 * Set unified ring functions 1516 */ 1517 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev) 1518 { 1519 int i; 1520 1521 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1522 if (adev->vcn.harvest_config & (1 << i)) 1523 continue; 1524 1525 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) 1526 vcn_v4_0_5_unified_ring_vm_funcs.secure_submission_supported = true; 1527 1528 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs; 1529 adev->vcn.inst[i].ring_enc[0].me = i; 1530 } 1531 } 1532 1533 /** 1534 * vcn_v4_0_5_is_idle - check VCN block is idle 1535 * 1536 * @ip_block: Pointer to the amdgpu_ip_block structure 1537 * 1538 * Check whether VCN block is idle 1539 */ 1540 static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block) 1541 { 1542 struct amdgpu_device *adev = ip_block->adev; 1543 int i, ret = 1; 1544 1545 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1546 if (adev->vcn.harvest_config & (1 << i)) 1547 continue; 1548 1549 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1550 } 1551 1552 return ret; 1553 } 1554 1555 /** 1556 * vcn_v4_0_5_wait_for_idle - wait for VCN block idle 1557 * 1558 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1559 * 1560 * Wait for VCN block idle 1561 */ 1562 static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 1563 { 1564 struct amdgpu_device *adev = ip_block->adev; 1565 int i, ret = 0; 1566 1567 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1568 if (adev->vcn.harvest_config & (1 << i)) 1569 continue; 1570 1571 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1572 UVD_STATUS__IDLE); 1573 if (ret) 1574 return ret; 1575 } 1576 1577 return ret; 1578 } 1579 1580 /** 1581 * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state 1582 * 1583 * @ip_block: amdgpu_ip_block pointer 1584 * @state: clock gating state 1585 * 1586 * Set VCN block clockgating state 1587 */ 1588 static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1589 enum amd_clockgating_state state) 1590 { 1591 struct amdgpu_device *adev = ip_block->adev; 1592 bool enable = state == AMD_CG_STATE_GATE; 1593 int i; 1594 1595 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1596 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1597 1598 if (adev->vcn.harvest_config & (1 << i)) 1599 continue; 1600 1601 if (enable) { 1602 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1603 return -EBUSY; 1604 vcn_v4_0_5_enable_clock_gating(vinst); 1605 } else { 1606 vcn_v4_0_5_disable_clock_gating(vinst); 1607 } 1608 } 1609 1610 return 0; 1611 } 1612 1613 static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 1614 enum amd_powergating_state state) 1615 { 1616 int ret = 0; 1617 1618 if (state == vinst->cur_state) 1619 return 0; 1620 1621 if (state == AMD_PG_STATE_GATE) 1622 ret = vcn_v4_0_5_stop(vinst); 1623 else 1624 ret = vcn_v4_0_5_start(vinst); 1625 1626 if (!ret) 1627 vinst->cur_state = state; 1628 1629 return ret; 1630 } 1631 1632 /** 1633 * vcn_v4_0_5_process_interrupt - process VCN block interrupt 1634 * 1635 * @adev: amdgpu_device pointer 1636 * @source: interrupt sources 1637 * @entry: interrupt entry from clients and sources 1638 * 1639 * Process VCN block interrupt 1640 */ 1641 static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1642 struct amdgpu_iv_entry *entry) 1643 { 1644 uint32_t ip_instance; 1645 1646 switch (entry->client_id) { 1647 case SOC15_IH_CLIENTID_VCN: 1648 ip_instance = 0; 1649 break; 1650 case SOC15_IH_CLIENTID_VCN1: 1651 ip_instance = 1; 1652 break; 1653 default: 1654 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1655 return 0; 1656 } 1657 1658 DRM_DEBUG("IH: VCN TRAP\n"); 1659 1660 switch (entry->src_id) { 1661 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1662 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1663 break; 1664 case VCN_4_0__SRCID_UVD_POISON: 1665 amdgpu_vcn_process_poison_irq(adev, source, entry); 1666 break; 1667 default: 1668 DRM_ERROR("Unhandled interrupt: %d %d\n", 1669 entry->src_id, entry->src_data[0]); 1670 break; 1671 } 1672 1673 return 0; 1674 } 1675 1676 static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = { 1677 .process = vcn_v4_0_5_process_interrupt, 1678 }; 1679 1680 /** 1681 * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions 1682 * 1683 * @adev: amdgpu_device pointer 1684 * 1685 * Set VCN block interrupt irq functions 1686 */ 1687 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) 1688 { 1689 int i; 1690 1691 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1692 if (adev->vcn.harvest_config & (1 << i)) 1693 continue; 1694 1695 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 1696 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs; 1697 } 1698 } 1699 1700 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { 1701 .name = "vcn_v4_0_5", 1702 .early_init = vcn_v4_0_5_early_init, 1703 .sw_init = vcn_v4_0_5_sw_init, 1704 .sw_fini = vcn_v4_0_5_sw_fini, 1705 .hw_init = vcn_v4_0_5_hw_init, 1706 .hw_fini = vcn_v4_0_5_hw_fini, 1707 .suspend = vcn_v4_0_5_suspend, 1708 .resume = vcn_v4_0_5_resume, 1709 .is_idle = vcn_v4_0_5_is_idle, 1710 .wait_for_idle = vcn_v4_0_5_wait_for_idle, 1711 .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, 1712 .set_powergating_state = vcn_set_powergating_state, 1713 .dump_ip_state = amdgpu_vcn_dump_ip_state, 1714 .print_ip_state = amdgpu_vcn_print_ip_state, 1715 }; 1716 1717 const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = { 1718 .type = AMD_IP_BLOCK_TYPE_VCN, 1719 .major = 4, 1720 .minor = 0, 1721 .rev = 5, 1722 .funcs = &vcn_v4_0_5_ip_funcs, 1723 }; 1724