1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_hw_ip.h" 33 #include "vcn_v2_0.h" 34 #include "vcn_v4_0_3.h" 35 #include "mmsch_v4_0_3.h" 36 37 #include "vcn/vcn_4_0_3_offset.h" 38 #include "vcn/vcn_4_0_3_sh_mask.h" 39 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 40 41 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 42 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 43 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 44 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 45 46 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 47 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 48 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 49 50 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 84 }; 85 86 #define NORMALIZE_VCN_REG_OFFSET(offset) \ 87 (offset & 0x1FFFF) 88 89 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); 90 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); 91 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 92 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 93 enum amd_powergating_state state); 94 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 95 struct dpg_pause_state *new_state); 96 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring); 97 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 99 int inst_idx, bool indirect); 100 101 static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 102 { 103 return (adev->vcn.caps & AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0; 104 } 105 106 /** 107 * vcn_v4_0_3_early_init - set function pointers 108 * 109 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 110 * 111 * Set ring and irq function pointers 112 */ 113 static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 119 /* re-use enc ring as unified ring */ 120 adev->vcn.inst[i].num_enc_rings = 1; 121 122 vcn_v4_0_3_set_unified_ring_funcs(adev); 123 vcn_v4_0_3_set_irq_funcs(adev); 124 vcn_v4_0_3_set_ras_funcs(adev); 125 126 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 127 adev->vcn.inst[i].set_pg_state = vcn_v4_0_3_set_pg_state; 128 129 r = amdgpu_vcn_early_init(adev, i); 130 if (r) 131 return r; 132 } 133 134 return 0; 135 } 136 137 static int vcn_v4_0_3_late_init(struct amdgpu_ip_block *ip_block) 138 { 139 struct amdgpu_device *adev = ip_block->adev; 140 141 adev->vcn.supported_reset = 142 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 143 144 if (amdgpu_dpm_reset_vcn_is_supported(adev)) 145 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 146 147 return 0; 148 } 149 150 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 151 { 152 struct amdgpu_vcn4_fw_shared *fw_shared; 153 154 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 155 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 156 fw_shared->sq.is_enabled = 1; 157 158 if (amdgpu_vcnfw_log) 159 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 160 161 return 0; 162 } 163 164 /** 165 * vcn_v4_0_3_sw_init - sw init for VCN block 166 * 167 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 168 * 169 * Load firmware and sw initialization 170 */ 171 static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 172 { 173 struct amdgpu_device *adev = ip_block->adev; 174 struct amdgpu_ring *ring; 175 int i, r, vcn_inst; 176 177 /* VCN DEC TRAP */ 178 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 179 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 180 if (r) 181 return r; 182 183 /* VCN POISON TRAP */ 184 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 185 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq); 186 187 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 188 189 r = amdgpu_vcn_sw_init(adev, i); 190 if (r) 191 return r; 192 193 amdgpu_vcn_setup_ucode(adev, i); 194 195 r = amdgpu_vcn_resume(adev, i); 196 if (r) 197 return r; 198 199 vcn_inst = GET_INST(VCN, i); 200 201 ring = &adev->vcn.inst[i].ring_enc[0]; 202 ring->use_doorbell = true; 203 204 if (!amdgpu_sriov_vf(adev)) 205 ring->doorbell_index = 206 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 207 9 * vcn_inst; 208 else 209 ring->doorbell_index = 210 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 211 32 * vcn_inst; 212 213 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 214 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 215 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 216 AMDGPU_RING_PRIO_DEFAULT, 217 &adev->vcn.inst[i].sched_score); 218 if (r) 219 return r; 220 221 vcn_v4_0_3_fw_shared_init(adev, i); 222 223 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 224 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; 225 } 226 227 if (amdgpu_sriov_vf(adev)) { 228 r = amdgpu_virt_alloc_mm_table(adev); 229 if (r) 230 return r; 231 } 232 233 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 234 r = amdgpu_vcn_ras_sw_init(adev); 235 if (r) { 236 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 237 return r; 238 } 239 } 240 241 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_3, ARRAY_SIZE(vcn_reg_list_4_0_3)); 242 if (r) 243 return r; 244 245 return amdgpu_vcn_sysfs_reset_mask_init(adev); 246 } 247 248 /** 249 * vcn_v4_0_3_sw_fini - sw fini for VCN block 250 * 251 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 252 * 253 * VCN suspend and free up sw allocation 254 */ 255 static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 256 { 257 struct amdgpu_device *adev = ip_block->adev; 258 int i, r, idx; 259 260 if (drm_dev_enter(&adev->ddev, &idx)) { 261 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 262 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 263 264 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 265 fw_shared->present_flag_0 = 0; 266 fw_shared->sq.is_enabled = cpu_to_le32(false); 267 } 268 drm_dev_exit(idx); 269 } 270 271 if (amdgpu_sriov_vf(adev)) 272 amdgpu_virt_free_mm_table(adev); 273 274 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 275 r = amdgpu_vcn_suspend(adev, i); 276 if (r) 277 return r; 278 } 279 280 amdgpu_vcn_sysfs_reset_mask_fini(adev); 281 282 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 283 r = amdgpu_vcn_sw_fini(adev, i); 284 if (r) 285 return r; 286 } 287 288 return 0; 289 } 290 291 static int vcn_v4_0_3_hw_init_inst(struct amdgpu_vcn_inst *vinst) 292 { 293 int vcn_inst; 294 struct amdgpu_device *adev = vinst->adev; 295 struct amdgpu_ring *ring; 296 int inst_idx = vinst->inst; 297 298 vcn_inst = GET_INST(VCN, inst_idx); 299 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 300 if (ring->use_doorbell) { 301 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 302 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * vcn_inst, 303 adev->vcn.inst[inst_idx].aid_id); 304 305 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 306 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 307 VCN_RB1_DB_CTRL__EN_MASK); 308 309 /* Read DB_CTRL to flush the write DB_CTRL command. */ 310 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 311 } 312 313 return 0; 314 } 315 316 /** 317 * vcn_v4_0_3_hw_init - start and test VCN block 318 * 319 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 320 * 321 * Initialize the hardware, boot up the VCPU and do some testing 322 */ 323 static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 324 { 325 struct amdgpu_device *adev = ip_block->adev; 326 struct amdgpu_ring *ring; 327 struct amdgpu_vcn_inst *vinst; 328 int i, r; 329 330 if (amdgpu_sriov_vf(adev)) { 331 r = vcn_v4_0_3_start_sriov(adev); 332 if (r) 333 return r; 334 335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 336 ring = &adev->vcn.inst[i].ring_enc[0]; 337 ring->wptr = 0; 338 ring->wptr_old = 0; 339 vcn_v4_0_3_unified_ring_set_wptr(ring); 340 ring->sched.ready = true; 341 } 342 } else { 343 /* This flag is not set for VF, assumed to be disabled always */ 344 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 345 0x100) 346 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 347 348 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 349 struct amdgpu_vcn4_fw_shared *fw_shared; 350 351 ring = &adev->vcn.inst[i].ring_enc[0]; 352 vinst = &adev->vcn.inst[i]; 353 vcn_v4_0_3_hw_init_inst(vinst); 354 355 /* Re-init fw_shared when RAS fatal error occurred */ 356 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 357 if (!fw_shared->sq.is_enabled) 358 vcn_v4_0_3_fw_shared_init(adev, i); 359 360 r = amdgpu_ring_test_helper(ring); 361 if (r) 362 return r; 363 } 364 } 365 366 return r; 367 } 368 369 /** 370 * vcn_v4_0_3_hw_fini - stop the hardware block 371 * 372 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 373 * 374 * Stop the VCN block, mark ring as not ready any more 375 */ 376 static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 377 { 378 struct amdgpu_device *adev = ip_block->adev; 379 int i; 380 381 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 382 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 383 384 cancel_delayed_work_sync(&vinst->idle_work); 385 386 if (vinst->cur_state != AMD_PG_STATE_GATE) 387 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 388 } 389 390 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN) && !amdgpu_sriov_vf(adev)) 391 amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0); 392 393 return 0; 394 } 395 396 /** 397 * vcn_v4_0_3_suspend - suspend VCN block 398 * 399 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 400 * 401 * HW fini and suspend VCN block 402 */ 403 static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 404 { 405 struct amdgpu_device *adev = ip_block->adev; 406 int r, i; 407 408 r = vcn_v4_0_3_hw_fini(ip_block); 409 if (r) 410 return r; 411 412 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 413 r = amdgpu_vcn_suspend(adev, i); 414 if (r) 415 return r; 416 } 417 418 return 0; 419 } 420 421 /** 422 * vcn_v4_0_3_resume - resume VCN block 423 * 424 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 425 * 426 * Resume firmware and hw init VCN block 427 */ 428 static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 429 { 430 struct amdgpu_device *adev = ip_block->adev; 431 int r, i; 432 433 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 434 r = amdgpu_vcn_resume(ip_block->adev, i); 435 if (r) 436 return r; 437 } 438 439 r = vcn_v4_0_3_hw_init(ip_block); 440 441 return r; 442 } 443 444 /** 445 * vcn_v4_0_3_mc_resume - memory controller programming 446 * 447 * @vinst: VCN instance 448 * 449 * Let the VCN memory controller know it's offsets 450 */ 451 static void vcn_v4_0_3_mc_resume(struct amdgpu_vcn_inst *vinst) 452 { 453 struct amdgpu_device *adev = vinst->adev; 454 int inst_idx = vinst->inst; 455 uint32_t offset, size, vcn_inst; 456 const struct common_firmware_header *hdr; 457 458 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 459 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 460 461 vcn_inst = GET_INST(VCN, inst_idx); 462 /* cache window 0: fw */ 463 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 464 WREG32_SOC15( 465 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 466 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 467 .tmr_mc_addr_lo)); 468 WREG32_SOC15( 469 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 470 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 471 .tmr_mc_addr_hi)); 472 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 473 offset = 0; 474 } else { 475 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 476 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 477 WREG32_SOC15(VCN, vcn_inst, 478 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 479 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 480 offset = size; 481 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 482 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 483 } 484 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 485 486 /* cache window 1: stack */ 487 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 488 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 489 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 490 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 491 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 492 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, 493 AMDGPU_VCN_STACK_SIZE); 494 495 /* cache window 2: context */ 496 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 497 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 498 AMDGPU_VCN_STACK_SIZE)); 499 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 500 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 501 AMDGPU_VCN_STACK_SIZE)); 502 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 503 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, 504 AMDGPU_VCN_CONTEXT_SIZE); 505 506 /* non-cache window */ 507 WREG32_SOC15( 508 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 509 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 510 WREG32_SOC15( 511 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 512 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 513 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 514 WREG32_SOC15( 515 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 516 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 517 } 518 519 /** 520 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode 521 * 522 * @vinst: VCN instance 523 * @indirect: indirectly write sram 524 * 525 * Let the VCN memory controller know it's offsets with dpg mode 526 */ 527 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 528 bool indirect) 529 { 530 struct amdgpu_device *adev = vinst->adev; 531 int inst_idx = vinst->inst; 532 uint32_t offset, size; 533 const struct common_firmware_header *hdr; 534 535 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 536 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 537 538 /* cache window 0: fw */ 539 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 540 if (!indirect) { 541 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 542 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 543 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 544 inst_idx].tmr_mc_addr_lo), 0, indirect); 545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 546 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 547 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 548 inst_idx].tmr_mc_addr_hi), 0, indirect); 549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 550 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 551 } else { 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 553 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 558 } 559 offset = 0; 560 } else { 561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 562 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 563 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 564 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 565 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 566 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 567 offset = size; 568 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 569 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 570 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 571 } 572 573 if (!indirect) 574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 575 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 576 else 577 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 578 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 579 580 /* cache window 1: stack */ 581 if (!indirect) { 582 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 583 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 584 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 586 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 587 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 590 } else { 591 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 592 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 593 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 594 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 595 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 596 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 597 } 598 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 599 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 600 601 /* cache window 2: context */ 602 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 603 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 604 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 605 AMDGPU_VCN_STACK_SIZE), 0, indirect); 606 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 607 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 608 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 609 AMDGPU_VCN_STACK_SIZE), 0, indirect); 610 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 611 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 612 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 613 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 614 615 /* non-cache window */ 616 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 617 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 618 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 619 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 620 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 621 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 622 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 623 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 624 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 625 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 626 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 627 628 /* VCN global tiling registers */ 629 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 630 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 631 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 632 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 633 } 634 635 /** 636 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating 637 * 638 * @vinst: VCN instance 639 * 640 * Disable clock gating for VCN block 641 */ 642 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 643 { 644 struct amdgpu_device *adev = vinst->adev; 645 int inst_idx = vinst->inst; 646 uint32_t data; 647 int vcn_inst; 648 649 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 650 return; 651 652 vcn_inst = GET_INST(VCN, inst_idx); 653 654 /* VCN disable CGC */ 655 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 656 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 657 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 658 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 659 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 660 661 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); 662 data &= ~(UVD_CGC_GATE__SYS_MASK 663 | UVD_CGC_GATE__MPEG2_MASK 664 | UVD_CGC_GATE__REGS_MASK 665 | UVD_CGC_GATE__RBC_MASK 666 | UVD_CGC_GATE__LMI_MC_MASK 667 | UVD_CGC_GATE__LMI_UMC_MASK 668 | UVD_CGC_GATE__MPC_MASK 669 | UVD_CGC_GATE__LBSI_MASK 670 | UVD_CGC_GATE__LRBBM_MASK 671 | UVD_CGC_GATE__WCB_MASK 672 | UVD_CGC_GATE__VCPU_MASK 673 | UVD_CGC_GATE__MMSCH_MASK); 674 675 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); 676 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 677 678 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 679 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK 680 | UVD_CGC_CTRL__MPEG2_MODE_MASK 681 | UVD_CGC_CTRL__REGS_MODE_MASK 682 | UVD_CGC_CTRL__RBC_MODE_MASK 683 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 684 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 685 | UVD_CGC_CTRL__MPC_MODE_MASK 686 | UVD_CGC_CTRL__LBSI_MODE_MASK 687 | UVD_CGC_CTRL__LRBBM_MODE_MASK 688 | UVD_CGC_CTRL__WCB_MODE_MASK 689 | UVD_CGC_CTRL__VCPU_MODE_MASK 690 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 691 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 692 693 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE); 694 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 695 | UVD_SUVD_CGC_GATE__SIT_MASK 696 | UVD_SUVD_CGC_GATE__SMP_MASK 697 | UVD_SUVD_CGC_GATE__SCM_MASK 698 | UVD_SUVD_CGC_GATE__SDB_MASK 699 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 700 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 701 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 702 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 703 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 704 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 705 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 706 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 707 | UVD_SUVD_CGC_GATE__ENT_MASK 708 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 709 | UVD_SUVD_CGC_GATE__SITE_MASK 710 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 711 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 712 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 713 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 714 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 715 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data); 716 717 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 718 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 719 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 720 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 721 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 722 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 723 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 724 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 725 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 726 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 727 } 728 729 /** 730 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 731 * 732 * @vinst: VCN instance 733 * @sram_sel: sram select 734 * @indirect: indirectly write sram 735 * 736 * Disable clock gating for VCN block with dpg mode 737 */ 738 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 739 uint8_t sram_sel, 740 uint8_t indirect) 741 { 742 struct amdgpu_device *adev = vinst->adev; 743 int inst_idx = vinst->inst; 744 uint32_t reg_data = 0; 745 746 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 747 return; 748 749 /* enable sw clock gating control */ 750 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 751 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 752 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 753 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | 754 UVD_CGC_CTRL__MPEG2_MODE_MASK | 755 UVD_CGC_CTRL__REGS_MODE_MASK | 756 UVD_CGC_CTRL__RBC_MODE_MASK | 757 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 758 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 759 UVD_CGC_CTRL__IDCT_MODE_MASK | 760 UVD_CGC_CTRL__MPRD_MODE_MASK | 761 UVD_CGC_CTRL__MPC_MODE_MASK | 762 UVD_CGC_CTRL__LBSI_MODE_MASK | 763 UVD_CGC_CTRL__LRBBM_MODE_MASK | 764 UVD_CGC_CTRL__WCB_MODE_MASK | 765 UVD_CGC_CTRL__VCPU_MODE_MASK); 766 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 767 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 768 769 /* turn off clock gating */ 770 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 771 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); 772 773 /* turn on SUVD clock gating */ 774 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 775 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 776 777 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 778 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 779 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 780 } 781 782 /** 783 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating 784 * 785 * @vinst: VCN instance 786 * 787 * Enable clock gating for VCN block 788 */ 789 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 790 { 791 struct amdgpu_device *adev = vinst->adev; 792 int inst_idx = vinst->inst; 793 uint32_t data; 794 int vcn_inst; 795 796 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 797 return; 798 799 vcn_inst = GET_INST(VCN, inst_idx); 800 801 /* enable VCN CGC */ 802 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 803 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 804 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 805 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 806 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 807 808 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 809 data |= (UVD_CGC_CTRL__SYS_MODE_MASK 810 | UVD_CGC_CTRL__MPEG2_MODE_MASK 811 | UVD_CGC_CTRL__REGS_MODE_MASK 812 | UVD_CGC_CTRL__RBC_MODE_MASK 813 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 814 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 815 | UVD_CGC_CTRL__MPC_MODE_MASK 816 | UVD_CGC_CTRL__LBSI_MODE_MASK 817 | UVD_CGC_CTRL__LRBBM_MODE_MASK 818 | UVD_CGC_CTRL__WCB_MODE_MASK 819 | UVD_CGC_CTRL__VCPU_MODE_MASK); 820 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 821 822 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 823 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 824 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 825 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 826 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 827 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 828 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 829 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 830 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 831 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 832 } 833 834 /** 835 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode 836 * 837 * @vinst: VCN instance 838 * @indirect: indirectly write sram 839 * 840 * Start VCN block with dpg mode 841 */ 842 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 843 bool indirect) 844 { 845 struct amdgpu_device *adev = vinst->adev; 846 int inst_idx = vinst->inst; 847 volatile struct amdgpu_vcn4_fw_shared *fw_shared = 848 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 849 struct amdgpu_ring *ring; 850 int vcn_inst, ret; 851 uint32_t tmp; 852 853 vcn_inst = GET_INST(VCN, inst_idx); 854 /* disable register anti-hang mechanism */ 855 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 856 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 857 /* enable dynamic power gating mode */ 858 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 859 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 860 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 861 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 862 863 if (indirect) { 864 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d", 865 inst_idx, adev->vcn.inst[inst_idx].aid_id); 866 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 867 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 868 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 869 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, 870 adev->vcn.inst[inst_idx].aid_id, 0, true); 871 } 872 873 /* enable clock gating */ 874 vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect); 875 876 /* enable VCPU clock */ 877 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 878 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 879 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 880 881 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 882 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 883 884 /* disable master interrupt */ 885 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 886 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 887 888 /* setup regUVD_LMI_CTRL */ 889 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 890 UVD_LMI_CTRL__REQ_MODE_MASK | 891 UVD_LMI_CTRL__CRC_RESET_MASK | 892 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 893 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 894 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 895 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 896 0x00100000L); 897 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 898 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 899 900 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 901 VCN, 0, regUVD_MPC_CNTL), 902 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 903 904 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 905 VCN, 0, regUVD_MPC_SET_MUXA0), 906 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 907 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 908 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 909 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 910 911 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 912 VCN, 0, regUVD_MPC_SET_MUXB0), 913 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 914 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 915 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 916 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 917 918 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 919 VCN, 0, regUVD_MPC_SET_MUX), 920 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 921 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 922 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 923 924 vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect); 925 926 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 927 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 928 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 929 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 930 931 /* enable LMI MC and UMC channels */ 932 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 933 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 934 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 935 936 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); 937 938 /* enable master interrupt */ 939 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 940 VCN, 0, regUVD_MASTINT_EN), 941 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 942 943 if (indirect) { 944 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 945 if (ret) { 946 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 947 return ret; 948 } 949 } 950 951 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 952 953 /* program the RB_BASE for ring buffer */ 954 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 955 lower_32_bits(ring->gpu_addr)); 956 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 957 upper_32_bits(ring->gpu_addr)); 958 959 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 960 ring->ring_size / sizeof(uint32_t)); 961 962 /* resetting ring, fw should not check RB ring */ 963 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 964 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 965 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 966 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 967 968 /* Initialize the ring buffer's read and write pointers */ 969 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 970 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 971 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 972 973 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 974 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 975 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 976 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 977 978 /*resetting done, fw can check RB ring */ 979 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 980 981 /* Keeping one read-back to ensure all register writes are done, 982 * otherwise it may introduce race conditions. 983 */ 984 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 985 986 return 0; 987 } 988 989 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev) 990 { 991 int i, vcn_inst; 992 struct amdgpu_ring *ring_enc; 993 uint64_t cache_addr; 994 uint64_t rb_enc_addr; 995 uint64_t ctx_addr; 996 uint32_t param, resp, expected; 997 uint32_t offset, cache_size; 998 uint32_t tmp, timeout; 999 1000 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1001 uint32_t *table_loc; 1002 uint32_t table_size; 1003 uint32_t size, size_dw; 1004 uint32_t init_status; 1005 uint32_t enabled_vcn; 1006 1007 struct mmsch_v4_0_cmd_direct_write 1008 direct_wt = { {0} }; 1009 struct mmsch_v4_0_cmd_direct_read_modify_write 1010 direct_rd_mod_wt = { {0} }; 1011 struct mmsch_v4_0_cmd_end end = { {0} }; 1012 struct mmsch_v4_0_3_init_header header; 1013 1014 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1015 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1016 1017 direct_wt.cmd_header.command_type = 1018 MMSCH_COMMAND__DIRECT_REG_WRITE; 1019 direct_rd_mod_wt.cmd_header.command_type = 1020 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1021 end.cmd_header.command_type = MMSCH_COMMAND__END; 1022 1023 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1024 vcn_inst = GET_INST(VCN, i); 1025 1026 vcn_v4_0_3_fw_shared_init(adev, vcn_inst); 1027 1028 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 1029 header.version = MMSCH_VERSION; 1030 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 1031 1032 table_loc = (uint32_t *)table->cpu_addr; 1033 table_loc += header.total_size; 1034 1035 table_size = 0; 1036 1037 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 1038 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1039 1040 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1041 1042 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1043 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1044 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1045 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1046 1047 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1048 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1049 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1050 1051 offset = 0; 1052 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1053 regUVD_VCPU_CACHE_OFFSET0), 0); 1054 } else { 1055 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1056 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1057 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1058 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1059 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1060 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1061 offset = cache_size; 1062 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1063 regUVD_VCPU_CACHE_OFFSET0), 1064 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1065 } 1066 1067 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1068 regUVD_VCPU_CACHE_SIZE0), 1069 cache_size); 1070 1071 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 1072 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1073 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1074 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1075 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1076 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1077 regUVD_VCPU_CACHE_OFFSET1), 0); 1078 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1079 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 1080 1081 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 1082 AMDGPU_VCN_STACK_SIZE; 1083 1084 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1085 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1086 1087 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1088 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1089 1090 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1091 regUVD_VCPU_CACHE_OFFSET2), 0); 1092 1093 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1094 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 1095 1096 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 1097 rb_setup = &fw_shared->rb_setup; 1098 1099 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 1100 ring_enc->wptr = 0; 1101 rb_enc_addr = ring_enc->gpu_addr; 1102 1103 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1104 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1105 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1106 rb_setup->rb_size = ring_enc->ring_size / 4; 1107 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1108 1109 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1110 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1111 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1112 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1113 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1114 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1115 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1116 regUVD_VCPU_NONCACHE_SIZE0), 1117 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1118 MMSCH_V4_0_INSERT_END(); 1119 1120 header.vcn0.init_status = 0; 1121 header.vcn0.table_offset = header.total_size; 1122 header.vcn0.table_size = table_size; 1123 header.total_size += table_size; 1124 1125 /* Send init table to mmsch */ 1126 size = sizeof(struct mmsch_v4_0_3_init_header); 1127 table_loc = (uint32_t *)table->cpu_addr; 1128 memcpy((void *)table_loc, &header, size); 1129 1130 ctx_addr = table->gpu_addr; 1131 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1132 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1133 1134 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 1135 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1136 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1137 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 1138 1139 size = header.total_size; 1140 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 1141 1142 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 1143 1144 param = 0x00000001; 1145 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 1146 tmp = 0; 1147 timeout = 1000; 1148 resp = 0; 1149 expected = MMSCH_VF_MAILBOX_RESP__OK; 1150 while (resp != expected) { 1151 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 1152 if (resp != 0) 1153 break; 1154 1155 udelay(10); 1156 tmp = tmp + 10; 1157 if (tmp >= timeout) { 1158 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1159 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1160 "(expected=0x%08x, readback=0x%08x)\n", 1161 tmp, expected, resp); 1162 return -EBUSY; 1163 } 1164 } 1165 1166 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1167 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status; 1168 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1169 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 1170 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1171 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1172 } 1173 } 1174 1175 return 0; 1176 } 1177 1178 /** 1179 * vcn_v4_0_3_start - VCN start 1180 * 1181 * @vinst: VCN instance 1182 * 1183 * Start VCN block 1184 */ 1185 static int vcn_v4_0_3_start(struct amdgpu_vcn_inst *vinst) 1186 { 1187 struct amdgpu_device *adev = vinst->adev; 1188 int i = vinst->inst; 1189 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1190 struct amdgpu_ring *ring; 1191 int j, k, r, vcn_inst; 1192 uint32_t tmp; 1193 1194 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1195 return vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1196 1197 vcn_inst = GET_INST(VCN, i); 1198 /* set VCN status busy */ 1199 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | 1200 UVD_STATUS__UVD_BUSY; 1201 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 1202 1203 /* SW clock gating */ 1204 vcn_v4_0_3_disable_clock_gating(vinst); 1205 1206 /* enable VCPU clock */ 1207 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1208 UVD_VCPU_CNTL__CLK_EN_MASK, 1209 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1210 1211 /* disable master interrupt */ 1212 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 1213 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1214 1215 /* enable LMI MC and UMC channels */ 1216 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 1217 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1218 1219 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1220 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1221 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1222 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1223 1224 /* setup regUVD_LMI_CTRL */ 1225 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 1226 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, 1227 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1228 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1229 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1230 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1231 1232 /* setup regUVD_MPC_CNTL */ 1233 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); 1234 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1235 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1236 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); 1237 1238 /* setup UVD_MPC_SET_MUXA0 */ 1239 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, 1240 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1241 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1242 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1243 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1244 1245 /* setup UVD_MPC_SET_MUXB0 */ 1246 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, 1247 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1248 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1249 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1250 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1251 1252 /* setup UVD_MPC_SET_MUX */ 1253 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX, 1254 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1255 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1256 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1257 1258 vcn_v4_0_3_mc_resume(vinst); 1259 1260 /* VCN global tiling registers */ 1261 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG, 1262 adev->gfx.config.gb_addr_config); 1263 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 1264 adev->gfx.config.gb_addr_config); 1265 1266 /* unblock VCPU register access */ 1267 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1268 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1269 1270 /* release VCPU reset to boot */ 1271 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1272 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1273 1274 for (j = 0; j < 10; ++j) { 1275 uint32_t status; 1276 1277 for (k = 0; k < 100; ++k) { 1278 status = RREG32_SOC15(VCN, vcn_inst, 1279 regUVD_STATUS); 1280 if (status & 2) 1281 break; 1282 mdelay(10); 1283 } 1284 r = 0; 1285 if (status & 2) 1286 break; 1287 1288 DRM_DEV_ERROR(adev->dev, 1289 "VCN decode not responding, trying to reset the VCPU!!!\n"); 1290 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1291 regUVD_VCPU_CNTL), 1292 UVD_VCPU_CNTL__BLK_RST_MASK, 1293 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1294 mdelay(10); 1295 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1296 regUVD_VCPU_CNTL), 1297 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); 1298 1299 mdelay(10); 1300 r = -1; 1301 } 1302 1303 if (r) { 1304 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n"); 1305 return r; 1306 } 1307 1308 /* enable master interrupt */ 1309 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1310 UVD_MASTINT_EN__VCPU_EN_MASK, 1311 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1312 1313 /* clear the busy bit of VCN_STATUS */ 1314 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1315 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1316 1317 ring = &adev->vcn.inst[i].ring_enc[0]; 1318 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1319 1320 /* program the RB_BASE for ring buffer */ 1321 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 1322 lower_32_bits(ring->gpu_addr)); 1323 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 1324 upper_32_bits(ring->gpu_addr)); 1325 1326 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 1327 ring->ring_size / sizeof(uint32_t)); 1328 1329 /* resetting ring, fw should not check RB ring */ 1330 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1331 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 1332 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1333 1334 /* Initialize the ring buffer's read and write pointers */ 1335 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1336 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1337 1338 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1339 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 1340 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1341 1342 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1343 fw_shared->sq.queue_mode &= 1344 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF)); 1345 1346 return 0; 1347 } 1348 1349 /** 1350 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode 1351 * 1352 * @vinst: VCN instance 1353 * 1354 * Stop VCN block with dpg mode 1355 */ 1356 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1357 { 1358 struct amdgpu_device *adev = vinst->adev; 1359 int inst_idx = vinst->inst; 1360 uint32_t tmp; 1361 int vcn_inst; 1362 1363 vcn_inst = GET_INST(VCN, inst_idx); 1364 1365 /* Wait for power status to be 1 */ 1366 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1367 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1368 1369 /* wait for read ptr to be equal to write ptr */ 1370 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1371 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1372 1373 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1374 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1375 1376 /* disable dynamic power gating mode */ 1377 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1378 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1379 1380 /* Keeping one read-back to ensure all register writes are done, 1381 * otherwise it may introduce race conditions. 1382 */ 1383 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1384 1385 return 0; 1386 } 1387 1388 /** 1389 * vcn_v4_0_3_stop - VCN stop 1390 * 1391 * @vinst: VCN instance 1392 * 1393 * Stop VCN block 1394 */ 1395 static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst) 1396 { 1397 struct amdgpu_device *adev = vinst->adev; 1398 int i = vinst->inst; 1399 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1400 int r = 0, vcn_inst; 1401 uint32_t tmp; 1402 1403 vcn_inst = GET_INST(VCN, i); 1404 1405 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1406 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1407 1408 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1409 vcn_v4_0_3_stop_dpg_mode(vinst); 1410 goto Done; 1411 } 1412 1413 /* wait for vcn idle */ 1414 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, 1415 UVD_STATUS__IDLE, 0x7); 1416 if (r) 1417 goto Done; 1418 1419 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1420 UVD_LMI_STATUS__READ_CLEAN_MASK | 1421 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1422 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1423 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1424 tmp); 1425 if (r) 1426 goto Done; 1427 1428 /* stall UMC channel */ 1429 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1430 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1431 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1432 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1433 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1434 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1435 tmp); 1436 if (r) 1437 goto Done; 1438 1439 /* Unblock VCPU Register access */ 1440 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1441 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1442 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1443 1444 /* release VCPU reset to boot */ 1445 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1446 UVD_VCPU_CNTL__BLK_RST_MASK, 1447 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1448 1449 /* disable VCPU clock */ 1450 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1451 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1452 1453 /* reset LMI UMC/LMI/VCPU */ 1454 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1455 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1456 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1457 1458 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1459 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1460 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1461 1462 /* clear VCN status */ 1463 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1464 1465 /* apply HW clock gating */ 1466 vcn_v4_0_3_enable_clock_gating(vinst); 1467 1468 /* Keeping one read-back to ensure all register writes are done, 1469 * otherwise it may introduce race conditions. 1470 */ 1471 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1472 1473 Done: 1474 return 0; 1475 } 1476 1477 /** 1478 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode 1479 * 1480 * @vinst: VCN instance 1481 * @new_state: pause state 1482 * 1483 * Pause dpg mode for VCN block 1484 */ 1485 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1486 struct dpg_pause_state *new_state) 1487 { 1488 1489 return 0; 1490 } 1491 1492 /** 1493 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer 1494 * 1495 * @ring: amdgpu_ring pointer 1496 * 1497 * Returns the current hardware unified read pointer 1498 */ 1499 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring) 1500 { 1501 struct amdgpu_device *adev = ring->adev; 1502 1503 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1504 DRM_ERROR("wrong ring id is identified in %s", __func__); 1505 1506 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1507 } 1508 1509 /** 1510 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer 1511 * 1512 * @ring: amdgpu_ring pointer 1513 * 1514 * Returns the current hardware unified write pointer 1515 */ 1516 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring) 1517 { 1518 struct amdgpu_device *adev = ring->adev; 1519 1520 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1521 DRM_ERROR("wrong ring id is identified in %s", __func__); 1522 1523 if (ring->use_doorbell) 1524 return *ring->wptr_cpu_addr; 1525 else 1526 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), 1527 regUVD_RB_WPTR); 1528 } 1529 1530 void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1531 uint32_t val, uint32_t mask) 1532 { 1533 /* Use normalized offsets when required */ 1534 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1535 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1536 1537 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1538 amdgpu_ring_write(ring, reg << 2); 1539 amdgpu_ring_write(ring, mask); 1540 amdgpu_ring_write(ring, val); 1541 } 1542 1543 void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 1544 uint32_t val) 1545 { 1546 /* Use normalized offsets when required */ 1547 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1548 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1549 1550 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1551 amdgpu_ring_write(ring, reg << 2); 1552 amdgpu_ring_write(ring, val); 1553 } 1554 1555 void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1556 unsigned int vmid, uint64_t pd_addr) 1557 { 1558 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1559 1560 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1561 1562 /* wait for reg writes */ 1563 vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1564 vmid * hub->ctx_addr_distance, 1565 lower_32_bits(pd_addr), 0xffffffff); 1566 } 1567 1568 void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1569 { 1570 /* VCN engine access for HDP flush doesn't work when RRMT is enabled. 1571 * This is a workaround to avoid any HDP flush through VCN ring. 1572 */ 1573 } 1574 1575 /** 1576 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer 1577 * 1578 * @ring: amdgpu_ring pointer 1579 * 1580 * Commits the enc write pointer to the hardware 1581 */ 1582 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) 1583 { 1584 struct amdgpu_device *adev = ring->adev; 1585 1586 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1587 DRM_ERROR("wrong ring id is identified in %s", __func__); 1588 1589 if (ring->use_doorbell) { 1590 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1591 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1592 } else { 1593 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1594 lower_32_bits(ring->wptr)); 1595 } 1596 } 1597 1598 static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, 1599 unsigned int vmid, 1600 struct amdgpu_fence *timedout_fence) 1601 { 1602 int r = 0; 1603 int vcn_inst; 1604 struct amdgpu_device *adev = ring->adev; 1605 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1606 1607 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1608 1609 vcn_inst = GET_INST(VCN, ring->me); 1610 r = amdgpu_dpm_reset_vcn(adev, 1 << vcn_inst); 1611 1612 if (r) { 1613 DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); 1614 return r; 1615 } 1616 1617 /* This flag is not set for VF, assumed to be disabled always */ 1618 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 1619 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 1620 vcn_v4_0_3_hw_init_inst(vinst); 1621 vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram); 1622 1623 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1624 } 1625 1626 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { 1627 .type = AMDGPU_RING_TYPE_VCN_ENC, 1628 .align_mask = 0x3f, 1629 .nop = VCN_ENC_CMD_NO_OP, 1630 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, 1631 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, 1632 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, 1633 .emit_frame_size = 1634 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1635 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1636 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1637 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1638 1, /* vcn_v2_0_enc_ring_insert_end */ 1639 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1640 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1641 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1642 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1643 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1644 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1645 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1646 .insert_nop = amdgpu_ring_insert_nop, 1647 .insert_end = vcn_v2_0_enc_ring_insert_end, 1648 .pad_ib = amdgpu_ring_generic_pad_ib, 1649 .begin_use = amdgpu_vcn_ring_begin_use, 1650 .end_use = amdgpu_vcn_ring_end_use, 1651 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1652 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1653 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1654 .reset = vcn_v4_0_3_ring_reset, 1655 }; 1656 1657 /** 1658 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions 1659 * 1660 * @adev: amdgpu_device pointer 1661 * 1662 * Set unified ring functions 1663 */ 1664 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev) 1665 { 1666 int i, vcn_inst; 1667 1668 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1669 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs; 1670 adev->vcn.inst[i].ring_enc[0].me = i; 1671 vcn_inst = GET_INST(VCN, i); 1672 adev->vcn.inst[i].aid_id = 1673 vcn_inst / adev->vcn.num_inst_per_aid; 1674 } 1675 } 1676 1677 /** 1678 * vcn_v4_0_3_is_idle - check VCN block is idle 1679 * 1680 * @ip_block: Pointer to the amdgpu_ip_block structure 1681 * 1682 * Check whether VCN block is idle 1683 */ 1684 static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block) 1685 { 1686 struct amdgpu_device *adev = ip_block->adev; 1687 int i, ret = 1; 1688 1689 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1690 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == 1691 UVD_STATUS__IDLE); 1692 } 1693 1694 return ret; 1695 } 1696 1697 /** 1698 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle 1699 * 1700 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1701 * 1702 * Wait for VCN block idle 1703 */ 1704 static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 1705 { 1706 struct amdgpu_device *adev = ip_block->adev; 1707 int i, ret = 0; 1708 1709 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1710 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, 1711 UVD_STATUS__IDLE, UVD_STATUS__IDLE); 1712 if (ret) 1713 return ret; 1714 } 1715 1716 return ret; 1717 } 1718 1719 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state 1720 * 1721 * @ip_block: amdgpu_ip_block pointer 1722 * @state: clock gating state 1723 * 1724 * Set VCN block clockgating state 1725 */ 1726 static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1727 enum amd_clockgating_state state) 1728 { 1729 struct amdgpu_device *adev = ip_block->adev; 1730 bool enable = state == AMD_CG_STATE_GATE; 1731 int i; 1732 1733 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1734 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1735 1736 if (enable) { 1737 if (RREG32_SOC15(VCN, GET_INST(VCN, i), 1738 regUVD_STATUS) != UVD_STATUS__IDLE) 1739 return -EBUSY; 1740 vcn_v4_0_3_enable_clock_gating(vinst); 1741 } else { 1742 vcn_v4_0_3_disable_clock_gating(vinst); 1743 } 1744 } 1745 return 0; 1746 } 1747 1748 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 1749 enum amd_powergating_state state) 1750 { 1751 struct amdgpu_device *adev = vinst->adev; 1752 int ret = 0; 1753 1754 /* for SRIOV, guest should not control VCN Power-gating 1755 * MMSCH FW should control Power-gating and clock-gating 1756 * guest should avoid touching CGC and PG 1757 */ 1758 if (amdgpu_sriov_vf(adev)) { 1759 vinst->cur_state = AMD_PG_STATE_UNGATE; 1760 return 0; 1761 } 1762 1763 if (state == vinst->cur_state) 1764 return 0; 1765 1766 if (state == AMD_PG_STATE_GATE) 1767 ret = vcn_v4_0_3_stop(vinst); 1768 else 1769 ret = vcn_v4_0_3_start(vinst); 1770 1771 if (!ret) 1772 vinst->cur_state = state; 1773 1774 return ret; 1775 } 1776 1777 /** 1778 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state 1779 * 1780 * @adev: amdgpu_device pointer 1781 * @source: interrupt sources 1782 * @type: interrupt types 1783 * @state: interrupt states 1784 * 1785 * Set VCN block interrupt state 1786 */ 1787 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1788 struct amdgpu_irq_src *source, 1789 unsigned int type, 1790 enum amdgpu_interrupt_state state) 1791 { 1792 return 0; 1793 } 1794 1795 /** 1796 * vcn_v4_0_3_process_interrupt - process VCN block interrupt 1797 * 1798 * @adev: amdgpu_device pointer 1799 * @source: interrupt sources 1800 * @entry: interrupt entry from clients and sources 1801 * 1802 * Process VCN block interrupt 1803 */ 1804 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1805 struct amdgpu_irq_src *source, 1806 struct amdgpu_iv_entry *entry) 1807 { 1808 uint32_t i, inst; 1809 1810 i = node_id_to_phys_map[entry->node_id]; 1811 1812 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1813 1814 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1815 if (adev->vcn.inst[inst].aid_id == i) 1816 break; 1817 1818 if (inst >= adev->vcn.num_vcn_inst) { 1819 dev_WARN_ONCE(adev->dev, 1, 1820 "Interrupt received for unknown VCN instance %d", 1821 entry->node_id); 1822 return 0; 1823 } 1824 1825 switch (entry->src_id) { 1826 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1827 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1828 break; 1829 default: 1830 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1831 entry->src_id, entry->src_data[0]); 1832 break; 1833 } 1834 1835 return 0; 1836 } 1837 1838 static int vcn_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev, 1839 struct amdgpu_irq_src *source, 1840 unsigned int type, 1841 enum amdgpu_interrupt_state state) 1842 { 1843 return 0; 1844 } 1845 1846 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 1847 .set = vcn_v4_0_3_set_interrupt_state, 1848 .process = vcn_v4_0_3_process_interrupt, 1849 }; 1850 1851 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_ras_irq_funcs = { 1852 .set = vcn_v4_0_3_set_ras_interrupt_state, 1853 .process = amdgpu_vcn_process_poison_irq, 1854 }; 1855 1856 /** 1857 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions 1858 * 1859 * @adev: amdgpu_device pointer 1860 * 1861 * Set VCN block interrupt irq functions 1862 */ 1863 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1864 { 1865 int i; 1866 1867 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1868 adev->vcn.inst->irq.num_types++; 1869 } 1870 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 1871 1872 adev->vcn.inst->ras_poison_irq.num_types = 1; 1873 adev->vcn.inst->ras_poison_irq.funcs = &vcn_v4_0_3_ras_irq_funcs; 1874 } 1875 1876 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 1877 .name = "vcn_v4_0_3", 1878 .early_init = vcn_v4_0_3_early_init, 1879 .late_init = vcn_v4_0_3_late_init, 1880 .sw_init = vcn_v4_0_3_sw_init, 1881 .sw_fini = vcn_v4_0_3_sw_fini, 1882 .hw_init = vcn_v4_0_3_hw_init, 1883 .hw_fini = vcn_v4_0_3_hw_fini, 1884 .suspend = vcn_v4_0_3_suspend, 1885 .resume = vcn_v4_0_3_resume, 1886 .is_idle = vcn_v4_0_3_is_idle, 1887 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 1888 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 1889 .set_powergating_state = vcn_set_powergating_state, 1890 .dump_ip_state = amdgpu_vcn_dump_ip_state, 1891 .print_ip_state = amdgpu_vcn_print_ip_state, 1892 }; 1893 1894 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { 1895 .type = AMD_IP_BLOCK_TYPE_VCN, 1896 .major = 4, 1897 .minor = 0, 1898 .rev = 3, 1899 .funcs = &vcn_v4_0_3_ip_funcs, 1900 }; 1901 1902 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = { 1903 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD), 1904 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"}, 1905 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV), 1906 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"}, 1907 }; 1908 1909 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1910 uint32_t vcn_inst, 1911 void *ras_err_status) 1912 { 1913 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1914 1915 /* vcn v4_0_3 only support query uncorrectable errors */ 1916 amdgpu_ras_inst_query_ras_error_count(adev, 1917 vcn_v4_0_3_ue_reg_list, 1918 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1919 NULL, 0, GET_INST(VCN, vcn_inst), 1920 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1921 &err_data->ue_count); 1922 } 1923 1924 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1925 void *ras_err_status) 1926 { 1927 uint32_t i; 1928 1929 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1930 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1931 return; 1932 } 1933 1934 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1935 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1936 } 1937 1938 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1939 uint32_t vcn_inst) 1940 { 1941 amdgpu_ras_inst_reset_ras_error_count(adev, 1942 vcn_v4_0_3_ue_reg_list, 1943 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1944 GET_INST(VCN, vcn_inst)); 1945 } 1946 1947 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1948 { 1949 uint32_t i; 1950 1951 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1952 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1953 return; 1954 } 1955 1956 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1957 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 1958 } 1959 1960 static uint32_t vcn_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev, 1961 uint32_t instance, uint32_t sub_block) 1962 { 1963 uint32_t poison_stat = 0, reg_value = 0; 1964 1965 switch (sub_block) { 1966 case AMDGPU_VCN_V4_0_3_VCPU_VCODEC: 1967 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 1968 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 1969 break; 1970 default: 1971 break; 1972 } 1973 1974 if (poison_stat) 1975 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 1976 instance, sub_block); 1977 1978 return poison_stat; 1979 } 1980 1981 static bool vcn_v4_0_3_query_poison_status(struct amdgpu_device *adev) 1982 { 1983 uint32_t inst, sub; 1984 uint32_t poison_stat = 0; 1985 1986 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 1987 for (sub = 0; sub < AMDGPU_VCN_V4_0_3_MAX_SUB_BLOCK; sub++) 1988 poison_stat += 1989 vcn_v4_0_3_query_poison_by_instance(adev, inst, sub); 1990 1991 return !!poison_stat; 1992 } 1993 1994 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 1995 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 1996 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 1997 .query_poison_status = vcn_v4_0_3_query_poison_status, 1998 }; 1999 2000 static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 2001 enum aca_smu_type type, void *data) 2002 { 2003 struct aca_bank_info info; 2004 u64 misc0; 2005 int ret; 2006 2007 ret = aca_bank_info_decode(bank, &info); 2008 if (ret) 2009 return ret; 2010 2011 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2012 switch (type) { 2013 case ACA_SMU_TYPE_UE: 2014 bank->aca_err_type = ACA_ERROR_TYPE_UE; 2015 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2016 1ULL); 2017 break; 2018 case ACA_SMU_TYPE_CE: 2019 bank->aca_err_type = ACA_ERROR_TYPE_CE; 2020 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 2021 ACA_REG__MISC0__ERRCNT(misc0)); 2022 break; 2023 default: 2024 return -EINVAL; 2025 } 2026 2027 return ret; 2028 } 2029 2030 /* reference to smu driver if header file */ 2031 static int vcn_v4_0_3_err_codes[] = { 2032 14, 15, /* VCN */ 2033 }; 2034 2035 static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2036 enum aca_smu_type type, void *data) 2037 { 2038 u32 instlo; 2039 2040 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2041 instlo &= GENMASK(31, 1); 2042 2043 if (instlo != mmSMNAID_AID0_MCA_SMU) 2044 return false; 2045 2046 if (aca_bank_check_error_codes(handle->adev, bank, 2047 vcn_v4_0_3_err_codes, 2048 ARRAY_SIZE(vcn_v4_0_3_err_codes))) 2049 return false; 2050 2051 return true; 2052 } 2053 2054 static const struct aca_bank_ops vcn_v4_0_3_aca_bank_ops = { 2055 .aca_bank_parser = vcn_v4_0_3_aca_bank_parser, 2056 .aca_bank_is_valid = vcn_v4_0_3_aca_bank_is_valid, 2057 }; 2058 2059 static const struct aca_info vcn_v4_0_3_aca_info = { 2060 .hwip = ACA_HWIP_TYPE_SMU, 2061 .mask = ACA_ERROR_UE_MASK, 2062 .bank_ops = &vcn_v4_0_3_aca_bank_ops, 2063 }; 2064 2065 static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2066 { 2067 int r; 2068 2069 r = amdgpu_ras_block_late_init(adev, ras_block); 2070 if (r) 2071 return r; 2072 2073 if (amdgpu_ras_is_supported(adev, ras_block->block) && 2074 adev->vcn.inst->ras_poison_irq.funcs) { 2075 r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0); 2076 if (r) 2077 goto late_fini; 2078 } 2079 2080 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN, 2081 &vcn_v4_0_3_aca_info, NULL); 2082 if (r) 2083 goto late_fini; 2084 2085 return 0; 2086 2087 late_fini: 2088 amdgpu_ras_block_late_fini(adev, ras_block); 2089 2090 return r; 2091 } 2092 2093 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = { 2094 .ras_block = { 2095 .hw_ops = &vcn_v4_0_3_ras_hw_ops, 2096 .ras_late_init = vcn_v4_0_3_ras_late_init, 2097 }, 2098 }; 2099 2100 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 2101 { 2102 adev->vcn.ras = &vcn_v4_0_3_ras; 2103 } 2104 2105 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 2106 int inst_idx, bool indirect) 2107 { 2108 uint32_t tmp; 2109 2110 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 2111 return; 2112 2113 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 2114 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 2115 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 2116 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 2117 WREG32_SOC15_DPG_MODE(inst_idx, 2118 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 2119 tmp, 0, indirect); 2120 2121 tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK; 2122 WREG32_SOC15_DPG_MODE(inst_idx, 2123 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2), 2124 tmp, 0, indirect); 2125 2126 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 2127 WREG32_SOC15_DPG_MODE(inst_idx, 2128 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 2129 tmp, 0, indirect); 2130 } 2131