1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_hw_ip.h" 33 #include "vcn_v2_0.h" 34 #include "mmsch_v4_0_3.h" 35 36 #include "vcn/vcn_4_0_3_offset.h" 37 #include "vcn/vcn_4_0_3_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 41 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 42 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 43 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 44 45 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 46 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 47 48 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { 49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 82 }; 83 84 #define NORMALIZE_VCN_REG_OFFSET(offset) \ 85 (offset & 0x1FFFF) 86 87 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); 88 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); 89 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 90 static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 91 enum amd_powergating_state state); 92 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, 93 int inst_idx, struct dpg_pause_state *new_state); 94 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring); 95 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 96 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 97 int inst_idx, bool indirect); 98 99 static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 100 { 101 return (adev->vcn.caps & AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0; 102 } 103 104 /** 105 * vcn_v4_0_3_early_init - set function pointers 106 * 107 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 108 * 109 * Set ring and irq function pointers 110 */ 111 static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 112 { 113 struct amdgpu_device *adev = ip_block->adev; 114 115 /* re-use enc ring as unified ring */ 116 adev->vcn.num_enc_rings = 1; 117 118 vcn_v4_0_3_set_unified_ring_funcs(adev); 119 vcn_v4_0_3_set_irq_funcs(adev); 120 vcn_v4_0_3_set_ras_funcs(adev); 121 122 return amdgpu_vcn_early_init(adev); 123 } 124 125 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 126 { 127 struct amdgpu_vcn4_fw_shared *fw_shared; 128 129 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 130 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 131 fw_shared->sq.is_enabled = 1; 132 133 if (amdgpu_vcnfw_log) 134 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 135 136 return 0; 137 } 138 139 /** 140 * vcn_v4_0_3_sw_init - sw init for VCN block 141 * 142 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 143 * 144 * Load firmware and sw initialization 145 */ 146 static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 147 { 148 struct amdgpu_device *adev = ip_block->adev; 149 struct amdgpu_ring *ring; 150 int i, r, vcn_inst; 151 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 152 uint32_t *ptr; 153 154 r = amdgpu_vcn_sw_init(adev); 155 if (r) 156 return r; 157 158 amdgpu_vcn_setup_ucode(adev); 159 160 r = amdgpu_vcn_resume(adev); 161 if (r) 162 return r; 163 164 /* VCN DEC TRAP */ 165 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 166 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 167 if (r) 168 return r; 169 170 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 171 vcn_inst = GET_INST(VCN, i); 172 173 ring = &adev->vcn.inst[i].ring_enc[0]; 174 ring->use_doorbell = true; 175 176 if (!amdgpu_sriov_vf(adev)) 177 ring->doorbell_index = 178 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 179 9 * vcn_inst; 180 else 181 ring->doorbell_index = 182 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 183 32 * vcn_inst; 184 185 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 186 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 187 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 188 AMDGPU_RING_PRIO_DEFAULT, 189 &adev->vcn.inst[i].sched_score); 190 if (r) 191 return r; 192 193 vcn_v4_0_3_fw_shared_init(adev, i); 194 } 195 196 /* TODO: Add queue reset mask when FW fully supports it */ 197 adev->vcn.supported_reset = 198 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 199 200 if (amdgpu_sriov_vf(adev)) { 201 r = amdgpu_virt_alloc_mm_table(adev); 202 if (r) 203 return r; 204 } 205 206 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 207 adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; 208 209 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 210 r = amdgpu_vcn_ras_sw_init(adev); 211 if (r) { 212 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 213 return r; 214 } 215 } 216 217 /* Allocate memory for VCN IP Dump buffer */ 218 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 219 if (!ptr) { 220 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 221 adev->vcn.ip_dump = NULL; 222 } else { 223 adev->vcn.ip_dump = ptr; 224 } 225 226 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 227 if (r) 228 return r; 229 230 return 0; 231 } 232 233 /** 234 * vcn_v4_0_3_sw_fini - sw fini for VCN block 235 * 236 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 237 * 238 * VCN suspend and free up sw allocation 239 */ 240 static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 241 { 242 struct amdgpu_device *adev = ip_block->adev; 243 int i, r, idx; 244 245 if (drm_dev_enter(&adev->ddev, &idx)) { 246 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 247 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 248 249 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 250 fw_shared->present_flag_0 = 0; 251 fw_shared->sq.is_enabled = cpu_to_le32(false); 252 } 253 drm_dev_exit(idx); 254 } 255 256 if (amdgpu_sriov_vf(adev)) 257 amdgpu_virt_free_mm_table(adev); 258 259 r = amdgpu_vcn_suspend(adev); 260 if (r) 261 return r; 262 263 amdgpu_vcn_sysfs_reset_mask_fini(adev); 264 r = amdgpu_vcn_sw_fini(adev); 265 266 kfree(adev->vcn.ip_dump); 267 268 return r; 269 } 270 271 /** 272 * vcn_v4_0_3_hw_init - start and test VCN block 273 * 274 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 275 * 276 * Initialize the hardware, boot up the VCPU and do some testing 277 */ 278 static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 279 { 280 struct amdgpu_device *adev = ip_block->adev; 281 struct amdgpu_ring *ring; 282 int i, r, vcn_inst; 283 284 if (amdgpu_sriov_vf(adev)) { 285 r = vcn_v4_0_3_start_sriov(adev); 286 if (r) 287 return r; 288 289 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 290 ring = &adev->vcn.inst[i].ring_enc[0]; 291 ring->wptr = 0; 292 ring->wptr_old = 0; 293 vcn_v4_0_3_unified_ring_set_wptr(ring); 294 ring->sched.ready = true; 295 } 296 } else { 297 /* This flag is not set for VF, assumed to be disabled always */ 298 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 299 0x100) 300 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 301 302 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 303 struct amdgpu_vcn4_fw_shared *fw_shared; 304 305 vcn_inst = GET_INST(VCN, i); 306 ring = &adev->vcn.inst[i].ring_enc[0]; 307 308 if (ring->use_doorbell) { 309 adev->nbio.funcs->vcn_doorbell_range( 310 adev, ring->use_doorbell, 311 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 312 9 * vcn_inst, 313 adev->vcn.inst[i].aid_id); 314 315 WREG32_SOC15( 316 VCN, GET_INST(VCN, ring->me), 317 regVCN_RB1_DB_CTRL, 318 ring->doorbell_index 319 << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 320 VCN_RB1_DB_CTRL__EN_MASK); 321 322 /* Read DB_CTRL to flush the write DB_CTRL command. */ 323 RREG32_SOC15( 324 VCN, GET_INST(VCN, ring->me), 325 regVCN_RB1_DB_CTRL); 326 } 327 328 /* Re-init fw_shared when RAS fatal error occurred */ 329 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 330 if (!fw_shared->sq.is_enabled) 331 vcn_v4_0_3_fw_shared_init(adev, i); 332 333 r = amdgpu_ring_test_helper(ring); 334 if (r) 335 return r; 336 } 337 } 338 339 return r; 340 } 341 342 /** 343 * vcn_v4_0_3_hw_fini - stop the hardware block 344 * 345 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 346 * 347 * Stop the VCN block, mark ring as not ready any more 348 */ 349 static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 350 { 351 struct amdgpu_device *adev = ip_block->adev; 352 353 cancel_delayed_work_sync(&adev->vcn.idle_work); 354 355 if (adev->vcn.cur_state != AMD_PG_STATE_GATE) 356 vcn_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 357 358 return 0; 359 } 360 361 /** 362 * vcn_v4_0_3_suspend - suspend VCN block 363 * 364 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 365 * 366 * HW fini and suspend VCN block 367 */ 368 static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 369 { 370 int r; 371 372 r = vcn_v4_0_3_hw_fini(ip_block); 373 if (r) 374 return r; 375 376 r = amdgpu_vcn_suspend(ip_block->adev); 377 378 return r; 379 } 380 381 /** 382 * vcn_v4_0_3_resume - resume VCN block 383 * 384 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 385 * 386 * Resume firmware and hw init VCN block 387 */ 388 static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 389 { 390 int r; 391 392 r = amdgpu_vcn_resume(ip_block->adev); 393 if (r) 394 return r; 395 396 r = vcn_v4_0_3_hw_init(ip_block); 397 398 return r; 399 } 400 401 /** 402 * vcn_v4_0_3_mc_resume - memory controller programming 403 * 404 * @adev: amdgpu_device pointer 405 * @inst_idx: instance number 406 * 407 * Let the VCN memory controller know it's offsets 408 */ 409 static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx) 410 { 411 uint32_t offset, size, vcn_inst; 412 const struct common_firmware_header *hdr; 413 414 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 415 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 416 417 vcn_inst = GET_INST(VCN, inst_idx); 418 /* cache window 0: fw */ 419 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 420 WREG32_SOC15( 421 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 422 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 423 .tmr_mc_addr_lo)); 424 WREG32_SOC15( 425 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 426 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 427 .tmr_mc_addr_hi)); 428 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 429 offset = 0; 430 } else { 431 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 432 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 433 WREG32_SOC15(VCN, vcn_inst, 434 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 435 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 436 offset = size; 437 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 438 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 439 } 440 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 441 442 /* cache window 1: stack */ 443 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 444 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 445 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 446 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 447 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 448 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, 449 AMDGPU_VCN_STACK_SIZE); 450 451 /* cache window 2: context */ 452 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 453 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 454 AMDGPU_VCN_STACK_SIZE)); 455 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 456 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 457 AMDGPU_VCN_STACK_SIZE)); 458 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 459 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, 460 AMDGPU_VCN_CONTEXT_SIZE); 461 462 /* non-cache window */ 463 WREG32_SOC15( 464 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 465 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 466 WREG32_SOC15( 467 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 468 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 469 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 470 WREG32_SOC15( 471 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 472 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 473 } 474 475 /** 476 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode 477 * 478 * @adev: amdgpu_device pointer 479 * @inst_idx: instance number index 480 * @indirect: indirectly write sram 481 * 482 * Let the VCN memory controller know it's offsets with dpg mode 483 */ 484 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 485 { 486 uint32_t offset, size; 487 const struct common_firmware_header *hdr; 488 489 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 490 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 491 492 /* cache window 0: fw */ 493 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 494 if (!indirect) { 495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 496 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 497 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 498 inst_idx].tmr_mc_addr_lo), 0, indirect); 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 501 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 502 inst_idx].tmr_mc_addr_hi), 0, indirect); 503 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 504 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 505 } else { 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 507 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 510 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 511 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 512 } 513 offset = 0; 514 } else { 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 517 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 519 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 520 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 521 offset = size; 522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 523 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 524 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 525 } 526 527 if (!indirect) 528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 529 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 530 else 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 533 534 /* cache window 1: stack */ 535 if (!indirect) { 536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 537 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 538 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 540 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 541 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 544 } else { 545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 546 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 547 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 548 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 550 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 551 } 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 553 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 554 555 /* cache window 2: context */ 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 558 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 559 AMDGPU_VCN_STACK_SIZE), 0, indirect); 560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 561 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 562 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 563 AMDGPU_VCN_STACK_SIZE), 0, indirect); 564 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 565 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 566 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 567 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 568 569 /* non-cache window */ 570 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 571 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 572 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 573 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 574 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 575 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 576 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 577 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 578 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 579 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 580 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 581 582 /* VCN global tiling registers */ 583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 584 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 586 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 587 } 588 589 /** 590 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating 591 * 592 * @adev: amdgpu_device pointer 593 * @inst_idx: instance number 594 * 595 * Disable clock gating for VCN block 596 */ 597 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 598 { 599 uint32_t data; 600 int vcn_inst; 601 602 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 603 return; 604 605 vcn_inst = GET_INST(VCN, inst_idx); 606 607 /* VCN disable CGC */ 608 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 609 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 610 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 611 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 612 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 613 614 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); 615 data &= ~(UVD_CGC_GATE__SYS_MASK 616 | UVD_CGC_GATE__MPEG2_MASK 617 | UVD_CGC_GATE__REGS_MASK 618 | UVD_CGC_GATE__RBC_MASK 619 | UVD_CGC_GATE__LMI_MC_MASK 620 | UVD_CGC_GATE__LMI_UMC_MASK 621 | UVD_CGC_GATE__MPC_MASK 622 | UVD_CGC_GATE__LBSI_MASK 623 | UVD_CGC_GATE__LRBBM_MASK 624 | UVD_CGC_GATE__WCB_MASK 625 | UVD_CGC_GATE__VCPU_MASK 626 | UVD_CGC_GATE__MMSCH_MASK); 627 628 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); 629 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 630 631 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 632 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK 633 | UVD_CGC_CTRL__MPEG2_MODE_MASK 634 | UVD_CGC_CTRL__REGS_MODE_MASK 635 | UVD_CGC_CTRL__RBC_MODE_MASK 636 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 637 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 638 | UVD_CGC_CTRL__MPC_MODE_MASK 639 | UVD_CGC_CTRL__LBSI_MODE_MASK 640 | UVD_CGC_CTRL__LRBBM_MODE_MASK 641 | UVD_CGC_CTRL__WCB_MODE_MASK 642 | UVD_CGC_CTRL__VCPU_MODE_MASK 643 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 644 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 645 646 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE); 647 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 648 | UVD_SUVD_CGC_GATE__SIT_MASK 649 | UVD_SUVD_CGC_GATE__SMP_MASK 650 | UVD_SUVD_CGC_GATE__SCM_MASK 651 | UVD_SUVD_CGC_GATE__SDB_MASK 652 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 653 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 654 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 655 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 656 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 657 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 658 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 659 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 660 | UVD_SUVD_CGC_GATE__ENT_MASK 661 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 662 | UVD_SUVD_CGC_GATE__SITE_MASK 663 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 664 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 665 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 666 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 667 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 668 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data); 669 670 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 671 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 672 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 673 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 674 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 675 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 676 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 677 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 678 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 679 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 680 } 681 682 /** 683 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 684 * 685 * @adev: amdgpu_device pointer 686 * @sram_sel: sram select 687 * @inst_idx: instance number index 688 * @indirect: indirectly write sram 689 * 690 * Disable clock gating for VCN block with dpg mode 691 */ 692 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 693 int inst_idx, uint8_t indirect) 694 { 695 uint32_t reg_data = 0; 696 697 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 698 return; 699 700 /* enable sw clock gating control */ 701 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 702 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 703 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 704 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | 705 UVD_CGC_CTRL__MPEG2_MODE_MASK | 706 UVD_CGC_CTRL__REGS_MODE_MASK | 707 UVD_CGC_CTRL__RBC_MODE_MASK | 708 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 709 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 710 UVD_CGC_CTRL__IDCT_MODE_MASK | 711 UVD_CGC_CTRL__MPRD_MODE_MASK | 712 UVD_CGC_CTRL__MPC_MODE_MASK | 713 UVD_CGC_CTRL__LBSI_MODE_MASK | 714 UVD_CGC_CTRL__LRBBM_MODE_MASK | 715 UVD_CGC_CTRL__WCB_MODE_MASK | 716 UVD_CGC_CTRL__VCPU_MODE_MASK); 717 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 718 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 719 720 /* turn off clock gating */ 721 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 722 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); 723 724 /* turn on SUVD clock gating */ 725 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 726 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 727 728 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 729 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 730 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 731 } 732 733 /** 734 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating 735 * 736 * @adev: amdgpu_device pointer 737 * @inst_idx: instance number 738 * 739 * Enable clock gating for VCN block 740 */ 741 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 742 { 743 uint32_t data; 744 int vcn_inst; 745 746 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 747 return; 748 749 vcn_inst = GET_INST(VCN, inst_idx); 750 751 /* enable VCN CGC */ 752 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 753 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 754 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 755 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 756 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 757 758 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 759 data |= (UVD_CGC_CTRL__SYS_MODE_MASK 760 | UVD_CGC_CTRL__MPEG2_MODE_MASK 761 | UVD_CGC_CTRL__REGS_MODE_MASK 762 | UVD_CGC_CTRL__RBC_MODE_MASK 763 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 764 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 765 | UVD_CGC_CTRL__MPC_MODE_MASK 766 | UVD_CGC_CTRL__LBSI_MODE_MASK 767 | UVD_CGC_CTRL__LRBBM_MODE_MASK 768 | UVD_CGC_CTRL__WCB_MODE_MASK 769 | UVD_CGC_CTRL__VCPU_MODE_MASK); 770 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 771 772 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 773 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 774 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 775 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 776 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 777 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 778 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 779 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 780 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 781 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 782 } 783 784 /** 785 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode 786 * 787 * @adev: amdgpu_device pointer 788 * @inst_idx: instance number index 789 * @indirect: indirectly write sram 790 * 791 * Start VCN block with dpg mode 792 */ 793 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 794 { 795 volatile struct amdgpu_vcn4_fw_shared *fw_shared = 796 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 797 struct amdgpu_ring *ring; 798 int vcn_inst; 799 uint32_t tmp; 800 801 vcn_inst = GET_INST(VCN, inst_idx); 802 /* disable register anti-hang mechanism */ 803 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 804 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 805 /* enable dynamic power gating mode */ 806 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 807 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 808 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 809 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 810 811 if (indirect) { 812 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d", 813 inst_idx, adev->vcn.inst[inst_idx].aid_id); 814 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 815 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 816 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 817 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, 818 adev->vcn.inst[inst_idx].aid_id, 0, true); 819 } 820 821 /* enable clock gating */ 822 vcn_v4_0_3_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 823 824 /* enable VCPU clock */ 825 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 826 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 827 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 828 829 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 830 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 831 832 /* disable master interrupt */ 833 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 834 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 835 836 /* setup regUVD_LMI_CTRL */ 837 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 838 UVD_LMI_CTRL__REQ_MODE_MASK | 839 UVD_LMI_CTRL__CRC_RESET_MASK | 840 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 841 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 842 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 843 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 844 0x00100000L); 845 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 846 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 847 848 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 849 VCN, 0, regUVD_MPC_CNTL), 850 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 851 852 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 853 VCN, 0, regUVD_MPC_SET_MUXA0), 854 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 855 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 856 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 857 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 858 859 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 860 VCN, 0, regUVD_MPC_SET_MUXB0), 861 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 862 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 863 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 864 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 865 866 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 867 VCN, 0, regUVD_MPC_SET_MUX), 868 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 869 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 870 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 871 872 vcn_v4_0_3_mc_resume_dpg_mode(adev, inst_idx, indirect); 873 874 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 875 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 876 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 877 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 878 879 /* enable LMI MC and UMC channels */ 880 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 881 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 882 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 883 884 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); 885 886 /* enable master interrupt */ 887 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 888 VCN, 0, regUVD_MASTINT_EN), 889 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 890 891 if (indirect) 892 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 893 894 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 895 896 /* program the RB_BASE for ring buffer */ 897 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 898 lower_32_bits(ring->gpu_addr)); 899 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 900 upper_32_bits(ring->gpu_addr)); 901 902 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 903 ring->ring_size / sizeof(uint32_t)); 904 905 /* resetting ring, fw should not check RB ring */ 906 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 907 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 908 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 909 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 910 911 /* Initialize the ring buffer's read and write pointers */ 912 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 913 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 914 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 915 916 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 917 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 918 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 919 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 920 921 /*resetting done, fw can check RB ring */ 922 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 923 924 return 0; 925 } 926 927 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev) 928 { 929 int i, vcn_inst; 930 struct amdgpu_ring *ring_enc; 931 uint64_t cache_addr; 932 uint64_t rb_enc_addr; 933 uint64_t ctx_addr; 934 uint32_t param, resp, expected; 935 uint32_t offset, cache_size; 936 uint32_t tmp, timeout; 937 938 struct amdgpu_mm_table *table = &adev->virt.mm_table; 939 uint32_t *table_loc; 940 uint32_t table_size; 941 uint32_t size, size_dw; 942 uint32_t init_status; 943 uint32_t enabled_vcn; 944 945 struct mmsch_v4_0_cmd_direct_write 946 direct_wt = { {0} }; 947 struct mmsch_v4_0_cmd_direct_read_modify_write 948 direct_rd_mod_wt = { {0} }; 949 struct mmsch_v4_0_cmd_end end = { {0} }; 950 struct mmsch_v4_0_3_init_header header; 951 952 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 953 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 954 955 direct_wt.cmd_header.command_type = 956 MMSCH_COMMAND__DIRECT_REG_WRITE; 957 direct_rd_mod_wt.cmd_header.command_type = 958 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 959 end.cmd_header.command_type = MMSCH_COMMAND__END; 960 961 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 962 vcn_inst = GET_INST(VCN, i); 963 964 vcn_v4_0_3_fw_shared_init(adev, vcn_inst); 965 966 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 967 header.version = MMSCH_VERSION; 968 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 969 970 table_loc = (uint32_t *)table->cpu_addr; 971 table_loc += header.total_size; 972 973 table_size = 0; 974 975 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 976 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 977 978 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 979 980 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 981 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 982 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 983 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 984 985 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 986 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 987 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 988 989 offset = 0; 990 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 991 regUVD_VCPU_CACHE_OFFSET0), 0); 992 } else { 993 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 994 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 995 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 996 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 997 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 998 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 999 offset = cache_size; 1000 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1001 regUVD_VCPU_CACHE_OFFSET0), 1002 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1003 } 1004 1005 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1006 regUVD_VCPU_CACHE_SIZE0), 1007 cache_size); 1008 1009 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 1010 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1011 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1012 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1013 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1014 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1015 regUVD_VCPU_CACHE_OFFSET1), 0); 1016 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1017 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 1018 1019 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 1020 AMDGPU_VCN_STACK_SIZE; 1021 1022 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1023 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1024 1025 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1026 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1027 1028 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1029 regUVD_VCPU_CACHE_OFFSET2), 0); 1030 1031 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1032 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 1033 1034 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 1035 rb_setup = &fw_shared->rb_setup; 1036 1037 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 1038 ring_enc->wptr = 0; 1039 rb_enc_addr = ring_enc->gpu_addr; 1040 1041 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1042 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1043 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1044 rb_setup->rb_size = ring_enc->ring_size / 4; 1045 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1046 1047 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1048 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1049 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1050 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1051 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1052 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1053 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1054 regUVD_VCPU_NONCACHE_SIZE0), 1055 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1056 MMSCH_V4_0_INSERT_END(); 1057 1058 header.vcn0.init_status = 0; 1059 header.vcn0.table_offset = header.total_size; 1060 header.vcn0.table_size = table_size; 1061 header.total_size += table_size; 1062 1063 /* Send init table to mmsch */ 1064 size = sizeof(struct mmsch_v4_0_3_init_header); 1065 table_loc = (uint32_t *)table->cpu_addr; 1066 memcpy((void *)table_loc, &header, size); 1067 1068 ctx_addr = table->gpu_addr; 1069 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1070 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1071 1072 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 1073 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1074 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1075 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 1076 1077 size = header.total_size; 1078 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 1079 1080 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 1081 1082 param = 0x00000001; 1083 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 1084 tmp = 0; 1085 timeout = 1000; 1086 resp = 0; 1087 expected = MMSCH_VF_MAILBOX_RESP__OK; 1088 while (resp != expected) { 1089 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 1090 if (resp != 0) 1091 break; 1092 1093 udelay(10); 1094 tmp = tmp + 10; 1095 if (tmp >= timeout) { 1096 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1097 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1098 "(expected=0x%08x, readback=0x%08x)\n", 1099 tmp, expected, resp); 1100 return -EBUSY; 1101 } 1102 } 1103 1104 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1105 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status; 1106 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1107 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 1108 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1109 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1110 } 1111 } 1112 1113 return 0; 1114 } 1115 1116 /** 1117 * vcn_v4_0_3_start - VCN start 1118 * 1119 * @adev: amdgpu_device pointer 1120 * 1121 * Start VCN block 1122 */ 1123 static int vcn_v4_0_3_start(struct amdgpu_device *adev) 1124 { 1125 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1126 struct amdgpu_ring *ring; 1127 int i, j, k, r, vcn_inst; 1128 uint32_t tmp; 1129 1130 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1131 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1132 r = vcn_v4_0_3_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1133 continue; 1134 } 1135 1136 vcn_inst = GET_INST(VCN, i); 1137 /* set VCN status busy */ 1138 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | 1139 UVD_STATUS__UVD_BUSY; 1140 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 1141 1142 /*SW clock gating */ 1143 vcn_v4_0_3_disable_clock_gating(adev, i); 1144 1145 /* enable VCPU clock */ 1146 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1147 UVD_VCPU_CNTL__CLK_EN_MASK, 1148 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1149 1150 /* disable master interrupt */ 1151 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 1152 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1153 1154 /* enable LMI MC and UMC channels */ 1155 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 1156 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1157 1158 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1159 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1160 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1161 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1162 1163 /* setup regUVD_LMI_CTRL */ 1164 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 1165 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, 1166 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1167 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1168 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1169 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1170 1171 /* setup regUVD_MPC_CNTL */ 1172 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); 1173 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1174 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1175 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); 1176 1177 /* setup UVD_MPC_SET_MUXA0 */ 1178 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, 1179 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1180 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1181 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1182 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1183 1184 /* setup UVD_MPC_SET_MUXB0 */ 1185 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, 1186 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1187 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1188 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1189 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1190 1191 /* setup UVD_MPC_SET_MUX */ 1192 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX, 1193 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1194 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1195 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1196 1197 vcn_v4_0_3_mc_resume(adev, i); 1198 1199 /* VCN global tiling registers */ 1200 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG, 1201 adev->gfx.config.gb_addr_config); 1202 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 1203 adev->gfx.config.gb_addr_config); 1204 1205 /* unblock VCPU register access */ 1206 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1207 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1208 1209 /* release VCPU reset to boot */ 1210 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1211 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1212 1213 for (j = 0; j < 10; ++j) { 1214 uint32_t status; 1215 1216 for (k = 0; k < 100; ++k) { 1217 status = RREG32_SOC15(VCN, vcn_inst, 1218 regUVD_STATUS); 1219 if (status & 2) 1220 break; 1221 mdelay(10); 1222 } 1223 r = 0; 1224 if (status & 2) 1225 break; 1226 1227 DRM_DEV_ERROR(adev->dev, 1228 "VCN decode not responding, trying to reset the VCPU!!!\n"); 1229 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1230 regUVD_VCPU_CNTL), 1231 UVD_VCPU_CNTL__BLK_RST_MASK, 1232 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1233 mdelay(10); 1234 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1235 regUVD_VCPU_CNTL), 1236 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); 1237 1238 mdelay(10); 1239 r = -1; 1240 } 1241 1242 if (r) { 1243 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n"); 1244 return r; 1245 } 1246 1247 /* enable master interrupt */ 1248 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1249 UVD_MASTINT_EN__VCPU_EN_MASK, 1250 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1251 1252 /* clear the busy bit of VCN_STATUS */ 1253 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1254 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1255 1256 ring = &adev->vcn.inst[i].ring_enc[0]; 1257 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1258 1259 /* program the RB_BASE for ring buffer */ 1260 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 1261 lower_32_bits(ring->gpu_addr)); 1262 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 1263 upper_32_bits(ring->gpu_addr)); 1264 1265 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 1266 ring->ring_size / sizeof(uint32_t)); 1267 1268 /* resetting ring, fw should not check RB ring */ 1269 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1270 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 1271 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1272 1273 /* Initialize the ring buffer's read and write pointers */ 1274 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1275 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1276 1277 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1278 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 1279 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1280 1281 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1282 fw_shared->sq.queue_mode &= 1283 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF)); 1284 1285 } 1286 return 0; 1287 } 1288 1289 /** 1290 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode 1291 * 1292 * @adev: amdgpu_device pointer 1293 * @inst_idx: instance number index 1294 * 1295 * Stop VCN block with dpg mode 1296 */ 1297 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1298 { 1299 uint32_t tmp; 1300 int vcn_inst; 1301 1302 vcn_inst = GET_INST(VCN, inst_idx); 1303 1304 /* Wait for power status to be 1 */ 1305 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1306 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1307 1308 /* wait for read ptr to be equal to write ptr */ 1309 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1310 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1311 1312 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1313 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1314 1315 /* disable dynamic power gating mode */ 1316 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1317 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1318 return 0; 1319 } 1320 1321 /** 1322 * vcn_v4_0_3_stop - VCN stop 1323 * 1324 * @adev: amdgpu_device pointer 1325 * 1326 * Stop VCN block 1327 */ 1328 static int vcn_v4_0_3_stop(struct amdgpu_device *adev) 1329 { 1330 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1331 int i, r = 0, vcn_inst; 1332 uint32_t tmp; 1333 1334 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1335 vcn_inst = GET_INST(VCN, i); 1336 1337 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1338 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1339 1340 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1341 vcn_v4_0_3_stop_dpg_mode(adev, i); 1342 continue; 1343 } 1344 1345 /* wait for vcn idle */ 1346 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, 1347 UVD_STATUS__IDLE, 0x7); 1348 if (r) 1349 goto Done; 1350 1351 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1352 UVD_LMI_STATUS__READ_CLEAN_MASK | 1353 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1354 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1355 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1356 tmp); 1357 if (r) 1358 goto Done; 1359 1360 /* stall UMC channel */ 1361 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1362 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1363 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1364 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1365 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1366 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1367 tmp); 1368 if (r) 1369 goto Done; 1370 1371 /* Unblock VCPU Register access */ 1372 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1373 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1374 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1375 1376 /* release VCPU reset to boot */ 1377 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1378 UVD_VCPU_CNTL__BLK_RST_MASK, 1379 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1380 1381 /* disable VCPU clock */ 1382 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1383 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1384 1385 /* reset LMI UMC/LMI/VCPU */ 1386 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1387 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1388 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1389 1390 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1391 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1392 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1393 1394 /* clear VCN status */ 1395 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1396 1397 /* apply HW clock gating */ 1398 vcn_v4_0_3_enable_clock_gating(adev, i); 1399 } 1400 Done: 1401 return 0; 1402 } 1403 1404 /** 1405 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode 1406 * 1407 * @adev: amdgpu_device pointer 1408 * @inst_idx: instance number index 1409 * @new_state: pause state 1410 * 1411 * Pause dpg mode for VCN block 1412 */ 1413 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1414 struct dpg_pause_state *new_state) 1415 { 1416 1417 return 0; 1418 } 1419 1420 /** 1421 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer 1422 * 1423 * @ring: amdgpu_ring pointer 1424 * 1425 * Returns the current hardware unified read pointer 1426 */ 1427 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring) 1428 { 1429 struct amdgpu_device *adev = ring->adev; 1430 1431 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1432 DRM_ERROR("wrong ring id is identified in %s", __func__); 1433 1434 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1435 } 1436 1437 /** 1438 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer 1439 * 1440 * @ring: amdgpu_ring pointer 1441 * 1442 * Returns the current hardware unified write pointer 1443 */ 1444 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring) 1445 { 1446 struct amdgpu_device *adev = ring->adev; 1447 1448 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1449 DRM_ERROR("wrong ring id is identified in %s", __func__); 1450 1451 if (ring->use_doorbell) 1452 return *ring->wptr_cpu_addr; 1453 else 1454 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), 1455 regUVD_RB_WPTR); 1456 } 1457 1458 static void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1459 uint32_t val, uint32_t mask) 1460 { 1461 /* Use normalized offsets when required */ 1462 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1463 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1464 1465 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1466 amdgpu_ring_write(ring, reg << 2); 1467 amdgpu_ring_write(ring, mask); 1468 amdgpu_ring_write(ring, val); 1469 } 1470 1471 static void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1472 { 1473 /* Use normalized offsets when required */ 1474 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1475 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1476 1477 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1478 amdgpu_ring_write(ring, reg << 2); 1479 amdgpu_ring_write(ring, val); 1480 } 1481 1482 static void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1483 unsigned int vmid, uint64_t pd_addr) 1484 { 1485 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1486 1487 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1488 1489 /* wait for reg writes */ 1490 vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1491 vmid * hub->ctx_addr_distance, 1492 lower_32_bits(pd_addr), 0xffffffff); 1493 } 1494 1495 static void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1496 { 1497 /* VCN engine access for HDP flush doesn't work when RRMT is enabled. 1498 * This is a workaround to avoid any HDP flush through VCN ring. 1499 */ 1500 } 1501 1502 /** 1503 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer 1504 * 1505 * @ring: amdgpu_ring pointer 1506 * 1507 * Commits the enc write pointer to the hardware 1508 */ 1509 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) 1510 { 1511 struct amdgpu_device *adev = ring->adev; 1512 1513 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1514 DRM_ERROR("wrong ring id is identified in %s", __func__); 1515 1516 if (ring->use_doorbell) { 1517 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1518 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1519 } else { 1520 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1521 lower_32_bits(ring->wptr)); 1522 } 1523 } 1524 1525 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { 1526 .type = AMDGPU_RING_TYPE_VCN_ENC, 1527 .align_mask = 0x3f, 1528 .nop = VCN_ENC_CMD_NO_OP, 1529 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, 1530 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, 1531 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, 1532 .emit_frame_size = 1533 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1534 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1535 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1536 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1537 1, /* vcn_v2_0_enc_ring_insert_end */ 1538 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1539 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1540 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1541 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1542 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1543 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1544 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1545 .insert_nop = amdgpu_ring_insert_nop, 1546 .insert_end = vcn_v2_0_enc_ring_insert_end, 1547 .pad_ib = amdgpu_ring_generic_pad_ib, 1548 .begin_use = amdgpu_vcn_ring_begin_use, 1549 .end_use = amdgpu_vcn_ring_end_use, 1550 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1551 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1552 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1553 }; 1554 1555 /** 1556 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions 1557 * 1558 * @adev: amdgpu_device pointer 1559 * 1560 * Set unified ring functions 1561 */ 1562 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev) 1563 { 1564 int i, vcn_inst; 1565 1566 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1567 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs; 1568 adev->vcn.inst[i].ring_enc[0].me = i; 1569 vcn_inst = GET_INST(VCN, i); 1570 adev->vcn.inst[i].aid_id = 1571 vcn_inst / adev->vcn.num_inst_per_aid; 1572 } 1573 } 1574 1575 /** 1576 * vcn_v4_0_3_is_idle - check VCN block is idle 1577 * 1578 * @handle: amdgpu_device pointer 1579 * 1580 * Check whether VCN block is idle 1581 */ 1582 static bool vcn_v4_0_3_is_idle(void *handle) 1583 { 1584 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1585 int i, ret = 1; 1586 1587 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1588 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == 1589 UVD_STATUS__IDLE); 1590 } 1591 1592 return ret; 1593 } 1594 1595 /** 1596 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle 1597 * 1598 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1599 * 1600 * Wait for VCN block idle 1601 */ 1602 static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 1603 { 1604 struct amdgpu_device *adev = ip_block->adev; 1605 int i, ret = 0; 1606 1607 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1608 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, 1609 UVD_STATUS__IDLE, UVD_STATUS__IDLE); 1610 if (ret) 1611 return ret; 1612 } 1613 1614 return ret; 1615 } 1616 1617 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state 1618 * 1619 * @ip_block: amdgpu_ip_block pointer 1620 * @state: clock gating state 1621 * 1622 * Set VCN block clockgating state 1623 */ 1624 static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1625 enum amd_clockgating_state state) 1626 { 1627 struct amdgpu_device *adev = ip_block->adev; 1628 bool enable = state == AMD_CG_STATE_GATE; 1629 int i; 1630 1631 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1632 if (enable) { 1633 if (RREG32_SOC15(VCN, GET_INST(VCN, i), 1634 regUVD_STATUS) != UVD_STATUS__IDLE) 1635 return -EBUSY; 1636 vcn_v4_0_3_enable_clock_gating(adev, i); 1637 } else { 1638 vcn_v4_0_3_disable_clock_gating(adev, i); 1639 } 1640 } 1641 return 0; 1642 } 1643 1644 /** 1645 * vcn_v4_0_3_set_powergating_state - set VCN block powergating state 1646 * 1647 * @ip_block: amdgpu_ip_block pointer 1648 * @state: power gating state 1649 * 1650 * Set VCN block powergating state 1651 */ 1652 static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 1653 enum amd_powergating_state state) 1654 { 1655 struct amdgpu_device *adev = ip_block->adev; 1656 int ret; 1657 1658 /* for SRIOV, guest should not control VCN Power-gating 1659 * MMSCH FW should control Power-gating and clock-gating 1660 * guest should avoid touching CGC and PG 1661 */ 1662 if (amdgpu_sriov_vf(adev)) { 1663 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1664 return 0; 1665 } 1666 1667 if (state == adev->vcn.cur_state) 1668 return 0; 1669 1670 if (state == AMD_PG_STATE_GATE) 1671 ret = vcn_v4_0_3_stop(adev); 1672 else 1673 ret = vcn_v4_0_3_start(adev); 1674 1675 if (!ret) 1676 adev->vcn.cur_state = state; 1677 1678 return ret; 1679 } 1680 1681 /** 1682 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state 1683 * 1684 * @adev: amdgpu_device pointer 1685 * @source: interrupt sources 1686 * @type: interrupt types 1687 * @state: interrupt states 1688 * 1689 * Set VCN block interrupt state 1690 */ 1691 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1692 struct amdgpu_irq_src *source, 1693 unsigned int type, 1694 enum amdgpu_interrupt_state state) 1695 { 1696 return 0; 1697 } 1698 1699 /** 1700 * vcn_v4_0_3_process_interrupt - process VCN block interrupt 1701 * 1702 * @adev: amdgpu_device pointer 1703 * @source: interrupt sources 1704 * @entry: interrupt entry from clients and sources 1705 * 1706 * Process VCN block interrupt 1707 */ 1708 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1709 struct amdgpu_irq_src *source, 1710 struct amdgpu_iv_entry *entry) 1711 { 1712 uint32_t i, inst; 1713 1714 i = node_id_to_phys_map[entry->node_id]; 1715 1716 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1717 1718 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1719 if (adev->vcn.inst[inst].aid_id == i) 1720 break; 1721 1722 if (inst >= adev->vcn.num_vcn_inst) { 1723 dev_WARN_ONCE(adev->dev, 1, 1724 "Interrupt received for unknown VCN instance %d", 1725 entry->node_id); 1726 return 0; 1727 } 1728 1729 switch (entry->src_id) { 1730 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1731 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1732 break; 1733 default: 1734 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1735 entry->src_id, entry->src_data[0]); 1736 break; 1737 } 1738 1739 return 0; 1740 } 1741 1742 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 1743 .set = vcn_v4_0_3_set_interrupt_state, 1744 .process = vcn_v4_0_3_process_interrupt, 1745 }; 1746 1747 /** 1748 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions 1749 * 1750 * @adev: amdgpu_device pointer 1751 * 1752 * Set VCN block interrupt irq functions 1753 */ 1754 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1755 { 1756 int i; 1757 1758 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1759 adev->vcn.inst->irq.num_types++; 1760 } 1761 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 1762 } 1763 1764 static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1765 { 1766 struct amdgpu_device *adev = ip_block->adev; 1767 int i, j; 1768 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 1769 uint32_t inst_off, is_powered; 1770 1771 if (!adev->vcn.ip_dump) 1772 return; 1773 1774 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1775 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1776 if (adev->vcn.harvest_config & (1 << i)) { 1777 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1778 continue; 1779 } 1780 1781 inst_off = i * reg_count; 1782 is_powered = (adev->vcn.ip_dump[inst_off] & 1783 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1784 1785 if (is_powered) { 1786 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1787 for (j = 0; j < reg_count; j++) 1788 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name, 1789 adev->vcn.ip_dump[inst_off + j]); 1790 } else { 1791 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1792 } 1793 } 1794 } 1795 1796 static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block) 1797 { 1798 struct amdgpu_device *adev = ip_block->adev; 1799 int i, j; 1800 bool is_powered; 1801 uint32_t inst_off, inst_id; 1802 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 1803 1804 if (!adev->vcn.ip_dump) 1805 return; 1806 1807 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1808 if (adev->vcn.harvest_config & (1 << i)) 1809 continue; 1810 1811 inst_id = GET_INST(VCN, i); 1812 inst_off = i * reg_count; 1813 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1814 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS); 1815 is_powered = (adev->vcn.ip_dump[inst_off] & 1816 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1817 1818 if (is_powered) 1819 for (j = 1; j < reg_count; j++) 1820 adev->vcn.ip_dump[inst_off + j] = 1821 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j], 1822 inst_id)); 1823 } 1824 } 1825 1826 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 1827 .name = "vcn_v4_0_3", 1828 .early_init = vcn_v4_0_3_early_init, 1829 .sw_init = vcn_v4_0_3_sw_init, 1830 .sw_fini = vcn_v4_0_3_sw_fini, 1831 .hw_init = vcn_v4_0_3_hw_init, 1832 .hw_fini = vcn_v4_0_3_hw_fini, 1833 .suspend = vcn_v4_0_3_suspend, 1834 .resume = vcn_v4_0_3_resume, 1835 .is_idle = vcn_v4_0_3_is_idle, 1836 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 1837 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 1838 .set_powergating_state = vcn_v4_0_3_set_powergating_state, 1839 .dump_ip_state = vcn_v4_0_3_dump_ip_state, 1840 .print_ip_state = vcn_v4_0_3_print_ip_state, 1841 }; 1842 1843 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { 1844 .type = AMD_IP_BLOCK_TYPE_VCN, 1845 .major = 4, 1846 .minor = 0, 1847 .rev = 3, 1848 .funcs = &vcn_v4_0_3_ip_funcs, 1849 }; 1850 1851 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = { 1852 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD), 1853 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"}, 1854 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV), 1855 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"}, 1856 }; 1857 1858 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1859 uint32_t vcn_inst, 1860 void *ras_err_status) 1861 { 1862 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1863 1864 /* vcn v4_0_3 only support query uncorrectable errors */ 1865 amdgpu_ras_inst_query_ras_error_count(adev, 1866 vcn_v4_0_3_ue_reg_list, 1867 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1868 NULL, 0, GET_INST(VCN, vcn_inst), 1869 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1870 &err_data->ue_count); 1871 } 1872 1873 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1874 void *ras_err_status) 1875 { 1876 uint32_t i; 1877 1878 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1879 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1880 return; 1881 } 1882 1883 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1884 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1885 } 1886 1887 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1888 uint32_t vcn_inst) 1889 { 1890 amdgpu_ras_inst_reset_ras_error_count(adev, 1891 vcn_v4_0_3_ue_reg_list, 1892 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1893 GET_INST(VCN, vcn_inst)); 1894 } 1895 1896 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1897 { 1898 uint32_t i; 1899 1900 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1901 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1902 return; 1903 } 1904 1905 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1906 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 1907 } 1908 1909 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 1910 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 1911 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 1912 }; 1913 1914 static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1915 enum aca_smu_type type, void *data) 1916 { 1917 struct aca_bank_info info; 1918 u64 misc0; 1919 int ret; 1920 1921 ret = aca_bank_info_decode(bank, &info); 1922 if (ret) 1923 return ret; 1924 1925 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 1926 switch (type) { 1927 case ACA_SMU_TYPE_UE: 1928 bank->aca_err_type = ACA_ERROR_TYPE_UE; 1929 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 1930 1ULL); 1931 break; 1932 case ACA_SMU_TYPE_CE: 1933 bank->aca_err_type = ACA_ERROR_TYPE_CE; 1934 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE, 1935 ACA_REG__MISC0__ERRCNT(misc0)); 1936 break; 1937 default: 1938 return -EINVAL; 1939 } 1940 1941 return ret; 1942 } 1943 1944 /* reference to smu driver if header file */ 1945 static int vcn_v4_0_3_err_codes[] = { 1946 14, 15, /* VCN */ 1947 }; 1948 1949 static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 1950 enum aca_smu_type type, void *data) 1951 { 1952 u32 instlo; 1953 1954 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 1955 instlo &= GENMASK(31, 1); 1956 1957 if (instlo != mmSMNAID_AID0_MCA_SMU) 1958 return false; 1959 1960 if (aca_bank_check_error_codes(handle->adev, bank, 1961 vcn_v4_0_3_err_codes, 1962 ARRAY_SIZE(vcn_v4_0_3_err_codes))) 1963 return false; 1964 1965 return true; 1966 } 1967 1968 static const struct aca_bank_ops vcn_v4_0_3_aca_bank_ops = { 1969 .aca_bank_parser = vcn_v4_0_3_aca_bank_parser, 1970 .aca_bank_is_valid = vcn_v4_0_3_aca_bank_is_valid, 1971 }; 1972 1973 static const struct aca_info vcn_v4_0_3_aca_info = { 1974 .hwip = ACA_HWIP_TYPE_SMU, 1975 .mask = ACA_ERROR_UE_MASK, 1976 .bank_ops = &vcn_v4_0_3_aca_bank_ops, 1977 }; 1978 1979 static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1980 { 1981 int r; 1982 1983 r = amdgpu_ras_block_late_init(adev, ras_block); 1984 if (r) 1985 return r; 1986 1987 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN, 1988 &vcn_v4_0_3_aca_info, NULL); 1989 if (r) 1990 goto late_fini; 1991 1992 return 0; 1993 1994 late_fini: 1995 amdgpu_ras_block_late_fini(adev, ras_block); 1996 1997 return r; 1998 } 1999 2000 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = { 2001 .ras_block = { 2002 .hw_ops = &vcn_v4_0_3_ras_hw_ops, 2003 .ras_late_init = vcn_v4_0_3_ras_late_init, 2004 }, 2005 }; 2006 2007 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 2008 { 2009 adev->vcn.ras = &vcn_v4_0_3_ras; 2010 } 2011 2012 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 2013 int inst_idx, bool indirect) 2014 { 2015 uint32_t tmp; 2016 2017 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 2018 return; 2019 2020 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 2021 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 2022 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 2023 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 2024 WREG32_SOC15_DPG_MODE(inst_idx, 2025 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 2026 tmp, 0, indirect); 2027 2028 tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK; 2029 WREG32_SOC15_DPG_MODE(inst_idx, 2030 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2), 2031 tmp, 0, indirect); 2032 2033 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 2034 WREG32_SOC15_DPG_MODE(inst_idx, 2035 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 2036 tmp, 0, indirect); 2037 } 2038