1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_hw_ip.h" 33 #include "vcn_v2_0.h" 34 #include "vcn_v4_0_3.h" 35 #include "mmsch_v4_0_3.h" 36 37 #include "vcn/vcn_4_0_3_offset.h" 38 #include "vcn/vcn_4_0_3_sh_mask.h" 39 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 40 41 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 42 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 43 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 44 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 45 46 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 47 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 48 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 49 50 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 84 }; 85 86 #define NORMALIZE_VCN_REG_OFFSET(offset) \ 87 (offset & 0x1FFFF) 88 89 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); 90 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); 91 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 92 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 93 enum amd_powergating_state state); 94 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 95 struct dpg_pause_state *new_state); 96 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring); 97 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 99 int inst_idx, bool indirect); 100 101 static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 102 { 103 return (adev->vcn.caps & AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0; 104 } 105 106 /** 107 * vcn_v4_0_3_early_init - set function pointers 108 * 109 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 110 * 111 * Set ring and irq function pointers 112 */ 113 static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 119 /* re-use enc ring as unified ring */ 120 adev->vcn.inst[i].num_enc_rings = 1; 121 122 vcn_v4_0_3_set_unified_ring_funcs(adev); 123 vcn_v4_0_3_set_irq_funcs(adev); 124 vcn_v4_0_3_set_ras_funcs(adev); 125 126 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 127 adev->vcn.inst[i].set_pg_state = vcn_v4_0_3_set_pg_state; 128 129 r = amdgpu_vcn_early_init(adev, i); 130 if (r) 131 return r; 132 } 133 134 return 0; 135 } 136 137 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 138 { 139 struct amdgpu_vcn4_fw_shared *fw_shared; 140 141 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 142 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 143 fw_shared->sq.is_enabled = 1; 144 145 if (amdgpu_vcnfw_log) 146 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 147 148 return 0; 149 } 150 151 /** 152 * vcn_v4_0_3_sw_init - sw init for VCN block 153 * 154 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 155 * 156 * Load firmware and sw initialization 157 */ 158 static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 159 { 160 struct amdgpu_device *adev = ip_block->adev; 161 struct amdgpu_ring *ring; 162 int i, r, vcn_inst; 163 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 164 uint32_t *ptr; 165 166 /* VCN DEC TRAP */ 167 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 168 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 169 if (r) 170 return r; 171 172 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 173 174 r = amdgpu_vcn_sw_init(adev, i); 175 if (r) 176 return r; 177 178 amdgpu_vcn_setup_ucode(adev, i); 179 180 r = amdgpu_vcn_resume(adev, i); 181 if (r) 182 return r; 183 184 vcn_inst = GET_INST(VCN, i); 185 186 ring = &adev->vcn.inst[i].ring_enc[0]; 187 ring->use_doorbell = true; 188 189 if (!amdgpu_sriov_vf(adev)) 190 ring->doorbell_index = 191 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 192 9 * vcn_inst; 193 else 194 ring->doorbell_index = 195 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 196 32 * vcn_inst; 197 198 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 199 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 200 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 201 AMDGPU_RING_PRIO_DEFAULT, 202 &adev->vcn.inst[i].sched_score); 203 if (r) 204 return r; 205 206 vcn_v4_0_3_fw_shared_init(adev, i); 207 208 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 209 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; 210 } 211 212 /* TODO: Add queue reset mask when FW fully supports it */ 213 adev->vcn.supported_reset = 214 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 215 216 if (amdgpu_sriov_vf(adev)) { 217 r = amdgpu_virt_alloc_mm_table(adev); 218 if (r) 219 return r; 220 } 221 222 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 223 r = amdgpu_vcn_ras_sw_init(adev); 224 if (r) { 225 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 226 return r; 227 } 228 } 229 230 /* Allocate memory for VCN IP Dump buffer */ 231 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 232 if (!ptr) { 233 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 234 adev->vcn.ip_dump = NULL; 235 } else { 236 adev->vcn.ip_dump = ptr; 237 } 238 239 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 240 if (r) 241 return r; 242 243 return 0; 244 } 245 246 /** 247 * vcn_v4_0_3_sw_fini - sw fini for VCN block 248 * 249 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 250 * 251 * VCN suspend and free up sw allocation 252 */ 253 static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 254 { 255 struct amdgpu_device *adev = ip_block->adev; 256 int i, r, idx; 257 258 if (drm_dev_enter(&adev->ddev, &idx)) { 259 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 260 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 261 262 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 263 fw_shared->present_flag_0 = 0; 264 fw_shared->sq.is_enabled = cpu_to_le32(false); 265 } 266 drm_dev_exit(idx); 267 } 268 269 if (amdgpu_sriov_vf(adev)) 270 amdgpu_virt_free_mm_table(adev); 271 272 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 273 r = amdgpu_vcn_suspend(adev, i); 274 if (r) 275 return r; 276 } 277 278 amdgpu_vcn_sysfs_reset_mask_fini(adev); 279 280 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 281 r = amdgpu_vcn_sw_fini(adev, i); 282 if (r) 283 return r; 284 } 285 286 kfree(adev->vcn.ip_dump); 287 288 return 0; 289 } 290 291 static int vcn_v4_0_3_hw_init_inst(struct amdgpu_vcn_inst *vinst) 292 { 293 int vcn_inst; 294 struct amdgpu_device *adev = vinst->adev; 295 struct amdgpu_ring *ring; 296 int inst_idx = vinst->inst; 297 298 vcn_inst = GET_INST(VCN, inst_idx); 299 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 300 if (ring->use_doorbell) { 301 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 302 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * vcn_inst, 303 adev->vcn.inst[inst_idx].aid_id); 304 305 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 306 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 307 VCN_RB1_DB_CTRL__EN_MASK); 308 309 /* Read DB_CTRL to flush the write DB_CTRL command. */ 310 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 311 } 312 313 return 0; 314 } 315 316 /** 317 * vcn_v4_0_3_hw_init - start and test VCN block 318 * 319 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 320 * 321 * Initialize the hardware, boot up the VCPU and do some testing 322 */ 323 static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 324 { 325 struct amdgpu_device *adev = ip_block->adev; 326 struct amdgpu_ring *ring; 327 struct amdgpu_vcn_inst *vinst; 328 int i, r; 329 330 if (amdgpu_sriov_vf(adev)) { 331 r = vcn_v4_0_3_start_sriov(adev); 332 if (r) 333 return r; 334 335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 336 ring = &adev->vcn.inst[i].ring_enc[0]; 337 ring->wptr = 0; 338 ring->wptr_old = 0; 339 vcn_v4_0_3_unified_ring_set_wptr(ring); 340 ring->sched.ready = true; 341 } 342 } else { 343 /* This flag is not set for VF, assumed to be disabled always */ 344 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 345 0x100) 346 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 347 348 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 349 struct amdgpu_vcn4_fw_shared *fw_shared; 350 351 ring = &adev->vcn.inst[i].ring_enc[0]; 352 vinst = &adev->vcn.inst[i]; 353 vcn_v4_0_3_hw_init_inst(vinst); 354 355 /* Re-init fw_shared when RAS fatal error occurred */ 356 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 357 if (!fw_shared->sq.is_enabled) 358 vcn_v4_0_3_fw_shared_init(adev, i); 359 360 r = amdgpu_ring_test_helper(ring); 361 if (r) 362 return r; 363 } 364 } 365 366 return r; 367 } 368 369 /** 370 * vcn_v4_0_3_hw_fini - stop the hardware block 371 * 372 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 373 * 374 * Stop the VCN block, mark ring as not ready any more 375 */ 376 static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 377 { 378 struct amdgpu_device *adev = ip_block->adev; 379 int i; 380 381 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 382 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 383 384 cancel_delayed_work_sync(&vinst->idle_work); 385 386 if (vinst->cur_state != AMD_PG_STATE_GATE) 387 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 388 } 389 390 return 0; 391 } 392 393 /** 394 * vcn_v4_0_3_suspend - suspend VCN block 395 * 396 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 397 * 398 * HW fini and suspend VCN block 399 */ 400 static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 401 { 402 struct amdgpu_device *adev = ip_block->adev; 403 int r, i; 404 405 r = vcn_v4_0_3_hw_fini(ip_block); 406 if (r) 407 return r; 408 409 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 410 r = amdgpu_vcn_suspend(adev, i); 411 if (r) 412 return r; 413 } 414 415 return 0; 416 } 417 418 /** 419 * vcn_v4_0_3_resume - resume VCN block 420 * 421 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 422 * 423 * Resume firmware and hw init VCN block 424 */ 425 static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 426 { 427 struct amdgpu_device *adev = ip_block->adev; 428 int r, i; 429 430 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 431 r = amdgpu_vcn_resume(ip_block->adev, i); 432 if (r) 433 return r; 434 } 435 436 r = vcn_v4_0_3_hw_init(ip_block); 437 438 return r; 439 } 440 441 /** 442 * vcn_v4_0_3_mc_resume - memory controller programming 443 * 444 * @vinst: VCN instance 445 * 446 * Let the VCN memory controller know it's offsets 447 */ 448 static void vcn_v4_0_3_mc_resume(struct amdgpu_vcn_inst *vinst) 449 { 450 struct amdgpu_device *adev = vinst->adev; 451 int inst_idx = vinst->inst; 452 uint32_t offset, size, vcn_inst; 453 const struct common_firmware_header *hdr; 454 455 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 456 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 457 458 vcn_inst = GET_INST(VCN, inst_idx); 459 /* cache window 0: fw */ 460 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 461 WREG32_SOC15( 462 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 463 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 464 .tmr_mc_addr_lo)); 465 WREG32_SOC15( 466 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 467 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 468 .tmr_mc_addr_hi)); 469 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 470 offset = 0; 471 } else { 472 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 473 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 474 WREG32_SOC15(VCN, vcn_inst, 475 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 476 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 477 offset = size; 478 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 479 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 480 } 481 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 482 483 /* cache window 1: stack */ 484 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 485 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 486 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 487 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 488 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 489 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, 490 AMDGPU_VCN_STACK_SIZE); 491 492 /* cache window 2: context */ 493 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 494 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 495 AMDGPU_VCN_STACK_SIZE)); 496 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 497 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 498 AMDGPU_VCN_STACK_SIZE)); 499 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 500 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, 501 AMDGPU_VCN_CONTEXT_SIZE); 502 503 /* non-cache window */ 504 WREG32_SOC15( 505 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 506 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 507 WREG32_SOC15( 508 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 509 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 510 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 511 WREG32_SOC15( 512 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 513 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 514 } 515 516 /** 517 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode 518 * 519 * @vinst: VCN instance 520 * @indirect: indirectly write sram 521 * 522 * Let the VCN memory controller know it's offsets with dpg mode 523 */ 524 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 525 bool indirect) 526 { 527 struct amdgpu_device *adev = vinst->adev; 528 int inst_idx = vinst->inst; 529 uint32_t offset, size; 530 const struct common_firmware_header *hdr; 531 532 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 533 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 534 535 /* cache window 0: fw */ 536 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 537 if (!indirect) { 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 540 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 541 inst_idx].tmr_mc_addr_lo), 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 544 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 545 inst_idx].tmr_mc_addr_hi), 0, indirect); 546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 547 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 548 } else { 549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 550 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 553 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 554 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 555 } 556 offset = 0; 557 } else { 558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 559 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 560 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 562 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 563 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 564 offset = size; 565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 566 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 567 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 568 } 569 570 if (!indirect) 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 573 else 574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 575 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 576 577 /* cache window 1: stack */ 578 if (!indirect) { 579 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 580 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 581 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 582 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 583 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 584 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 586 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 587 } else { 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 590 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 591 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 592 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 593 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 594 } 595 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 596 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 597 598 /* cache window 2: context */ 599 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 600 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 601 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 602 AMDGPU_VCN_STACK_SIZE), 0, indirect); 603 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 604 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 605 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 606 AMDGPU_VCN_STACK_SIZE), 0, indirect); 607 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 608 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 609 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 610 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 611 612 /* non-cache window */ 613 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 614 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 615 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 616 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 617 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 618 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 619 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 620 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 621 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 622 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 623 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 624 625 /* VCN global tiling registers */ 626 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 627 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 628 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 629 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 630 } 631 632 /** 633 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating 634 * 635 * @vinst: VCN instance 636 * 637 * Disable clock gating for VCN block 638 */ 639 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 640 { 641 struct amdgpu_device *adev = vinst->adev; 642 int inst_idx = vinst->inst; 643 uint32_t data; 644 int vcn_inst; 645 646 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 647 return; 648 649 vcn_inst = GET_INST(VCN, inst_idx); 650 651 /* VCN disable CGC */ 652 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 653 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 654 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 655 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 656 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 657 658 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); 659 data &= ~(UVD_CGC_GATE__SYS_MASK 660 | UVD_CGC_GATE__MPEG2_MASK 661 | UVD_CGC_GATE__REGS_MASK 662 | UVD_CGC_GATE__RBC_MASK 663 | UVD_CGC_GATE__LMI_MC_MASK 664 | UVD_CGC_GATE__LMI_UMC_MASK 665 | UVD_CGC_GATE__MPC_MASK 666 | UVD_CGC_GATE__LBSI_MASK 667 | UVD_CGC_GATE__LRBBM_MASK 668 | UVD_CGC_GATE__WCB_MASK 669 | UVD_CGC_GATE__VCPU_MASK 670 | UVD_CGC_GATE__MMSCH_MASK); 671 672 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); 673 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 674 675 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 676 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK 677 | UVD_CGC_CTRL__MPEG2_MODE_MASK 678 | UVD_CGC_CTRL__REGS_MODE_MASK 679 | UVD_CGC_CTRL__RBC_MODE_MASK 680 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 681 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 682 | UVD_CGC_CTRL__MPC_MODE_MASK 683 | UVD_CGC_CTRL__LBSI_MODE_MASK 684 | UVD_CGC_CTRL__LRBBM_MODE_MASK 685 | UVD_CGC_CTRL__WCB_MODE_MASK 686 | UVD_CGC_CTRL__VCPU_MODE_MASK 687 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 688 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 689 690 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE); 691 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 692 | UVD_SUVD_CGC_GATE__SIT_MASK 693 | UVD_SUVD_CGC_GATE__SMP_MASK 694 | UVD_SUVD_CGC_GATE__SCM_MASK 695 | UVD_SUVD_CGC_GATE__SDB_MASK 696 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 697 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 698 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 699 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 700 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 701 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 702 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 703 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 704 | UVD_SUVD_CGC_GATE__ENT_MASK 705 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 706 | UVD_SUVD_CGC_GATE__SITE_MASK 707 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 708 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 709 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 710 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 711 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 712 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data); 713 714 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 715 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 716 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 717 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 718 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 719 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 720 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 721 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 722 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 723 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 724 } 725 726 /** 727 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 728 * 729 * @vinst: VCN instance 730 * @sram_sel: sram select 731 * @indirect: indirectly write sram 732 * 733 * Disable clock gating for VCN block with dpg mode 734 */ 735 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 736 uint8_t sram_sel, 737 uint8_t indirect) 738 { 739 struct amdgpu_device *adev = vinst->adev; 740 int inst_idx = vinst->inst; 741 uint32_t reg_data = 0; 742 743 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 744 return; 745 746 /* enable sw clock gating control */ 747 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 748 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 749 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 750 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | 751 UVD_CGC_CTRL__MPEG2_MODE_MASK | 752 UVD_CGC_CTRL__REGS_MODE_MASK | 753 UVD_CGC_CTRL__RBC_MODE_MASK | 754 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 755 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 756 UVD_CGC_CTRL__IDCT_MODE_MASK | 757 UVD_CGC_CTRL__MPRD_MODE_MASK | 758 UVD_CGC_CTRL__MPC_MODE_MASK | 759 UVD_CGC_CTRL__LBSI_MODE_MASK | 760 UVD_CGC_CTRL__LRBBM_MODE_MASK | 761 UVD_CGC_CTRL__WCB_MODE_MASK | 762 UVD_CGC_CTRL__VCPU_MODE_MASK); 763 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 764 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 765 766 /* turn off clock gating */ 767 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 768 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); 769 770 /* turn on SUVD clock gating */ 771 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 772 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 773 774 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 775 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 776 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 777 } 778 779 /** 780 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating 781 * 782 * @vinst: VCN instance 783 * 784 * Enable clock gating for VCN block 785 */ 786 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 787 { 788 struct amdgpu_device *adev = vinst->adev; 789 int inst_idx = vinst->inst; 790 uint32_t data; 791 int vcn_inst; 792 793 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 794 return; 795 796 vcn_inst = GET_INST(VCN, inst_idx); 797 798 /* enable VCN CGC */ 799 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 800 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 801 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 802 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 803 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 804 805 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 806 data |= (UVD_CGC_CTRL__SYS_MODE_MASK 807 | UVD_CGC_CTRL__MPEG2_MODE_MASK 808 | UVD_CGC_CTRL__REGS_MODE_MASK 809 | UVD_CGC_CTRL__RBC_MODE_MASK 810 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 811 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 812 | UVD_CGC_CTRL__MPC_MODE_MASK 813 | UVD_CGC_CTRL__LBSI_MODE_MASK 814 | UVD_CGC_CTRL__LRBBM_MODE_MASK 815 | UVD_CGC_CTRL__WCB_MODE_MASK 816 | UVD_CGC_CTRL__VCPU_MODE_MASK); 817 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 818 819 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 820 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 822 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 823 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 824 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 825 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 826 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 827 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 828 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 829 } 830 831 /** 832 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode 833 * 834 * @vinst: VCN instance 835 * @indirect: indirectly write sram 836 * 837 * Start VCN block with dpg mode 838 */ 839 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 840 bool indirect) 841 { 842 struct amdgpu_device *adev = vinst->adev; 843 int inst_idx = vinst->inst; 844 volatile struct amdgpu_vcn4_fw_shared *fw_shared = 845 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 846 struct amdgpu_ring *ring; 847 int vcn_inst; 848 uint32_t tmp; 849 850 vcn_inst = GET_INST(VCN, inst_idx); 851 /* disable register anti-hang mechanism */ 852 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 853 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 854 /* enable dynamic power gating mode */ 855 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 856 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 857 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 858 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 859 860 if (indirect) { 861 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d", 862 inst_idx, adev->vcn.inst[inst_idx].aid_id); 863 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 864 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 865 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 866 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, 867 adev->vcn.inst[inst_idx].aid_id, 0, true); 868 } 869 870 /* enable clock gating */ 871 vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect); 872 873 /* enable VCPU clock */ 874 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 875 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 876 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 877 878 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 879 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 880 881 /* disable master interrupt */ 882 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 883 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 884 885 /* setup regUVD_LMI_CTRL */ 886 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 887 UVD_LMI_CTRL__REQ_MODE_MASK | 888 UVD_LMI_CTRL__CRC_RESET_MASK | 889 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 890 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 891 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 892 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 893 0x00100000L); 894 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 895 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 896 897 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 898 VCN, 0, regUVD_MPC_CNTL), 899 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 900 901 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 902 VCN, 0, regUVD_MPC_SET_MUXA0), 903 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 904 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 905 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 906 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 907 908 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 909 VCN, 0, regUVD_MPC_SET_MUXB0), 910 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 911 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 912 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 913 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 914 915 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 916 VCN, 0, regUVD_MPC_SET_MUX), 917 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 918 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 919 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 920 921 vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect); 922 923 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 924 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 925 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 926 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 927 928 /* enable LMI MC and UMC channels */ 929 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 930 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 931 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 932 933 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); 934 935 /* enable master interrupt */ 936 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 937 VCN, 0, regUVD_MASTINT_EN), 938 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 939 940 if (indirect) 941 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 942 943 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 944 945 /* program the RB_BASE for ring buffer */ 946 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 947 lower_32_bits(ring->gpu_addr)); 948 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 949 upper_32_bits(ring->gpu_addr)); 950 951 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 952 ring->ring_size / sizeof(uint32_t)); 953 954 /* resetting ring, fw should not check RB ring */ 955 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 956 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 957 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 958 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 959 960 /* Initialize the ring buffer's read and write pointers */ 961 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 962 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 963 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 964 965 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 966 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 967 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 968 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 969 970 /*resetting done, fw can check RB ring */ 971 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 972 973 return 0; 974 } 975 976 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev) 977 { 978 int i, vcn_inst; 979 struct amdgpu_ring *ring_enc; 980 uint64_t cache_addr; 981 uint64_t rb_enc_addr; 982 uint64_t ctx_addr; 983 uint32_t param, resp, expected; 984 uint32_t offset, cache_size; 985 uint32_t tmp, timeout; 986 987 struct amdgpu_mm_table *table = &adev->virt.mm_table; 988 uint32_t *table_loc; 989 uint32_t table_size; 990 uint32_t size, size_dw; 991 uint32_t init_status; 992 uint32_t enabled_vcn; 993 994 struct mmsch_v4_0_cmd_direct_write 995 direct_wt = { {0} }; 996 struct mmsch_v4_0_cmd_direct_read_modify_write 997 direct_rd_mod_wt = { {0} }; 998 struct mmsch_v4_0_cmd_end end = { {0} }; 999 struct mmsch_v4_0_3_init_header header; 1000 1001 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1002 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1003 1004 direct_wt.cmd_header.command_type = 1005 MMSCH_COMMAND__DIRECT_REG_WRITE; 1006 direct_rd_mod_wt.cmd_header.command_type = 1007 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1008 end.cmd_header.command_type = MMSCH_COMMAND__END; 1009 1010 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1011 vcn_inst = GET_INST(VCN, i); 1012 1013 vcn_v4_0_3_fw_shared_init(adev, vcn_inst); 1014 1015 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 1016 header.version = MMSCH_VERSION; 1017 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 1018 1019 table_loc = (uint32_t *)table->cpu_addr; 1020 table_loc += header.total_size; 1021 1022 table_size = 0; 1023 1024 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 1025 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1026 1027 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1028 1029 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1030 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1031 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1032 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1033 1034 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1035 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1036 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1037 1038 offset = 0; 1039 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1040 regUVD_VCPU_CACHE_OFFSET0), 0); 1041 } else { 1042 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1043 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1044 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1045 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1046 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1047 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1048 offset = cache_size; 1049 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1050 regUVD_VCPU_CACHE_OFFSET0), 1051 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1052 } 1053 1054 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1055 regUVD_VCPU_CACHE_SIZE0), 1056 cache_size); 1057 1058 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 1059 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1060 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1061 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1062 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1063 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1064 regUVD_VCPU_CACHE_OFFSET1), 0); 1065 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1066 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 1067 1068 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 1069 AMDGPU_VCN_STACK_SIZE; 1070 1071 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1072 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1073 1074 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1075 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1076 1077 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1078 regUVD_VCPU_CACHE_OFFSET2), 0); 1079 1080 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1081 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 1082 1083 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 1084 rb_setup = &fw_shared->rb_setup; 1085 1086 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 1087 ring_enc->wptr = 0; 1088 rb_enc_addr = ring_enc->gpu_addr; 1089 1090 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1091 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1092 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1093 rb_setup->rb_size = ring_enc->ring_size / 4; 1094 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1095 1096 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1097 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1098 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1099 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1100 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1101 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1102 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1103 regUVD_VCPU_NONCACHE_SIZE0), 1104 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1105 MMSCH_V4_0_INSERT_END(); 1106 1107 header.vcn0.init_status = 0; 1108 header.vcn0.table_offset = header.total_size; 1109 header.vcn0.table_size = table_size; 1110 header.total_size += table_size; 1111 1112 /* Send init table to mmsch */ 1113 size = sizeof(struct mmsch_v4_0_3_init_header); 1114 table_loc = (uint32_t *)table->cpu_addr; 1115 memcpy((void *)table_loc, &header, size); 1116 1117 ctx_addr = table->gpu_addr; 1118 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1119 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1120 1121 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 1122 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1123 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1124 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 1125 1126 size = header.total_size; 1127 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 1128 1129 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 1130 1131 param = 0x00000001; 1132 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 1133 tmp = 0; 1134 timeout = 1000; 1135 resp = 0; 1136 expected = MMSCH_VF_MAILBOX_RESP__OK; 1137 while (resp != expected) { 1138 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 1139 if (resp != 0) 1140 break; 1141 1142 udelay(10); 1143 tmp = tmp + 10; 1144 if (tmp >= timeout) { 1145 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1146 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1147 "(expected=0x%08x, readback=0x%08x)\n", 1148 tmp, expected, resp); 1149 return -EBUSY; 1150 } 1151 } 1152 1153 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1154 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status; 1155 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1156 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 1157 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1158 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1159 } 1160 } 1161 1162 return 0; 1163 } 1164 1165 /** 1166 * vcn_v4_0_3_start - VCN start 1167 * 1168 * @vinst: VCN instance 1169 * 1170 * Start VCN block 1171 */ 1172 static int vcn_v4_0_3_start(struct amdgpu_vcn_inst *vinst) 1173 { 1174 struct amdgpu_device *adev = vinst->adev; 1175 int i = vinst->inst; 1176 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1177 struct amdgpu_ring *ring; 1178 int j, k, r, vcn_inst; 1179 uint32_t tmp; 1180 1181 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1182 return vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1183 1184 vcn_inst = GET_INST(VCN, i); 1185 /* set VCN status busy */ 1186 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | 1187 UVD_STATUS__UVD_BUSY; 1188 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 1189 1190 /* SW clock gating */ 1191 vcn_v4_0_3_disable_clock_gating(vinst); 1192 1193 /* enable VCPU clock */ 1194 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1195 UVD_VCPU_CNTL__CLK_EN_MASK, 1196 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1197 1198 /* disable master interrupt */ 1199 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 1200 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1201 1202 /* enable LMI MC and UMC channels */ 1203 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 1204 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1205 1206 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1207 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1208 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1209 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1210 1211 /* setup regUVD_LMI_CTRL */ 1212 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 1213 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, 1214 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1215 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1216 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1217 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1218 1219 /* setup regUVD_MPC_CNTL */ 1220 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); 1221 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1222 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1223 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); 1224 1225 /* setup UVD_MPC_SET_MUXA0 */ 1226 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, 1227 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1228 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1229 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1230 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1231 1232 /* setup UVD_MPC_SET_MUXB0 */ 1233 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, 1234 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1235 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1236 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1237 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1238 1239 /* setup UVD_MPC_SET_MUX */ 1240 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX, 1241 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1242 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1243 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1244 1245 vcn_v4_0_3_mc_resume(vinst); 1246 1247 /* VCN global tiling registers */ 1248 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG, 1249 adev->gfx.config.gb_addr_config); 1250 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 1251 adev->gfx.config.gb_addr_config); 1252 1253 /* unblock VCPU register access */ 1254 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1255 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1256 1257 /* release VCPU reset to boot */ 1258 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1259 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1260 1261 for (j = 0; j < 10; ++j) { 1262 uint32_t status; 1263 1264 for (k = 0; k < 100; ++k) { 1265 status = RREG32_SOC15(VCN, vcn_inst, 1266 regUVD_STATUS); 1267 if (status & 2) 1268 break; 1269 mdelay(10); 1270 } 1271 r = 0; 1272 if (status & 2) 1273 break; 1274 1275 DRM_DEV_ERROR(adev->dev, 1276 "VCN decode not responding, trying to reset the VCPU!!!\n"); 1277 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1278 regUVD_VCPU_CNTL), 1279 UVD_VCPU_CNTL__BLK_RST_MASK, 1280 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1281 mdelay(10); 1282 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1283 regUVD_VCPU_CNTL), 1284 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); 1285 1286 mdelay(10); 1287 r = -1; 1288 } 1289 1290 if (r) { 1291 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n"); 1292 return r; 1293 } 1294 1295 /* enable master interrupt */ 1296 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1297 UVD_MASTINT_EN__VCPU_EN_MASK, 1298 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1299 1300 /* clear the busy bit of VCN_STATUS */ 1301 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1302 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1303 1304 ring = &adev->vcn.inst[i].ring_enc[0]; 1305 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1306 1307 /* program the RB_BASE for ring buffer */ 1308 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 1309 lower_32_bits(ring->gpu_addr)); 1310 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 1311 upper_32_bits(ring->gpu_addr)); 1312 1313 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 1314 ring->ring_size / sizeof(uint32_t)); 1315 1316 /* resetting ring, fw should not check RB ring */ 1317 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1318 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 1319 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1320 1321 /* Initialize the ring buffer's read and write pointers */ 1322 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1323 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1324 1325 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1326 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 1327 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1328 1329 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1330 fw_shared->sq.queue_mode &= 1331 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF)); 1332 1333 return 0; 1334 } 1335 1336 /** 1337 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode 1338 * 1339 * @vinst: VCN instance 1340 * 1341 * Stop VCN block with dpg mode 1342 */ 1343 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1344 { 1345 struct amdgpu_device *adev = vinst->adev; 1346 int inst_idx = vinst->inst; 1347 uint32_t tmp; 1348 int vcn_inst; 1349 1350 vcn_inst = GET_INST(VCN, inst_idx); 1351 1352 /* Wait for power status to be 1 */ 1353 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1354 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1355 1356 /* wait for read ptr to be equal to write ptr */ 1357 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1358 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1359 1360 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1361 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1362 1363 /* disable dynamic power gating mode */ 1364 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1365 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1366 return 0; 1367 } 1368 1369 /** 1370 * vcn_v4_0_3_stop - VCN stop 1371 * 1372 * @vinst: VCN instance 1373 * 1374 * Stop VCN block 1375 */ 1376 static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst) 1377 { 1378 struct amdgpu_device *adev = vinst->adev; 1379 int i = vinst->inst; 1380 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1381 int r = 0, vcn_inst; 1382 uint32_t tmp; 1383 1384 vcn_inst = GET_INST(VCN, i); 1385 1386 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1387 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1388 1389 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1390 vcn_v4_0_3_stop_dpg_mode(vinst); 1391 goto Done; 1392 } 1393 1394 /* wait for vcn idle */ 1395 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, 1396 UVD_STATUS__IDLE, 0x7); 1397 if (r) 1398 goto Done; 1399 1400 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1401 UVD_LMI_STATUS__READ_CLEAN_MASK | 1402 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1403 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1404 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1405 tmp); 1406 if (r) 1407 goto Done; 1408 1409 /* stall UMC channel */ 1410 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1411 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1412 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1413 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1414 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1415 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1416 tmp); 1417 if (r) 1418 goto Done; 1419 1420 /* Unblock VCPU Register access */ 1421 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1422 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1423 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1424 1425 /* release VCPU reset to boot */ 1426 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1427 UVD_VCPU_CNTL__BLK_RST_MASK, 1428 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1429 1430 /* disable VCPU clock */ 1431 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1432 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1433 1434 /* reset LMI UMC/LMI/VCPU */ 1435 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1436 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1437 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1438 1439 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1440 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1441 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1442 1443 /* clear VCN status */ 1444 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1445 1446 /* apply HW clock gating */ 1447 vcn_v4_0_3_enable_clock_gating(vinst); 1448 1449 Done: 1450 return 0; 1451 } 1452 1453 /** 1454 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode 1455 * 1456 * @vinst: VCN instance 1457 * @new_state: pause state 1458 * 1459 * Pause dpg mode for VCN block 1460 */ 1461 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1462 struct dpg_pause_state *new_state) 1463 { 1464 1465 return 0; 1466 } 1467 1468 /** 1469 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer 1470 * 1471 * @ring: amdgpu_ring pointer 1472 * 1473 * Returns the current hardware unified read pointer 1474 */ 1475 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring) 1476 { 1477 struct amdgpu_device *adev = ring->adev; 1478 1479 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1480 DRM_ERROR("wrong ring id is identified in %s", __func__); 1481 1482 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1483 } 1484 1485 /** 1486 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer 1487 * 1488 * @ring: amdgpu_ring pointer 1489 * 1490 * Returns the current hardware unified write pointer 1491 */ 1492 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring) 1493 { 1494 struct amdgpu_device *adev = ring->adev; 1495 1496 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1497 DRM_ERROR("wrong ring id is identified in %s", __func__); 1498 1499 if (ring->use_doorbell) 1500 return *ring->wptr_cpu_addr; 1501 else 1502 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), 1503 regUVD_RB_WPTR); 1504 } 1505 1506 void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1507 uint32_t val, uint32_t mask) 1508 { 1509 /* Use normalized offsets when required */ 1510 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1511 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1512 1513 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1514 amdgpu_ring_write(ring, reg << 2); 1515 amdgpu_ring_write(ring, mask); 1516 amdgpu_ring_write(ring, val); 1517 } 1518 1519 void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 1520 uint32_t val) 1521 { 1522 /* Use normalized offsets when required */ 1523 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1524 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1525 1526 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1527 amdgpu_ring_write(ring, reg << 2); 1528 amdgpu_ring_write(ring, val); 1529 } 1530 1531 void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1532 unsigned int vmid, uint64_t pd_addr) 1533 { 1534 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1535 1536 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1537 1538 /* wait for reg writes */ 1539 vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1540 vmid * hub->ctx_addr_distance, 1541 lower_32_bits(pd_addr), 0xffffffff); 1542 } 1543 1544 void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1545 { 1546 /* VCN engine access for HDP flush doesn't work when RRMT is enabled. 1547 * This is a workaround to avoid any HDP flush through VCN ring. 1548 */ 1549 } 1550 1551 /** 1552 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer 1553 * 1554 * @ring: amdgpu_ring pointer 1555 * 1556 * Commits the enc write pointer to the hardware 1557 */ 1558 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) 1559 { 1560 struct amdgpu_device *adev = ring->adev; 1561 1562 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1563 DRM_ERROR("wrong ring id is identified in %s", __func__); 1564 1565 if (ring->use_doorbell) { 1566 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1567 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1568 } else { 1569 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1570 lower_32_bits(ring->wptr)); 1571 } 1572 } 1573 1574 static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) 1575 { 1576 int r = 0; 1577 int vcn_inst; 1578 struct amdgpu_device *adev = ring->adev; 1579 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1580 1581 if (amdgpu_sriov_vf(ring->adev)) 1582 return -EOPNOTSUPP; 1583 1584 if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) 1585 return -EOPNOTSUPP; 1586 1587 vcn_inst = GET_INST(VCN, ring->me); 1588 r = amdgpu_dpm_reset_vcn(adev, 1 << vcn_inst); 1589 1590 if (r) { 1591 DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); 1592 return r; 1593 } 1594 1595 /* This flag is not set for VF, assumed to be disabled always */ 1596 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 1597 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 1598 vcn_v4_0_3_hw_init_inst(vinst); 1599 vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram); 1600 r = amdgpu_ring_test_helper(ring); 1601 1602 return r; 1603 } 1604 1605 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { 1606 .type = AMDGPU_RING_TYPE_VCN_ENC, 1607 .align_mask = 0x3f, 1608 .nop = VCN_ENC_CMD_NO_OP, 1609 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, 1610 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, 1611 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, 1612 .emit_frame_size = 1613 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1614 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1615 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1616 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1617 1, /* vcn_v2_0_enc_ring_insert_end */ 1618 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1619 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1620 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1621 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1622 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1623 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1624 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1625 .insert_nop = amdgpu_ring_insert_nop, 1626 .insert_end = vcn_v2_0_enc_ring_insert_end, 1627 .pad_ib = amdgpu_ring_generic_pad_ib, 1628 .begin_use = amdgpu_vcn_ring_begin_use, 1629 .end_use = amdgpu_vcn_ring_end_use, 1630 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1631 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1632 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1633 .reset = vcn_v4_0_3_ring_reset, 1634 }; 1635 1636 /** 1637 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions 1638 * 1639 * @adev: amdgpu_device pointer 1640 * 1641 * Set unified ring functions 1642 */ 1643 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev) 1644 { 1645 int i, vcn_inst; 1646 1647 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1648 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs; 1649 adev->vcn.inst[i].ring_enc[0].me = i; 1650 vcn_inst = GET_INST(VCN, i); 1651 adev->vcn.inst[i].aid_id = 1652 vcn_inst / adev->vcn.num_inst_per_aid; 1653 } 1654 } 1655 1656 /** 1657 * vcn_v4_0_3_is_idle - check VCN block is idle 1658 * 1659 * @ip_block: Pointer to the amdgpu_ip_block structure 1660 * 1661 * Check whether VCN block is idle 1662 */ 1663 static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block) 1664 { 1665 struct amdgpu_device *adev = ip_block->adev; 1666 int i, ret = 1; 1667 1668 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1669 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == 1670 UVD_STATUS__IDLE); 1671 } 1672 1673 return ret; 1674 } 1675 1676 /** 1677 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle 1678 * 1679 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1680 * 1681 * Wait for VCN block idle 1682 */ 1683 static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 1684 { 1685 struct amdgpu_device *adev = ip_block->adev; 1686 int i, ret = 0; 1687 1688 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1689 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, 1690 UVD_STATUS__IDLE, UVD_STATUS__IDLE); 1691 if (ret) 1692 return ret; 1693 } 1694 1695 return ret; 1696 } 1697 1698 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state 1699 * 1700 * @ip_block: amdgpu_ip_block pointer 1701 * @state: clock gating state 1702 * 1703 * Set VCN block clockgating state 1704 */ 1705 static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1706 enum amd_clockgating_state state) 1707 { 1708 struct amdgpu_device *adev = ip_block->adev; 1709 bool enable = state == AMD_CG_STATE_GATE; 1710 int i; 1711 1712 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1713 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1714 1715 if (enable) { 1716 if (RREG32_SOC15(VCN, GET_INST(VCN, i), 1717 regUVD_STATUS) != UVD_STATUS__IDLE) 1718 return -EBUSY; 1719 vcn_v4_0_3_enable_clock_gating(vinst); 1720 } else { 1721 vcn_v4_0_3_disable_clock_gating(vinst); 1722 } 1723 } 1724 return 0; 1725 } 1726 1727 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 1728 enum amd_powergating_state state) 1729 { 1730 struct amdgpu_device *adev = vinst->adev; 1731 int ret = 0; 1732 1733 /* for SRIOV, guest should not control VCN Power-gating 1734 * MMSCH FW should control Power-gating and clock-gating 1735 * guest should avoid touching CGC and PG 1736 */ 1737 if (amdgpu_sriov_vf(adev)) { 1738 vinst->cur_state = AMD_PG_STATE_UNGATE; 1739 return 0; 1740 } 1741 1742 if (state == vinst->cur_state) 1743 return 0; 1744 1745 if (state == AMD_PG_STATE_GATE) 1746 ret = vcn_v4_0_3_stop(vinst); 1747 else 1748 ret = vcn_v4_0_3_start(vinst); 1749 1750 if (!ret) 1751 vinst->cur_state = state; 1752 1753 return ret; 1754 } 1755 1756 /** 1757 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state 1758 * 1759 * @adev: amdgpu_device pointer 1760 * @source: interrupt sources 1761 * @type: interrupt types 1762 * @state: interrupt states 1763 * 1764 * Set VCN block interrupt state 1765 */ 1766 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1767 struct amdgpu_irq_src *source, 1768 unsigned int type, 1769 enum amdgpu_interrupt_state state) 1770 { 1771 return 0; 1772 } 1773 1774 /** 1775 * vcn_v4_0_3_process_interrupt - process VCN block interrupt 1776 * 1777 * @adev: amdgpu_device pointer 1778 * @source: interrupt sources 1779 * @entry: interrupt entry from clients and sources 1780 * 1781 * Process VCN block interrupt 1782 */ 1783 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1784 struct amdgpu_irq_src *source, 1785 struct amdgpu_iv_entry *entry) 1786 { 1787 uint32_t i, inst; 1788 1789 i = node_id_to_phys_map[entry->node_id]; 1790 1791 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1792 1793 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1794 if (adev->vcn.inst[inst].aid_id == i) 1795 break; 1796 1797 if (inst >= adev->vcn.num_vcn_inst) { 1798 dev_WARN_ONCE(adev->dev, 1, 1799 "Interrupt received for unknown VCN instance %d", 1800 entry->node_id); 1801 return 0; 1802 } 1803 1804 switch (entry->src_id) { 1805 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1806 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1807 break; 1808 default: 1809 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1810 entry->src_id, entry->src_data[0]); 1811 break; 1812 } 1813 1814 return 0; 1815 } 1816 1817 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 1818 .set = vcn_v4_0_3_set_interrupt_state, 1819 .process = vcn_v4_0_3_process_interrupt, 1820 }; 1821 1822 /** 1823 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions 1824 * 1825 * @adev: amdgpu_device pointer 1826 * 1827 * Set VCN block interrupt irq functions 1828 */ 1829 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1830 { 1831 int i; 1832 1833 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1834 adev->vcn.inst->irq.num_types++; 1835 } 1836 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 1837 } 1838 1839 static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1840 { 1841 struct amdgpu_device *adev = ip_block->adev; 1842 int i, j; 1843 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 1844 uint32_t inst_off, is_powered; 1845 1846 if (!adev->vcn.ip_dump) 1847 return; 1848 1849 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1850 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1851 if (adev->vcn.harvest_config & (1 << i)) { 1852 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1853 continue; 1854 } 1855 1856 inst_off = i * reg_count; 1857 is_powered = (adev->vcn.ip_dump[inst_off] & 1858 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1859 1860 if (is_powered) { 1861 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1862 for (j = 0; j < reg_count; j++) 1863 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name, 1864 adev->vcn.ip_dump[inst_off + j]); 1865 } else { 1866 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1867 } 1868 } 1869 } 1870 1871 static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block) 1872 { 1873 struct amdgpu_device *adev = ip_block->adev; 1874 int i, j; 1875 bool is_powered; 1876 uint32_t inst_off, inst_id; 1877 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 1878 1879 if (!adev->vcn.ip_dump) 1880 return; 1881 1882 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1883 if (adev->vcn.harvest_config & (1 << i)) 1884 continue; 1885 1886 inst_id = GET_INST(VCN, i); 1887 inst_off = i * reg_count; 1888 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1889 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS); 1890 is_powered = (adev->vcn.ip_dump[inst_off] & 1891 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1892 1893 if (is_powered) 1894 for (j = 1; j < reg_count; j++) 1895 adev->vcn.ip_dump[inst_off + j] = 1896 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j], 1897 inst_id)); 1898 } 1899 } 1900 1901 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 1902 .name = "vcn_v4_0_3", 1903 .early_init = vcn_v4_0_3_early_init, 1904 .sw_init = vcn_v4_0_3_sw_init, 1905 .sw_fini = vcn_v4_0_3_sw_fini, 1906 .hw_init = vcn_v4_0_3_hw_init, 1907 .hw_fini = vcn_v4_0_3_hw_fini, 1908 .suspend = vcn_v4_0_3_suspend, 1909 .resume = vcn_v4_0_3_resume, 1910 .is_idle = vcn_v4_0_3_is_idle, 1911 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 1912 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 1913 .set_powergating_state = vcn_set_powergating_state, 1914 .dump_ip_state = vcn_v4_0_3_dump_ip_state, 1915 .print_ip_state = vcn_v4_0_3_print_ip_state, 1916 }; 1917 1918 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { 1919 .type = AMD_IP_BLOCK_TYPE_VCN, 1920 .major = 4, 1921 .minor = 0, 1922 .rev = 3, 1923 .funcs = &vcn_v4_0_3_ip_funcs, 1924 }; 1925 1926 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = { 1927 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD), 1928 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"}, 1929 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV), 1930 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"}, 1931 }; 1932 1933 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1934 uint32_t vcn_inst, 1935 void *ras_err_status) 1936 { 1937 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1938 1939 /* vcn v4_0_3 only support query uncorrectable errors */ 1940 amdgpu_ras_inst_query_ras_error_count(adev, 1941 vcn_v4_0_3_ue_reg_list, 1942 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1943 NULL, 0, GET_INST(VCN, vcn_inst), 1944 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1945 &err_data->ue_count); 1946 } 1947 1948 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1949 void *ras_err_status) 1950 { 1951 uint32_t i; 1952 1953 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1954 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1955 return; 1956 } 1957 1958 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1959 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1960 } 1961 1962 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1963 uint32_t vcn_inst) 1964 { 1965 amdgpu_ras_inst_reset_ras_error_count(adev, 1966 vcn_v4_0_3_ue_reg_list, 1967 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1968 GET_INST(VCN, vcn_inst)); 1969 } 1970 1971 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1972 { 1973 uint32_t i; 1974 1975 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1976 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1977 return; 1978 } 1979 1980 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1981 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 1982 } 1983 1984 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 1985 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 1986 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 1987 }; 1988 1989 static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1990 enum aca_smu_type type, void *data) 1991 { 1992 struct aca_bank_info info; 1993 u64 misc0; 1994 int ret; 1995 1996 ret = aca_bank_info_decode(bank, &info); 1997 if (ret) 1998 return ret; 1999 2000 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2001 switch (type) { 2002 case ACA_SMU_TYPE_UE: 2003 bank->aca_err_type = ACA_ERROR_TYPE_UE; 2004 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2005 1ULL); 2006 break; 2007 case ACA_SMU_TYPE_CE: 2008 bank->aca_err_type = ACA_ERROR_TYPE_CE; 2009 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 2010 ACA_REG__MISC0__ERRCNT(misc0)); 2011 break; 2012 default: 2013 return -EINVAL; 2014 } 2015 2016 return ret; 2017 } 2018 2019 /* reference to smu driver if header file */ 2020 static int vcn_v4_0_3_err_codes[] = { 2021 14, 15, /* VCN */ 2022 }; 2023 2024 static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2025 enum aca_smu_type type, void *data) 2026 { 2027 u32 instlo; 2028 2029 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2030 instlo &= GENMASK(31, 1); 2031 2032 if (instlo != mmSMNAID_AID0_MCA_SMU) 2033 return false; 2034 2035 if (aca_bank_check_error_codes(handle->adev, bank, 2036 vcn_v4_0_3_err_codes, 2037 ARRAY_SIZE(vcn_v4_0_3_err_codes))) 2038 return false; 2039 2040 return true; 2041 } 2042 2043 static const struct aca_bank_ops vcn_v4_0_3_aca_bank_ops = { 2044 .aca_bank_parser = vcn_v4_0_3_aca_bank_parser, 2045 .aca_bank_is_valid = vcn_v4_0_3_aca_bank_is_valid, 2046 }; 2047 2048 static const struct aca_info vcn_v4_0_3_aca_info = { 2049 .hwip = ACA_HWIP_TYPE_SMU, 2050 .mask = ACA_ERROR_UE_MASK, 2051 .bank_ops = &vcn_v4_0_3_aca_bank_ops, 2052 }; 2053 2054 static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2055 { 2056 int r; 2057 2058 r = amdgpu_ras_block_late_init(adev, ras_block); 2059 if (r) 2060 return r; 2061 2062 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN, 2063 &vcn_v4_0_3_aca_info, NULL); 2064 if (r) 2065 goto late_fini; 2066 2067 return 0; 2068 2069 late_fini: 2070 amdgpu_ras_block_late_fini(adev, ras_block); 2071 2072 return r; 2073 } 2074 2075 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = { 2076 .ras_block = { 2077 .hw_ops = &vcn_v4_0_3_ras_hw_ops, 2078 .ras_late_init = vcn_v4_0_3_ras_late_init, 2079 }, 2080 }; 2081 2082 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 2083 { 2084 adev->vcn.ras = &vcn_v4_0_3_ras; 2085 } 2086 2087 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 2088 int inst_idx, bool indirect) 2089 { 2090 uint32_t tmp; 2091 2092 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 2093 return; 2094 2095 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 2096 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 2097 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 2098 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 2099 WREG32_SOC15_DPG_MODE(inst_idx, 2100 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 2101 tmp, 0, indirect); 2102 2103 tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK; 2104 WREG32_SOC15_DPG_MODE(inst_idx, 2105 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2), 2106 tmp, 0, indirect); 2107 2108 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 2109 WREG32_SOC15_DPG_MODE(inst_idx, 2110 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 2111 tmp, 0, indirect); 2112 } 2113