1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_hw_ip.h" 33 #include "vcn_v2_0.h" 34 #include "mmsch_v4_0_3.h" 35 36 #include "vcn/vcn_4_0_3_offset.h" 37 #include "vcn/vcn_4_0_3_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 41 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 42 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 43 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 44 45 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 46 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 47 48 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { 49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 82 }; 83 84 #define NORMALIZE_VCN_REG_OFFSET(offset) \ 85 (offset & 0x1FFFF) 86 87 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); 88 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); 89 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 90 static int vcn_v4_0_3_set_powergating_state(void *handle, 91 enum amd_powergating_state state); 92 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, 93 int inst_idx, struct dpg_pause_state *new_state); 94 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring); 95 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 96 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 97 int inst_idx, bool indirect); 98 /** 99 * vcn_v4_0_3_early_init - set function pointers 100 * 101 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 102 * 103 * Set ring and irq function pointers 104 */ 105 static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 106 { 107 struct amdgpu_device *adev = ip_block->adev; 108 109 /* re-use enc ring as unified ring */ 110 adev->vcn.num_enc_rings = 1; 111 112 vcn_v4_0_3_set_unified_ring_funcs(adev); 113 vcn_v4_0_3_set_irq_funcs(adev); 114 vcn_v4_0_3_set_ras_funcs(adev); 115 116 return amdgpu_vcn_early_init(adev); 117 } 118 119 /** 120 * vcn_v4_0_3_sw_init - sw init for VCN block 121 * 122 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 123 * 124 * Load firmware and sw initialization 125 */ 126 static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 127 { 128 struct amdgpu_device *adev = ip_block->adev; 129 struct amdgpu_ring *ring; 130 int i, r, vcn_inst; 131 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 132 uint32_t *ptr; 133 134 r = amdgpu_vcn_sw_init(adev); 135 if (r) 136 return r; 137 138 amdgpu_vcn_setup_ucode(adev); 139 140 r = amdgpu_vcn_resume(adev); 141 if (r) 142 return r; 143 144 /* VCN DEC TRAP */ 145 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 146 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 147 if (r) 148 return r; 149 150 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 151 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 152 153 vcn_inst = GET_INST(VCN, i); 154 155 ring = &adev->vcn.inst[i].ring_enc[0]; 156 ring->use_doorbell = true; 157 158 if (!amdgpu_sriov_vf(adev)) 159 ring->doorbell_index = 160 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 161 9 * vcn_inst; 162 else 163 ring->doorbell_index = 164 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 165 32 * vcn_inst; 166 167 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 168 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 169 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 170 AMDGPU_RING_PRIO_DEFAULT, 171 &adev->vcn.inst[i].sched_score); 172 if (r) 173 return r; 174 175 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 176 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 177 fw_shared->sq.is_enabled = true; 178 179 if (amdgpu_vcnfw_log) 180 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 181 } 182 183 if (amdgpu_sriov_vf(adev)) { 184 r = amdgpu_virt_alloc_mm_table(adev); 185 if (r) 186 return r; 187 } 188 189 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 190 adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; 191 192 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 193 r = amdgpu_vcn_ras_sw_init(adev); 194 if (r) { 195 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 196 return r; 197 } 198 } 199 200 /* Allocate memory for VCN IP Dump buffer */ 201 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 202 if (!ptr) { 203 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 204 adev->vcn.ip_dump = NULL; 205 } else { 206 adev->vcn.ip_dump = ptr; 207 } 208 209 return 0; 210 } 211 212 /** 213 * vcn_v4_0_3_sw_fini - sw fini for VCN block 214 * 215 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 216 * 217 * VCN suspend and free up sw allocation 218 */ 219 static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 220 { 221 struct amdgpu_device *adev = ip_block->adev; 222 int i, r, idx; 223 224 if (drm_dev_enter(&adev->ddev, &idx)) { 225 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 226 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 227 228 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 229 fw_shared->present_flag_0 = 0; 230 fw_shared->sq.is_enabled = cpu_to_le32(false); 231 } 232 drm_dev_exit(idx); 233 } 234 235 if (amdgpu_sriov_vf(adev)) 236 amdgpu_virt_free_mm_table(adev); 237 238 r = amdgpu_vcn_suspend(adev); 239 if (r) 240 return r; 241 242 r = amdgpu_vcn_sw_fini(adev); 243 244 kfree(adev->vcn.ip_dump); 245 246 return r; 247 } 248 249 /** 250 * vcn_v4_0_3_hw_init - start and test VCN block 251 * 252 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 253 * 254 * Initialize the hardware, boot up the VCPU and do some testing 255 */ 256 static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 257 { 258 struct amdgpu_device *adev = ip_block->adev; 259 struct amdgpu_ring *ring; 260 int i, r, vcn_inst; 261 262 if (amdgpu_sriov_vf(adev)) { 263 r = vcn_v4_0_3_start_sriov(adev); 264 if (r) 265 return r; 266 267 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 268 ring = &adev->vcn.inst[i].ring_enc[0]; 269 ring->wptr = 0; 270 ring->wptr_old = 0; 271 vcn_v4_0_3_unified_ring_set_wptr(ring); 272 ring->sched.ready = true; 273 } 274 } else { 275 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 276 vcn_inst = GET_INST(VCN, i); 277 ring = &adev->vcn.inst[i].ring_enc[0]; 278 279 if (ring->use_doorbell) { 280 adev->nbio.funcs->vcn_doorbell_range( 281 adev, ring->use_doorbell, 282 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 283 9 * vcn_inst, 284 adev->vcn.inst[i].aid_id); 285 286 WREG32_SOC15( 287 VCN, GET_INST(VCN, ring->me), 288 regVCN_RB1_DB_CTRL, 289 ring->doorbell_index 290 << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 291 VCN_RB1_DB_CTRL__EN_MASK); 292 293 /* Read DB_CTRL to flush the write DB_CTRL command. */ 294 RREG32_SOC15( 295 VCN, GET_INST(VCN, ring->me), 296 regVCN_RB1_DB_CTRL); 297 } 298 299 r = amdgpu_ring_test_helper(ring); 300 if (r) 301 return r; 302 } 303 } 304 305 return r; 306 } 307 308 /** 309 * vcn_v4_0_3_hw_fini - stop the hardware block 310 * 311 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 312 * 313 * Stop the VCN block, mark ring as not ready any more 314 */ 315 static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 316 { 317 struct amdgpu_device *adev = ip_block->adev; 318 319 cancel_delayed_work_sync(&adev->vcn.idle_work); 320 321 if (adev->vcn.cur_state != AMD_PG_STATE_GATE) 322 vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); 323 324 return 0; 325 } 326 327 /** 328 * vcn_v4_0_3_suspend - suspend VCN block 329 * 330 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 331 * 332 * HW fini and suspend VCN block 333 */ 334 static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 335 { 336 int r; 337 338 r = vcn_v4_0_3_hw_fini(ip_block); 339 if (r) 340 return r; 341 342 r = amdgpu_vcn_suspend(ip_block->adev); 343 344 return r; 345 } 346 347 /** 348 * vcn_v4_0_3_resume - resume VCN block 349 * 350 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 351 * 352 * Resume firmware and hw init VCN block 353 */ 354 static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 355 { 356 int r; 357 358 r = amdgpu_vcn_resume(ip_block->adev); 359 if (r) 360 return r; 361 362 r = vcn_v4_0_3_hw_init(ip_block); 363 364 return r; 365 } 366 367 /** 368 * vcn_v4_0_3_mc_resume - memory controller programming 369 * 370 * @adev: amdgpu_device pointer 371 * @inst_idx: instance number 372 * 373 * Let the VCN memory controller know it's offsets 374 */ 375 static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx) 376 { 377 uint32_t offset, size, vcn_inst; 378 const struct common_firmware_header *hdr; 379 380 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data; 381 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 382 383 vcn_inst = GET_INST(VCN, inst_idx); 384 /* cache window 0: fw */ 385 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 386 WREG32_SOC15( 387 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 388 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 389 .tmr_mc_addr_lo)); 390 WREG32_SOC15( 391 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 392 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 393 .tmr_mc_addr_hi)); 394 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 395 offset = 0; 396 } else { 397 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 398 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 399 WREG32_SOC15(VCN, vcn_inst, 400 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 401 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 402 offset = size; 403 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 404 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 405 } 406 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 407 408 /* cache window 1: stack */ 409 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 410 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 411 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 412 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 413 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 414 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, 415 AMDGPU_VCN_STACK_SIZE); 416 417 /* cache window 2: context */ 418 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 419 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 420 AMDGPU_VCN_STACK_SIZE)); 421 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 422 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 423 AMDGPU_VCN_STACK_SIZE)); 424 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 425 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, 426 AMDGPU_VCN_CONTEXT_SIZE); 427 428 /* non-cache window */ 429 WREG32_SOC15( 430 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 431 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 432 WREG32_SOC15( 433 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 434 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 435 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 436 WREG32_SOC15( 437 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 438 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 439 } 440 441 /** 442 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode 443 * 444 * @adev: amdgpu_device pointer 445 * @inst_idx: instance number index 446 * @indirect: indirectly write sram 447 * 448 * Let the VCN memory controller know it's offsets with dpg mode 449 */ 450 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 451 { 452 uint32_t offset, size; 453 const struct common_firmware_header *hdr; 454 455 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data; 456 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 457 458 /* cache window 0: fw */ 459 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 460 if (!indirect) { 461 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 462 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 463 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 464 inst_idx].tmr_mc_addr_lo), 0, indirect); 465 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 466 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 467 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 468 inst_idx].tmr_mc_addr_hi), 0, indirect); 469 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 470 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 471 } else { 472 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 473 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 474 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 475 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 477 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 478 } 479 offset = 0; 480 } else { 481 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 482 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 483 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 484 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 485 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 486 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 487 offset = size; 488 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 489 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 490 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 491 } 492 493 if (!indirect) 494 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 495 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 496 else 497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 498 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 499 500 /* cache window 1: stack */ 501 if (!indirect) { 502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 503 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 504 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 506 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 507 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 510 } else { 511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 512 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 517 } 518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 519 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 520 521 /* cache window 2: context */ 522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 523 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 524 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 525 AMDGPU_VCN_STACK_SIZE), 0, indirect); 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 528 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 529 AMDGPU_VCN_STACK_SIZE), 0, indirect); 530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 531 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 533 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 534 535 /* non-cache window */ 536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 537 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 538 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 540 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 541 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 545 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 546 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 547 548 /* VCN global tiling registers */ 549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 550 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 553 } 554 555 /** 556 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating 557 * 558 * @adev: amdgpu_device pointer 559 * @inst_idx: instance number 560 * 561 * Disable clock gating for VCN block 562 */ 563 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 564 { 565 uint32_t data; 566 int vcn_inst; 567 568 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 569 return; 570 571 vcn_inst = GET_INST(VCN, inst_idx); 572 573 /* VCN disable CGC */ 574 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 575 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 576 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 577 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 578 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 579 580 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); 581 data &= ~(UVD_CGC_GATE__SYS_MASK 582 | UVD_CGC_GATE__MPEG2_MASK 583 | UVD_CGC_GATE__REGS_MASK 584 | UVD_CGC_GATE__RBC_MASK 585 | UVD_CGC_GATE__LMI_MC_MASK 586 | UVD_CGC_GATE__LMI_UMC_MASK 587 | UVD_CGC_GATE__MPC_MASK 588 | UVD_CGC_GATE__LBSI_MASK 589 | UVD_CGC_GATE__LRBBM_MASK 590 | UVD_CGC_GATE__WCB_MASK 591 | UVD_CGC_GATE__VCPU_MASK 592 | UVD_CGC_GATE__MMSCH_MASK); 593 594 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); 595 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 596 597 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 598 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK 599 | UVD_CGC_CTRL__MPEG2_MODE_MASK 600 | UVD_CGC_CTRL__REGS_MODE_MASK 601 | UVD_CGC_CTRL__RBC_MODE_MASK 602 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 603 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 604 | UVD_CGC_CTRL__MPC_MODE_MASK 605 | UVD_CGC_CTRL__LBSI_MODE_MASK 606 | UVD_CGC_CTRL__LRBBM_MODE_MASK 607 | UVD_CGC_CTRL__WCB_MODE_MASK 608 | UVD_CGC_CTRL__VCPU_MODE_MASK 609 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 610 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 611 612 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE); 613 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 614 | UVD_SUVD_CGC_GATE__SIT_MASK 615 | UVD_SUVD_CGC_GATE__SMP_MASK 616 | UVD_SUVD_CGC_GATE__SCM_MASK 617 | UVD_SUVD_CGC_GATE__SDB_MASK 618 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 619 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 620 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 621 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 622 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 623 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 624 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 625 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 626 | UVD_SUVD_CGC_GATE__ENT_MASK 627 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 628 | UVD_SUVD_CGC_GATE__SITE_MASK 629 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 630 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 631 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 632 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 633 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 634 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data); 635 636 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 637 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 638 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 639 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 640 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 641 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 642 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 643 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 644 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 645 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 646 } 647 648 /** 649 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 650 * 651 * @adev: amdgpu_device pointer 652 * @sram_sel: sram select 653 * @inst_idx: instance number index 654 * @indirect: indirectly write sram 655 * 656 * Disable clock gating for VCN block with dpg mode 657 */ 658 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 659 int inst_idx, uint8_t indirect) 660 { 661 uint32_t reg_data = 0; 662 663 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 664 return; 665 666 /* enable sw clock gating control */ 667 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 668 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 669 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 670 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | 671 UVD_CGC_CTRL__MPEG2_MODE_MASK | 672 UVD_CGC_CTRL__REGS_MODE_MASK | 673 UVD_CGC_CTRL__RBC_MODE_MASK | 674 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 675 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 676 UVD_CGC_CTRL__IDCT_MODE_MASK | 677 UVD_CGC_CTRL__MPRD_MODE_MASK | 678 UVD_CGC_CTRL__MPC_MODE_MASK | 679 UVD_CGC_CTRL__LBSI_MODE_MASK | 680 UVD_CGC_CTRL__LRBBM_MODE_MASK | 681 UVD_CGC_CTRL__WCB_MODE_MASK | 682 UVD_CGC_CTRL__VCPU_MODE_MASK); 683 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 684 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 685 686 /* turn off clock gating */ 687 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 688 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); 689 690 /* turn on SUVD clock gating */ 691 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 692 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 693 694 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 695 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 696 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 697 } 698 699 /** 700 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating 701 * 702 * @adev: amdgpu_device pointer 703 * @inst_idx: instance number 704 * 705 * Enable clock gating for VCN block 706 */ 707 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 708 { 709 uint32_t data; 710 int vcn_inst; 711 712 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 713 return; 714 715 vcn_inst = GET_INST(VCN, inst_idx); 716 717 /* enable VCN CGC */ 718 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 719 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 720 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 721 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 722 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 723 724 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 725 data |= (UVD_CGC_CTRL__SYS_MODE_MASK 726 | UVD_CGC_CTRL__MPEG2_MODE_MASK 727 | UVD_CGC_CTRL__REGS_MODE_MASK 728 | UVD_CGC_CTRL__RBC_MODE_MASK 729 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 730 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 731 | UVD_CGC_CTRL__MPC_MODE_MASK 732 | UVD_CGC_CTRL__LBSI_MODE_MASK 733 | UVD_CGC_CTRL__LRBBM_MODE_MASK 734 | UVD_CGC_CTRL__WCB_MODE_MASK 735 | UVD_CGC_CTRL__VCPU_MODE_MASK); 736 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 737 738 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 739 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 740 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 741 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 742 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 743 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 744 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 745 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 746 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 747 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 748 } 749 750 /** 751 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode 752 * 753 * @adev: amdgpu_device pointer 754 * @inst_idx: instance number index 755 * @indirect: indirectly write sram 756 * 757 * Start VCN block with dpg mode 758 */ 759 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 760 { 761 volatile struct amdgpu_vcn4_fw_shared *fw_shared = 762 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 763 struct amdgpu_ring *ring; 764 int vcn_inst; 765 uint32_t tmp; 766 767 vcn_inst = GET_INST(VCN, inst_idx); 768 /* disable register anti-hang mechanism */ 769 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 770 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 771 /* enable dynamic power gating mode */ 772 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 773 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 774 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 775 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 776 777 if (indirect) { 778 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d", 779 inst_idx, adev->vcn.inst[inst_idx].aid_id); 780 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 781 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 782 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 783 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, 784 adev->vcn.inst[inst_idx].aid_id, 0, true); 785 } 786 787 /* enable clock gating */ 788 vcn_v4_0_3_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 789 790 /* enable VCPU clock */ 791 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 792 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 793 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 794 795 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 796 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 797 798 /* disable master interrupt */ 799 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 800 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 801 802 /* setup regUVD_LMI_CTRL */ 803 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 804 UVD_LMI_CTRL__REQ_MODE_MASK | 805 UVD_LMI_CTRL__CRC_RESET_MASK | 806 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 807 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 808 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 809 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 810 0x00100000L); 811 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 812 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 813 814 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 815 VCN, 0, regUVD_MPC_CNTL), 816 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 817 818 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 819 VCN, 0, regUVD_MPC_SET_MUXA0), 820 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 821 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 822 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 823 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 824 825 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 826 VCN, 0, regUVD_MPC_SET_MUXB0), 827 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 828 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 829 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 830 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 831 832 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 833 VCN, 0, regUVD_MPC_SET_MUX), 834 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 835 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 836 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 837 838 vcn_v4_0_3_mc_resume_dpg_mode(adev, inst_idx, indirect); 839 840 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 841 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 842 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 843 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 844 845 /* enable LMI MC and UMC channels */ 846 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 847 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 848 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 849 850 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); 851 852 /* enable master interrupt */ 853 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 854 VCN, 0, regUVD_MASTINT_EN), 855 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 856 857 if (indirect) 858 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 859 860 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 861 862 /* program the RB_BASE for ring buffer */ 863 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 864 lower_32_bits(ring->gpu_addr)); 865 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 866 upper_32_bits(ring->gpu_addr)); 867 868 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 869 ring->ring_size / sizeof(uint32_t)); 870 871 /* resetting ring, fw should not check RB ring */ 872 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 873 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 874 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 875 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 876 877 /* Initialize the ring buffer's read and write pointers */ 878 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 879 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 880 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 881 882 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 883 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 884 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 885 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 886 887 /*resetting done, fw can check RB ring */ 888 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 889 890 return 0; 891 } 892 893 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev) 894 { 895 int i, vcn_inst; 896 struct amdgpu_ring *ring_enc; 897 uint64_t cache_addr; 898 uint64_t rb_enc_addr; 899 uint64_t ctx_addr; 900 uint32_t param, resp, expected; 901 uint32_t offset, cache_size; 902 uint32_t tmp, timeout; 903 904 struct amdgpu_mm_table *table = &adev->virt.mm_table; 905 uint32_t *table_loc; 906 uint32_t table_size; 907 uint32_t size, size_dw; 908 uint32_t init_status; 909 uint32_t enabled_vcn; 910 911 struct mmsch_v4_0_cmd_direct_write 912 direct_wt = { {0} }; 913 struct mmsch_v4_0_cmd_direct_read_modify_write 914 direct_rd_mod_wt = { {0} }; 915 struct mmsch_v4_0_cmd_end end = { {0} }; 916 struct mmsch_v4_0_3_init_header header; 917 918 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 919 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 920 921 direct_wt.cmd_header.command_type = 922 MMSCH_COMMAND__DIRECT_REG_WRITE; 923 direct_rd_mod_wt.cmd_header.command_type = 924 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 925 end.cmd_header.command_type = MMSCH_COMMAND__END; 926 927 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 928 vcn_inst = GET_INST(VCN, i); 929 930 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 931 header.version = MMSCH_VERSION; 932 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 933 934 table_loc = (uint32_t *)table->cpu_addr; 935 table_loc += header.total_size; 936 937 table_size = 0; 938 939 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 940 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 941 942 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4); 943 944 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 945 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 946 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 947 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 948 949 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 950 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 951 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 952 953 offset = 0; 954 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 955 regUVD_VCPU_CACHE_OFFSET0), 0); 956 } else { 957 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 958 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 959 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 960 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 961 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 962 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 963 offset = cache_size; 964 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 965 regUVD_VCPU_CACHE_OFFSET0), 966 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 967 } 968 969 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 970 regUVD_VCPU_CACHE_SIZE0), 971 cache_size); 972 973 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 974 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 975 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 976 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 977 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 978 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 979 regUVD_VCPU_CACHE_OFFSET1), 0); 980 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 981 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 982 983 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 984 AMDGPU_VCN_STACK_SIZE; 985 986 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 987 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 988 989 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 990 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 991 992 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 993 regUVD_VCPU_CACHE_OFFSET2), 0); 994 995 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 996 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 997 998 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 999 rb_setup = &fw_shared->rb_setup; 1000 1001 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 1002 ring_enc->wptr = 0; 1003 rb_enc_addr = ring_enc->gpu_addr; 1004 1005 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1006 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1007 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1008 rb_setup->rb_size = ring_enc->ring_size / 4; 1009 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1010 1011 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1012 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1013 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1014 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1015 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1016 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1017 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1018 regUVD_VCPU_NONCACHE_SIZE0), 1019 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1020 MMSCH_V4_0_INSERT_END(); 1021 1022 header.vcn0.init_status = 0; 1023 header.vcn0.table_offset = header.total_size; 1024 header.vcn0.table_size = table_size; 1025 header.total_size += table_size; 1026 1027 /* Send init table to mmsch */ 1028 size = sizeof(struct mmsch_v4_0_3_init_header); 1029 table_loc = (uint32_t *)table->cpu_addr; 1030 memcpy((void *)table_loc, &header, size); 1031 1032 ctx_addr = table->gpu_addr; 1033 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1034 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1035 1036 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 1037 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1038 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1039 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 1040 1041 size = header.total_size; 1042 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 1043 1044 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 1045 1046 param = 0x00000001; 1047 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 1048 tmp = 0; 1049 timeout = 1000; 1050 resp = 0; 1051 expected = MMSCH_VF_MAILBOX_RESP__OK; 1052 while (resp != expected) { 1053 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 1054 if (resp != 0) 1055 break; 1056 1057 udelay(10); 1058 tmp = tmp + 10; 1059 if (tmp >= timeout) { 1060 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1061 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1062 "(expected=0x%08x, readback=0x%08x)\n", 1063 tmp, expected, resp); 1064 return -EBUSY; 1065 } 1066 } 1067 1068 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1069 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status; 1070 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1071 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 1072 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1073 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1074 } 1075 } 1076 1077 return 0; 1078 } 1079 1080 /** 1081 * vcn_v4_0_3_start - VCN start 1082 * 1083 * @adev: amdgpu_device pointer 1084 * 1085 * Start VCN block 1086 */ 1087 static int vcn_v4_0_3_start(struct amdgpu_device *adev) 1088 { 1089 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1090 struct amdgpu_ring *ring; 1091 int i, j, k, r, vcn_inst; 1092 uint32_t tmp; 1093 1094 if (adev->pm.dpm_enabled) 1095 amdgpu_dpm_enable_uvd(adev, true); 1096 1097 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1098 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1099 r = vcn_v4_0_3_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1100 continue; 1101 } 1102 1103 vcn_inst = GET_INST(VCN, i); 1104 /* set VCN status busy */ 1105 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | 1106 UVD_STATUS__UVD_BUSY; 1107 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 1108 1109 /*SW clock gating */ 1110 vcn_v4_0_3_disable_clock_gating(adev, i); 1111 1112 /* enable VCPU clock */ 1113 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1114 UVD_VCPU_CNTL__CLK_EN_MASK, 1115 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1116 1117 /* disable master interrupt */ 1118 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 1119 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1120 1121 /* enable LMI MC and UMC channels */ 1122 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 1123 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1124 1125 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1126 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1127 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1128 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1129 1130 /* setup regUVD_LMI_CTRL */ 1131 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 1132 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, 1133 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1134 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1135 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1136 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1137 1138 /* setup regUVD_MPC_CNTL */ 1139 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); 1140 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1141 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1142 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); 1143 1144 /* setup UVD_MPC_SET_MUXA0 */ 1145 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, 1146 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1147 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1148 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1149 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1150 1151 /* setup UVD_MPC_SET_MUXB0 */ 1152 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, 1153 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1154 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1155 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1156 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1157 1158 /* setup UVD_MPC_SET_MUX */ 1159 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX, 1160 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1161 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1162 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1163 1164 vcn_v4_0_3_mc_resume(adev, i); 1165 1166 /* VCN global tiling registers */ 1167 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG, 1168 adev->gfx.config.gb_addr_config); 1169 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 1170 adev->gfx.config.gb_addr_config); 1171 1172 /* unblock VCPU register access */ 1173 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1174 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1175 1176 /* release VCPU reset to boot */ 1177 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1178 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1179 1180 for (j = 0; j < 10; ++j) { 1181 uint32_t status; 1182 1183 for (k = 0; k < 100; ++k) { 1184 status = RREG32_SOC15(VCN, vcn_inst, 1185 regUVD_STATUS); 1186 if (status & 2) 1187 break; 1188 mdelay(10); 1189 } 1190 r = 0; 1191 if (status & 2) 1192 break; 1193 1194 DRM_DEV_ERROR(adev->dev, 1195 "VCN decode not responding, trying to reset the VCPU!!!\n"); 1196 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1197 regUVD_VCPU_CNTL), 1198 UVD_VCPU_CNTL__BLK_RST_MASK, 1199 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1200 mdelay(10); 1201 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1202 regUVD_VCPU_CNTL), 1203 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); 1204 1205 mdelay(10); 1206 r = -1; 1207 } 1208 1209 if (r) { 1210 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n"); 1211 return r; 1212 } 1213 1214 /* enable master interrupt */ 1215 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1216 UVD_MASTINT_EN__VCPU_EN_MASK, 1217 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1218 1219 /* clear the busy bit of VCN_STATUS */ 1220 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1221 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1222 1223 ring = &adev->vcn.inst[i].ring_enc[0]; 1224 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1225 1226 /* program the RB_BASE for ring buffer */ 1227 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 1228 lower_32_bits(ring->gpu_addr)); 1229 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 1230 upper_32_bits(ring->gpu_addr)); 1231 1232 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 1233 ring->ring_size / sizeof(uint32_t)); 1234 1235 /* resetting ring, fw should not check RB ring */ 1236 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1237 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 1238 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1239 1240 /* Initialize the ring buffer's read and write pointers */ 1241 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1242 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1243 1244 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1245 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 1246 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1247 1248 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1249 fw_shared->sq.queue_mode &= 1250 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF)); 1251 1252 } 1253 return 0; 1254 } 1255 1256 /** 1257 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode 1258 * 1259 * @adev: amdgpu_device pointer 1260 * @inst_idx: instance number index 1261 * 1262 * Stop VCN block with dpg mode 1263 */ 1264 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1265 { 1266 uint32_t tmp; 1267 int vcn_inst; 1268 1269 vcn_inst = GET_INST(VCN, inst_idx); 1270 1271 /* Wait for power status to be 1 */ 1272 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1273 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1274 1275 /* wait for read ptr to be equal to write ptr */ 1276 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1277 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1278 1279 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1280 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1281 1282 /* disable dynamic power gating mode */ 1283 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1284 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1285 return 0; 1286 } 1287 1288 /** 1289 * vcn_v4_0_3_stop - VCN stop 1290 * 1291 * @adev: amdgpu_device pointer 1292 * 1293 * Stop VCN block 1294 */ 1295 static int vcn_v4_0_3_stop(struct amdgpu_device *adev) 1296 { 1297 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1298 int i, r = 0, vcn_inst; 1299 uint32_t tmp; 1300 1301 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1302 vcn_inst = GET_INST(VCN, i); 1303 1304 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1305 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1306 1307 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1308 vcn_v4_0_3_stop_dpg_mode(adev, i); 1309 continue; 1310 } 1311 1312 /* wait for vcn idle */ 1313 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, 1314 UVD_STATUS__IDLE, 0x7); 1315 if (r) 1316 goto Done; 1317 1318 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1319 UVD_LMI_STATUS__READ_CLEAN_MASK | 1320 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1321 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1322 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1323 tmp); 1324 if (r) 1325 goto Done; 1326 1327 /* stall UMC channel */ 1328 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1329 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1330 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1331 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1332 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1333 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1334 tmp); 1335 if (r) 1336 goto Done; 1337 1338 /* Unblock VCPU Register access */ 1339 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1340 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1341 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1342 1343 /* release VCPU reset to boot */ 1344 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1345 UVD_VCPU_CNTL__BLK_RST_MASK, 1346 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1347 1348 /* disable VCPU clock */ 1349 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1350 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1351 1352 /* reset LMI UMC/LMI/VCPU */ 1353 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1354 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1355 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1356 1357 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1358 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1359 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1360 1361 /* clear VCN status */ 1362 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1363 1364 /* apply HW clock gating */ 1365 vcn_v4_0_3_enable_clock_gating(adev, i); 1366 } 1367 Done: 1368 if (adev->pm.dpm_enabled) 1369 amdgpu_dpm_enable_uvd(adev, false); 1370 1371 return 0; 1372 } 1373 1374 /** 1375 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode 1376 * 1377 * @adev: amdgpu_device pointer 1378 * @inst_idx: instance number index 1379 * @new_state: pause state 1380 * 1381 * Pause dpg mode for VCN block 1382 */ 1383 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1384 struct dpg_pause_state *new_state) 1385 { 1386 1387 return 0; 1388 } 1389 1390 /** 1391 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer 1392 * 1393 * @ring: amdgpu_ring pointer 1394 * 1395 * Returns the current hardware unified read pointer 1396 */ 1397 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring) 1398 { 1399 struct amdgpu_device *adev = ring->adev; 1400 1401 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1402 DRM_ERROR("wrong ring id is identified in %s", __func__); 1403 1404 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1405 } 1406 1407 /** 1408 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer 1409 * 1410 * @ring: amdgpu_ring pointer 1411 * 1412 * Returns the current hardware unified write pointer 1413 */ 1414 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring) 1415 { 1416 struct amdgpu_device *adev = ring->adev; 1417 1418 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1419 DRM_ERROR("wrong ring id is identified in %s", __func__); 1420 1421 if (ring->use_doorbell) 1422 return *ring->wptr_cpu_addr; 1423 else 1424 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), 1425 regUVD_RB_WPTR); 1426 } 1427 1428 static void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1429 uint32_t val, uint32_t mask) 1430 { 1431 /* For VF, only local offsets should be used */ 1432 if (amdgpu_sriov_vf(ring->adev)) 1433 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1434 1435 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1436 amdgpu_ring_write(ring, reg << 2); 1437 amdgpu_ring_write(ring, mask); 1438 amdgpu_ring_write(ring, val); 1439 } 1440 1441 static void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1442 { 1443 /* For VF, only local offsets should be used */ 1444 if (amdgpu_sriov_vf(ring->adev)) 1445 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1446 1447 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1448 amdgpu_ring_write(ring, reg << 2); 1449 amdgpu_ring_write(ring, val); 1450 } 1451 1452 static void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1453 unsigned int vmid, uint64_t pd_addr) 1454 { 1455 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1456 1457 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1458 1459 /* wait for reg writes */ 1460 vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1461 vmid * hub->ctx_addr_distance, 1462 lower_32_bits(pd_addr), 0xffffffff); 1463 } 1464 1465 static void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1466 { 1467 /* VCN engine access for HDP flush doesn't work when RRMT is enabled. 1468 * This is a workaround to avoid any HDP flush through VCN ring. 1469 */ 1470 } 1471 1472 /** 1473 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer 1474 * 1475 * @ring: amdgpu_ring pointer 1476 * 1477 * Commits the enc write pointer to the hardware 1478 */ 1479 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) 1480 { 1481 struct amdgpu_device *adev = ring->adev; 1482 1483 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1484 DRM_ERROR("wrong ring id is identified in %s", __func__); 1485 1486 if (ring->use_doorbell) { 1487 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1488 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1489 } else { 1490 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1491 lower_32_bits(ring->wptr)); 1492 } 1493 } 1494 1495 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { 1496 .type = AMDGPU_RING_TYPE_VCN_ENC, 1497 .align_mask = 0x3f, 1498 .nop = VCN_ENC_CMD_NO_OP, 1499 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, 1500 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, 1501 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, 1502 .emit_frame_size = 1503 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1504 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1505 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1506 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1507 1, /* vcn_v2_0_enc_ring_insert_end */ 1508 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1509 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1510 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1511 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1512 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1513 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1514 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1515 .insert_nop = amdgpu_ring_insert_nop, 1516 .insert_end = vcn_v2_0_enc_ring_insert_end, 1517 .pad_ib = amdgpu_ring_generic_pad_ib, 1518 .begin_use = amdgpu_vcn_ring_begin_use, 1519 .end_use = amdgpu_vcn_ring_end_use, 1520 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1521 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1522 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1523 }; 1524 1525 /** 1526 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions 1527 * 1528 * @adev: amdgpu_device pointer 1529 * 1530 * Set unified ring functions 1531 */ 1532 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev) 1533 { 1534 int i, vcn_inst; 1535 1536 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1537 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs; 1538 adev->vcn.inst[i].ring_enc[0].me = i; 1539 vcn_inst = GET_INST(VCN, i); 1540 adev->vcn.inst[i].aid_id = 1541 vcn_inst / adev->vcn.num_inst_per_aid; 1542 } 1543 } 1544 1545 /** 1546 * vcn_v4_0_3_is_idle - check VCN block is idle 1547 * 1548 * @handle: amdgpu_device pointer 1549 * 1550 * Check whether VCN block is idle 1551 */ 1552 static bool vcn_v4_0_3_is_idle(void *handle) 1553 { 1554 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1555 int i, ret = 1; 1556 1557 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1558 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == 1559 UVD_STATUS__IDLE); 1560 } 1561 1562 return ret; 1563 } 1564 1565 /** 1566 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle 1567 * 1568 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1569 * 1570 * Wait for VCN block idle 1571 */ 1572 static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 1573 { 1574 struct amdgpu_device *adev = ip_block->adev; 1575 int i, ret = 0; 1576 1577 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1578 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, 1579 UVD_STATUS__IDLE, UVD_STATUS__IDLE); 1580 if (ret) 1581 return ret; 1582 } 1583 1584 return ret; 1585 } 1586 1587 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state 1588 * 1589 * @handle: amdgpu_device pointer 1590 * @state: clock gating state 1591 * 1592 * Set VCN block clockgating state 1593 */ 1594 static int vcn_v4_0_3_set_clockgating_state(void *handle, 1595 enum amd_clockgating_state state) 1596 { 1597 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1598 bool enable = state == AMD_CG_STATE_GATE; 1599 int i; 1600 1601 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1602 if (enable) { 1603 if (RREG32_SOC15(VCN, GET_INST(VCN, i), 1604 regUVD_STATUS) != UVD_STATUS__IDLE) 1605 return -EBUSY; 1606 vcn_v4_0_3_enable_clock_gating(adev, i); 1607 } else { 1608 vcn_v4_0_3_disable_clock_gating(adev, i); 1609 } 1610 } 1611 return 0; 1612 } 1613 1614 /** 1615 * vcn_v4_0_3_set_powergating_state - set VCN block powergating state 1616 * 1617 * @handle: amdgpu_device pointer 1618 * @state: power gating state 1619 * 1620 * Set VCN block powergating state 1621 */ 1622 static int vcn_v4_0_3_set_powergating_state(void *handle, 1623 enum amd_powergating_state state) 1624 { 1625 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1626 int ret; 1627 1628 /* for SRIOV, guest should not control VCN Power-gating 1629 * MMSCH FW should control Power-gating and clock-gating 1630 * guest should avoid touching CGC and PG 1631 */ 1632 if (amdgpu_sriov_vf(adev)) { 1633 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1634 return 0; 1635 } 1636 1637 if (state == adev->vcn.cur_state) 1638 return 0; 1639 1640 if (state == AMD_PG_STATE_GATE) 1641 ret = vcn_v4_0_3_stop(adev); 1642 else 1643 ret = vcn_v4_0_3_start(adev); 1644 1645 if (!ret) 1646 adev->vcn.cur_state = state; 1647 1648 return ret; 1649 } 1650 1651 /** 1652 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state 1653 * 1654 * @adev: amdgpu_device pointer 1655 * @source: interrupt sources 1656 * @type: interrupt types 1657 * @state: interrupt states 1658 * 1659 * Set VCN block interrupt state 1660 */ 1661 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1662 struct amdgpu_irq_src *source, 1663 unsigned int type, 1664 enum amdgpu_interrupt_state state) 1665 { 1666 return 0; 1667 } 1668 1669 /** 1670 * vcn_v4_0_3_process_interrupt - process VCN block interrupt 1671 * 1672 * @adev: amdgpu_device pointer 1673 * @source: interrupt sources 1674 * @entry: interrupt entry from clients and sources 1675 * 1676 * Process VCN block interrupt 1677 */ 1678 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1679 struct amdgpu_irq_src *source, 1680 struct amdgpu_iv_entry *entry) 1681 { 1682 uint32_t i, inst; 1683 1684 i = node_id_to_phys_map[entry->node_id]; 1685 1686 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1687 1688 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1689 if (adev->vcn.inst[inst].aid_id == i) 1690 break; 1691 1692 if (inst >= adev->vcn.num_vcn_inst) { 1693 dev_WARN_ONCE(adev->dev, 1, 1694 "Interrupt received for unknown VCN instance %d", 1695 entry->node_id); 1696 return 0; 1697 } 1698 1699 switch (entry->src_id) { 1700 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1701 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1702 break; 1703 default: 1704 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1705 entry->src_id, entry->src_data[0]); 1706 break; 1707 } 1708 1709 return 0; 1710 } 1711 1712 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 1713 .set = vcn_v4_0_3_set_interrupt_state, 1714 .process = vcn_v4_0_3_process_interrupt, 1715 }; 1716 1717 /** 1718 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions 1719 * 1720 * @adev: amdgpu_device pointer 1721 * 1722 * Set VCN block interrupt irq functions 1723 */ 1724 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1725 { 1726 int i; 1727 1728 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1729 adev->vcn.inst->irq.num_types++; 1730 } 1731 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 1732 } 1733 1734 static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1735 { 1736 struct amdgpu_device *adev = ip_block->adev; 1737 int i, j; 1738 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 1739 uint32_t inst_off, is_powered; 1740 1741 if (!adev->vcn.ip_dump) 1742 return; 1743 1744 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1745 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1746 if (adev->vcn.harvest_config & (1 << i)) { 1747 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1748 continue; 1749 } 1750 1751 inst_off = i * reg_count; 1752 is_powered = (adev->vcn.ip_dump[inst_off] & 1753 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1754 1755 if (is_powered) { 1756 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1757 for (j = 0; j < reg_count; j++) 1758 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name, 1759 adev->vcn.ip_dump[inst_off + j]); 1760 } else { 1761 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1762 } 1763 } 1764 } 1765 1766 static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block) 1767 { 1768 struct amdgpu_device *adev = ip_block->adev; 1769 int i, j; 1770 bool is_powered; 1771 uint32_t inst_off, inst_id; 1772 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 1773 1774 if (!adev->vcn.ip_dump) 1775 return; 1776 1777 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1778 if (adev->vcn.harvest_config & (1 << i)) 1779 continue; 1780 1781 inst_id = GET_INST(VCN, i); 1782 inst_off = i * reg_count; 1783 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1784 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS); 1785 is_powered = (adev->vcn.ip_dump[inst_off] & 1786 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1787 1788 if (is_powered) 1789 for (j = 1; j < reg_count; j++) 1790 adev->vcn.ip_dump[inst_off + j] = 1791 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j], 1792 inst_id)); 1793 } 1794 } 1795 1796 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 1797 .name = "vcn_v4_0_3", 1798 .early_init = vcn_v4_0_3_early_init, 1799 .sw_init = vcn_v4_0_3_sw_init, 1800 .sw_fini = vcn_v4_0_3_sw_fini, 1801 .hw_init = vcn_v4_0_3_hw_init, 1802 .hw_fini = vcn_v4_0_3_hw_fini, 1803 .suspend = vcn_v4_0_3_suspend, 1804 .resume = vcn_v4_0_3_resume, 1805 .is_idle = vcn_v4_0_3_is_idle, 1806 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 1807 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 1808 .set_powergating_state = vcn_v4_0_3_set_powergating_state, 1809 .dump_ip_state = vcn_v4_0_3_dump_ip_state, 1810 .print_ip_state = vcn_v4_0_3_print_ip_state, 1811 }; 1812 1813 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { 1814 .type = AMD_IP_BLOCK_TYPE_VCN, 1815 .major = 4, 1816 .minor = 0, 1817 .rev = 3, 1818 .funcs = &vcn_v4_0_3_ip_funcs, 1819 }; 1820 1821 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = { 1822 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD), 1823 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"}, 1824 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV), 1825 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"}, 1826 }; 1827 1828 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1829 uint32_t vcn_inst, 1830 void *ras_err_status) 1831 { 1832 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1833 1834 /* vcn v4_0_3 only support query uncorrectable errors */ 1835 amdgpu_ras_inst_query_ras_error_count(adev, 1836 vcn_v4_0_3_ue_reg_list, 1837 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1838 NULL, 0, GET_INST(VCN, vcn_inst), 1839 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1840 &err_data->ue_count); 1841 } 1842 1843 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1844 void *ras_err_status) 1845 { 1846 uint32_t i; 1847 1848 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1849 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1850 return; 1851 } 1852 1853 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1854 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1855 } 1856 1857 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1858 uint32_t vcn_inst) 1859 { 1860 amdgpu_ras_inst_reset_ras_error_count(adev, 1861 vcn_v4_0_3_ue_reg_list, 1862 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1863 GET_INST(VCN, vcn_inst)); 1864 } 1865 1866 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1867 { 1868 uint32_t i; 1869 1870 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1871 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1872 return; 1873 } 1874 1875 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1876 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 1877 } 1878 1879 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 1880 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 1881 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 1882 }; 1883 1884 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = { 1885 .ras_block = { 1886 .hw_ops = &vcn_v4_0_3_ras_hw_ops, 1887 }, 1888 }; 1889 1890 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1891 { 1892 adev->vcn.ras = &vcn_v4_0_3_ras; 1893 } 1894 1895 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 1896 int inst_idx, bool indirect) 1897 { 1898 uint32_t tmp; 1899 1900 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 1901 return; 1902 1903 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 1904 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 1905 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 1906 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 1907 WREG32_SOC15_DPG_MODE(inst_idx, 1908 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 1909 tmp, 0, indirect); 1910 1911 tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK; 1912 WREG32_SOC15_DPG_MODE(inst_idx, 1913 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2), 1914 tmp, 0, indirect); 1915 1916 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 1917 WREG32_SOC15_DPG_MODE(inst_idx, 1918 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 1919 tmp, 0, indirect); 1920 } 1921