1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_hw_ip.h" 33 #include "vcn_v2_0.h" 34 #include "vcn_v4_0_3.h" 35 #include "mmsch_v4_0_3.h" 36 37 #include "vcn/vcn_4_0_3_offset.h" 38 #include "vcn/vcn_4_0_3_sh_mask.h" 39 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 40 41 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 42 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 43 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 44 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 45 46 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 47 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 48 49 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { 50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 83 }; 84 85 #define NORMALIZE_VCN_REG_OFFSET(offset) \ 86 (offset & 0x1FFFF) 87 88 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); 89 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); 90 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 91 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 92 enum amd_powergating_state state); 93 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 94 struct dpg_pause_state *new_state); 95 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring); 96 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 97 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 98 int inst_idx, bool indirect); 99 100 static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 101 { 102 return (adev->vcn.caps & AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0; 103 } 104 105 /** 106 * vcn_v4_0_3_early_init - set function pointers 107 * 108 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 109 * 110 * Set ring and irq function pointers 111 */ 112 static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 113 { 114 struct amdgpu_device *adev = ip_block->adev; 115 int i, r; 116 117 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 118 /* re-use enc ring as unified ring */ 119 adev->vcn.inst[i].num_enc_rings = 1; 120 121 vcn_v4_0_3_set_unified_ring_funcs(adev); 122 vcn_v4_0_3_set_irq_funcs(adev); 123 vcn_v4_0_3_set_ras_funcs(adev); 124 125 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 126 adev->vcn.inst[i].set_pg_state = vcn_v4_0_3_set_pg_state; 127 128 r = amdgpu_vcn_early_init(adev, i); 129 if (r) 130 return r; 131 } 132 133 return 0; 134 } 135 136 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 137 { 138 struct amdgpu_vcn4_fw_shared *fw_shared; 139 140 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 141 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 142 fw_shared->sq.is_enabled = 1; 143 144 if (amdgpu_vcnfw_log) 145 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 146 147 return 0; 148 } 149 150 /** 151 * vcn_v4_0_3_sw_init - sw init for VCN block 152 * 153 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 154 * 155 * Load firmware and sw initialization 156 */ 157 static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 158 { 159 struct amdgpu_device *adev = ip_block->adev; 160 struct amdgpu_ring *ring; 161 int i, r, vcn_inst; 162 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 163 uint32_t *ptr; 164 165 /* VCN DEC TRAP */ 166 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 167 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 168 if (r) 169 return r; 170 171 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 172 173 r = amdgpu_vcn_sw_init(adev, i); 174 if (r) 175 return r; 176 177 amdgpu_vcn_setup_ucode(adev, i); 178 179 r = amdgpu_vcn_resume(adev, i); 180 if (r) 181 return r; 182 183 vcn_inst = GET_INST(VCN, i); 184 185 ring = &adev->vcn.inst[i].ring_enc[0]; 186 ring->use_doorbell = true; 187 188 if (!amdgpu_sriov_vf(adev)) 189 ring->doorbell_index = 190 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 191 9 * vcn_inst; 192 else 193 ring->doorbell_index = 194 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 195 32 * vcn_inst; 196 197 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 198 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 199 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 200 AMDGPU_RING_PRIO_DEFAULT, 201 &adev->vcn.inst[i].sched_score); 202 if (r) 203 return r; 204 205 vcn_v4_0_3_fw_shared_init(adev, i); 206 207 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 208 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; 209 } 210 211 /* TODO: Add queue reset mask when FW fully supports it */ 212 adev->vcn.supported_reset = 213 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 214 215 if (amdgpu_sriov_vf(adev)) { 216 r = amdgpu_virt_alloc_mm_table(adev); 217 if (r) 218 return r; 219 } 220 221 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 222 r = amdgpu_vcn_ras_sw_init(adev); 223 if (r) { 224 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 225 return r; 226 } 227 } 228 229 /* Allocate memory for VCN IP Dump buffer */ 230 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 231 if (!ptr) { 232 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 233 adev->vcn.ip_dump = NULL; 234 } else { 235 adev->vcn.ip_dump = ptr; 236 } 237 238 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 239 if (r) 240 return r; 241 242 return 0; 243 } 244 245 /** 246 * vcn_v4_0_3_sw_fini - sw fini for VCN block 247 * 248 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 249 * 250 * VCN suspend and free up sw allocation 251 */ 252 static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 253 { 254 struct amdgpu_device *adev = ip_block->adev; 255 int i, r, idx; 256 257 if (drm_dev_enter(&adev->ddev, &idx)) { 258 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 259 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 260 261 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 262 fw_shared->present_flag_0 = 0; 263 fw_shared->sq.is_enabled = cpu_to_le32(false); 264 } 265 drm_dev_exit(idx); 266 } 267 268 if (amdgpu_sriov_vf(adev)) 269 amdgpu_virt_free_mm_table(adev); 270 271 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 272 r = amdgpu_vcn_suspend(adev, i); 273 if (r) 274 return r; 275 } 276 277 amdgpu_vcn_sysfs_reset_mask_fini(adev); 278 279 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 280 r = amdgpu_vcn_sw_fini(adev, i); 281 if (r) 282 return r; 283 } 284 285 kfree(adev->vcn.ip_dump); 286 287 return 0; 288 } 289 290 static int vcn_v4_0_3_hw_init_inst(struct amdgpu_vcn_inst *vinst) 291 { 292 int vcn_inst; 293 struct amdgpu_device *adev = vinst->adev; 294 struct amdgpu_ring *ring; 295 int inst_idx = vinst->inst; 296 297 vcn_inst = GET_INST(VCN, inst_idx); 298 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 299 if (ring->use_doorbell) { 300 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 301 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * vcn_inst, 302 adev->vcn.inst[inst_idx].aid_id); 303 304 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 305 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 306 VCN_RB1_DB_CTRL__EN_MASK); 307 308 /* Read DB_CTRL to flush the write DB_CTRL command. */ 309 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 310 } 311 312 return 0; 313 } 314 315 /** 316 * vcn_v4_0_3_hw_init - start and test VCN block 317 * 318 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 319 * 320 * Initialize the hardware, boot up the VCPU and do some testing 321 */ 322 static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 323 { 324 struct amdgpu_device *adev = ip_block->adev; 325 struct amdgpu_ring *ring; 326 struct amdgpu_vcn_inst *vinst; 327 int i, r; 328 329 if (amdgpu_sriov_vf(adev)) { 330 r = vcn_v4_0_3_start_sriov(adev); 331 if (r) 332 return r; 333 334 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 335 ring = &adev->vcn.inst[i].ring_enc[0]; 336 ring->wptr = 0; 337 ring->wptr_old = 0; 338 vcn_v4_0_3_unified_ring_set_wptr(ring); 339 ring->sched.ready = true; 340 } 341 } else { 342 /* This flag is not set for VF, assumed to be disabled always */ 343 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 344 0x100) 345 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 346 347 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 348 struct amdgpu_vcn4_fw_shared *fw_shared; 349 350 ring = &adev->vcn.inst[i].ring_enc[0]; 351 vinst = &adev->vcn.inst[i]; 352 vcn_v4_0_3_hw_init_inst(vinst); 353 354 /* Re-init fw_shared when RAS fatal error occurred */ 355 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 356 if (!fw_shared->sq.is_enabled) 357 vcn_v4_0_3_fw_shared_init(adev, i); 358 359 r = amdgpu_ring_test_helper(ring); 360 if (r) 361 return r; 362 } 363 } 364 365 return r; 366 } 367 368 /** 369 * vcn_v4_0_3_hw_fini - stop the hardware block 370 * 371 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 372 * 373 * Stop the VCN block, mark ring as not ready any more 374 */ 375 static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 376 { 377 struct amdgpu_device *adev = ip_block->adev; 378 int i; 379 380 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 381 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 382 383 cancel_delayed_work_sync(&vinst->idle_work); 384 385 if (vinst->cur_state != AMD_PG_STATE_GATE) 386 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 387 } 388 389 return 0; 390 } 391 392 /** 393 * vcn_v4_0_3_suspend - suspend VCN block 394 * 395 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 396 * 397 * HW fini and suspend VCN block 398 */ 399 static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 400 { 401 struct amdgpu_device *adev = ip_block->adev; 402 int r, i; 403 404 r = vcn_v4_0_3_hw_fini(ip_block); 405 if (r) 406 return r; 407 408 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 409 r = amdgpu_vcn_suspend(adev, i); 410 if (r) 411 return r; 412 } 413 414 return 0; 415 } 416 417 /** 418 * vcn_v4_0_3_resume - resume VCN block 419 * 420 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 421 * 422 * Resume firmware and hw init VCN block 423 */ 424 static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 425 { 426 struct amdgpu_device *adev = ip_block->adev; 427 int r, i; 428 429 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 430 r = amdgpu_vcn_resume(ip_block->adev, i); 431 if (r) 432 return r; 433 } 434 435 r = vcn_v4_0_3_hw_init(ip_block); 436 437 return r; 438 } 439 440 /** 441 * vcn_v4_0_3_mc_resume - memory controller programming 442 * 443 * @vinst: VCN instance 444 * 445 * Let the VCN memory controller know it's offsets 446 */ 447 static void vcn_v4_0_3_mc_resume(struct amdgpu_vcn_inst *vinst) 448 { 449 struct amdgpu_device *adev = vinst->adev; 450 int inst_idx = vinst->inst; 451 uint32_t offset, size, vcn_inst; 452 const struct common_firmware_header *hdr; 453 454 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 455 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 456 457 vcn_inst = GET_INST(VCN, inst_idx); 458 /* cache window 0: fw */ 459 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 460 WREG32_SOC15( 461 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 462 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 463 .tmr_mc_addr_lo)); 464 WREG32_SOC15( 465 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 466 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 467 .tmr_mc_addr_hi)); 468 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 469 offset = 0; 470 } else { 471 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 472 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 473 WREG32_SOC15(VCN, vcn_inst, 474 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 475 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 476 offset = size; 477 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 478 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 479 } 480 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 481 482 /* cache window 1: stack */ 483 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 484 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 485 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 486 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 487 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 488 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, 489 AMDGPU_VCN_STACK_SIZE); 490 491 /* cache window 2: context */ 492 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 493 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 494 AMDGPU_VCN_STACK_SIZE)); 495 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 496 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 497 AMDGPU_VCN_STACK_SIZE)); 498 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 499 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, 500 AMDGPU_VCN_CONTEXT_SIZE); 501 502 /* non-cache window */ 503 WREG32_SOC15( 504 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 505 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 506 WREG32_SOC15( 507 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 508 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 509 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 510 WREG32_SOC15( 511 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 512 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 513 } 514 515 /** 516 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode 517 * 518 * @vinst: VCN instance 519 * @indirect: indirectly write sram 520 * 521 * Let the VCN memory controller know it's offsets with dpg mode 522 */ 523 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 524 bool indirect) 525 { 526 struct amdgpu_device *adev = vinst->adev; 527 int inst_idx = vinst->inst; 528 uint32_t offset, size; 529 const struct common_firmware_header *hdr; 530 531 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 532 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 533 534 /* cache window 0: fw */ 535 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 536 if (!indirect) { 537 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 538 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 539 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 540 inst_idx].tmr_mc_addr_lo), 0, indirect); 541 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 542 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 543 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 544 inst_idx].tmr_mc_addr_hi), 0, indirect); 545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 546 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 547 } else { 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 549 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 550 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 551 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 553 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 554 } 555 offset = 0; 556 } else { 557 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 558 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 559 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 561 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 562 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 563 offset = size; 564 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 565 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 566 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 567 } 568 569 if (!indirect) 570 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 571 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 572 else 573 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 574 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 575 576 /* cache window 1: stack */ 577 if (!indirect) { 578 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 579 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 580 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 581 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 582 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 583 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 584 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 585 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 586 } else { 587 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 588 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 589 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 590 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 591 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 592 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 593 } 594 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 595 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 596 597 /* cache window 2: context */ 598 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 599 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 600 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 601 AMDGPU_VCN_STACK_SIZE), 0, indirect); 602 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 603 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 604 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 605 AMDGPU_VCN_STACK_SIZE), 0, indirect); 606 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 607 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 608 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 609 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 610 611 /* non-cache window */ 612 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 613 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 614 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 615 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 616 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 617 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 618 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 619 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 620 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 621 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 622 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 623 624 /* VCN global tiling registers */ 625 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 626 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 627 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 628 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 629 } 630 631 /** 632 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating 633 * 634 * @vinst: VCN instance 635 * 636 * Disable clock gating for VCN block 637 */ 638 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 639 { 640 struct amdgpu_device *adev = vinst->adev; 641 int inst_idx = vinst->inst; 642 uint32_t data; 643 int vcn_inst; 644 645 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 646 return; 647 648 vcn_inst = GET_INST(VCN, inst_idx); 649 650 /* VCN disable CGC */ 651 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 652 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 653 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 654 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 655 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 656 657 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); 658 data &= ~(UVD_CGC_GATE__SYS_MASK 659 | UVD_CGC_GATE__MPEG2_MASK 660 | UVD_CGC_GATE__REGS_MASK 661 | UVD_CGC_GATE__RBC_MASK 662 | UVD_CGC_GATE__LMI_MC_MASK 663 | UVD_CGC_GATE__LMI_UMC_MASK 664 | UVD_CGC_GATE__MPC_MASK 665 | UVD_CGC_GATE__LBSI_MASK 666 | UVD_CGC_GATE__LRBBM_MASK 667 | UVD_CGC_GATE__WCB_MASK 668 | UVD_CGC_GATE__VCPU_MASK 669 | UVD_CGC_GATE__MMSCH_MASK); 670 671 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); 672 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 673 674 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 675 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK 676 | UVD_CGC_CTRL__MPEG2_MODE_MASK 677 | UVD_CGC_CTRL__REGS_MODE_MASK 678 | UVD_CGC_CTRL__RBC_MODE_MASK 679 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 680 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 681 | UVD_CGC_CTRL__MPC_MODE_MASK 682 | UVD_CGC_CTRL__LBSI_MODE_MASK 683 | UVD_CGC_CTRL__LRBBM_MODE_MASK 684 | UVD_CGC_CTRL__WCB_MODE_MASK 685 | UVD_CGC_CTRL__VCPU_MODE_MASK 686 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 687 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 688 689 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE); 690 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 691 | UVD_SUVD_CGC_GATE__SIT_MASK 692 | UVD_SUVD_CGC_GATE__SMP_MASK 693 | UVD_SUVD_CGC_GATE__SCM_MASK 694 | UVD_SUVD_CGC_GATE__SDB_MASK 695 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 696 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 697 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 698 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 699 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 700 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 701 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 702 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 703 | UVD_SUVD_CGC_GATE__ENT_MASK 704 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 705 | UVD_SUVD_CGC_GATE__SITE_MASK 706 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 707 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 708 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 709 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 710 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 711 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data); 712 713 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 714 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 715 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 716 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 717 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 718 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 719 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 720 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 721 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 722 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 723 } 724 725 /** 726 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 727 * 728 * @vinst: VCN instance 729 * @sram_sel: sram select 730 * @indirect: indirectly write sram 731 * 732 * Disable clock gating for VCN block with dpg mode 733 */ 734 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 735 uint8_t sram_sel, 736 uint8_t indirect) 737 { 738 struct amdgpu_device *adev = vinst->adev; 739 int inst_idx = vinst->inst; 740 uint32_t reg_data = 0; 741 742 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 743 return; 744 745 /* enable sw clock gating control */ 746 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 747 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 748 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 749 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | 750 UVD_CGC_CTRL__MPEG2_MODE_MASK | 751 UVD_CGC_CTRL__REGS_MODE_MASK | 752 UVD_CGC_CTRL__RBC_MODE_MASK | 753 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 754 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 755 UVD_CGC_CTRL__IDCT_MODE_MASK | 756 UVD_CGC_CTRL__MPRD_MODE_MASK | 757 UVD_CGC_CTRL__MPC_MODE_MASK | 758 UVD_CGC_CTRL__LBSI_MODE_MASK | 759 UVD_CGC_CTRL__LRBBM_MODE_MASK | 760 UVD_CGC_CTRL__WCB_MODE_MASK | 761 UVD_CGC_CTRL__VCPU_MODE_MASK); 762 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 763 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 764 765 /* turn off clock gating */ 766 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 767 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); 768 769 /* turn on SUVD clock gating */ 770 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 771 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 772 773 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 774 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 775 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 776 } 777 778 /** 779 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating 780 * 781 * @vinst: VCN instance 782 * 783 * Enable clock gating for VCN block 784 */ 785 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 786 { 787 struct amdgpu_device *adev = vinst->adev; 788 int inst_idx = vinst->inst; 789 uint32_t data; 790 int vcn_inst; 791 792 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 793 return; 794 795 vcn_inst = GET_INST(VCN, inst_idx); 796 797 /* enable VCN CGC */ 798 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 799 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 800 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 801 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 802 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 803 804 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 805 data |= (UVD_CGC_CTRL__SYS_MODE_MASK 806 | UVD_CGC_CTRL__MPEG2_MODE_MASK 807 | UVD_CGC_CTRL__REGS_MODE_MASK 808 | UVD_CGC_CTRL__RBC_MODE_MASK 809 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 810 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 811 | UVD_CGC_CTRL__MPC_MODE_MASK 812 | UVD_CGC_CTRL__LBSI_MODE_MASK 813 | UVD_CGC_CTRL__LRBBM_MODE_MASK 814 | UVD_CGC_CTRL__WCB_MODE_MASK 815 | UVD_CGC_CTRL__VCPU_MODE_MASK); 816 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 817 818 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 819 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 820 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 822 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 823 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 824 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 825 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 826 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 827 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 828 } 829 830 /** 831 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode 832 * 833 * @vinst: VCN instance 834 * @indirect: indirectly write sram 835 * 836 * Start VCN block with dpg mode 837 */ 838 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 839 bool indirect) 840 { 841 struct amdgpu_device *adev = vinst->adev; 842 int inst_idx = vinst->inst; 843 volatile struct amdgpu_vcn4_fw_shared *fw_shared = 844 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 845 struct amdgpu_ring *ring; 846 int vcn_inst; 847 uint32_t tmp; 848 849 vcn_inst = GET_INST(VCN, inst_idx); 850 /* disable register anti-hang mechanism */ 851 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 852 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 853 /* enable dynamic power gating mode */ 854 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 855 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 856 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 857 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 858 859 if (indirect) { 860 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d", 861 inst_idx, adev->vcn.inst[inst_idx].aid_id); 862 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 863 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 864 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 865 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, 866 adev->vcn.inst[inst_idx].aid_id, 0, true); 867 } 868 869 /* enable clock gating */ 870 vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect); 871 872 /* enable VCPU clock */ 873 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 874 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 875 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 876 877 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 878 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 879 880 /* disable master interrupt */ 881 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 882 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 883 884 /* setup regUVD_LMI_CTRL */ 885 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 886 UVD_LMI_CTRL__REQ_MODE_MASK | 887 UVD_LMI_CTRL__CRC_RESET_MASK | 888 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 889 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 890 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 891 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 892 0x00100000L); 893 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 894 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 895 896 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 897 VCN, 0, regUVD_MPC_CNTL), 898 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 899 900 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 901 VCN, 0, regUVD_MPC_SET_MUXA0), 902 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 903 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 904 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 905 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 906 907 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 908 VCN, 0, regUVD_MPC_SET_MUXB0), 909 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 910 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 911 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 912 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 913 914 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 915 VCN, 0, regUVD_MPC_SET_MUX), 916 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 917 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 918 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 919 920 vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect); 921 922 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 923 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 924 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 925 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 926 927 /* enable LMI MC and UMC channels */ 928 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 929 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 930 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 931 932 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); 933 934 /* enable master interrupt */ 935 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 936 VCN, 0, regUVD_MASTINT_EN), 937 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 938 939 if (indirect) 940 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 941 942 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 943 944 /* program the RB_BASE for ring buffer */ 945 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 946 lower_32_bits(ring->gpu_addr)); 947 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 948 upper_32_bits(ring->gpu_addr)); 949 950 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 951 ring->ring_size / sizeof(uint32_t)); 952 953 /* resetting ring, fw should not check RB ring */ 954 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 955 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 956 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 957 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 958 959 /* Initialize the ring buffer's read and write pointers */ 960 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 961 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 962 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 963 964 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 965 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 966 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 967 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 968 969 /*resetting done, fw can check RB ring */ 970 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 971 972 return 0; 973 } 974 975 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev) 976 { 977 int i, vcn_inst; 978 struct amdgpu_ring *ring_enc; 979 uint64_t cache_addr; 980 uint64_t rb_enc_addr; 981 uint64_t ctx_addr; 982 uint32_t param, resp, expected; 983 uint32_t offset, cache_size; 984 uint32_t tmp, timeout; 985 986 struct amdgpu_mm_table *table = &adev->virt.mm_table; 987 uint32_t *table_loc; 988 uint32_t table_size; 989 uint32_t size, size_dw; 990 uint32_t init_status; 991 uint32_t enabled_vcn; 992 993 struct mmsch_v4_0_cmd_direct_write 994 direct_wt = { {0} }; 995 struct mmsch_v4_0_cmd_direct_read_modify_write 996 direct_rd_mod_wt = { {0} }; 997 struct mmsch_v4_0_cmd_end end = { {0} }; 998 struct mmsch_v4_0_3_init_header header; 999 1000 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1001 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1002 1003 direct_wt.cmd_header.command_type = 1004 MMSCH_COMMAND__DIRECT_REG_WRITE; 1005 direct_rd_mod_wt.cmd_header.command_type = 1006 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1007 end.cmd_header.command_type = MMSCH_COMMAND__END; 1008 1009 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1010 vcn_inst = GET_INST(VCN, i); 1011 1012 vcn_v4_0_3_fw_shared_init(adev, vcn_inst); 1013 1014 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 1015 header.version = MMSCH_VERSION; 1016 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 1017 1018 table_loc = (uint32_t *)table->cpu_addr; 1019 table_loc += header.total_size; 1020 1021 table_size = 0; 1022 1023 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 1024 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1025 1026 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1027 1028 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1029 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1030 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1031 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1032 1033 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1034 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1035 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1036 1037 offset = 0; 1038 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1039 regUVD_VCPU_CACHE_OFFSET0), 0); 1040 } else { 1041 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1042 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1043 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1044 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1045 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1046 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1047 offset = cache_size; 1048 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1049 regUVD_VCPU_CACHE_OFFSET0), 1050 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1051 } 1052 1053 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1054 regUVD_VCPU_CACHE_SIZE0), 1055 cache_size); 1056 1057 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 1058 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1059 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1060 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1061 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1062 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1063 regUVD_VCPU_CACHE_OFFSET1), 0); 1064 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1065 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 1066 1067 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 1068 AMDGPU_VCN_STACK_SIZE; 1069 1070 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1071 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1072 1073 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1074 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1075 1076 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1077 regUVD_VCPU_CACHE_OFFSET2), 0); 1078 1079 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1080 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 1081 1082 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 1083 rb_setup = &fw_shared->rb_setup; 1084 1085 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 1086 ring_enc->wptr = 0; 1087 rb_enc_addr = ring_enc->gpu_addr; 1088 1089 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1090 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1091 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1092 rb_setup->rb_size = ring_enc->ring_size / 4; 1093 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1094 1095 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1096 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1097 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1098 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1099 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1100 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1101 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1102 regUVD_VCPU_NONCACHE_SIZE0), 1103 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1104 MMSCH_V4_0_INSERT_END(); 1105 1106 header.vcn0.init_status = 0; 1107 header.vcn0.table_offset = header.total_size; 1108 header.vcn0.table_size = table_size; 1109 header.total_size += table_size; 1110 1111 /* Send init table to mmsch */ 1112 size = sizeof(struct mmsch_v4_0_3_init_header); 1113 table_loc = (uint32_t *)table->cpu_addr; 1114 memcpy((void *)table_loc, &header, size); 1115 1116 ctx_addr = table->gpu_addr; 1117 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1118 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1119 1120 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 1121 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1122 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1123 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 1124 1125 size = header.total_size; 1126 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 1127 1128 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 1129 1130 param = 0x00000001; 1131 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 1132 tmp = 0; 1133 timeout = 1000; 1134 resp = 0; 1135 expected = MMSCH_VF_MAILBOX_RESP__OK; 1136 while (resp != expected) { 1137 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 1138 if (resp != 0) 1139 break; 1140 1141 udelay(10); 1142 tmp = tmp + 10; 1143 if (tmp >= timeout) { 1144 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1145 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1146 "(expected=0x%08x, readback=0x%08x)\n", 1147 tmp, expected, resp); 1148 return -EBUSY; 1149 } 1150 } 1151 1152 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1153 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status; 1154 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1155 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 1156 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1157 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1158 } 1159 } 1160 1161 return 0; 1162 } 1163 1164 /** 1165 * vcn_v4_0_3_start - VCN start 1166 * 1167 * @vinst: VCN instance 1168 * 1169 * Start VCN block 1170 */ 1171 static int vcn_v4_0_3_start(struct amdgpu_vcn_inst *vinst) 1172 { 1173 struct amdgpu_device *adev = vinst->adev; 1174 int i = vinst->inst; 1175 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1176 struct amdgpu_ring *ring; 1177 int j, k, r, vcn_inst; 1178 uint32_t tmp; 1179 1180 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1181 return vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1182 1183 vcn_inst = GET_INST(VCN, i); 1184 /* set VCN status busy */ 1185 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | 1186 UVD_STATUS__UVD_BUSY; 1187 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 1188 1189 /* SW clock gating */ 1190 vcn_v4_0_3_disable_clock_gating(vinst); 1191 1192 /* enable VCPU clock */ 1193 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1194 UVD_VCPU_CNTL__CLK_EN_MASK, 1195 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1196 1197 /* disable master interrupt */ 1198 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 1199 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1200 1201 /* enable LMI MC and UMC channels */ 1202 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 1203 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1204 1205 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1206 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1207 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1208 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1209 1210 /* setup regUVD_LMI_CTRL */ 1211 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 1212 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, 1213 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1214 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1215 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1216 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1217 1218 /* setup regUVD_MPC_CNTL */ 1219 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); 1220 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1221 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1222 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); 1223 1224 /* setup UVD_MPC_SET_MUXA0 */ 1225 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, 1226 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1227 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1228 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1229 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1230 1231 /* setup UVD_MPC_SET_MUXB0 */ 1232 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, 1233 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1234 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1235 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1236 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1237 1238 /* setup UVD_MPC_SET_MUX */ 1239 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX, 1240 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1241 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1242 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1243 1244 vcn_v4_0_3_mc_resume(vinst); 1245 1246 /* VCN global tiling registers */ 1247 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG, 1248 adev->gfx.config.gb_addr_config); 1249 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 1250 adev->gfx.config.gb_addr_config); 1251 1252 /* unblock VCPU register access */ 1253 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1254 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1255 1256 /* release VCPU reset to boot */ 1257 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1258 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1259 1260 for (j = 0; j < 10; ++j) { 1261 uint32_t status; 1262 1263 for (k = 0; k < 100; ++k) { 1264 status = RREG32_SOC15(VCN, vcn_inst, 1265 regUVD_STATUS); 1266 if (status & 2) 1267 break; 1268 mdelay(10); 1269 } 1270 r = 0; 1271 if (status & 2) 1272 break; 1273 1274 DRM_DEV_ERROR(adev->dev, 1275 "VCN decode not responding, trying to reset the VCPU!!!\n"); 1276 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1277 regUVD_VCPU_CNTL), 1278 UVD_VCPU_CNTL__BLK_RST_MASK, 1279 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1280 mdelay(10); 1281 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1282 regUVD_VCPU_CNTL), 1283 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); 1284 1285 mdelay(10); 1286 r = -1; 1287 } 1288 1289 if (r) { 1290 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n"); 1291 return r; 1292 } 1293 1294 /* enable master interrupt */ 1295 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1296 UVD_MASTINT_EN__VCPU_EN_MASK, 1297 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1298 1299 /* clear the busy bit of VCN_STATUS */ 1300 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1301 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1302 1303 ring = &adev->vcn.inst[i].ring_enc[0]; 1304 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1305 1306 /* program the RB_BASE for ring buffer */ 1307 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 1308 lower_32_bits(ring->gpu_addr)); 1309 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 1310 upper_32_bits(ring->gpu_addr)); 1311 1312 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 1313 ring->ring_size / sizeof(uint32_t)); 1314 1315 /* resetting ring, fw should not check RB ring */ 1316 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1317 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 1318 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1319 1320 /* Initialize the ring buffer's read and write pointers */ 1321 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1322 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1323 1324 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1325 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 1326 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1327 1328 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1329 fw_shared->sq.queue_mode &= 1330 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF)); 1331 1332 return 0; 1333 } 1334 1335 /** 1336 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode 1337 * 1338 * @vinst: VCN instance 1339 * 1340 * Stop VCN block with dpg mode 1341 */ 1342 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1343 { 1344 struct amdgpu_device *adev = vinst->adev; 1345 int inst_idx = vinst->inst; 1346 uint32_t tmp; 1347 int vcn_inst; 1348 1349 vcn_inst = GET_INST(VCN, inst_idx); 1350 1351 /* Wait for power status to be 1 */ 1352 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1353 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1354 1355 /* wait for read ptr to be equal to write ptr */ 1356 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1357 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1358 1359 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1360 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1361 1362 /* disable dynamic power gating mode */ 1363 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1364 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1365 return 0; 1366 } 1367 1368 /** 1369 * vcn_v4_0_3_stop - VCN stop 1370 * 1371 * @vinst: VCN instance 1372 * 1373 * Stop VCN block 1374 */ 1375 static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst) 1376 { 1377 struct amdgpu_device *adev = vinst->adev; 1378 int i = vinst->inst; 1379 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1380 int r = 0, vcn_inst; 1381 uint32_t tmp; 1382 1383 vcn_inst = GET_INST(VCN, i); 1384 1385 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1386 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1387 1388 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1389 vcn_v4_0_3_stop_dpg_mode(vinst); 1390 goto Done; 1391 } 1392 1393 /* wait for vcn idle */ 1394 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, 1395 UVD_STATUS__IDLE, 0x7); 1396 if (r) 1397 goto Done; 1398 1399 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1400 UVD_LMI_STATUS__READ_CLEAN_MASK | 1401 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1402 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1403 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1404 tmp); 1405 if (r) 1406 goto Done; 1407 1408 /* stall UMC channel */ 1409 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1410 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1411 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1412 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1413 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1414 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1415 tmp); 1416 if (r) 1417 goto Done; 1418 1419 /* Unblock VCPU Register access */ 1420 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1421 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1422 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1423 1424 /* release VCPU reset to boot */ 1425 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1426 UVD_VCPU_CNTL__BLK_RST_MASK, 1427 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1428 1429 /* disable VCPU clock */ 1430 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1431 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1432 1433 /* reset LMI UMC/LMI/VCPU */ 1434 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1435 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1436 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1437 1438 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1439 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1440 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1441 1442 /* clear VCN status */ 1443 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1444 1445 /* apply HW clock gating */ 1446 vcn_v4_0_3_enable_clock_gating(vinst); 1447 1448 Done: 1449 return 0; 1450 } 1451 1452 /** 1453 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode 1454 * 1455 * @vinst: VCN instance 1456 * @new_state: pause state 1457 * 1458 * Pause dpg mode for VCN block 1459 */ 1460 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1461 struct dpg_pause_state *new_state) 1462 { 1463 1464 return 0; 1465 } 1466 1467 /** 1468 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer 1469 * 1470 * @ring: amdgpu_ring pointer 1471 * 1472 * Returns the current hardware unified read pointer 1473 */ 1474 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring) 1475 { 1476 struct amdgpu_device *adev = ring->adev; 1477 1478 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1479 DRM_ERROR("wrong ring id is identified in %s", __func__); 1480 1481 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1482 } 1483 1484 /** 1485 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer 1486 * 1487 * @ring: amdgpu_ring pointer 1488 * 1489 * Returns the current hardware unified write pointer 1490 */ 1491 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring) 1492 { 1493 struct amdgpu_device *adev = ring->adev; 1494 1495 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1496 DRM_ERROR("wrong ring id is identified in %s", __func__); 1497 1498 if (ring->use_doorbell) 1499 return *ring->wptr_cpu_addr; 1500 else 1501 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), 1502 regUVD_RB_WPTR); 1503 } 1504 1505 void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1506 uint32_t val, uint32_t mask) 1507 { 1508 /* Use normalized offsets when required */ 1509 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1510 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1511 1512 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1513 amdgpu_ring_write(ring, reg << 2); 1514 amdgpu_ring_write(ring, mask); 1515 amdgpu_ring_write(ring, val); 1516 } 1517 1518 void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 1519 uint32_t val) 1520 { 1521 /* Use normalized offsets when required */ 1522 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1523 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1524 1525 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1526 amdgpu_ring_write(ring, reg << 2); 1527 amdgpu_ring_write(ring, val); 1528 } 1529 1530 void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1531 unsigned int vmid, uint64_t pd_addr) 1532 { 1533 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1534 1535 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1536 1537 /* wait for reg writes */ 1538 vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1539 vmid * hub->ctx_addr_distance, 1540 lower_32_bits(pd_addr), 0xffffffff); 1541 } 1542 1543 void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1544 { 1545 /* VCN engine access for HDP flush doesn't work when RRMT is enabled. 1546 * This is a workaround to avoid any HDP flush through VCN ring. 1547 */ 1548 } 1549 1550 /** 1551 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer 1552 * 1553 * @ring: amdgpu_ring pointer 1554 * 1555 * Commits the enc write pointer to the hardware 1556 */ 1557 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) 1558 { 1559 struct amdgpu_device *adev = ring->adev; 1560 1561 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1562 DRM_ERROR("wrong ring id is identified in %s", __func__); 1563 1564 if (ring->use_doorbell) { 1565 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1566 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1567 } else { 1568 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1569 lower_32_bits(ring->wptr)); 1570 } 1571 } 1572 1573 static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) 1574 { 1575 int r = 0; 1576 int vcn_inst; 1577 struct amdgpu_device *adev = ring->adev; 1578 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1579 1580 if (amdgpu_sriov_vf(ring->adev)) 1581 return -EOPNOTSUPP; 1582 1583 if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) 1584 return -EOPNOTSUPP; 1585 1586 vcn_inst = GET_INST(VCN, ring->me); 1587 r = amdgpu_dpm_reset_vcn(adev, 1 << vcn_inst); 1588 1589 if (r) { 1590 DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); 1591 return r; 1592 } 1593 1594 /* This flag is not set for VF, assumed to be disabled always */ 1595 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 1596 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 1597 vcn_v4_0_3_hw_init_inst(vinst); 1598 vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram); 1599 r = amdgpu_ring_test_helper(ring); 1600 1601 return r; 1602 } 1603 1604 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { 1605 .type = AMDGPU_RING_TYPE_VCN_ENC, 1606 .align_mask = 0x3f, 1607 .nop = VCN_ENC_CMD_NO_OP, 1608 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, 1609 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, 1610 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, 1611 .emit_frame_size = 1612 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1613 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1614 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1615 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1616 1, /* vcn_v2_0_enc_ring_insert_end */ 1617 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1618 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1619 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1620 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1621 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1622 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1623 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1624 .insert_nop = amdgpu_ring_insert_nop, 1625 .insert_end = vcn_v2_0_enc_ring_insert_end, 1626 .pad_ib = amdgpu_ring_generic_pad_ib, 1627 .begin_use = amdgpu_vcn_ring_begin_use, 1628 .end_use = amdgpu_vcn_ring_end_use, 1629 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1630 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1631 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1632 .reset = vcn_v4_0_3_ring_reset, 1633 }; 1634 1635 /** 1636 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions 1637 * 1638 * @adev: amdgpu_device pointer 1639 * 1640 * Set unified ring functions 1641 */ 1642 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev) 1643 { 1644 int i, vcn_inst; 1645 1646 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1647 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs; 1648 adev->vcn.inst[i].ring_enc[0].me = i; 1649 vcn_inst = GET_INST(VCN, i); 1650 adev->vcn.inst[i].aid_id = 1651 vcn_inst / adev->vcn.num_inst_per_aid; 1652 } 1653 } 1654 1655 /** 1656 * vcn_v4_0_3_is_idle - check VCN block is idle 1657 * 1658 * @ip_block: Pointer to the amdgpu_ip_block structure 1659 * 1660 * Check whether VCN block is idle 1661 */ 1662 static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block) 1663 { 1664 struct amdgpu_device *adev = ip_block->adev; 1665 int i, ret = 1; 1666 1667 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1668 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == 1669 UVD_STATUS__IDLE); 1670 } 1671 1672 return ret; 1673 } 1674 1675 /** 1676 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle 1677 * 1678 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1679 * 1680 * Wait for VCN block idle 1681 */ 1682 static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 1683 { 1684 struct amdgpu_device *adev = ip_block->adev; 1685 int i, ret = 0; 1686 1687 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1688 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, 1689 UVD_STATUS__IDLE, UVD_STATUS__IDLE); 1690 if (ret) 1691 return ret; 1692 } 1693 1694 return ret; 1695 } 1696 1697 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state 1698 * 1699 * @ip_block: amdgpu_ip_block pointer 1700 * @state: clock gating state 1701 * 1702 * Set VCN block clockgating state 1703 */ 1704 static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1705 enum amd_clockgating_state state) 1706 { 1707 struct amdgpu_device *adev = ip_block->adev; 1708 bool enable = state == AMD_CG_STATE_GATE; 1709 int i; 1710 1711 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1712 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1713 1714 if (enable) { 1715 if (RREG32_SOC15(VCN, GET_INST(VCN, i), 1716 regUVD_STATUS) != UVD_STATUS__IDLE) 1717 return -EBUSY; 1718 vcn_v4_0_3_enable_clock_gating(vinst); 1719 } else { 1720 vcn_v4_0_3_disable_clock_gating(vinst); 1721 } 1722 } 1723 return 0; 1724 } 1725 1726 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 1727 enum amd_powergating_state state) 1728 { 1729 struct amdgpu_device *adev = vinst->adev; 1730 int ret = 0; 1731 1732 /* for SRIOV, guest should not control VCN Power-gating 1733 * MMSCH FW should control Power-gating and clock-gating 1734 * guest should avoid touching CGC and PG 1735 */ 1736 if (amdgpu_sriov_vf(adev)) { 1737 vinst->cur_state = AMD_PG_STATE_UNGATE; 1738 return 0; 1739 } 1740 1741 if (state == vinst->cur_state) 1742 return 0; 1743 1744 if (state == AMD_PG_STATE_GATE) 1745 ret = vcn_v4_0_3_stop(vinst); 1746 else 1747 ret = vcn_v4_0_3_start(vinst); 1748 1749 if (!ret) 1750 vinst->cur_state = state; 1751 1752 return ret; 1753 } 1754 1755 /** 1756 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state 1757 * 1758 * @adev: amdgpu_device pointer 1759 * @source: interrupt sources 1760 * @type: interrupt types 1761 * @state: interrupt states 1762 * 1763 * Set VCN block interrupt state 1764 */ 1765 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1766 struct amdgpu_irq_src *source, 1767 unsigned int type, 1768 enum amdgpu_interrupt_state state) 1769 { 1770 return 0; 1771 } 1772 1773 /** 1774 * vcn_v4_0_3_process_interrupt - process VCN block interrupt 1775 * 1776 * @adev: amdgpu_device pointer 1777 * @source: interrupt sources 1778 * @entry: interrupt entry from clients and sources 1779 * 1780 * Process VCN block interrupt 1781 */ 1782 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1783 struct amdgpu_irq_src *source, 1784 struct amdgpu_iv_entry *entry) 1785 { 1786 uint32_t i, inst; 1787 1788 i = node_id_to_phys_map[entry->node_id]; 1789 1790 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1791 1792 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1793 if (adev->vcn.inst[inst].aid_id == i) 1794 break; 1795 1796 if (inst >= adev->vcn.num_vcn_inst) { 1797 dev_WARN_ONCE(adev->dev, 1, 1798 "Interrupt received for unknown VCN instance %d", 1799 entry->node_id); 1800 return 0; 1801 } 1802 1803 switch (entry->src_id) { 1804 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1805 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1806 break; 1807 default: 1808 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1809 entry->src_id, entry->src_data[0]); 1810 break; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 1817 .set = vcn_v4_0_3_set_interrupt_state, 1818 .process = vcn_v4_0_3_process_interrupt, 1819 }; 1820 1821 /** 1822 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions 1823 * 1824 * @adev: amdgpu_device pointer 1825 * 1826 * Set VCN block interrupt irq functions 1827 */ 1828 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1829 { 1830 int i; 1831 1832 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1833 adev->vcn.inst->irq.num_types++; 1834 } 1835 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 1836 } 1837 1838 static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1839 { 1840 struct amdgpu_device *adev = ip_block->adev; 1841 int i, j; 1842 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 1843 uint32_t inst_off, is_powered; 1844 1845 if (!adev->vcn.ip_dump) 1846 return; 1847 1848 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1849 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1850 if (adev->vcn.harvest_config & (1 << i)) { 1851 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1852 continue; 1853 } 1854 1855 inst_off = i * reg_count; 1856 is_powered = (adev->vcn.ip_dump[inst_off] & 1857 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1858 1859 if (is_powered) { 1860 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1861 for (j = 0; j < reg_count; j++) 1862 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name, 1863 adev->vcn.ip_dump[inst_off + j]); 1864 } else { 1865 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1866 } 1867 } 1868 } 1869 1870 static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block) 1871 { 1872 struct amdgpu_device *adev = ip_block->adev; 1873 int i, j; 1874 bool is_powered; 1875 uint32_t inst_off, inst_id; 1876 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 1877 1878 if (!adev->vcn.ip_dump) 1879 return; 1880 1881 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1882 if (adev->vcn.harvest_config & (1 << i)) 1883 continue; 1884 1885 inst_id = GET_INST(VCN, i); 1886 inst_off = i * reg_count; 1887 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1888 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS); 1889 is_powered = (adev->vcn.ip_dump[inst_off] & 1890 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1891 1892 if (is_powered) 1893 for (j = 1; j < reg_count; j++) 1894 adev->vcn.ip_dump[inst_off + j] = 1895 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j], 1896 inst_id)); 1897 } 1898 } 1899 1900 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 1901 .name = "vcn_v4_0_3", 1902 .early_init = vcn_v4_0_3_early_init, 1903 .sw_init = vcn_v4_0_3_sw_init, 1904 .sw_fini = vcn_v4_0_3_sw_fini, 1905 .hw_init = vcn_v4_0_3_hw_init, 1906 .hw_fini = vcn_v4_0_3_hw_fini, 1907 .suspend = vcn_v4_0_3_suspend, 1908 .resume = vcn_v4_0_3_resume, 1909 .is_idle = vcn_v4_0_3_is_idle, 1910 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 1911 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 1912 .set_powergating_state = vcn_set_powergating_state, 1913 .dump_ip_state = vcn_v4_0_3_dump_ip_state, 1914 .print_ip_state = vcn_v4_0_3_print_ip_state, 1915 }; 1916 1917 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { 1918 .type = AMD_IP_BLOCK_TYPE_VCN, 1919 .major = 4, 1920 .minor = 0, 1921 .rev = 3, 1922 .funcs = &vcn_v4_0_3_ip_funcs, 1923 }; 1924 1925 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = { 1926 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD), 1927 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"}, 1928 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV), 1929 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"}, 1930 }; 1931 1932 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1933 uint32_t vcn_inst, 1934 void *ras_err_status) 1935 { 1936 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1937 1938 /* vcn v4_0_3 only support query uncorrectable errors */ 1939 amdgpu_ras_inst_query_ras_error_count(adev, 1940 vcn_v4_0_3_ue_reg_list, 1941 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1942 NULL, 0, GET_INST(VCN, vcn_inst), 1943 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1944 &err_data->ue_count); 1945 } 1946 1947 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1948 void *ras_err_status) 1949 { 1950 uint32_t i; 1951 1952 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1953 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1954 return; 1955 } 1956 1957 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1958 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1959 } 1960 1961 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1962 uint32_t vcn_inst) 1963 { 1964 amdgpu_ras_inst_reset_ras_error_count(adev, 1965 vcn_v4_0_3_ue_reg_list, 1966 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1967 GET_INST(VCN, vcn_inst)); 1968 } 1969 1970 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1971 { 1972 uint32_t i; 1973 1974 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1975 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1976 return; 1977 } 1978 1979 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1980 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 1981 } 1982 1983 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 1984 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 1985 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 1986 }; 1987 1988 static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1989 enum aca_smu_type type, void *data) 1990 { 1991 struct aca_bank_info info; 1992 u64 misc0; 1993 int ret; 1994 1995 ret = aca_bank_info_decode(bank, &info); 1996 if (ret) 1997 return ret; 1998 1999 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2000 switch (type) { 2001 case ACA_SMU_TYPE_UE: 2002 bank->aca_err_type = ACA_ERROR_TYPE_UE; 2003 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2004 1ULL); 2005 break; 2006 case ACA_SMU_TYPE_CE: 2007 bank->aca_err_type = ACA_ERROR_TYPE_CE; 2008 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 2009 ACA_REG__MISC0__ERRCNT(misc0)); 2010 break; 2011 default: 2012 return -EINVAL; 2013 } 2014 2015 return ret; 2016 } 2017 2018 /* reference to smu driver if header file */ 2019 static int vcn_v4_0_3_err_codes[] = { 2020 14, 15, /* VCN */ 2021 }; 2022 2023 static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2024 enum aca_smu_type type, void *data) 2025 { 2026 u32 instlo; 2027 2028 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2029 instlo &= GENMASK(31, 1); 2030 2031 if (instlo != mmSMNAID_AID0_MCA_SMU) 2032 return false; 2033 2034 if (aca_bank_check_error_codes(handle->adev, bank, 2035 vcn_v4_0_3_err_codes, 2036 ARRAY_SIZE(vcn_v4_0_3_err_codes))) 2037 return false; 2038 2039 return true; 2040 } 2041 2042 static const struct aca_bank_ops vcn_v4_0_3_aca_bank_ops = { 2043 .aca_bank_parser = vcn_v4_0_3_aca_bank_parser, 2044 .aca_bank_is_valid = vcn_v4_0_3_aca_bank_is_valid, 2045 }; 2046 2047 static const struct aca_info vcn_v4_0_3_aca_info = { 2048 .hwip = ACA_HWIP_TYPE_SMU, 2049 .mask = ACA_ERROR_UE_MASK, 2050 .bank_ops = &vcn_v4_0_3_aca_bank_ops, 2051 }; 2052 2053 static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2054 { 2055 int r; 2056 2057 r = amdgpu_ras_block_late_init(adev, ras_block); 2058 if (r) 2059 return r; 2060 2061 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN, 2062 &vcn_v4_0_3_aca_info, NULL); 2063 if (r) 2064 goto late_fini; 2065 2066 return 0; 2067 2068 late_fini: 2069 amdgpu_ras_block_late_fini(adev, ras_block); 2070 2071 return r; 2072 } 2073 2074 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = { 2075 .ras_block = { 2076 .hw_ops = &vcn_v4_0_3_ras_hw_ops, 2077 .ras_late_init = vcn_v4_0_3_ras_late_init, 2078 }, 2079 }; 2080 2081 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 2082 { 2083 adev->vcn.ras = &vcn_v4_0_3_ras; 2084 } 2085 2086 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 2087 int inst_idx, bool indirect) 2088 { 2089 uint32_t tmp; 2090 2091 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 2092 return; 2093 2094 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 2095 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 2096 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 2097 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 2098 WREG32_SOC15_DPG_MODE(inst_idx, 2099 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 2100 tmp, 0, indirect); 2101 2102 tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK; 2103 WREG32_SOC15_DPG_MODE(inst_idx, 2104 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2), 2105 tmp, 0, indirect); 2106 2107 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 2108 WREG32_SOC15_DPG_MODE(inst_idx, 2109 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 2110 tmp, 0, indirect); 2111 } 2112